Stacked broadband RF amplifier and its wireless transceiver circuit

Abstract

This invention belongs to the field of radio frequency integrated circuit technology and discloses a stacked broadband radio frequency amplifier and its wireless transceiver circuit. The stacked broadband radio frequency amplifier includes an input impedance matching network, a first stacked amplifier circuit, a second stacked amplifier circuit, and an output impedance matching network. The input terminal of the input impedance matching network serves as the input terminal of the stacked broadband radio frequency amplifier and is connected to the radio frequency signal input terminal. The output terminal of the input impedance matching network outputs the radio frequency signal to the first stacked amplifier circuit. After receiving the radio frequency signal, the input terminal of the first stacked amplifier circuit outputs a first-stage amplified radio frequency signal. After receiving the first-stage amplified radio frequency signal, the first stacked amplifier circuit further amplifies and outputs a second-stage amplified radio frequency signal. The input terminal of the output impedance matching network receives the second-stage amplified radio frequency signal and outputs the amplified radio frequency signal. The amplifier structure of this invention is simple and has excellent high power output, low phase distortion, and wide temperature stability.

Description

Technical Field

[0001] This utility model belongs to the field of radio frequency integrated circuit technology, and relates to a stacked broadband radio frequency amplifier and its wireless transceiver circuit. Background Technology

[0002] With the explosive growth in demand for wireless communication speeds from applications such as 5G / 6G millimeter-wave communication and phased-array radar, the X-band (8-12GHz) has become a research hotspot due to its wider signal spectrum bandwidth. Modern wireless transceiver systems face multiple challenges, including low cost, high energy efficiency, miniaturization, and high reliability. CMOS technology, with its extremely low power consumption, excellent noise immunity, and ultra-high integration, has become a core technology path to achieve these goals. This process not only supports higher frequency band operation through process miniaturization, but its inherent compatibility with digital chips also enables monolithic integration of the RF front-end and baseband, significantly reducing system complexity and production costs.

[0003] As a crucial component of wireless communication systems, radio frequency (RF) amplifiers amplify low-power RF signals without distortion, enabling them to be radiated through antennas. The performance of the RF amplifier directly impacts key system parameters such as dynamic range, power consumption, and sensitivity. Especially in systems like phased array radar and 5G / 6G millimeter-wave communication, the RF amplifier, as a core module, must simultaneously meet the requirements of high power output, low phase distortion, and wide temperature stability. Traditional amplifier structures, limited by the breakdown voltage of CMOS processes, struggle to achieve these specifications. Therefore, there is an urgent need to research and develop a stacked broadband RF amplifier to overcome these bottlenecks and construct power amplifiers for communication standards. Utility Model Content

[0004] The purpose of this invention is to provide a stacked broadband RF amplifier that achieves high power output, low phase distortion, and wide temperature stability by employing an input impedance matching network, a first stacked amplifier circuit consisting of three transistors stacked with their drains and sources connected together, a second stacked amplifier circuit consisting of three transistors stacked with their drains and sources connected together, and an output impedance matching network.

[0005] Another objective of this invention is to provide a wireless transceiver circuit.

[0006] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0007] A stacked broadband RF amplifier includes an input impedance matching network, a first stacked amplifier circuit consisting of three transistors stacked with their drains and sources connected, a second stacked amplifier circuit consisting of three transistors stacked with their drains and sources connected, and an output impedance matching network.

[0008] The input terminal of the input impedance matching network is connected to the input terminal of the stacked broadband RF amplifier and the RF signal input terminal. The output terminal of the input impedance matching network outputs the RF signal to the first stacked amplifier circuit. After receiving the RF signal, the input terminal of the first stacked amplifier circuit outputs a first-stage amplified RF signal. After receiving the first-stage amplified RF signal, the first stacked amplifier circuit further amplifies and outputs a second-stage amplified RF signal. After receiving the second-stage amplified RF signal, the input terminal of the output impedance matching network outputs the amplified RF signal.

[0009] As a limitation, the input impedance matching network adopts an LC series resonant circuit;

[0010] One end of the LC series resonant circuit is connected to the RF signal input terminal RFIN as the input terminal of the input impedance matching network, and the other end is connected to the input terminal of the first stacked amplifier circuit as the output terminal of the input impedance matching network.

[0011] As a second limitation, the first stacked amplifier circuit includes a first transistor, a second transistor, a third transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first RF resistor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, and a first choke inductor; the first transistor, the second transistor, and the third transistor form the first amplifier circuit, the second resistor, the third resistor, and the fourth resistor form the first bias circuit, the first resistor is the first negative feedback circuit, and the fifth capacitor and the fifth resistor are connected in series to form a resonant circuit;

[0012] One end of the first resistor and one end of the second capacitor are connected together and serve as the input terminal of the first stacked amplifier circuit, which is connected to the output terminal of the input impedance matching network. The other end of the second capacitor is connected to one end of the first RF resistor and the gate of the first transistor. The other end of the first RF resistor is connected to the positive terminal of the first bias voltage, and the negative terminal of the first bias voltage is grounded. The source of the first transistor is grounded, and the drain of the first transistor is connected to the source of the second transistor and one end of the fifth resistor. The other end of the fifth resistor is connected to one end of the fifth capacitor. The drain of the second transistor is connected to the source of the third transistor. The gate of the second transistor is connected to one end of the fourth capacitor, one end of the third resistor, and one end of the fourth resistor. The other ends of the fourth capacitor and the fourth resistor are both grounded. The other end of the third resistor is connected to one end of the second resistor, one end of the third capacitor, and the gate of the third transistor. The other end of the third capacitor is grounded. The drain of the third transistor, the other end of the first resistor, the other end of the second resistor, the other end of the fifth capacitor, and one end of the first choke inductor are all connected to one end of the sixth capacitor. The other end of the first choke inductor is connected to the power supply voltage. The other end of the sixth capacitor serves as the output terminal of the first stacked amplifier circuit and is connected to the input terminal of the second stacked amplifier circuit.

[0013] As a further limitation, the size of the first transistor in the first stacked amplifier circuit is larger than the size of the second transistor and the third transistor, while the second transistor and the third transistor are the same size.

[0014] As a third limitation, the second stacked amplifier circuit includes a fourth transistor, a fifth transistor, a sixth transistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a second RF resistor, a seventh capacitor, an eighth capacitor, a ninth capacitor, and a second choke inductor; the fourth transistor, the fifth transistor, and the sixth transistor form the second amplifier circuit, the seventh resistor, the eighth resistor, and the ninth resistor form the second bias circuit, and the sixth resistor is the second negative feedback circuit.

[0015] One end of the sixth resistor and one end of the seventh capacitor are connected together to serve as the input terminal of the second stacked amplifier circuit and are connected to the output terminal of the first stacked amplifier circuit. The other end of the seventh capacitor is connected to the second RF resistor and the gate of the fourth transistor. The other end of the second RF resistor is connected to the positive terminal of the second bias voltage, and the negative terminal of the second bias voltage is grounded. The source of the fourth transistor is grounded, and the drain of the fourth transistor is connected to the source of the fifth transistor. The drain of the fifth transistor is connected to the source of the sixth transistor. The gate of the fifth transistor is connected to one end of the ninth capacitor, one end of the eighth resistor, and one end of the ninth resistor. The other ends of the ninth capacitor and the ninth resistor are both grounded. The other end of the eighth resistor is connected to one end of the seventh resistor, one end of the eighth capacitor, and the gate of the sixth transistor. The other end of the eighth capacitor is grounded. The drain of the sixth transistor, the other end of the sixth resistor, the other end of the seventh resistor, and one end of the second choke inductor are connected together to serve as the output terminal of the second stacked amplifier circuit and are connected to the input terminal of the output impedance matching network. The other end of the second choke inductor is connected to the power supply voltage.

[0016] As a further limitation, the fourth, fifth, and sixth transistors in the second stacked amplifier circuit are of the same size.

[0017] As a fourth limitation, the output impedance matching network includes a tenth resistor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, and a second inductor;

[0018] One end of the tenth resistor and one end of the tenth capacitor are connected together and then used as the input terminal of the output impedance matching network and connected to the output terminal of the second stacked amplifier circuit. The other ends of the tenth resistor and the tenth capacitor are both connected to one end of the eleventh capacitor. The other end of the eleventh capacitor is connected to one end of the twelfth capacitor and one end of the second inductor, respectively. The other end of the second inductor is grounded, and the other end of the twelfth capacitor is connected to the radio frequency signal output terminal.

[0019] This invention also provides a wireless transceiver circuit, including the aforementioned stacked broadband radio frequency amplifier.

[0020] The technological advancements achieved by this invention compared to existing technologies, due to the adoption of the aforementioned technical solution, are as follows:

[0021] (1) This utility model includes an input impedance matching network, a first stacked amplifier circuit consisting of three transistors connected by their drain and source, a second stacked amplifier circuit consisting of three transistors connected by their drain and source, and an output impedance matching network. Through the design of a stacked broadband RF amplifier, the amplification function is integrated into the first and second stacked amplifier circuits, reducing the number of modules, improving the integration, and making the overall structure simpler. In addition, through the design of two stacked amplifier circuits, each stage amplifies the RF signal, effectively improving the amplification efficiency. At the same time, the stacked structure helps to reduce inter-stage matching losses and improve overall performance.

[0022] (2) In this utility model, the first stacked amplifier circuit adopts a combination of a first amplifier circuit, a first negative feedback circuit, a first bias circuit and a resonant circuit composed of three stacked transistors, and the second stacked amplifier circuit adopts a combination of a second amplifier circuit, a second negative feedback circuit and a second bias circuit composed of three stacked transistors, thereby achieving excellent performance such as wide bandwidth, low power consumption, high linearity and low standing wave ratio.

[0023] (3) The present invention can use an active bias circuit with temperature compensation circuit to provide a second bias voltage and a second bias voltage, thereby avoiding the degradation of amplifier performance caused by temperature changes and process deviations.

[0024] In summary, this utility model has a simple structure and excellent high power output, low phase distortion and wide temperature stability. Attached Figure Description

[0025] Figure 1 The diagram shown is a circuit schematic of a stacked broadband radio frequency amplifier according to an embodiment of this utility model.

[0026] Figure 2 The figure shown is a simulation result of the 1dB compression point of the stacked broadband RF amplifier according to an embodiment of this utility model.

[0027] Figure 3 The figure shown is the stability factor B of the stacked broadband RF amplifier according to an embodiment of this utility model. 1f Simulation results diagram;

[0028] Figure 4 The figure shown is a fabrication test curve of the S-parameters of the stacked broadband RF amplifier according to an embodiment of this utility model.

[0029] Figure 5 The diagram shown is a layout of a stacked broadband RF amplifier according to an embodiment of this utility model. Detailed Implementation

[0030] To better explain and facilitate understanding of this utility model, the present utility model will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0031] An embodiment of a stacked broadband radio frequency amplifier and its wireless transceiver circuit.

[0032] like Figure 1 As shown, this embodiment is a stacked broadband RF amplifier, including an input impedance matching network, a first stacked amplifier circuit consisting of three transistors stacked with their drains and sources connected together, a second stacked amplifier circuit consisting of three transistors stacked with their drains and sources connected together, and an output impedance matching network.

[0033] The input terminal of the input impedance matching network is connected to the RF signal input terminal RFIN as the input terminal of the stacked broadband RF amplifier. The output terminal of the input impedance matching network outputs the RF signal to the first stacked amplifier circuit. After receiving the RF signal, the input terminal of the first stacked amplifier circuit outputs a first-stage amplified RF signal. After receiving the first-stage amplified RF signal, the first stacked amplifier circuit further amplifies and outputs a second-stage amplified RF signal. After receiving the second-stage amplified RF signal, the input terminal of the output impedance matching network outputs the amplified RF signal.

[0034] In this embodiment, the input impedance matching network adopts an LC series resonant circuit. The LC series resonant circuit is obtained by connecting the first capacitor C1 and the first inductor Lg in series. One end of the first inductor Lg is connected to the RF signal input terminal RFIN as the input terminal of the input impedance matching network. One end of the first capacitor C1 is connected to the input terminal of the first stacked amplifier circuit, i.e., the first resistor R1 and one end of the second capacitor C2 are connected.

[0035] The input impedance matching network is used to achieve wideband matching and low noise performance of the stacked wideband RF amplifier. The input impedance matching network is connected to the first resistor R1 of the first stacked amplifier circuit and to the first transistor M1 through the second capacitor C2. The first inductor Lg is used to cancel the reactance generated by the parasitic capacitance in the input impedance matching network, so that the input impedance is a real number, thus making it easy to achieve impedance matching.

[0036] The first stacked amplifier circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a first RF resistor R. f1 The capacitors are: C2 (second capacitor), C3 (third capacitor), C4 (fourth capacitor), C5 (fifth capacitor), C6 (sixth capacitor), and L (first choke inductor). d1The first transistor M1, the second transistor M2 and the third transistor M3 form the first amplifier circuit, the second resistor R2, the third resistor R3 and the fourth resistor R4 form the first bias circuit, the first resistor R1 is the first negative feedback circuit, and the fifth capacitor C5 and the fifth resistor R5 are connected in series to form the resonant circuit.

[0037] The first resistor R1 and one end of the second capacitor C2 are connected together and serve as the input terminal of the first stacked amplifier circuit and the output terminal of the input impedance matching network. The other end of the second capacitor C2 is connected to the first RF resistor R1. f1 One end is connected to the gate of the first transistor M1, and the first RF resistor R f1 The other end is connected to the first bias voltage V g1 The positive terminal is connected, and the first bias voltage V g1 The negative terminal of the first transistor M1 is grounded; the source of the first transistor M1 is grounded, and the drain of the first transistor M1 is connected to the source of the second transistor M2 and one end of the fifth resistor R5; the other end of the fifth resistor R5 is connected to one end of the fifth capacitor C5; the drain of the second transistor M2 is connected to the source of the third transistor M3, and the gate of the second transistor M2 is connected to one end of the fourth capacitor C4, one end of the third resistor R3, and one end of the fourth resistor R4, with the other ends of the fourth capacitor C4 and the fourth resistor R4 both grounded; the other end of the third resistor R3 is connected to one end of the second resistor R2, one end of the third capacitor C3, and the gate of the third transistor M3, with the other end of the third capacitor C3 grounded; the drain of the third transistor M3, the other end of the first resistor R1, the other end of the second resistor R2, the other end of the fifth capacitor C5, and the first choke inductor L... d1 One end of each capacitor is connected to one end of the sixth capacitor C6, and the first choke inductor L d1 The other end is connected to the power supply voltage VDD, and the other end of the sixth capacitor C6 is connected to the output terminal of the first stacked amplifier circuit and the input terminal of the second stacked amplifier circuit.

[0038] In the first stacked amplifier circuit, the size of the first transistor M1 is larger than that of the second transistor M2 and the third transistor M3 to better reduce noise, while the second transistor M2 and the third transistor M3 are the same size. The resonant circuit consists of a fifth capacitor C5 and a fifth resistor R5 connected in series. The use of the resonant circuit increases the bandwidth of the amplifier, effectively improves the gain flatness, and also effectively improves the input matching performance.

[0039] The second stacked amplifier circuit includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a second RF resistor R. f2 Seventh capacitor C7, eighth capacitor C8, ninth capacitor C9, and second choke inductor L d2The fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 form the second amplifier circuit; the seventh resistor R7, the eighth resistor R8, and the ninth resistor R9 form the second bias circuit; and the sixth resistor R6 is the second negative feedback circuit.

[0040] One end of the sixth resistor R6 and one end of the seventh capacitor C7 are connected together to serve as the input terminal of the second stacked amplifier circuit and connected to the output terminal of the first stacked amplifier circuit. The other end of the seventh capacitor C7 is connected to the second RF resistor R6. f2 The second RF resistor R is connected to the gate of the fourth transistor M4. f2 The other end is connected to the second bias voltage V g2 The positive terminal is connected, and the second bias voltage V g2 The negative terminal of transistor M4 is grounded; the source of transistor M4 is grounded, and the drain of transistor M4 is connected to the source of transistor M5; the drain of transistor M5 is connected to the source of transistor M6; the gate of transistor M5 is connected to one end of capacitor C9, one end of resistor R8, and one end of resistor R9, respectively; the other ends of capacitor C9 and resistor R9 are both grounded; the other end of resistor R8 is connected to one end of resistor R7, one end of capacitor C8, and the gate of transistor M6, respectively; the other end of capacitor C8 is grounded; the drain of transistor M6, the other end of resistor R6, the other end of resistor R7, and the second choke inductor L... d2 One end of the circuit is connected to the output of the second stacked amplifier circuit and then connected to the input of the output impedance matching network. The second choke inductor L d2 The other end is connected to the power supply voltage VDD.

[0041] In the second stacked amplifier circuit, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are the same size. The interstage matching between the second and first stacked amplifier circuits is achieved using the sixth capacitor C6, which not only reduces the number of components used, thus saving chip area, but also improves the amplifier's stability.

[0042] The output impedance matching network includes a tenth resistor R10, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, and a second inductor Lm. One end of the tenth resistor R10 and one end of the tenth capacitor C10 are connected together as the input terminal of the output impedance matching network and connected to the output terminal of the second stacked amplifier circuit. The other ends of the tenth resistor R10 and the tenth capacitor C10 are both connected to one end of the eleventh capacitor C11. The other end of the eleventh capacitor C11 is connected to one end of the twelfth capacitor C12 and one end of the second inductor Lm. The other end of the second inductor Lm is grounded. The other end of the twelfth capacitor C12 is connected to the RF signal output terminal RFOUT.

[0043] In this embodiment, the output impedance matching network is used to achieve wideband output matching performance of the stacked wideband RF amplifier. The output impedance matching network adopts a combination of lossy matching and T-type matching networks, which not only improves the effective operating bandwidth of the amplifier, but also ensures that the gain and output power meet the performance specifications throughout the entire frequency band. The introduction of the lossy resistor, namely the tenth resistor R10, can effectively adjust the gain at high and low frequencies to improve the gain flatness within the operating frequency band. By consuming the additional gain at low frequencies, it avoids reflection and improves output matching, achieving gain compensation while also reducing signal reflection.

[0044] To avoid the effects of temperature variations and process deviations, this embodiment employs an existing active bias circuit with temperature compensation. A bandgap reference circuit generates a temperature-independent reference voltage, which is then provided by the subsequent temperature compensation circuit. The current mirror circuit in the active bias circuit replicates this temperature-stable current, making the bias current proportional to the threshold voltage Vt of the transistor in the first or second stacked amplifier circuit. This offsets changes in the transistor's base-emitter voltage Vbe, thereby providing the amplifier in this embodiment with a stable bias that effectively shields against ambient temperature variations, i.e., the second bias voltage V. g1 Second bias voltage V g2 .

[0045] The stacked broadband RF amplifier in this embodiment is a high-linearity, wide-bandwidth, low-VSWR, and low-power RF amplifier with an operating frequency band of 8-12GHz, a gain ≥ 21dB, a VSWR ≤ 1.4, an output 1dB compression point P1dB ≥ 14.5dBm, a stability factor Kf > 1, and B1f > 0. By combining a first stacked amplifier circuit and a second stacked amplifier circuit, the amplifier's operating bandwidth is effectively improved, and the power consumption is reduced while increasing the gain.

[0046] Both the first and second stacked amplifier circuits employ a three-layer transistor stacking method. The transistor stack structure connects multiple transistors sequentially through drain and source, achieving a higher output voltage swing to overcome the requirement of high output power under low breakdown voltage. Simultaneously, the gate-source capacitors, third capacitor C3, and fourth capacitor C4 of the three transistors in the first stacked amplifier circuit, and the gate-source capacitors, eighth capacitor C8, and ninth capacitor C9 of the three transistors in the second stacked amplifier circuit, can be used to adjust the drain voltage phase of each transistor, ensuring consistent drain voltage phase and solving the problem of reduced drain voltage swing due to phase misalignment. This allows the stacked broadband RF amplifier to meet the output 1dB compression point P1dB≥14.5dBm. Figure 2 The figure shown is a simulation result of the 1dB compression point output in this embodiment. It can be seen from the figure that the 1dB compression point P1dB≥14.5dBm.

[0047] Furthermore, due to the wide operating bandwidth of the stacked broadband RF amplifier, this embodiment employs negative feedback and resonant circuit structures in both the first and second stacked amplifier circuits to extend the bandwidth. The first resistor R1 in the first stacked amplifier circuit and the sixth resistor R6 in the second stacked amplifier circuit, acting as negative feedback resistors, not only effectively increase the amplifier's operating bandwidth but also improve the gain flatness across the entire operating frequency band. The fifth capacitor C5 and the fifth resistor R5, connected in series in the first stacked amplifier circuit, form a resonant circuit, improving the gain at low frequencies and optimizing input matching. This enables the stacked broadband RF amplifier to meet the gain requirement of ≥21dB.

[0048] Figure 3 The figure shown is the stability factor B in this embodiment. 1f The simulation results are shown in the figure. It can be seen from the figure that the stability factor B of the stacked broadband RF amplifier in this embodiment is... 1f If the value is greater than 0, the amplifier is unconditionally stable across the entire frequency range.

[0049] Figure 4 The figure shows the S-parameter fabrication test curve of this embodiment. As can be seen from the figure, the stacked broadband RF amplifier of this embodiment has a gain of 21dB, a gain flatness of ±0.3dB, excellent input and output backoff losses, both less than -15dB, and the output 1dB compression point P1dB is greater than 14.5dBm, with good linearity.

[0050] like Figure 5 The diagram shown is the layout of the stacked broadband RF amplifier in this embodiment, powered by a +3.3V DC supply. The layout simulation results and... Figure 4 The S-parameter fabrication test results are similar, showing that the stacked broadband RF amplifier has a gain of 21dB, a gain flatness of ±0.3dB, excellent input and output backlash losses (both less than -15dB), and an output 1dB compression point P1dB greater than 14.5dBm, indicating good linearity. Figure 3 The stability factor B shown 1f Simulation results show that the stability factor B of the stacked broadband RF amplifier in this embodiment is... 1f In the 0-100GHz frequency range, Kf>1 and B 1f >0, the amplifier in this embodiment is unconditionally stable across the entire frequency range, and the chip area is 0.3 × 0.57 mm. 2 It has performance advantages such as high linearity, wide bandwidth, low VSWR and small size.

[0051] Therefore, this embodiment is a high linearity, wide bandwidth, low VSWR and low power consumption RF amplifier chip with a working frequency band of 8-12GHz, gain ≥21dB, VSWR ≤1.4, output 1dB compression point P1dB ≥14.5dBm, stability factor Kf>1, B1f>0; it not only effectively improves the amplifier's working bandwidth, but also reduces the amplifier's power consumption while increasing the gain, and is used in wireless transceiver circuits.

[0052] It should be noted that the above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model. Although the present utility model has been described in detail with reference to the above embodiments, those skilled in the art can still modify the technical solutions described in the above embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A stacked broadband radio frequency amplifier, characterized in that, It includes an input impedance matching network, a first stacked amplifier circuit consisting of three transistors connected at their drain and source, a second stacked amplifier circuit consisting of three transistors connected at their drain and source, and an output impedance matching network; The input terminal of the input impedance matching network is connected to the input terminal of the stacked broadband RF amplifier and the RF signal input terminal. The output terminal of the input impedance matching network outputs the RF signal to the first stacked amplifier circuit. After receiving the RF signal, the input terminal of the first stacked amplifier circuit outputs a first-stage amplified RF signal. After receiving the first-stage amplified RF signal, the first stacked amplifier circuit further amplifies and outputs a second-stage amplified RF signal. After receiving the second-stage amplified RF signal, the input terminal of the output impedance matching network outputs the amplified RF signal.

2. The stacked broadband RF amplifier according to claim 1, characterized in that, The input impedance matching network adopts an LC series resonant circuit. One end of the LC series resonant circuit is connected to the RF signal input terminal RFIN as the input terminal of the input impedance matching network, and the other end is connected to the input terminal of the first stacked amplifier circuit as the output terminal of the input impedance matching network.

3. The stacked broadband RF amplifier according to claim 1 or 2, characterized in that, The first stacked amplifier circuit includes a first transistor, a second transistor, a third transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first RF resistor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, and a first choke inductor; the first transistor, the second transistor, and the third transistor form the first amplifier circuit, the second resistor, the third resistor, and the fourth resistor form the first bias circuit, the first resistor is the first negative feedback circuit, and the fifth capacitor and the fifth resistor are connected in series to form a resonant circuit; One end of the first resistor and one end of the second capacitor are connected together and serve as the input terminal of the first stacked amplifier circuit and are connected to the output terminal of the input impedance matching network. The other end of the second capacitor is connected to one end of the first RF resistor and the gate of the first transistor, respectively. The other end of the first RF resistor is connected to the positive terminal of the first bias voltage, and the negative terminal of the first bias voltage is grounded. The source of the first transistor is grounded, and the drain of the first transistor is connected to the source of the second transistor and one end of the fifth resistor, respectively. The other end of the fifth resistor is connected to one end of the fifth capacitor; the drain of the second transistor is connected to the source of the third transistor, and the gate of the second transistor is connected to one end of the fourth capacitor, one end of the third resistor, and one end of the fourth resistor, respectively. The other ends of the fourth capacitor and the fourth resistor are both grounded. The other end of the third resistor is connected to one end of the second resistor, one end of the third capacitor, and the gate of the third transistor, respectively. The other end of the third capacitor is grounded. The drain of the third transistor, the other end of the first resistor, the other end of the second resistor, the other end of the fifth capacitor, and one end of the first choke inductor are all connected to one end of the sixth capacitor. The other end of the first choke inductor is connected to the power supply voltage. The other end of the sixth capacitor is connected as the output terminal of the first stacked amplifier circuit and the input terminal of the second stacked amplifier circuit.

4. The stacked broadband RF amplifier according to claim 3, characterized in that, In the first stacked amplifier circuit, the size of the first transistor is larger than that of the second and third transistors, while the second and third transistors are the same size.

5. The stacked broadband RF amplifier according to claim 1 or 2, characterized in that, The second stacked amplifier circuit includes a fourth transistor, a fifth transistor, a sixth transistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a second RF resistor, a seventh capacitor, an eighth capacitor, a ninth capacitor, and a second choke inductor; the fourth transistor, the fifth transistor, and the sixth transistor form the second amplifier circuit, the seventh resistor, the eighth resistor, and the ninth resistor form the second bias circuit, and the sixth resistor is the second negative feedback circuit. One end of the sixth resistor and one end of the seventh capacitor are connected together to serve as the input terminal of the second stacked amplifier circuit and are connected to the output terminal of the first stacked amplifier circuit. The other end of the seventh capacitor is connected to the second RF resistor and the gate of the fourth transistor. The other end of the second RF resistor is connected to the positive terminal of the second bias voltage, and the negative terminal of the second bias voltage is grounded. The source of the fourth transistor is grounded, and the drain of the fourth transistor is connected to the source of the fifth transistor. The drain of the fifth transistor is connected to the source of the sixth transistor. The gate of the fifth transistor is connected to one end of the ninth capacitor, one end of the eighth resistor, and one end of the ninth resistor. The other ends of the ninth capacitor and the ninth resistor are both grounded. The other end of the eighth resistor is connected to one end of the seventh resistor, one end of the eighth capacitor, and the gate of the sixth transistor. The other end of the eighth capacitor is grounded. The drain of the sixth transistor, the other end of the sixth resistor, the other end of the seventh resistor, and one end of the second choke inductor are connected together to serve as the output terminal of the second stacked amplifier circuit and are connected to the input terminal of the output impedance matching network. The other end of the second choke inductor is connected to the power supply voltage.

6. The stacked broadband RF amplifier according to claim 5, characterized in that, The fourth, fifth, and sixth transistors in the second stacked amplifier circuit are of the same size.

7. The stacked broadband RF amplifier according to claim 1 or 2, characterized in that, The output impedance matching network includes a tenth resistor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, and a second inductor. One end of the tenth resistor and one end of the tenth capacitor are connected together and then used as the input terminal of the output impedance matching network and connected to the output terminal of the second stacked amplifier circuit. The other ends of the tenth resistor and the tenth capacitor are both connected to one end of the eleventh capacitor. The other end of the eleventh capacitor is connected to one end of the twelfth capacitor and one end of the second inductor, respectively. The other end of the second inductor is grounded, and the other end of the twelfth capacitor is connected to the radio frequency signal output terminal.

8. A wireless transceiver circuit, characterized in that, Includes the stacked broadband RF amplifier as described in any one of claims 1 to 7.

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