A new packaging structure of photoelectric co-sealing based on glass core carrier board
Patent Information
- Application Number
- CN202521986677.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-16
- Publication Date
- 2026-09-11
- Estimated Expiration
- 2035-09-16
AI Technical Summary
[0004]本实用新型的目的在于提供一种基于玻璃芯载板的光电共封新封装结构，旨在解决现有技术中光源和光子芯片距离数字芯片通常较远，在整个信号链路中，铜的互联距离太长，在低频率和数据带宽的情况下，数据损耗和能耗尚可接受，当数据传输速率高达3.2Tbps时，能耗和数据延迟严重影响数据中心的运算速度；这种长距离的铜线传输导致信号损耗和延迟较大，无法满足高速数据传输的需求，限制了半导体设备性能的进一步提升的技术问题
[0010]本实用新型的一种基于玻璃芯载板的光电共封新封装结构，所述玻璃芯基板采用双层结构，通过垂直互联技术缩短了水平铜互联距离；所述硅基芯片贴装于所述玻璃芯基板上并通过所述铜凸块与光子芯片、光源实现高效连接，同时所述基板介质层通过曝光显影电镀工艺精确制作，减少了信号传输路径中的损耗；所述光子芯片和所述光源直接集成于所述第二玻璃芯上，进一步缩短了与数字芯片的物理距离，配合所述ABF材料的压合连接工艺，显著提升了信号传输效率并降低了能耗，从而满足了高速数据传输需求，推动了半导体设备性能的进一步提升。
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Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a novel optoelectronic co-packaging structure based on a glass core substrate. Background Technology
[0002] In the field of semiconductor packaging, existing FCBGA technology has driven the development of semiconductor packaging to a certain extent. This technology enables chip packaging and connection, providing basic support for the normal operation of electronic devices. In some application scenarios where data transmission rate requirements are not high, FCBGA technology can meet basic signal transmission needs. Moreover, its technology is relatively mature, its manufacturing process is relatively stable, and it has been widely used in the market, making a certain contribution to the development of the semiconductor industry.
[0003] However, in existing technologies, the light source and photonic chip are usually far from the digital chip. In the entire signal link, the interconnect distance of copper is too long. At low frequencies and data bandwidths, data loss and energy consumption are acceptable. However, when the data transmission rate is as high as 3.2Tbps, energy consumption and data latency seriously affect the computing speed of data centers. This long-distance copper wire transmission results in large signal loss and latency, which cannot meet the needs of high-speed data transmission and limits the further improvement of semiconductor device performance. Utility Model Content
[0004] The purpose of this invention is to provide a novel optoelectronic co-packaging structure based on a glass core substrate. This addresses the problem that in existing technologies, the distance between the light source and photonic chip and the digital chip is typically far, resulting in excessively long copper interconnect distances throughout the signal chain. While data loss and energy consumption are acceptable at low frequencies and data bandwidths, they become severely impacted by data transmission rates as high as 3.2Tbps, significantly affecting the processing speed of data centers. This long-distance copper wire transmission leads to significant signal loss and delay, failing to meet the demands of high-speed data transmission and limiting further improvements in semiconductor device performance.
[0005] To achieve the above objectives, this utility model employs a novel optoelectronic co-packaging structure based on a glass core substrate, comprising a glass core substrate, a silicon-based chip, a photonic chip, a light source, a substrate dielectric layer, copper bumps, and ABF material. The glass core substrate has a double-layer structure. The silicon-based chip is fixed to the glass core substrate by mounting and bottom filling, and is located on the glass core substrate, and is also connected to the copper bumps. The photonic chip and the light source are both disposed on the glass core substrate. The substrate dielectric layer is distributed at corresponding positions on the glass core substrate. The silicon-based chip, the photonic chip, and the copper bumps are connected by pressing together with ABF material.
[0006] The glass core substrate has a double-layer structure consisting of a first glass core and a second glass core. The first glass core and the second glass core are connected by pressing, and the photonic chip and the light source are both disposed on the second glass core.
[0007] The first glass core has multiple first through holes, and the second glass core has multiple second through holes.
[0008] The substrate dielectric layer comprises a first substrate dielectric layer, a second substrate dielectric layer, a third substrate dielectric layer, and a fourth substrate dielectric layer.
[0009] The first substrate dielectric layer, the second substrate dielectric layer, the third substrate dielectric layer and the fourth substrate dielectric layer are connected by an exposure, development and electroplating process.
[0010] This invention discloses a novel optoelectronic co-packaging structure based on a glass core substrate. The glass core substrate employs a double-layer structure, shortening the horizontal copper interconnect distance through vertical interconnect technology. The silicon-based chip is mounted on the glass core substrate and efficiently connected to the photonic chip and light source through copper bumps. Simultaneously, the substrate dielectric layer is precisely fabricated using an exposure, development, and electroplating process, reducing losses in the signal transmission path. The photonic chip and the light source are directly integrated onto the second glass core, further shortening the physical distance to the digital chip. Combined with the ABF material pressing and connection process, this significantly improves signal transmission efficiency and reduces energy consumption, thereby meeting the requirements of high-speed data transmission and promoting further performance improvements in semiconductor devices. Attached Figure Description
[0011] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0012] Figure 1 This is a schematic diagram of the novel optoelectronic co-encapsulation structure based on a glass core substrate according to this utility model.
[0013] 1-Glass core substrate, 2-Silicon-based chip, 3-Photonic chip, 4-Light source, 5-Substrate dielectric layer, 6-Copper bump, 7-First glass core, 8-Second glass core, 9-First through hole, 10-Second through hole, 11-First substrate dielectric layer, 12-Second substrate dielectric layer, 13-Third substrate dielectric layer, 14-Fourth substrate dielectric layer. Detailed Implementation
[0014] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this utility model, and should not be construed as limiting this utility model.
[0015] Please see Figure 1 This utility model provides a novel optoelectronic co-packaging structure based on a glass core substrate, comprising a glass core substrate 1, a silicon-based chip 2, a photonic chip 3, a light source 4, a substrate dielectric layer 5, copper bumps 6, and ABF material. The glass core substrate 1 has a double-layer structure. The silicon-based chip 2 is fixed to the glass core substrate 1 by mounting and bottom filling, and is located on the glass core substrate 1, and is also connected to the copper bumps 6. The photonic chip 3 and the light source 4 are both disposed on the glass core substrate 1. The substrate dielectric layer 5 is distributed at corresponding positions on the glass core substrate 1. The silicon-based chip 2, the photonic chip 3, and the copper bumps 6 are connected by pressing together with ABF material.
[0016] In this embodiment, by using the glass core substrate 1 as the core carrier, combined with the integrated design of the silicon-based chip 2, the photonic chip 3, and the light source 4, and the synergistic effect of the substrate dielectric layer 5, the copper bumps 6, and the ABF material, efficient interconnection between the photonic chip 3 and the digital chip is achieved. This structure not only significantly shortens the copper interconnect distance, reducing signal loss and delay, but also improves the overall structural stability and signal transmission efficiency through the pressing connection of the ABF material. This effectively solves the data loss and energy consumption problems caused by long-distance copper wire transmission in existing technologies, meeting the needs of high-speed data transmission.
[0017] Furthermore, the double-layer structure of the glass core substrate 1 consists of a first glass core 7 and a second glass core 8, which are connected by pressing. The photonic chip 3 and the light source 4 are both disposed on the second glass core 8.
[0018] In this embodiment, this design allows the photonic chip 3 and the light source 4 to be more tightly integrated on the second glass core 8, further shortening the physical distance with the silicon-based chip 2, reducing the signal transmission path, thereby significantly reducing signal loss and latency, and improving the computing speed and overall performance of the data center.
[0019] Furthermore, the first glass core 7 has a plurality of first through holes 9, and the second glass core 8 has a plurality of second through holes 10.
[0020] In this embodiment, by optimizing the layout and number of vias, signal transmission efficiency can be further improved, signal reflection and crosstalk can be reduced, thereby ensuring high-speed data transmission while improving the reliability and durability of the entire packaging structure.
[0021] Furthermore, the substrate dielectric layer 5 comprises a first substrate dielectric layer 11, a second substrate dielectric layer 12, a third substrate dielectric layer 13, and a fourth substrate dielectric layer 14.
[0022] In this embodiment, by arranging signal lines, power lines, and ground lines on different layers, signal interference and electromagnetic radiation can be effectively reduced, and signal integrity can be improved. At the same time, the multilayer dielectric layers also enhance the mechanical strength and anti-warping ability of the substrate, providing a stable physical basis for high-speed data transmission.
[0023] Furthermore, the first substrate dielectric layer 11, the second substrate dielectric layer 12, the third substrate dielectric layer 13 and the fourth substrate dielectric layer 14 are connected by an exposure, development and electroplating process.
[0024] In this embodiment, this process allows for precise control of the dielectric layer thickness and pattern, achieving high-precision substrate wiring. By optimizing exposure, development, and electroplating parameters, the adhesion and conductivity of the dielectric layer can be further improved, reducing signal loss and distortion during transmission.
[0025] In this invention, the technology solves the interconnection distance problem between the photonic chip 3, the light source 4, and the digital switching chip, improving the product's integration. It can provide a higher number of I / O pins, utilizes more space in the stacking process, integrates more chips, and results in a more powerful and highly integrated product. Furthermore, the substrate carrier is fabricated using a combination of glass core and ABF or photosensitive PI materials, improving substrate strength, integration, and warping resistance, providing favorable conditions for finer substrate wiring. Simultaneously, the low dielectric constant of the glass core substrate 1 reduces losses and improves signal and data transmission efficiency. Additionally, the double-layer glass core substrate 1 stacking structure makes the glass material more suitable for integrating photonic chips 3, light sources 4, optical waveguides, optical couplers, and other devices. It can serve as an assembly carrier for individual components or as an integration carrier for heterogeneous integrated optical engines (OEs), offering greater process flexibility. Finally, this design offers flexible and highly compatible processes, allowing for assembly using existing PoP packaging technology or ABF embedding methods, providing greater process flexibility and facilitating packaging.
[0026] The above-disclosed embodiments are merely preferred embodiments of the present utility model and should not be construed as limiting the scope of the present utility model. Those skilled in the art can understand that implementing all or part of the above-described embodiments and making equivalent changes in accordance with the claims of the present utility model are still within the scope of the utility model.
Claims
1. A novel optoelectronic co-encapsulation structure based on a glass core substrate, characterized in that, The device includes a glass core substrate, a silicon-based chip, a photonic chip, a light source, a substrate dielectric layer, copper bumps, and ABF material. The glass core substrate has a double-layer structure. The silicon-based chip is fixed to the glass core substrate by mounting and bottom filling, and is located on the glass core substrate and connected to the copper bumps. The photonic chip and the light source are both disposed on the glass core substrate. The substrate dielectric layer is distributed at corresponding positions on the glass core substrate. The silicon-based chip, the photonic chip, and the copper bumps are bonded together by ABF material.
2. The novel optoelectronic co-encapsulation structure based on a glass core substrate as described in claim 1, characterized in that, The glass core substrate has a double-layer structure consisting of a first glass core and a second glass core. The first glass core and the second glass core are connected by pressing, and the photonic chip and the light source are both disposed on the second glass core.
3. The novel optoelectronic co-encapsulation structure based on a glass core substrate as described in claim 2, characterized in that, The first glass core has multiple first through holes, and the second glass core has multiple second through holes.
4. The novel optoelectronic co-encapsulation structure based on a glass core substrate as described in claim 3, characterized in that, The substrate dielectric layer comprises a first substrate dielectric layer, a second substrate dielectric layer, a third substrate dielectric layer, and a fourth substrate dielectric layer.
5. The novel optoelectronic co-encapsulation structure based on a glass core substrate as described in claim 4, characterized in that, The first substrate dielectric layer, the second substrate dielectric layer, the third substrate dielectric layer and the fourth substrate dielectric layer are connected by an exposure, development and electroplating process.