Procedure for processing a carrier

Abstract

Method (100) for processing a carrier, comprising the following steps: forming several structural elements over and / or in a support, wherein at least two adjacent structural elements have a first distance between them (110), Deposition of a first layer comprising an electrically conductive material over the multiple structural elements, wherein the first layer has a thickness equal to the first distance between the at least two adjacent structural elements (120), Forming at least one additional layer over the first layer, wherein the at least one additional layer covers an exposed area of ​​the first layer (130), wherein the formation of the at least one additional layer (130) comprises the formation of at least one second layer over the first layer, and wherein the formation of the at least one second layer comprises growing the at least one second layer using high-temperature oxidation of the first layer, removing an area of ​​the at least one additional layer to partially expose the first layer (140), and Partial removal of the first layer, whereby at least one side wall of at least two adjacent structural elements is partially exposed (150).

Description

[0001] Various embodiments generally relate to a method for processing a carrier.

[0002] The fabrication of an integrated circuit, chip, or single chip, or the processing of a substrate, may involve at least one etching process to create the desired shape of a structural element. While employing an etching process such as plasma etching or reactive plasma etching offers many advantages, it can be problematic due to charging mechanisms (charging effects), such as microcharging or aspect ratio-dependent etching. This can result in a hole (or recess) in an integrated circuit on a substrate with a larger open area ultimately having a greater depth than another hole (or recess) with a smaller open area, even though the same etching process is used for both.Therefore, the distance between adjacent structural elements on a wafer and the dimensions of a structural element can influence the etch rate during an etching process.

[0003] US 2004 / 262676 A1 discloses a method for manufacturing fin-field effect transistors. US 2011 / 068401 A1 discloses a semiconductor device comprising a substrate and a plurality of fins. US 2008 / 073723 A1 discloses a device and a method for manufacturing a working-function metal-gate electrode.

[0004] Methods for machining a carrier according to claims 1, 2 and 11 are provided. Further embodiments are described in the dependent claims.

[0005] A method for processing a carrier according to one or more embodiments may comprise the following steps: forming several structural elements over and / or in a carrier, wherein at least two adjacent structural elements have a first distance between them; depositing a first layer over the several structural elements, wherein the first layer has a thickness equal to the first distance between the at least two adjacent structural elements; forming at least one additional layer over the first layer, wherein the at least one additional layer covers an exposed area of ​​the first layer; removing an area of ​​the at least one additional layer to partially expose the first layer; and partially removing the first layer, wherein at least one side wall of the at least two adjacent structural elements is partially exposed.

[0006] In one embodiment, at least two adjacent structural elements of the multiple structural elements can have a distance between them that is greater than twice the first distance. In yet another embodiment, the multiple structural elements can comprise at least one electrically insulating layer on a surface of at least one of the multiple structural elements. In yet another embodiment, the at least one electrically insulating layer can have an oxide layer. In yet another embodiment, at least one of the multiple structural elements can have the shape of a fin. In yet another embodiment, at least one of the multiple structural elements can be part of a FinFET. In yet another embodiment, the deposition of the first layer over the multiple structural elements can be conformal deposition of the first layer over the multiple structural elements.

[0007] In yet another embodiment, the first layer can comprise an electrically conductive material. In yet another embodiment, the first layer can comprise electrically conductive polycrystalline silicon. In yet another embodiment, the formation of the at least one additional layer can comprise the deposition of at least one layer using a conformal deposition process. In yet another embodiment, the formation of the at least one additional layer can comprise the growth of at least one layer using high-temperature oxidation. In yet another embodiment, the at least one additional layer can comprise a material that is different from a material of the first layer.In yet another embodiment, the formation of at least one additional layer can have the following characteristics: Forming at least one second layer above the first layer, wherein the second layer fills any remaining space between adjacent structural elements of the multiple structural elements.

[0008] In various embodiments, a method for processing a carrier is provided, comprising the following steps: forming several structural elements over and / or in a carrier, wherein at least two adjacent structural elements have a first distance between them; depositing a first layer over the several structural elements, wherein the first layer has a thickness that is less than half the first distance between the at least two adjacent structural elements; forming at least one additional layer over the first layer, wherein the at least one additional layer covers an exposed area of ​​the first layer; removing an area of ​​the at least one additional layer to partially expose the first layer; and partially removing the first layer, wherein at least one side wall of the at least two adjacent structural elements is partially exposed.

[0009] In one embodiment, at least two adjacent structural elements of the multiple structural elements can have a distance between them that is greater than the first distance. In yet another embodiment, the multiple structural elements can comprise at least one electrically insulating layer on a surface of at least one of the multiple structural elements. In yet another embodiment, the at least one electrically insulating layer can have an oxide layer. In yet another embodiment, at least one of the multiple structural elements can have the shape of a fin. In yet another embodiment, at least one of the multiple structural elements can be part of a FinFET. In yet another embodiment, the deposition of the first layer over the multiple structural elements can be conformal deposition of the first layer over the multiple structural elements.In yet another embodiment, the first layer can comprise an electrically conductive material. In yet another embodiment, the formation of the at least one additional layer can comprise the deposition of at least one layer using a conformal deposition process. In yet another embodiment, the formation of the at least one additional layer can comprise the growth of at least one layer using high-temperature oxidation. In yet another embodiment, the at least one additional layer can comprise a material that is different from a material of the first layer.In yet another embodiment, the formation of the at least one additional layer can include: forming a second layer above the first layer and forming a third layer above the second layer, wherein at least one of the second layer and the third layer fills a remaining space between adjacent structural elements of the multiple structural elements.

[0010] In the drawing, the same reference numerals generally denote the same parts in the different views. The drawing is not necessarily to scale; rather, the emphasis is placed on explaining the basic concepts of the invention. The following description details various embodiments of the invention with reference to the following drawing. The drawing shows: Fig. 1 a flowchart of a process 100 for processing a carrier according to different embodiments, Fig. 2 a flowchart of a process 200 for processing a carrier according to different embodiments, the Fig. 3A to 3H each represent a cross-section of a carrier at different processing stages with reference to method 100 according to different embodiments, the Fig. 4A and Fig. 4B each a cross-section of a carrier at different processing stages with reference to method 200 according to different embodiments, the Fig. 5A and Fig. 5B each a cross-section of a carrier at different processing stages with reference to method 100 according to different embodiments, the Fig. 6A and Fig. 6B each a cross-section of a carrier at different processing stages with reference to method 200 according to different embodiments, the Fig. 7A and Fig. 7B each a cross-section of a carrier at different processing stages with reference to method 200 according to different embodiments, Fig. 8 a top view and a cross-section of a beam with multiple holes according to various embodiments and Fig. 9 a top view and a cross-section of a beam with several recesses according to different embodiments.

[0011] The following detailed description relates to the attached drawing, in which specific details and embodiments in which the invention can be implemented are shown for clarification.

[0012] The phrase "serving as an example" here means "serving as an example, a case, or an illustration." All embodiments or designs described here as "serving as examples" should not necessarily be interpreted as being preferable or advantageous over other embodiments or designs.

[0013] The word "over" used here in reference to deposited material formed "over" a side or surface can be used to indicate that the deposited material may be formed "directly on" the side or surface in question, for example, in direct contact with it. The word "over" used here in reference to deposited material formed "over" a side or surface can also be used to indicate that the deposited material may be formed "indirectly on" the side or surface in question, with one or more additional layers arranged between the side or surface in question and the deposited material.

[0014] The term "lateral," used in reference to the lateral dimension of a structure (or the lateral dimension of a structural element), can be used here to denote a dimension along a direction parallel to the surface of a support. This means that the surface of a support (for example, the surface of a substrate or the surface of a wafer) can serve as a reference. Furthermore, the term "width," used in reference to the width of a structure (or the width of a structural element), can be used here to denote the lateral dimension of a structure (or the lateral extent of a structural element). Similarly, the term "height," used in reference to the height of a structure (or the height of a structural element), can be used here to denote the dimension of a structure (or a structural element) along a direction perpendicular to the surface of a support.

[0015] The word "covering," used here in reference to a deposited material covering a structure (or structural element), can indicate that a deposited material can completely cover a structure (or structural element), for example, covering all exposed sides and surfaces of a structure (or structural element). The word "covering," used here in reference to a deposited material covering a structure (or structural element), can also indicate that the deposited material can at least partially cover a structure (or structural element), for example, at least partially covering the exposed sides and surfaces of a structure (or structural element).

[0016] According to various embodiments, the formation of a layer (for example, the deposition of a layer, for example, the deposition of a material, for example, using a layer formation process), as described herein, can also include the formation of a layer in which the layer may have different sublayers, wherein the different sublayers may each have different materials. In other words, several different sublayers can be incorporated into a layer, or several different regions can be incorporated into a deposited layer or material.

[0017] Because there can be many individual processes used in semiconductor processing (for example, in the fabrication of an integrated circuit, a chip, or a single chip, or in the processing of a carrier, substrate, or wafer), which are usually performed in a sequence, several basic fabrication techniques can be used at least once in the overall process. The following description of basic techniques should be understood as illustrative examples, and these techniques can be incorporated into processes described subsequently. The basic techniques described here as examples need not necessarily be considered preferred or advantageous over other techniques or methods, because they only serve to illustrate how one or more embodiments of the invention can be realized.For the sake of brevity, the explanation of the basic techniques described here as examples is only a brief overview and should not be considered an exhaustive description.

[0018] According to various embodiments, the specific depth of an etched recess or the specific height of a structural element in an integrated circuit can be relevant to the functionality of the structural element. Typically, a feature (for example, an opening, such as a hole or a recess) with a larger open area can be etched faster during an etching process (for example, during reactive plasma etching) than a feature with a smaller open area. In other words, a larger open area during an etching process can produce a larger recess (or a deeper recess) than a smaller open area.Therefore, if the respective distances between several adjacent structural elements differ from one another, for example as a result of the specific design or layout of the integrated circuit, so that even two open areas can differ from one another, an etching process can produce different etching results depending on the environment of an individual structural element.

[0019] The use of an etching process during the structuring of a structural element (for example, plasma etching) can therefore cause several problems because the etch rate can depend on the environment of the structural element. For example, the height of a control gate on a side wall of a fin, as described below in various embodiments, can deviate from the specific desired value due to charging effects during plasma etching of the gate material. Therefore, the electrical properties of a fin field-effect transistor (FinFET) may not be as desired, and the operational capability of the FinFET may be affected.

[0020] According to various embodiments, the method for processing a substrate can provide a homogeneous (e.g., symmetrical) environment (with respect to an etching process) for each structural element of several structural elements, even if the distance between adjacent structural elements (e.g., fins) cannot be the same for all structural elements on a substrate, so that charging effects during at least one processing stage can be avoided or significantly reduced.

[0021] According to various embodiments, one or more of the following basic techniques can be incorporated into the process for processing a carrier.

[0022] Layer deposition is one of the techniques used in semiconductor processing. In a layer deposition process, a layer (or a layer-forming material) can be deposited over a surface (for example, over a support, a wafer, a substrate, another layer, or the like) according to various embodiments using deposition techniques that may include chemical vapor deposition (CVD or a CVD process) and physical vapor deposition (PVD or a PVD process). According to different embodiments, the thickness of a deposited layer can range from a few nanometers to several micrometers, depending on the specific function of the layer.Furthermore, according to various embodiments, a layer can comprise at least one electrically insulating material, one electrically semiconducting material, and one electrically conductive material, depending on the specific function of the layer. According to various embodiments, electrically conductive materials, such as aluminum, aluminum-silicon alloys, aluminum-copper alloys, nichrome (an alloy of nickel, chromium, and / or iron), tungsten, titanium, molybdenum, or gold (or the like), can be deposited using CVD or PVD.According to various embodiments, semiconducting materials such as silicon (e.g., epitaxially grown silicon or polycrystalline silicon (also known as polysilicon)), germanium, and semiconductor compound materials such as gallium arsenide (GaAs), indium phosphide (InP), or indium gallium arsenide (InGaAs) can be deposited using CVD. Insulating materials such as silicon oxide or silicon nitride (or the like) can be deposited using CVD or PVD. Modifications of these processes can be used according to various embodiments, as described below.

[0023] According to various embodiments, a chemical vapor deposition (CVD) process can include a variety of modifications, such as atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), ultra-high vacuum CVD (UHVCVD), plasma-enhanced CVD (PECVD), high-density plasma CVD (HDPCVD), remote plasma-enhanced CVD (RPECVD), atomic layer CVD (ALCVD), vapor phase epitaxy (VPE), metal-organic CVD (MOCVD), hybrid physical CVD (HPCVD), and the like. According to various embodiments, polysilicon, silicon dioxide, silicon nitride, and the like can be deposited using LPCVD; however, molybdenum, tantalum, titanium, nickel, tungsten, and the like can also be deposited using LPCVD.

[0024] According to various embodiments, physical vapor deposition can include a variety of modifications, such as magnetron sputtering, ion beam sputtering (IBS), reactive sputtering, high-intensity pulse magnetron sputtering (HIPIMS), vacuum evaporation, molecular beam epitaxy (MBE), and the like.

[0025] According to various embodiments, a layer formation process can also include thermal oxidation (also referred to as a thermal oxidation process). In various embodiments, thermal oxidation can be used to grow high-quality silicon oxide layers (so-called high-temperature oxide layers (HTO)) on a silicon surface, for example, at temperatures in the range of approximately 800 °C to approximately 1200 °C. Thermal oxidation can be carried out at atmospheric pressure or at high pressure, and as a further development, as a rapid thermal oxidation process (RTO).According to various embodiments, thermal nitriding can also be used to produce high-quality nitride or oxynitride layers (for example, silicon nitride layers or silicon oxynitride layers), for example, using rapid thermal nitriding (for example, at temperatures up to about 1300 °C).

[0026] It should be noted that a wide variety of material and process combinations can be used within a layer formation process according to different embodiments. Depending on specific aspects, such as crystal quality, surface roughness, edge coverage behavior, growth rate, and yield, the most suitable process for the respective material can be applied according to different embodiments.

[0027] According to various embodiments, some processes during the processing of a substrate may require a conformally deposited layer or the conformal deposition of a layer (for example, forming a conformal layer over multiple structural elements, such as forming a conformal layer over multiple fins), which means that a layer (or a material forming a layer) along an interface with another body may exhibit only small thickness variations, such as small thickness variations along edges, steps, and / or other elements of the interface morphology. According to various embodiments, layer formation processes such as electroplating, atomic layer deposition (ALD), or several CVD processes (for example, ALCVD or LPCVD) may be suitable for producing a conformal layer or a conformally deposited layer from a material.In other words, a conformal deposition process can exhibit high edge coverage. Depending on various embodiments, the growth of a high-temperature oxide layer (for example, using an RTA process) on a silicon surface can be considered a conformal deposition process, or more precisely, a conformal growth of a high-temperature oxide layer.

[0028] Furthermore, according to various embodiments, a conformal deposition of a layer or a conformal growth of a high-temperature oxide layer can completely fill a recess or trench if the width of the recess or trench is less than twice the thickness of the conformal layer. According to various embodiments, a recess or trench can be partially filled with material from a conformally deposited layer or a conformally grown high-temperature oxide layer if the thickness of the conformal layer is less than half the width of the recess or trench.According to various embodiments, if a recess or trench is partially filled with material from a conformally deposited layer or a conformally grown high-temperature oxide layer, a residual space can be created within the recess or trench, or a residual space can be created between the respective side walls of the at least two adjacent structural elements forming the recess or trench. According to various embodiments, if an area between two adjacent structural elements is partially filled with material from a conformally deposited layer or a conformally grown high-temperature oxide layer, a residual space can be created in the area between the two adjacent structural elements.More precisely, a residual space can be free of any material deposited in a previous process (for example, the residual space can be free of any material that may have been deposited previously during the formation of several structural elements and during the deposition of a material over the several structural elements).

[0029] Structuring is another technique used in semiconductor processing. Depending on the specific implementation, a structuring process can involve removing selected areas of a surface layer or material. After a surface layer has been partially removed, a pattern (or structured layer or surface layer) may remain over the underlying structure (for example, a structural pattern may remain on a wafer).Because several processes may be involved, there are several ways to perform a structuring process according to different embodiments, with aspects that may include: selecting at least one area of ​​a surface layer (or material) to be removed, for example using at least one lithography process, and removing the at least one selected area of ​​the surface layer, for example using at least one etching process.

[0030] According to various embodiments, a variety of lithographic processes can be used to produce a lithographic mask (a so-called photomask), such as photolithography, microlithography or nanolithography, electron beam lithography, X-ray lithography, extreme ultraviolet lithography (EUV or EUVL), interference lithography, and the like. According to various embodiments, a lithographic process can comprise at least one of the following steps: an initial cleaning process, a preparation process, the application of a resist (for example, a photoresist), exposure of the resist (for example, exposure of the photoresist with a light pattern), and development of the resist (for example, development of the photoresist using a chemical photoresist developer).

[0031] According to various embodiments, an initial cleaning process, or a cleaning process that may be incorporated into a lithographic process (or that may be incorporated into a general process in semiconductor processing), can be applied to the removal of organic or inorganic contaminants (or material) from a surface (for example, from a surface layer, from a support, from a wafer, and the like), for example, by wet chemical treatment.According to various embodiments, the initial cleaning process or a cleaning process may include at least one of the following: RCA (Radio Corporation of America) cleaning (also known as organic cleaning (SC1) and ionic cleaning (SC2)), SCROD (single-wafer centrifugal cleaning with repeated use of ozonated water and dilute HF), IMEC wafer cleaning, a post-chemical-mechanical polishing (post-CMP) cleaning process, cleaning by deionized water (DIW), piranha etching, and / or metal etching (and the like). According to various embodiments, a cleaning process may also be used to remove a thin oxide layer (for example, a thin silicon oxide layer) from a surface (for example, a surface layer, a substrate, or a wafer, and the like).

[0032] According to various embodiments, a preparation process, which may be incorporated into a lithographic process, can be used to promote the adhesion of a photoresist to a surface (for example, a surface layer, a support, a wafer, and the like). According to various embodiments, the preparation process may involve the application of a liquid or gaseous adhesion promoter (for example, bis(trimethylsilyl)amine (HMDS)).

[0033] According to various embodiments, a resist, which may be incorporated into a lithographic process, can be applied to homogeneously cover a surface (for example, a surface layer, a substrate, or a wafer, and the like). According to various embodiments, the application of a resist may include centrifugal coating to produce a thin, homogeneous layer of the resist. Subsequently, according to various embodiments, the resist may be preheated to drive off excess resist solvent. According to various embodiments, several types of resist (for example, a photoresist) may be used, adapted to the resist exposure process to achieve desired results.According to various embodiments, positive photoresists (e.g., DNQ-Novolac, PMMA, PMIPK, PBS and the like) can be used, wherein the resist, when exposed to light, becomes soluble for a photoresist developer, and / or negative photoresists (e.g., SU-8, polyisoprene, COP and the like) can be used, wherein the resist, when exposed to light, becomes insoluble for a photoresist developer.

[0034] According to various embodiments, a resist can be exposed (for example, by subjecting the photoresist to a light pattern), which can then be incorporated into a lithographic process to transfer a desired pattern onto the resist, for example, using light or electrons, where the desired pattern can be defined by a structured mask (for example, a glass substrate with a structured chromium layer). According to various embodiments, maskless lithography can be used, where a precise beam (for example, an electron beam or a laser beam) can be projected directly onto the surface containing the resist without the use of a mask.According to various embodiments, exposure to light can induce a reaction in the resist that allows a portion of the resist to be removed by a special solution (a so-called developer, for example, a photoresist developer). Because the resolution of an optical imaging process is limited by the wavelength used, the wavelength of the light used can, according to various embodiments, range from the wavelength of visible light to a shorter wavelength in the ultraviolet range. According to various embodiments, exposure can be carried out using X-rays or electrons with an even shorter wavelength than ultraviolet light.According to various embodiments, projection exposure systems (for example, steppers or scanners) can be used which project the mask many times onto a surface having a resist in order to create the complete exposure pattern.

[0035] In various embodiments, a resist can be developed (for example, by developing the photoresist using a photoresist developer) and then incorporated into a lithographic process to partially remove the resist, thereby creating a structured resist layer that remains on the surface (for example, on a surface layer or on a support, wafer, and the like). In various embodiments, the development of a resist can include a post-exposure bake-out (a heat treatment, for example, rapid thermal processing) before the actual development process can be carried out. In various embodiments, a development process can use a special chemical solution (called a developer), such as sodium hydroxide or tetramethylammonium hydroxide (TMAH, a metal-ion-free developer).According to various embodiments, a residual structured resist can be solidified in a hard heating process (heat treatment, for example, rapid thermal processing), thereby creating a more durable protective layer for subsequent processes such as ion implantation, wet chemical etching or plasma etching (and the like).

[0036] Regardless of the lithographic processes described, a resist can be completely removed at a desired processing stage (for example, after at least one etching, ion implantation, and deposition process) in a so-called resist removal process. According to various embodiments, a resist can be removed chemically and / or using an oxygen plasma.

[0037] It should be noted that a lithographic process according to various embodiments, including the application of a resist, the exposure of a resist, and the development of a resist, can also be considered a structuring process, wherein a structured resist layer (a soft mask or a resist mask) can be produced by the lithographic process. Furthermore, according to various embodiments, a pattern can subsequently be transferred from a structured resist layer to a previously deposited or grown layer (or a support, etc.) following the use of an etching process, wherein the previously deposited or grown layer may comprise a hard mask material, such as an oxide or a nitride (e.g., silicon oxide, for example, silicon nitride), to produce a so-called hard mask.

[0038] According to various embodiments, an etching process, which may be incorporated into a structuring process, can be used to remove material from a previously deposited layer, a grown surface layer, a support (or a substrate or wafer), and the like. According to various embodiments, an etching process can be performed depending on the specific requirements for this process. According to various embodiments, an etching process can be selective or non-selective with respect to a specific material.According to various embodiments, an etching process can be isotropic or anisotropic, wherein an anisotropic etching process (for example, an anisotropic wet etching process) can have a different etch rate along a respective crystallographic direction of a specific material, or wherein an anisotropic etching process (for example, an anisotropic dry etching process) can have a different etch rate for surfaces with a specific geometric orientation.

[0039] Depending on the specific embodiment, a dry etching process can be used, such as plasma etching, ion beam etching or reactive ion etching (RIE).

[0040] Plasma etching generates charged ions, neutral atoms, and / or radicals. During the plasma etching process, chemical reactions between the elements of the etched material and the reactive species generated by the plasma can produce volatile etch products (for example, etch products that are volatile at room temperature). Therefore, a plasma etching process can be isotropic according to various embodiments and, depending on the gaseous plasma etchants used and the materials involved, highly selective, partially selective, or non-selective.According to various embodiments, silicon can be etched using plasma etchants such as CF4, SF6, NF3, or Cl2, and silicon dioxide can be etched using plasma etchants such as CF4, SF6, or NF3. The plasma etching process can be selective for silicon (for example, using Cl2 as the plasma etchant), and the plasma etching process can be non-selective for silicon and silicon dioxide (for example, using CF4, SF6, or NF3 as the plasma etchant). According to various embodiments, the plasma etching process can be selective for silicon dioxide. According to various embodiments, the plasma etching process can be selective for silicon.

[0041] In various embodiments, a physical etching process (for example, ion beam etching or sputtering etching) can be used, wherein a material is bombarded with energetic ions of noble gases (for example, argon ions), atoms being removed from the bombarded material by the transferred momentum. In various embodiments, the ions can approach a material from approximately one direction, and the ion beam etching can therefore be highly anisotropic, and because no chemical reaction can be involved, ion etching is usually non-selective.

[0042] In various embodiments, a reactive ion etching (RIE) process can be employed. In these embodiments, the ions can react chemically with a material, or, alternatively, remove atoms from the surface of a material through the transferred momentum (sputtering). Depending on the etchants and the materials involved, the RIE can be designed to be selective or non-selective for specific materials. In some embodiments, reactive ion etching can be an anisotropic process due to the predominantly vertical supply of reactive ions. The etching conditions in an RIE system can depend on process parameters such as pressure, gas flow, and radio frequency (RF) power.Furthermore, the etching conditions during a RIE process can depend on the aspect ratio of the structure to be etched due to so-called charging effects (e.g., aspect ratio-dependent etching (ARDE)) and on the distance between structural elements to be etched due to so-called microcharging.

[0043] Furthermore, according to various embodiments, deep reactive ion etching (DRIE) can be used to create deep penetrations, holes, and trenches with steep sides in a material (for example, in a wafer, a substrate, a deposited or grown layer, and the like). Deep reactive ion etching is an anisotropic etching process, typically with high aspect ratios. According to various embodiments, pulsed etching (time-division multiplexed etching) can also be used. Pulsed etching is an anisotropic etching process that can be used to create structural features with high aspect ratios.

[0044] It should be noted that anisotropy in a dry etching process can arise from the anisotropic momentum of the ions (or atoms or molecules). Therefore, unlike in a wet etching process, the crystal structure may have a smaller influence on the resulting etched structures when using a dry etching process. Additionally, unlike wet etching processes, polycrystalline materials (e.g., polysilicon) exhibiting randomly oriented crystallites can be anisotropically etched, producing structures with high aspect ratios (ratio between the width and height of a structural element), for example, 1:10 or even larger, such as 1:50 or even larger.

[0045] According to various embodiments, a structured layer can also serve as a mask for other processes, such as etching, ion implantation, or layer formation (a so-called hard mask). Furthermore, according to various embodiments, a structured photoresist can also serve as a mask (a so-called soft mask). According to various embodiments, a soft mask can be used for a peel-off process. The mask material can usually be selected with respect to specific requirements, such as chemical stability, for example, to perform a selective etching process that does not affect the mask material (e.g., complete etching of the mask material) or to ensure mechanical stability, for example, to protect areas from ion penetration, or to define the shape of generated structural elements during a layer formation process, and the like.

[0046] Because the desired shapes and structural elements can be created in their exact dimensions (feature size) during a structuring process, structuring can be the most critical process in terms of feature size reduction. Errors during a structuring process can result in a distorted or misaligned pattern and therefore alter the electrical behavior of a device or integrated circuit. Errors in the depth of an etched recess or deviations in the shape of a created structural element from a desired design or layout, for example, due to charging effects during an etching process, can affect the functionality of a structural element. Therefore, the structuring process can be tailored to the specific design or layout of an integrated circuit.

[0047] According to various embodiments, heat treatment can be incorporated at different points, for example, in combination with a structuring process, such as after an ion implantation process, after the application of photoresist for solvent expulsion, or after the deposition of electrical contacts to alloy the electrically conductive material (e.g., a metal) with a support (e.g., a wafer, etc.) or to provide optimal deposition conditions for CVD processes (and the like). According to various embodiments, heating a support (a wafer, a substrate, etc.) can be carried out by direct contact, for example, a hot plate, or by radiation, for example, using a laser or lamps.According to various embodiments, rapid thermal processing (RTP) can be applied, which can be carried out under vacuum conditions using a laser heater or a lamp heater, whereby a material (for example, a wafer, a substrate, a support, and the like) can be heated to several hundred degrees Celsius or to about 1000 °C or even higher within a short period of time, for example, within several seconds (for example, about 1 s to about 10 s). Subgroups of rapid thermal processing are rapid thermal annealing (RTA) and rapid thermal oxidation (RTO).

[0048] According to various embodiments, a planarization process can be applied, for example, to reduce the surface roughness or the variations in the depth profile of a substrate or wafer surface that has structural elements of different heights, because some processes may require a flat surface (e.g., a planar surface) (e.g., high-resolution lithography). According to various embodiments, a planarization process may be necessary when the number of layering and structuring processes increases and a planar surface is required.

[0049] According to various embodiments, a chemical-mechanical polishing process (CMP or CMP process) can be performed, wherein this process can be selective for at least one specific material on the surface of a support (for example, on the main processing area of ​​a wafer or a substrate, such as a surface layer, etc.). According to various embodiments, a chemical-mechanical polishing process (CMP) can be performed, wherein this process can be non-selective for a specific material on the surface of a support (for example, on the main processing area of ​​a wafer or a substrate, such as a surface layer, etc.). According to various embodiments, a planarization process can additionally be incorporated into several processes, such as layer formation processes, structuring processes, and the like.

[0050] According to various embodiments, chemical-mechanical polishing (a CMP process) can be used to remove at least one material from a surface layer, or to remove at least one material at least partially from a surface layer (for example, from a main processing area of ​​a wafer or a substrate). According to various embodiments, chemical-mechanical polishing can be used to remove various materials from an exposed area on the surface of a support. According to various embodiments, a flat surface can be produced by at least partially removing at least one material from the surface of a support using a chemical-mechanical polishing process. According to various embodiments, the surface of the support can be a main processing area of ​​a wafer or a main processing area of ​​a substrate.According to various embodiments, the main processing area can have at least one structural element.

[0051] According to various embodiments, the support (for example, a substrate, a wafer, and the like) can consist of semiconductor materials of various types, including silicon, germanium, Group III to V, or other types, including polymers, although according to another embodiment, other suitable materials may also be used. According to one embodiment, the wafer substrate consists of silicon (doped or undoped), and according to an alternative embodiment, the wafer substrate is a silicon-on-insulator (SOI) wafer. Alternatively, any other suitable semiconductor materials may be used for the wafer substrate, such as a semiconductor compound material like gallium arsenide (GaAs) or indium phosphide (InP), but also any suitable ternary semiconductor compound material or quaternary semiconductor compound material, such as indium gallium arsenide (InGaAs).

[0052] Fig. Figure 1 shows a flowchart of a process 100 for machining a carrier according to different embodiments.Method 100 can comprise the following steps: 110 forming several structural elements over and / or in a support, wherein at least two adjacent structural elements of the several structural elements can have a first distance between them; 120 depositing a first layer over the several structural elements with a thickness equal to the first distance between the at least two adjacent structural elements; 130 forming at least one additional layer over the first layer, wherein the at least one additional layer can cover an exposed area of ​​the first layer; 140 removing an area of ​​the at least one additional layer to partially expose the first layer; and 150 partially removing the first layer, wherein at least one side wall of the at least two adjacent structural elements can be partially exposed.

[0053] Fig. Figure 2 shows a flowchart of a process 200 for processing a carrier according to different embodiments.Method 200 may comprise the following steps: 210 forming several structural elements over and / or in a support, wherein the at least two adjacent structural elements have a first distance between them; 220 depositing a first layer over the several structural elements with a thickness that is less than half the first distance between the at least two adjacent structural elements; 230 forming at least one additional layer over the first layer, wherein the at least one additional layer may cover an exposed area of ​​the first layer; 240 removing an area of ​​the at least one additional layer to partially expose the first layer; and 250 partially removing the first layer, wherein at least one side wall of the at least two adjacent structural elements may be partially exposed.

[0054] According to various embodiments, the several structural elements, as described with reference to method 100 and method 200 and in Fig. 1 and Fig. 2 shown, are provided on a main processing surface of the carrier (for example, provided above and / or in the surface of the carrier). According to various embodiments, forming multiple structural elements above the surface of the carrier can be considered equivalent to forming multiple structural elements in the surface of the carrier with respect to applying method 100 and method 200, as described below.

[0055] According to various embodiments, at least two adjacent structural elements can be separated from the multiple structural elements as described with reference to method 100 and in Fig. As shown in Figure 1, the structural elements can have a distance between them that is greater than twice the first distance. This means that in Figure 110, several structural elements can be formed, where at least two adjacent structural elements can have a first distance between them, and at least two adjacent structural elements can have a distance between them that is greater than twice the first distance.

[0056] According to various embodiments, the formation of the at least one additional layer, as described with reference to method 100 and as in Fig. Figure 1 shows the formation of at least one second layer above the first layer, wherein the second layer can fill any remaining space between adjacent structural elements of the multiple structural elements. According to various embodiments, if at least two adjacent structural elements of the multiple structural elements have a first distance between them, and at least two adjacent structural elements of the multiple structural elements have a distance between them that is greater than twice the first distance, the filling of any remaining space between adjacent structural elements of the multiple structural elements can comprise filling at least one remaining space with a first width or filling several remaining spaces, which may include remaining spaces with different widths.

[0057] According to various embodiments, at least two adjacent structural elements can be separated from the multiple structural elements as described with reference to method 200 and in Fig. As shown in Figure 2, the structural elements can have a distance between them that is greater than the first distance. This means that in Figure 210, several structural elements can be formed, where at least two adjacent structural elements can have a first distance between them, and at least two adjacent structural elements can have a distance between them that is greater than the first distance.

[0058] According to various embodiments, the formation of at least one additional layer, as described with reference to method 200 and as in Fig. Figure 2 shows the formation of a second layer over the first layer and the subsequent formation of a third layer over the second layer, wherein at least one of the second layer and one of the third layer can fill a residual space between the at least two adjacent structural elements. According to various embodiments, if at least two adjacent structural elements have a first distance between them and at least two adjacent structural elements have a distance between them that is greater than the first distance, the filling of a residual space between adjacent structural elements can comprise filling at least one residual space with a first width and filling at least one residual space with a width that is greater than the first width.

[0059] According to various embodiments, the formation of several structural elements above and / or in a support, as described in 110 with reference to method 100 and in 210 with reference to method 200, can involve the formation of several structural elements, wherein each of the several structural elements can have at least one side wall and at least one top surface. According to various embodiments, the top surfaces of the several structural elements can be parallel to each other, or they can have a small deviation from parallelism, and they can be aligned parallel to the surface of the support or have a small deviation from parallelism to the surface of the support.According to various embodiments, the side walls of the several structural elements can run parallel to each other, or they can have a small deviation from parallelism to each other, and they can be oriented perpendicular to the surface of the support or have a small deviation from being perpendicular to the surface of the support.

[0060] According to various embodiments, multiple structural elements can be formed in a carrier, for example, by removing a portion of the carrier material (for example, by structuring the carrier using at least one structuring process). Furthermore, according to various embodiments, the formation of multiple structural elements in a carrier can include a layering process, for example, a layering process that can be performed after structuring the carrier to provide the multiple structural elements within the carrier. According to various embodiments, the at least one upper surface of each of the multiple structural elements can form a common surface with the surface of the carrier.

[0061] According to various embodiments, multiple structural elements can be formed on a support, for example, using at least one layering process and at least one structuring process to provide the multiple structural elements on the support. According to various embodiments, the upper surfaces of the multiple structural elements can form a common surface.

[0062] According to various embodiments, the base surface of at least one of the several structural elements can have a rectangular shape or a small deviation from a rectangular shape (the base surface can be viewed in a plan view or in a cross-section parallel to the surface of the support). According to various embodiments, the cross-section of at least one of the several structural elements can have a rectangular shape or a small deviation from a rectangular shape. A small deviation can, as mentioned above, be, for example, a deviation in an angular range of zero to five degrees (for example, 1° to 5°, 0.1° to 2°, or in a similar range).

[0063] According to various embodiments, a structural element can be, for example, a cuboid with respect to the shape of its base and the shape of its cross-section, except for some minor differences. According to various embodiments, at least one structural element can be a fin. According to various embodiments, all of the multiple structural elements can have the same shape, for example, the shape of a fin. According to various embodiments, the multiple structural elements can include structural elements that can have different shapes. According to various embodiments, at least one of the multiple structural elements can have a different shape than another of the multiple structural elements.According to various embodiments, at least one structural element of the multiple structural elements can have a different external dimension (or size) than another structural element of the multiple structural elements.

[0064] Fig. Figure 3A schematically shows a cross-section of a support 302 at an initial processing stage according to various embodiments. According to these embodiments, the support 302 can be a silicon wafer, a silicon substrate, or a support comprising another semiconductor material, as described above. According to these embodiments, the support 302 can have a main processing surface 304, which, according to some embodiments, can be the top surface of the support 302.

[0065] As with 110 with reference to the in Fig. In the method described in 100, several structural elements can be formed above and / or in the support 302, wherein, according to various embodiments, at least two adjacent structural elements can have a first distance between them and at least two adjacent structural elements can have a distance between them that is greater than twice the first distance.

[0066] Fig. Figure 3B schematically shows a cross-section of the carrier 302, which has several structural elements (also referred to as structure 301) at a first processing stage. As in Fig. As shown in Figure 3B, the structure 301 can be formed in the support 302. According to various embodiments, the structure 301 can have several structural elements 302a - 302e (five structural elements 302a, 302b, 302c, 302d and 302e are shown as an example; however, the number of structural elements can also be less than five or greater than five, and generally any number greater than one), wherein at least two adjacent structural elements (for example, the structural elements 302a and 302b, as well as the structural elements 302d and 302a according to the embodiment shown) can have a first distance 303 between them, and at least two adjacent structural elements (for example, the structural elements 302b and 302c, as well as the structural elements 302c and 302e according to the embodiment shown) can have a distance 305 between them that is greater than twice the first distance 303.

[0067] According to various embodiments, each of the multiple structural elements 302a-302e can have a first side wall 306a, a second side wall 306b, and a top surface 306c, as illustrated by way of example for structural elements 302a and 302b. According to various embodiments, the distance between two adjacent structural elements can be the distance between the respective first and second side walls 306a, 306b of the two opposing adjacent structural elements, wherein, for example, the first distance 303 between the two adjacent structural elements 302a and 302b can be the distance between the second side wall 306b of structural element 302a and the first side wall 306a of structural element 302b.According to various embodiments, the distance 305 (for example, the distance between the second side wall 306b of the structural element 302b and the first side wall 306a of the structural element 302c) between the two adjacent structural elements 302b and 302c can be greater than twice the first distance 303 between adjacent structural elements 302a and 302b. Furthermore, according to various embodiments, the surface 304 of the support 302 can form a common surface with the respective upper surface 306c of each of the several structural elements 302a - 302e formed in the support 302.

[0068] According to various embodiments, the upper surfaces 306c of the structural elements 302a, 302b, 302c, 302d, 302e can be, as in Fig. 3B, they can run parallel to each other, or they can have a small deviation from parallelism to each other, and they can be aligned parallel to the surface 304 of the support 302 or have a small deviation from parallelism to the surface 304 of the support 302. According to various embodiments, the first and second side walls 306a, 306b of a structural element, as shown in Fig. 3B is shown, running parallel to each other, or they may have a small deviation from parallelism to each other, and they may be aligned perpendicular to the surface 304 of the support 302, or they may have a small deviation from the perpendicular position to the surface 304 of the support 302.

[0069] According to various embodiments, the cross-sectional shape of the structural elements 302a, 302b, 302c, 302d, 302e can be rectangular, or it can have a small deviation from a rectangular shape. A small deviation can, as mentioned previously, be, for example, an angular deviation in the range of zero to five degrees (for example, 1° to 5°, 0.1° to 2°, or a similar range). According to various embodiments, the structural elements 302a, 302b, 302c, 302d, 302e can be fins. According to various embodiments, all of the structural elements 302a–302e can have the same shape, for example, the shape of a fin.

[0070] According to various embodiments, the structural elements 302a-302e can be formed using one or more of the semiconductor processing techniques described above, such as layering and structuring. According to various embodiments, the structure 301 in the support 302 can be formed by removing material from the support 302 (for example, using at least one lithographic process followed by an etching process), such that the multiple structural elements 302a-302e are formed in the support 302, as shown in Fig. Figure 3B is shown. According to various embodiments, the formation of the multiple structural elements 302a - 302e (or the structure 301) can include at least one structuring process. According to various embodiments, the formation of the multiple structural elements 302a - 302e (or the structure 301) can include at least one structuring process and at least one layer formation process (for example, structuring a silicon wafer and subsequently growing a high-temperature oxide layer over the structured silicon wafer).

[0071] According to various embodiments, the structural elements 302a - 302e can comprise at least one of the following materials: silicon, silicon oxide, silicon nitride, silicon oxynitride, other semiconductor materials (for example, germanium, gallium arsenide and / or indium phosphide), or other substrate materials, for example, metal oxides and / or metal nitrides. According to various embodiments, the processes described herein may not be limited to structural elements formed from a specific support material, as described below.

[0072] According to various embodiments, multiple structural elements can be formed on a support, wherein at least one layer formation process and at least one structuring process can be used to form the multiple structural elements. According to various embodiments, the structural elements can be formed from any suitable or desired material using the at least one layer formation process (for example, depositing a silicon layer) and the at least one structuring process (for example, structuring the previously deposited silicon layer) to form the multiple structural elements. According to various embodiments, the formation of multiple structural elements on a support can lead to a structure similar to that described in Fig. The structure 301 shown in Figure 3B leads to the following, which is why the processes described here with reference to structure 301 can also be applied to a similar structure, whereby the several structural elements are formed above the support.

[0073] As above in 120 with reference to the in Fig. As described in the method 100, a first layer can be deposited over the several structural elements, wherein the first layer can have a thickness equal to the first distance between the at least two adjacent structural elements.

[0074] Fig. Figure 3C schematically shows a cross-section of the carrier 302 at a second processing stage, wherein a first layer 308 can be deposited over the multiple structural elements 302a-302e, the first layer 308 having a thickness 309 equal to the first distance 303 between the two adjacent structural elements 302a and 302b and between the two adjacent structural elements 302d and 302a, as shown. According to various embodiments, the first distance 303, and thus also the thickness of the first layer 309, can be the smallest distance between any two adjacent structural elements contained in the multiple structural elements (for example, contained in the structure 301).According to various embodiments, any two adjacent structural elements in the multiple structural elements can have either the first distance 303 or any distance greater than twice the first distance 303, for example, the distance 305.

[0075] As in Fig. As shown in 3C, the first layer 308 can cover the structure 301, which means that the lower surfaces of areas between these adjacent structural elements, which have a distance greater than twice the first distance 303 (for example, the lower surface of area 311 between adjacent structural elements 302c and 302e), can also be covered with material of the first layer 308.

[0076] According to various embodiments, the first layer 308 may not cover the lower surfaces of regions between these adjacent structural elements that are spaced more than twice the first spacing 303. For example, the lower surface of region 311 between structural elements 302c and 302e, or the first layer 308, may be partially removed from the lower surfaces in these regions, for example, in region 311 between structural elements 302c and 302e, after the first layer 308 has been deposited over the structure 301 (for example, using a structuring process). According to various embodiments, the first layer 308 may cover the second side wall 306b of structural element 302b and the first side wall 306a of structural element 302e, these regions not being electrically connected by material of the first layer 308.

[0077] According to various embodiments, the first layer 308 can be deposited using a conformal deposition process, for example CVD, LPCVD, or atomic layer deposition (for example ALCVD), as described above, such that the thickness 309 of the first layer 308 on the side walls 306a, 306b of the structural elements 302a-302e can be the same as on the top surface 306c of the structural elements 302a-302e. According to various embodiments, the first layer 308 can comprise an electrically conductive material, such as at least one of a metal, an alloy, and an electrically conductive semiconductor material (for example, aluminum, aluminum-silicon alloys, aluminum-copper alloys, nichrome (an alloy of nickel, chromium, and / or iron), tungsten, titanium, molybdenum, or gold (or the like)).According to various embodiments, the first layer 308 can comprise silicon (for example, polycrystalline silicon), for example, electrically conductive silicon (for example, doped silicon, for example, doped polycrystalline silicon). According to various embodiments, the material of the first layer 308 can be selected from a group of materials that can be selectively etched with respect to a material of the structural elements 302a - 302e incorporated into the structure 301. According to various embodiments, the material of the first layer 308 can be selected from a group of materials that can be selectively etched with respect to a surface material of the several structural elements 302a - 302e incorporated into the structure 301.

[0078] According to various embodiments, the conformal deposition of the first layer 308 can have a thickness equal to the first distance 303 between the two adjacent structural elements 302a and 302b (and also between the two adjacent structural elements 302d and 302a according to the embodiment shown), as in Fig. As shown in Figure 3C, this leads to the formation of a residual space 310 between adjacent structural elements with a distance between them greater than twice the first distance 303 (for example, between structural elements 302b and 302c with a distance 305, and also between structural elements 302c and 302e according to the illustrated embodiment). According to various embodiments, the lateral dimension of the residual space 310 can be large enough to be subsequently filled using an additional layering process. According to various embodiments, the layer thickness of the first layer 308 can be in the range of about 10 nm to about 200 nm, for example, from about 30 nm to about 150 nm, or from about 60 nm to about 120 nm, and according to one embodiment, for example, a layer thickness of about 90 nm (or, according to another embodiment, greater than 200 nm).According to various embodiments, the lateral dimension of the remaining space 310 (for example, the distance 305 minus twice the first distance 303) can be greater than 20 nm, for example in the range of about 20 nm to about 1000 nm.

[0079] As above in 130 with reference to the in Fig. In the method described in 100, at least one additional layer can be formed above the first layer, wherein the at least one additional layer can cover an exposed area of ​​the first layer, as further detailed below with reference to Fig. It is described in 3D.

[0080] Fig. Figure 3D schematically shows a cross-section of the carrier 302 at a third processing stage, where an additional layer 312 is formed over the first layer 308. Accordingly, a structure 301a can be obtained. According to various embodiments, the additional layer 312 can cover the first layer 308, as shown in Fig. The additional layer 312 is shown in 3D. According to various embodiments, the additional layer 312 can comprise an insulating material. According to various embodiments, the additional layer 312 can comprise an oxide, for example, silicon oxide. According to various embodiments, the additional layer 312 can comprise a nitride, for example, silicon nitride or titanium nitride. According to various embodiments, the additional layer 312 can comprise carbon. According to various embodiments, the material of the additional layer 312 can be selected from a group of suitable materials so that the material of the first layer 308 can be selectively etched with respect to the additional layer 312. According to various embodiments, the additional layer 312 can comprise the same material as the several structural elements 302a–302e incorporated into the structure 301.According to various embodiments, the additional layer 312 can have the same material as a surface layer of the structural elements 302a - 302e.

[0081] According to various embodiments, the additional layer 312 can be formed by a layer formation process as described above. According to various embodiments, the additional layer 312 can be deposited using CVD or PVD as described above. According to various embodiments, the additional layer 312 can be grown by thermal oxidation (for example, RTO) or thermal nitriding (for example, rapid thermal nitriding) of the first layer 308, whereby a high-temperature oxide (high-temperature silicon oxide) or a high-temperature nitride (high-temperature silicon nitride) can be formed over the first layer 308.

[0082] According to various embodiments, the additional layer 312 can fill the remaining space 310 between the two adjacent structural elements 302b and 302c, and also between the two adjacent structural elements 302c and 302e according to this embodiment. According to various embodiments, the additional layer 312 can fill a remaining space between two adjacent structural elements (for example, structural elements 302b and 302c) with a distance between them that is greater than twice the first distance 303 (for example, the distance 305 between the two adjacent structural elements 302b and 302c, wherein the distance 305 is greater than twice the first distance 303 between the two adjacent structural elements 302a and 302b).

[0083] According to various embodiments, more than one additional layer can be formed on top of the first layer 308 using more than one layer formation process. According to various embodiments, at least one of the additional layers can be formed by thermal oxidation or thermal nitriding of the first layer 308, as described above. According to various embodiments, at least one of the additional layers can be formed using a deposition process, such as a CVD process or a PVD process (for example, by depositing silicon oxide using a CVD process).

[0084] According to various embodiments, at least one of the additional layers can be formed by a conformal deposition process (e.g., LPCVD, atomic layer deposition, ALCVD) or a conformal growth process (e.g., conformal growth of a high-temperature oxide layer or conformal growth of a high-temperature nitride layer). If, for example, the remaining space between two adjacent structural elements has a small width (e.g., a width in the range of approximately 10 nm to approximately 100 nm, or between approximately 20 nm and approximately 75 nm, or in the range of approximately 20 nm to approximately 1000 nm), at least one conformal additional layer can fill the remaining space with this small width.

[0085] As above in 140 with reference to the in Fig. As described in the procedure 100, an area of ​​at least one additional layer can be removed to partially expose the first layer, as detailed below with reference to Fig. 3E is described.

[0086] Fig. Figure 3E schematically shows a cross-section of the carrier 302 at a fourth processing stage, where the additional layer 312 can be partially removed. According to various embodiments, a portion of the additional layer 312 can remain after the partial removal of the additional layer 312 (referred to as a residual portion 312a of the additional layer 312). As shown in Fig. As shown in 3E, the additional layer 312 can be added according to various embodiments by etching the surface of the Fig. The 3D-represented structure 301a can be partially removed. According to various embodiments, the additional layer 312 can be partially removed using at least one etching process (for example, reactive ion etching, for example, chemical-mechanical polishing). According to various embodiments, the at least one etching process can be selective for the additional layer 312, so that the first layer 308 cannot be etched in the same etching process, as in Fig. Figure 3E is shown. According to various embodiments, removing an area of ​​the additional layer 312 can partially expose the first layer 308. According to various embodiments, one or more areas 314 of the first layer 308 can be exposed, as shown in Fig. 3E is shown.

[0087] As above in 150 with reference to the in Fig. In the method described in section 100, the first layer can be partially removed, whereby at least one side wall of the at least two adjacent structural elements is partially exposed, as further detailed below with reference to Fig. 3F is described.

[0088] Fig. Figure 3F schematically shows a cross-section of the carrier 302 at a fifth processing stage, wherein the first layer 308 is partially removed, and the side walls 306a, 306b of the multiple structural elements 302a–302e are partially exposed. According to various embodiments, the first layer 308 can be partially removed using an etching process, such as a plasma etching process. According to various embodiments, the first layer 308 can be partially removed using reactive ion etching. According to various embodiments, the etching process that partially removes the first layer 308 can be selective for the material of the first layer 308 and the material of the additional layer 312, meaning that the structural elements 302a–302e and the remaining part 312a of the additional layer 312 cannot be etched in this process.Therefore, according to various embodiments, the height 316 of the remaining material of the first layer 308 on the side walls 306a, 306b of the structural elements 302a - 302e can be the same (or substantially the same) for each of the multiple structural elements 302a - 302e, although the distance 305 between the two adjacent structural elements 302b and 302c and between the two adjacent structural elements 302c and 302e can be greater than twice the first distance 303 between the structural elements 302a and 302b.In this regard, it should be noted that the dependence of the etch rate on the aspect ratio can be reduced or prevented by the remaining material of the additional layer 312 (for example, the remaining part 312a of the additional layer 312) between the structural elements with a distance greater than twice the first distance 303, because the actual open area for etching the first layer 308 can be defined by the layer thickness 309 of the first layer 308, which is equal to the first distance 303, as in . Fig. 3F is shown.

[0089] According to various embodiments, when the first layer 308 is etched, which partially covers the side walls 306a, 306b of the structural elements 302a - 302e, the height 316 of the remaining part of the first layer 308, in other words, the etching result, does not depend on the distance between adjacent structural elements. This means that the exposed area of ​​the side walls 306a, 306b of a structural element (for example, the exposed area 314a and 314b, as in Fig. 3F shown) for each structural element of the multiple structural elements 302a - 302e can be the same.

[0090] The following are various modifications, extensions, and details relating to the described procedure 100, as presented in Fig. 1 shown and in the Fig. 3A to 3F and the attached description are presented and described by way of example.

[0091] With reference to method 100, it should be noted that according to various embodiments, at 140 an area of ​​the at least one additional layer can be removed to partially expose the first layer. Subsequently, at 150 the first layer can be partially removed, whereby at least one side wall of the at least two adjacent structural elements is partially exposed. According to various embodiments, method 100 can also be carried out in the following modification (at 140), as shown in Fig. 3G is shown as an example.

[0092] Fig. Figure 3G shows that an area of ​​the additional layer 312 can be removed, exposing the top surface of the multiple structural elements 302a–302e. It should be noted that an area of ​​the first layer 308 at 140 can also be removed. As a result of removing an area of ​​the additional layer 312 and an area of ​​the first layer 308 (for example, using a CMP process or another suitable surface etching process), a flat surface can be formed that exposes the top surface 306c of at least one structural element (the top surface 306c of structural element 302a).

[0093] This allows, according to various embodiments, a remaining area of ​​the first layer 308 between two adjacent structural elements that have the first distance 303 between them (for example, the remaining area 308a of the first layer 308 between the two adjacent structural elements 302a and 302b, as in Fig. 3G is shown) and a remaining area of ​​the first layer 308 between a structural element and the remaining part 312a of the additional layer 312 (for example, the remaining area 308b (or 308c) of the first layer 308 between the structural element 302b (or 302c) and the remaining part 312a of the additional layer 312a between the two adjacent structural elements 302b and 302c) regardless of the distance between the adjacent structural elements (for example, the distance 303 or the distance 305, as in Fig. 3B shown) have the same width (for example, the width equal to the first spacing 303). According to various embodiments, the material of the first layer 308 (for example, the remaining areas 308a, 308b and 308c of the first layer 308), which covers the side walls 306a, 306b of the structural elements 302a - 302e (as shown in Fig. 3G shown), have an open area of ​​the same size, so that each structural element of the multiple structural elements 302a - 302e can have a similar environment despite the different distances 303, 305 between adjacent structural elements.

[0094] With reference to procedure 100, it should be noted that after removing an area of ​​at least one additional layer at 140, as in Fig. As shown in 3G and described in the attached description, the first layer at 150 can be partially removed, whereby at least one side wall of the at least two adjacent structural elements is partially exposed.

[0095] As in Fig. As shown in 3H, a selective etching process can be carried out (for example, reactive ion etching), whereby a portion of the material of the first layer 308 is removed, which, after the partial removal of the additional layer 312, as described above in connection with Fig. 3G described, between adjacent structural elements of the multiple structural elements 302a - 302e. According to various embodiments, as a result of the remaining part 312a of the additional layer 312 between the adjacent structural elements 302b and 302c, the open area for etching the first layer 308 can be the same for all structural elements of the multiple structural elements 302a - 302e (for example, the open area can be defined by the first spacing 303), as in Fig. 3H is shown.

[0096] Fig. Figure 2 shows a flowchart of a method 200 for processing a carrier according to different embodiments, wherein the method 200 for processing a carrier may be similar to the method 100 to some extent.In particular, 210 in process 200 can be carried out in the same way and have the same materials and processes as 110 in process 100, 230 in process 200 can be carried out in the same way and have the same materials and processes as 130 in process 100, 240 in process 200 can be carried out in the same way and have the same materials and processes as 140 in process 100, and 250 in process 200 can be carried out in the same way and have the same materials and processes as 150 in process 100, while 220 in process 200 can differ from 120 in process 100 and can have the deposition of a first layer over the multiple structural elements with a thickness that is less than half the first distance between the at least two adjacent structural elements, as shown.Furthermore, according to various embodiments, several structural elements (for example, those in . Fig. The structural elements 402a, 402b, 402c, 402d and 402e shown in Figure 4A are formed at 210 above and / or in a support 302, wherein at least two adjacent structural elements (for example, the two adjacent structural elements 402a and 402b) can have a first distance between them (for example, the distance shown in Figure 4A). Fig. 4A first distance 403) and at least two adjacent structural elements (for example, those shown in Fig. The two adjacent structural elements 402b and 402c shown in Figure 4A can have a distance between them that is greater than the first distance (for example, the one shown in Figure 4A). Fig. 4A (distance shown 405).

[0097] Fig. Figure 4A schematically shows a cross-section of the carrier 302 at a second processing stage, wherein a first layer 408 can be deposited over several structural elements 402a-402e (five structural elements 402a, 402b, 402c, 402d, and 402e are shown as an example; however, the number of structural elements can also be less than five or greater than five, and generally any number greater than one), wherein the first layer 408 can have a thickness 409 that is less than half the first distance 403 between the two structural elements 402a and 402b. According to various embodiments, the first distance 403 can be the smallest distance between any two adjacent structural elements contained within the several structural elements 402a-402e. In other words, any two adjacent structural elements within the several structural elements can have a distance greater than or equal to the first distance 403.

[0098] As in Fig. As shown in Figure 4A, the first layer 408 can cover the multiple structural elements 402a–402e, meaning that areas between the structural elements 402a–402e can also be covered with the material of the first layer 408 (for example, area 411). According to various embodiments, the first layer 408 can be formed analogously to 120 in process 100 in a conformal deposition process, as described above. According to various embodiments, the first layer 408 can be formed analogously to the first layer 308, as described with reference to process 100, as shown in Figure 4A. Fig. The first layer 408, as shown in Figure 4A, comprises an electrically conductive material, such as at least one of a metal, an alloy, and an electrically conductive semiconductor material (for example, aluminum, aluminum-silicon alloys, aluminum-copper alloys, nichrome (an alloy of nickel, chromium, and / or iron), tungsten, titanium, molybdenum, or gold (or the like)). According to various embodiments, the first layer 408 may comprise silicon (for example, polycrystalline silicon), for example, electrically conductive silicon (for example, doped silicon, for example, polycrystalline silicon). According to various embodiments, the material of the first layer 408 may be selected from a group of materials that can be selectively etched with respect to the material used to form the structural elements 402a-402e.According to various embodiments, the material of the first layer 408 can be selected from a group of materials which can be selectively etched with respect to a surface material by the several structural elements 402a - 402e.

[0099] According to various embodiments, the conformal deposition of the first layer 408 with a thickness less than half the first spacing 403 can be carried out as in Fig. 4A is shown, leading to the formation of a residual space 410a between two adjacent structural elements 402a and 402b with the first distance 403 between them and to the formation of a residual space 410b between two adjacent structural elements 402b and 402c with a distance 405 between them, where the distance 405 can be greater than the first distance 403.

[0100] According to various embodiments, the first spacing 403 can be in the range of about 10 nm to about 300 nm, for example about 20 nm to about 200 nm, for example about 70 nm to about 110 nm, for example about 80 nm to about 100 nm, for example about 90 nm, or for example be smaller than 90 nm or for example larger than 90 nm.

[0101] According to various embodiments, the layer thickness of the first layer 408 can be in the range of about 20 nm to 500 nm, for example from 50 nm to 200 nm, for example from 20 nm to 40 nm or in the range of about 30 nm, or for example greater than 30 nm or for example less than 30 nm.

[0102] According to various embodiments, the lateral extent of the remaining space (for example, the remaining space 410a and the remaining space 410b) between the respective two adjacent structural elements can be large enough to be filled by at least one additional layering process in a subsequently performed layering process. According to various embodiments, the lateral extent of a remaining space (for example, the remaining space 410a (first distance 403 minus twice the thickness 409 of the first layer 408) and the remaining space 410b (distance 405 minus twice the thickness 409 of the first layer 408)) can be greater than 20 nm, for example, in the range of about 20 nm to about 1000 nm.

[0103] According to various embodiments, after 220 of the method 200 has been carried out, as with reference to Fig. 4A described, 230, 240 and 250 are carried out analogously using method 100, which leads to the in Fig. The structure shown in 4B leads to this.

[0104] As in Fig. As shown in Figure 4B, the open areas for etching the first layer 408 can be defined by the thickness 409 of the first layer 408. According to various embodiments, at least one additional layer 412 can be formed above the first layer 408, which fills the remaining space between the structural elements 402a - 402e (for example, the remaining space 410a between the two adjacent structural elements 402a and 402b and the remaining space 410b between the two adjacent structural elements 402b and 402c, as shown in Figure 4B). Fig. 4A is shown). According to various embodiments, the remaining part 412a of the additional layer 412 (obtained after removing an area of ​​the additional layer 412 at 240) can fill the remaining spaces 410a and 410b.

[0105] Finally, according to various embodiments, regardless of the distance between two adjacent structural elements, material of the first layer 408 can remain between the structural elements 402a-402e and the remaining part 412a of the at least one additional layer 412. This allows the open areas of the first layer 408 to be independent of the distance between adjacent structural elements, and therefore, according to various embodiments, an etching process (for example, reactive plasma etching) for removing part of the first layer 408 to partially expose the sidewalls 406a, 406b of the multiple structural elements 402a-402e can be independent of an aspect ratio (the etching rates, for example, can be independent of the distance between two adjacent structural elements).According to various embodiments, the open area of ​​the first layer 408 can be proportional to the open width (for example, the open area 418 of the first layer 408 can be proportional to the open width (same layer thickness 409 of the first layer 408) between the structural element 402c and the remaining part 412a of the additional layer 412). According to various embodiments, after the method 200 has been carried out as described above, the remaining material of the first layer 408 can everywhere have the same (or substantially the same) height 416, regardless of the distance between adjacent structural elements, as shown in Figure 1. Fig. 4B is shown.

[0106] According to various embodiments, the method 100, as in Fig. 1 shown and with reference to the Fig. As described in 3A to 3H, the structural element comprises the formation of several structural elements, wherein a structural element may have a surface layer, the surface layer of which may be of a different material than or consist of the body of the structural element. According to various embodiments, a structural element may have the form of a fin, wherein the fin may comprise silicon and the surface layer of the fin may comprise an electrically insulating material (for example, an oxide, for example, a nitride, for example, silicon oxide, for example, silicon nitride, for example, silicon oxynitride, and the like), or the surface layer may comprise a stack of layers consisting of more than one electrically insulating layer (for example, an oxide-nitride-oxide layer stack comprising silicon oxide and silicon nitride).According to various embodiments, at least one structural element (for example, all structural elements of the several structural elements) can be formed by structuring a silicon wafer, thereby creating a silicon structure, wherein the electrically insulating surface layer can be formed by high-temperature oxidation of the silicon structure. According to various embodiments, the electrically insulating surface layer or the stack of electrically insulating surface layers can be formed using a deposition process, for example, a conformal deposition process, such as a conformal CVD process, as described above.The following figures can illustrate various modifications, extensions and details relating to the described method 100 and method 200, wherein the multiple structural elements or at least one of the multiple structural elements may have an insulating surface layer.

[0107] As in Fig. As shown in Figure 5A, the multiple structural elements 302a - 302e can, according to various embodiments, have an electrically insulating surface layer 502, wherein the surface layer 502 can be formed on the upper surface 306c of the structural elements 302a - 302e (for example, the upper surface 306c of the structural element 302c), on the side walls 306a, 306b of the structural elements 302a - 302e (for example, the side walls 306a, 306b of the structural element 302c), and in the lower regions between the structural elements 302a - 302e (for example, in the lower region 506b between the structural elements 302b and 302c). According to various embodiments, Fig. 5A shows the cross-section of several structural elements 302a - 302e (for example, several fins), including an insulating surface layer 502, wherein two adjacent structural elements (for example, two adjacent fins) can have a first distance between them (for example, the first distance 303 between structural elements 302a and 302b) and two adjacent structural elements (for example, two other adjacent fins) can have a distance between them (for example, the distance 305 between structural elements 302b and 302c) that is greater than twice the first distance (for example, the first distance 303). According to various embodiments, 130, 140 and 150 of the method 100 can then be carried out as already described above, analogously with the Fig. 3D to 3H and the attached description of a in Fig. Structure 501 shown in 5B can lead to.

[0108] According to various embodiments, the method 200, as in Fig. 2 shown and with reference to the Fig. 4A and Fig. 4B and with reference to the method described above, 100, which includes the formation of several structural elements, wherein the structural elements may have a surface layer, the surface layer being of a different material than the body of the structural element. According to various embodiments, a structural element may have the form of a fin, wherein, according to some embodiments, the fin may comprise silicon and the surface layer of the fin may comprise an electrically insulating material (for example, an oxide, for example, a nitride, for example, silicon oxide, for example, silicon nitride, for example, silicon oxynitride, and the like), or the surface layer may comprise a stack of layers of more than one electrically insulating layer (for example, an oxide-nitride-oxide layer stack comprising silicon oxide and silicon nitride).According to various embodiments, at least one structural element (for example, all structural elements of the several structural elements) can be formed by structuring a silicon wafer, thereby creating a silicon structure, wherein the electrically insulating surface layer can be formed by high-temperature oxidation of the silicon structure. According to various embodiments, the formation of the several structural elements can include at least one layer formation process (for example, the deposition of at least one layer using LPCVD or atomic layer deposition).

[0109] As in Fig. As shown in 6A, according to various embodiments an electrically insulating layer 602 can form the surface layer of several structural elements and, for example, coat the surface of the structural elements analogously with Fig. Form 5A. Fig. Figure 6A shows a cross-section of several structural elements 402a - 402e (for example, several fins) which have an insulating surface layer 602 according to various embodiments (five structural elements 402a, 402b, 402c, 402d and 402e are shown as an example, but the number of structural elements can also be less than or greater than five and generally any number greater than one).wherein at least two adjacent structural elements (for example, at least two adjacent fins) can have a first distance between them (for example, the first distance 403 between the two adjacent structural elements 402a and 402b and between the two adjacent structural elements 402d and 402a according to the illustrated embodiment) and at least two adjacent structural elements (for example, at least two adjacent fins) can have a distance between them (for example, the distance 405 between the two adjacent structural elements 402b and 402c and between the two adjacent structural elements 402c and 402e according to the illustrated embodiment) that is greater than the first distance (for example, the first distance 403). According to various embodiments, 230, 240 and 250 of method 200 can then be carried out as already described above, which is analogous to the , Fig. 4A and Fig. 4B and the Fig. 5A and Fig. 5B and the corresponding description can lead to a structure 601, as in Fig. 6B is shown.

[0110] According to various embodiments, an insulating surface layer (or an insulating surface layer stack) of the structural elements (for example, surface layer 502 or surface layer 602) can have a thickness in the range of about 1 nm to about 100 nm, for example about 2 nm to about 80 nm, for example about 5 nm to about 40 nm, for example in the range of about 5 nm.

[0111] According to various embodiments, structure 501 and structure 601, which are described in the Fig. 5B and Fig. Figure 6B shows cross-sections of a FinFET arrangement (see Figure 6B). Fig. 9).

[0112] According to various embodiments, several structural elements can have a silicon fin surrounded by a gate oxide (for example, insulating layer 502 or insulating layer 602), wherein the first electrically conductive layer (for example, the remaining regions 308a, 308b and 308c of the first layer 308, which cover the side walls 306a, 306b of the structural elements 302a - 302e, as in Fig. 3G is shown) can form the control gate of a FinFET. According to various embodiments, the height of the control gate (for example, the height 316 of the remaining material of the first layer 308 at the side walls 306a, 306b of the in Fig. 3H shown structural elements 302a - 302e or the height 416 of the remaining material of the first layer 408 on the side walls 406a, 406b of the in Fig. The electrical properties of the FinFETs (structural elements 402a - 402e) shown in Figure 4B are the same for all gates on the side walls of the multiple structural elements, regardless of the distance between two adjacent structural elements. According to various embodiments, the electrical properties of the FinFETs, which can be formed at least partially using Method 100 or Method 200 as described herein, can be the same for all FinFETs of the multiple FinFETs, regardless of the distance between two adjacent fins (for example, as a result of all FinFETs having the same gate height).According to various embodiments, the first layer (for example, the first layer 308 or the first layer 408) can be partially removed to partially expose the side walls of the multiple fins, wherein the removal of an area of ​​the first layer in regions between the adjacent fins can be carried out using an etching process, for example, reactive ion etching or plasma etching.Because, according to various embodiments, the open areas of the first layer on the side walls of the structural elements can be independent of the distance between the adjacent structural elements as a result of applying method 100 or method 200 as described herein, an etching process, such as reactive ion etching or plasma etching, can be used without the effects of the charging mechanisms that typically occur during plasma etching or reactive ion etching, or with reduced effects from these.

[0113] According to various embodiments, at 230 (or also at 130) more than one additional layer can be formed above the first layer, wherein the multiple additional layers can cover the exposed surface of the first layer. According to various embodiments, the formation of more than one additional layer can include the formation of a second layer above the first layer and subsequently the formation of a third layer above the second layer, wherein at least one of the second layer and one of the third layer can fill any remaining space between the at least two adjacent structural elements.

[0114] As in Fig. As shown in 7A, a first residual space, for example the residual space 410a between the structural elements 402a and 402b, can be found, as in Fig. 4A, is filled by a second layer 712 which covers the first layer 408, wherein, according to various embodiments, the second remaining space, for example the remaining space 410b between the structural elements 402b and 402c, as shown in Fig. 4A shows that the second layer 712 cannot be completely filled. Furthermore, after the formation of the second layer 712, there may be a remaining space that cannot be completely filled by the second layer 712 (for example, the remaining space 710, as shown in Fig. (7A shown), is filled by a third layer 714, which covers the second layer 712. According to various embodiments, the first layer 408 can be formed, for example, using a conformal deposition process, such that it has a small thickness (for example, a thickness in the range of about 10 nm to about 100 nm, or a thickness in the range of about 20 nm to about 50 nm). According to various embodiments, the second layer 712 can be formed, for example, by a CVD process (as described above), such that it has a greater thickness (for example, a thickness in the range of 100 nm to 1 µm, or a thickness in the range of about 40 nm to about 200 nm, or a thickness in the range of about 80 nm to about 160 nm, or, for example, a thickness of about 100 nm according to one embodiment (or, according to another embodiment, a thickness greater than 100 nm)).According to various embodiments, the second layer 712 can be grown by thermal oxidation of the first layer 408, for example by forming a high-temperature oxide, such as a high-temperature silicon oxide if the first layer 408 comprises silicon (for example, polycrystalline silicon). According to various embodiments, the second layer 712 and the third layer 714 can comprise an electrically insulating material. According to various embodiments, the second layer 712 and the third layer 714 can comprise an oxide layer, for example, a silicon oxide layer, or a nitride layer, for example, a silicon nitride layer.

[0115] According to various embodiments, the material or materials forming the additional layer (for example, additional layer 312, for example, additional layer 412) or the multiple additional layers, for example, the second layer (for example, second layer 712) and the third layer (for example, third layer 714), can be selected from a group of suitable materials such that the first layer (for example, first layer 308 or 408) can be selectively etched at 150 and 250, whereby the first layer can be partially removed to partially expose the sidewalls of at least two adjacent structural elements. For example, according to various embodiments, the first layer can comprise silicon and the at least one additional layer can comprise silicon oxide.According to various embodiments, the surface layer of the several structural elements (for example, the surface layer 502, for example, the surface layer 602) or the several structural elements (for example, the structural elements 302a, 302b and 302c, for example, the structural elements 402a, 402b and 402c) can have silicon oxide, so that the first layer (for example, the first layer 308 or 408) can be selectively etched with respect to the structural elements and the at least one additional layer (for example, the additional layer 312, for example, the additional layer 412, for example, the second layer 712 and the third layer 714).

[0116] According to various embodiments, the selective etching process of the first layer 408, as with reference to Fig. 7A described, analogous to the processes described above with reference to procedure 100 and procedure 200, to a in Fig. 7B shows structure 701.

[0117] Because, according to various embodiments, an opening, for example a hole, a recess or a trench, can also be commonly referred to as a structural element (for example, a multiple arrangement of holes can generate a complex structure of residual material between two respective adjacent holes), it should be noted that, in the description with reference to method 100 and method 200, an opening, for example a hole, a recess or a trench, cannot itself be considered a structural element, but rather that at least one opening, for example at least one hole, at least one recess or at least one trench, can generate at least one structural element, wherein the at least one structural element can be formed by residual material between adjacent openings, for example adjacent holes, adjacent recesses or adjacent trenches.In this case, the distance between two adjacent structural elements can be defined by the lateral dimension of an opening (for example, a hole, a recess, or a trench), and the width of a generated structural element can be defined by the distance between the respective side walls of adjacent openings (for example, holes, recesses, or trenches). According to various embodiments, the formation of multiple structural elements over and / or within a support, as included in 110, can be achieved as shown in . Fig. Figure 1 shows the creation of at least one structural element by forming an opening (for example, at least one of a hole, a trench and a recess).

[0118] According to various embodiments, the formation of several structural elements over and / or in a support, as described with reference to Method 100 and Method 200, can include the formation of several holes, as exemplified in Fig. Figure 8 is shown. According to various embodiments, it shows Fig. 8 a top view 801 and a cross-section 802 of a beam 302 with several holes 804a, 804b (two holes 804a and 804b are shown as an example, but the number of holes can also be greater than two and generally any integer greater than or equal to two) (for example at a first processing stage, such as after 110 or 210 in process 100 or in process 200, as has been described), wherein at least one hole (for example the hole 804a) can have a first diameter 803 and at least one hole (for example the hole 804b) can have a diameter 805 that is larger than the first diameter 803.

[0119] As in Fig. As shown in Figure 8, according to various embodiments, the distance between two adjacent structural elements, as described above with reference to Method 100 and Method 200, can in this case be determined by the lateral dimension of the hole (for example, the diameter of the respective hole, as shown in Figure 8). Fig. 8) can be defined and the width of a generated structural element (for example, the generated structural element 807) can be defined by a distance, for example, the smallest distance (for example, the distance 807a) between the respective side walls of two adjacent holes (for example, by the distance 807a between the side wall 806a of the first hole 804a and the side wall 806b of the second hole 804b). According to various embodiments, the formation of several structural elements over and / or in a support, as in the Fig. 1. The procedure shown in 100 and in the Fig. The two methods shown in Figure 200 include the creation of at least one structural element by forming at least one hole.

[0120] As shown by the in Fig. As can be seen from the example shown in Figure 8, methods 100 and 200 can also be applied to a carrier 302 having several holes, wherein at least one hole 804a can have a first diameter 803 and at least one hole 804b can have a diameter 805 that is larger than the first diameter (for example, with reference to method 200), or wherein at least one hole 804a can have a first diameter 803 and at least one hole 804b can have a diameter 805 that is larger than twice the first diameter 803 (for example, with reference to method 100). Similarly, the height of the remaining material of a first layer at the side walls (for example, the one shown in Figure 8) can be determined by the method 100. Fig. The sidewalls 806a and 806b of the multiple holes shown in Figure 8 are the same for all holes, regardless of the respective diameter of the hole (for example, diameters 803 and 805), if the method 100 or the method 200 is carried out as described above. With reference to this, according to various embodiments, charging effects (for example, aspect ratio-dependent etching) during the formation of a structure that partially covers the respective sidewalls of multiple holes (for example, the partially removed first layer) can be reduced or avoided by using the method 100 or the method 200 as described above.

[0121] According to various embodiments, the diameter of a hole (for example 804a or 804b) can be in the range of about 5 nm to about 200 nm, for example about 20 nm to about 150 nm, for example about 60 nm to about 120 nm, or according to one embodiment about 90 nm (or according to another embodiment be greater than 200 nm).

[0122] According to various embodiments, the formation of several structural elements over and / or in a support, as described with reference to Method 100 and Method 200, can include the formation of several recesses (or trenches), as shown in Fig. Figure 9 is shown as an example. According to various embodiments, it shows Fig. 9 a top view 901 and a sectional view 902 of a beam 302 (for example at a first processing stage, for example after 110 or 210 have been carried out), including several recesses (or trenches), such as a recess 904a and a recess 904b, wherein at least one recess (for example the recess 904a) may have a first dimension 903 and at least one recess (for example the recess 904b) may have a dimension 905 which is larger than the first dimension 903.According to various embodiments, the first dimension 903 of the recess 904a can define a first distance between two adjacent structural elements (for example, the first distance 903 between the structural element 302a and the structural element 302b), and the dimension 905 of the recess 904b (which is larger than the first dimension 903) can define a distance between two adjacent structural elements (for example, the distance 905 between the structural element 302b and the structural element 302c) that is larger than the first distance (for example, the first distance 903 between the structural element 302a and the structural element 302b).

[0123] As in Fig. As shown in Figure 9, according to various embodiments, the distance between two adjacent structural elements, as described above with reference to Method 100 and Method 200, can in this case be defined by the lateral dimension of the recess, and the width of the corresponding structural element (for example, the generated structural element 302b) can be defined by a distance (for example, the distance 907a) between the respective side walls of two adjacent recesses (for example, by the distance 907a between the side wall 906a of recess 904b and the side wall 906b of recess 904c). According to various embodiments, the formation of several structural elements over and / or in a support, as shown in Figure 9, can be achieved by means of a distance (for example, the distance 907a) between the respective side walls of two adjacent recesses (for example, the distance 907a between the side wall 906a of recess 904b and the side wall 906b of recess 904c). Fig. 1. The procedure shown in 100 and in the Fig. The two methods shown include the creation of at least one structural element by forming at least one recess (or trench).

[0124] As shown by the in Fig. As can be seen from the example shown in Figure 9, Method 100 and Method 200 can also be applied to a support 302 which has several recesses (or trenches), wherein at least one recess (or at least one trench) can have a first dimension and at least one recess (or at least one trench) can have a dimension that is larger than the first dimension (for example, with reference to Method 200), or wherein at least one recess (or at least one trench) can have a first dimension and at least one recess (or at least one trench) can have a dimension that is larger than twice the first dimension (for example, with reference to Method 100).Similarly, the height of the remaining material of a first layer on the side walls (for example, on side walls 906a and 906b) of the multiple recesses (or trenches) can be the same for all recesses (or trenches), regardless of the respective dimensions of the recess (or trench) (for example, dimensions 903 and 905), if method 100 or method 200 is carried out as described above. In this regard, it should be noted that, according to various embodiments, charging effects (for example, aspect ratio-dependent etching) during the formation of a structure that partially covers the respective side wall of multiple recesses (or trenches) (for example, the partially removed first layer 308 or 408 after 150 or 250 in method 100 or 200, respectively) can be reduced or avoided by using method 100 or method 200 as described above.

[0125] Furthermore, according to various embodiments, the first distance (for example, the distance 303, 403, 803, 903) can be in the range of about 10 nm to about 300 nm, for example about 20 nm to about 200 nm, for example about 70 nm to about 110 nm, for example about 80 nm to about 100 nm, for example at about 90 nm, or even be smaller than 90 nm or, for example, larger than 90 nm. According to various embodiments, at least two adjacent structural elements can have a distance between them (for example, the distance 305, 405, 805, 905) that is greater than the corresponding first distance (for example, the distance 303, 403, 803, 903), wherein, for example, the distance 305, 405, 805, 905 can be in the range of about 10 nm to about 600 nm, for example, about 50 nm to about 500 nm, for example, about 90 nm to about 300 nm, for example, about 170 nm to about 300 nm, for example, less than 180 nm or, for example, greater than 180 nm.

[0126] According to various embodiments, at least two adjacent structural elements can have a distance between them that is a multiple of the first distance between two adjacent structural elements (for example, three, five, or seven times the first distance according to some embodiments, or another multiple of the first distance according to other embodiments). According to various embodiments, at least two adjacent structural elements can have a distance between them that is three times the first distance between two adjacent structural elements (for example, the first distance can be about 90 nm, and two adjacent structural elements can have a distance of about 270 nm between them).

[0127] According to various embodiments, the width (or lateral dimension) of a structural element can be in the range of approximately 10 nm to 200 nm, for example approximately 20 nm to approximately 170 nm, for example approximately 70 nm to approximately 110 nm, for example approximately 80 nm to approximately 100 nm, for example approximately 90 nm.

[0128] According to various embodiments, at least one of the several structural elements can have a different height than the other structural elements. Furthermore, according to various embodiments, at least one opening, for example at least one recess, at least one trench, or at least one hole (as in the Fig. 8 and Fig. (as shown in Figure 9) may have a different depth than the other openings, such as the recesses, trenches, or holes. Therefore, according to various embodiments, the side walls of the structural elements may not necessarily have the same size (or area).

[0129] According to various embodiments, at least one of the several structural elements can be a dummy structural element that cannot have any electrical functionality in an integrated circuit. According to various embodiments, at least one of the several structural elements can be designed differently from the other structural elements.

[0130] According to another embodiment, the first layer (for example, the first layer 308 or the first layer 408) can be the lower surfaces of the regions between at least one pair of adjacent structural elements (for example, the lower surface of region 311 between structural elements 302c and 302e, as in Fig. 3C shown, or the lower surface of area 411 between structural elements 402c and 402e, as in Fig. 4A) do not cover. According to another embodiment, the first layer (for example, the first layer 308 or the first layer 408) can be covered by the areas of the lower surfaces between the structural elements (for example, by the lower surface of area 311 between structural elements 302c and 302e, as shown in Fig. 3C shown, or from the lower surface of area 411 between structural elements 402c and 402e, as in Fig. (shown in Figure 4A) can be partially removed after the first layer (for example, the first layer 308 or the first layer 408) has been deposited over the structural elements (for example, using a structuring process). According to another embodiment, the first layer (for example, the first layer 308 or the first layer 408) can at least partially cover the side walls of the structural elements (for example, the side walls 306a, 306b of the structural elements 302a-302e or the side walls 406a, 406b of the structural elements 402a-402e), wherein the areas (or at least two areas) formed by the material of the first layer 308 on the side walls of the respective structural elements are not electrically connected to each other by the material of the first layer 308.

[0131] According to various embodiments, the term ‘surface layer’ used here in reference to a ‘surface layer or stack of surface layers’ of a structural element or a ‘surface layer’ of several structural elements can refer at least to the top surface and the side walls of each of the several structural elements.

[0132] According to various embodiments, two control gates provided by the electrically conductive first layer on the adjacent side walls of two adjacent structural elements (for example, two adjacent control gates of two adjacent FinFETs) can be electrically connected to each other by the remaining material of the first layer between the two adjacent structural elements (for example, the lower region 506b between structural elements 302b and 302c, as in the Fig. 5A and Fig. 5B shows the respective control gates electrically connected by the first layer 308).

[0133] According to another embodiment (not shown in the figures), the control gates provided by the electrically conductive first layer on the respective side walls of the structural elements (for example, the FinFET) cannot be obstructed by any residual material of the first layer between two adjacent structural elements (for example, by the residual material in the lower region 506b between structural elements 302b and 302c, as in the Fig. 5A and Fig. (5B shown) are electrically connected to each other. Therefore, according to various embodiments, residual material in the lower region between two adjacent structural elements, which connects two adjacent control gates on the respective side walls of two adjacent structural elements (for example, residual material of the first layer 308 in the lower region 506b between the structural elements 302b and 302c, as shown, for example, in Fig. 5A and Fig. (as shown in 5B) electrically connects, must be removed, for example, before at least one additional layer can be formed above the first layer (for example, layer 312 formed above layer 308).

[0134] According to various embodiments, part of the first layer can be removed before at least one additional layer can be formed above the first layer, so that the gate electrodes of the FinFET can be separated from each other.

[0135] According to various embodiments, a method for processing a carrier may comprise the following steps: forming several structural elements over and / or in a carrier, wherein at least two adjacent structural elements may have a first distance between them; depositing a first layer over the several structural elements, wherein the first layer has a thickness equal to the first distance between the at least two adjacent structural elements; forming at least one additional layer over the first layer, wherein the at least one additional layer may cover an exposed area of ​​the first layer; removing an area of ​​the at least one additional layer to partially expose the first layer; and partially removing the first layer, wherein at least one side wall of the at least two adjacent structural elements may be partially exposed.

[0136] According to various embodiments, a method for processing a carrier may comprise the following steps: forming several structural elements over and / or in a carrier, wherein at least two adjacent structural elements may have a first distance between them; depositing a first layer over the several structural elements, wherein the first layer has a thickness that is less than half the first distance between the at least two adjacent structural elements; forming at least one additional layer over the first layer, wherein the at least one additional layer may cover an exposed area of ​​the first layer; removing an area of ​​the at least one additional layer to partially expose the first layer; and partially removing the first layer, wherein at least one side wall of the at least two adjacent structural elements is partially exposed.

[0137] According to various embodiments, the multiple structural elements can be formed over a main processing surface of the carrier.

[0138] According to various embodiments, the multiple structural elements can have at least one electrically insulating layer on a surface of at least one of the multiple structural elements.

[0139] According to various embodiments, the at least one electrically insulating layer can have an oxide layer.

[0140] According to various embodiments, at least one of the several structural elements can have the shape of a fin.

[0141] According to various embodiments, at least one of the several structural elements can be part of a FinFET.

[0142] According to various embodiments, the deposition of the first layer over the multiple structural elements can have conformal deposition of the first layer over the multiple structural elements.

[0143] According to various embodiments, the first layer can comprise at least one electrically conductive material.

[0144] According to various embodiments, the first layer can consist of electrically conductive polycrystalline silicon.

[0145] According to various embodiments, the formation of at least one additional layer above the first layer can involve the deposition of at least one layer using a conformal deposition process.

[0146] According to various embodiments, the formation of at least one additional layer above the first layer can involve the growth of at least one layer using thermal oxidation.

[0147] According to various embodiments, the at least one additional layer can have a material that is different from a material of the first layer.

[0148] According to various embodiments, the formation of the at least one additional layer above the first layer can include: forming at least one second layer above the first layer, wherein the second layer can fill any remaining space between adjacent structural elements of the multiple structural elements.

[0149] According to various embodiments, at least two adjacent structural elements of the multiple structural elements can have a distance between them that is greater than twice the first distance.

[0150] According to various embodiments, at least two adjacent structural elements of the multiple structural elements can have a distance between them that is greater than twice the first distance, wherein the first layer can have a thickness equal to the first distance.

[0151] According to various embodiments, at least two adjacent structural elements (for example, at least one pair of adjacent structural elements) can have a first distance between them from the multiple structural elements, and at least two adjacent structural elements (for example, at least one other pair of adjacent structural elements) can have a distance between them that is greater than twice the first distance, wherein the first layer can be formed over the multiple structural elements, the first layer having a thickness equal to the first distance.

[0152] According to various embodiments, the formation of the at least one additional layer can include: forming a second layer over the first layer and forming a third layer over the second layer, wherein at least one of the second layer and the third layer can fill a remaining space between at least two adjacent structural elements of the multiple structural elements.

[0153] According to various embodiments, at least two adjacent structural elements of the multiple structural elements can have a first distance between them, and at least two adjacent structural elements of the multiple structural elements can have a distance between them that is greater than the first distance.

[0154] According to various embodiments, at least two adjacent structural elements of the multiple structural elements can have a distance between them that is greater than the first distance.

[0155] According to various embodiments, at least two adjacent structural elements of the multiple structural elements can have a distance between them that is greater than the first distance, wherein the first layer can be formed over the multiple structural elements, wherein the first layer has a thickness that is less than half the first distance.

[0156] According to various embodiments, at least two adjacent structural elements (for example, at least one pair of adjacent structural elements) of the multiple structural elements can have the first distance between them, and at least two adjacent structural elements (for example, at least one other pair of adjacent structural elements) of the multiple structural elements can have a distance between them that is greater than the first distance, wherein the first layer can be formed over the multiple structural elements, wherein the first layer has a thickness that is less than half the first distance.

[0157] According to various embodiments, removing the area of ​​the at least one additional layer to partially expose the first layer can comprise the partial removal of the at least one additional layer and the removal of an area of ​​the first layer, so that a common surface is exposed, wherein the common surface can be formed at least by the upper surfaces of the several structural elements (for example, additionally also by the surface of the support, as with reference to Fig. 3B described). According to various embodiments, exposing the common surface by partially removing the at least one additional layer and removing the area of ​​the first layer can involve a CMP process which may be selective or non-selective for the specific material of the first layer and the at least one additional layer.

[0158] According to various embodiments, a method for processing a support can comprise the following steps: forming several structural elements over and / or in a support, wherein at least two adjacent structural elements can have a first distance between them and at least two adjacent structural elements can have a distance between them that is greater than the first distance, depositing a first layer over the support, wherein the first layer has a thickness that is less than half the first distance, filling any remaining space between the adjacent structural elements with a filler material after the deposit of the first layer and partially removing the first layer, wherein at least one side wall of at least one structural element can be partially exposed by the several structural elements.

[0159] According to various embodiments, a method for processing a carrier can comprise the following steps: forming several structural elements over and / or in a carrier, wherein at least two adjacent structural elements can have a first distance between them and at least two adjacent structural elements can have a distance between them that is greater than twice the first distance, depositing a first layer over the carrier, wherein the first layer has a thickness equal to the first distance, filling any remaining space between the adjacent structural elements with a filler material after depositing the first layer, and partially removing the first layer, wherein at least one side wall of at least one structural element can be partially exposed by the several structural elements.

[0160] According to various embodiments, the multiple structural elements can have at least one electrically insulating layer on the surface of at least one of the multiple structural elements.

[0161] According to various embodiments, filling the remaining space between the adjacent structural elements can include: forming a second layer over the first layer, depositing a third layer over the second layer, wherein at least one of the second layer and the third layer can fill the remaining space between the adjacent structural elements, and partially removing material from at least the second layer and the third layer to partially expose the first layer.

[0162] According to various embodiments, the formation of the second layer over the first layer can involve the formation of the second layer over the first layer using a conformal deposition process.

[0163] According to various embodiments, the formation of the third layer over the second layer can involve the formation of the third layer over the second layer using a conformal deposition process.

[0164] According to various embodiments, at least one of the second layer and the third layer can have a material that is different from a material of the first layer.

[0165] According to various embodiments, the formation of the second layer over the first layer can involve the formation of the second layer using high-temperature oxidation.

[0166] According to various embodiments, filling the remaining space between adjacent structural elements can involve: forming a second layer over the first layer which can fill the remaining space between adjacent structural elements, and partially removing material from at least the second layer to at least partially expose the first layer.

[0167] According to various embodiments, the deposition of the first layer over the support can feature conformal deposition of the first layer.

[0168] According to various embodiments, the first layer can have an electrically conductive material.

[0169] According to various embodiments, the first layer can consist of polycrystalline silicon.

[0170] According to various embodiments, at least one of the several structural elements can be at least one part of a FinFET.

[0171] According to various embodiments, the at least one additional layer can serve as an etching mask for the partial removal of the first layer, whereby at least one side wall of the multiple structural elements is partially exposed. According to various embodiments, the insulating surface layer (which can be part of at least one of the multiple structural elements) can serve as an etching mask for the partial removal of the first layer, whereby at least one side wall of the multiple structural elements is partially exposed.

Claims

[1] Method (100) for processing a carrier comprising the following steps: forming several structural elements over and / or in a support, wherein at least two adjacent structural elements have a first distance between them (110), Deposition of a first layer comprising an electrically conductive material over the multiple structural elements, wherein the first layer has a thickness equal to the first distance between the at least two adjacent structural elements (120), Forming at least one additional layer over the first layer, wherein the at least one additional layer covers an exposed area of ​​the first layer (130), wherein the formation of the at least one additional layer (130) comprises the formation of at least one second layer over the first layer, and wherein the formation of the at least one second layer comprises growing the at least one second layer using high-temperature oxidation of the first layer, removing an area of ​​the at least one additional layer to partially expose the first layer (140), and Partial removal of the first layer, whereby at least one side wall of at least two adjacent structural elements is partially exposed (150). [2] Method (100) for processing a carrier comprising the following steps: forming several structural elements over and / or in a support, wherein at least two adjacent structural elements of the several structural elements have a first distance between them (110), and at least two adjacent structural elements of the several structural elements have a distance between them that is greater than twice the first distance; Deposition of a first layer comprising an electrically conductive material over the multiple structural elements, wherein the first layer has a thickness equal to the first distance between the at least two adjacent structural elements (120), Forming at least one additional layer above the first layer, wherein the at least one additional layer covers an exposed area of ​​the first layer (130), wherein the formation of the at least one additional layer (130) comprises the formation of at least one second layer above the first layer, and wherein the second layer fills a residual space between adjacent structural elements of the multiple structural elements, Removing an area of ​​at least one additional layer to partially expose the first layer (140), and Partial removal of the first layer, whereby at least one side wall of at least two adjacent structural elements is partially exposed (150). [3] Method (100) according to claim 1 or 2, wherein the multiple structural elements comprise at least one electrically insulating layer on a surface of at least one of the multiple structural elements; wherein preferably the at least one electrically insulating layer comprises an oxide layer. [4] Method (100) according to one of claims 1 to 3, wherein at least one of the several structural elements has the shape of a fin. [5] Method (100) according to any one of claims 1 to 4, wherein at least one of the several structural elements is part of a FinFET. [6] Method (100) according to any one of claims 1 to 5, wherein the deposition (120) of the first layer over the multiple structural elements comprises conformal deposition of the first layer over the multiple structural elements. [7] Method (100) according to any one of claims 1 to 6, wherein the first layer comprises electrically conductive polycrystalline silicon. [8] Method (100) according to any one of claims 1 to 7, wherein the formation (130) of the at least one additional layer comprises the deposition of at least one layer using a conformal deposition process. [9] Method (100) according to any one of claims 2 to 8, wherein the formation of the at least one second layer comprises growing at least one layer using high-temperature oxidation. [10] Method (100) according to any one of claims 1 to 9, wherein the at least one additional layer comprises a material that is different from a material of the first layer. [11] Method (200) for processing a carrier comprising the following steps: forming several structural elements over and / or in a support, wherein at least two adjacent structural elements have a first distance between them (210), Deposition of a first layer comprising an electrically conductive material over the multiple structural elements, wherein the first layer has a thickness that is less than half the first distance between the at least two adjacent structural elements (220), Forming at least one additional layer over the first layer, wherein the at least one additional layer covers an exposed area of ​​the first layer (230), wherein the formation of the at least one additional layer (230) comprises forming at least one second layer over the first layer, and wherein the formation of the at least one second layer comprises growing the at least one second layer using high-temperature oxidation of the first layer, removing an area of ​​the at least one additional layer to partially expose the first layer (240), and Partial removal of the first layer, whereby at least one side wall of at least two adjacent structural elements is partially exposed (250). [12] Method (200) according to claim 11, wherein at least two adjacent structural elements of the multiple structural elements have a distance between them that is greater than the first distance. [13] Method (200) according to claim 11 or 12, wherein the multiple structural elements comprise at least one electrically insulating layer on a surface of at least one of the multiple structural elements; wherein preferably the at least one electrically insulating layer comprises an oxide layer. [14] Method (200) according to one of claims 11 to 13, wherein at least one of the several structural elements has the shape of a fin. [15] Method (200) according to any one of claims 11 to 14, wherein at least one of the several structural elements is part of a FinFET. [16] Method (200) according to any one of claims 11 to 15, wherein the deposition of the first layer over the multiple structural elements comprises conformal deposition of the first layer over the multiple structural elements. [17] Method (200) according to any one of claims 11 to 16, wherein the formation (230) of the at least one additional layer comprises the deposition of at least one layer using a conformal deposition process. [18] Method (200) according to any one of claims 11 to 17, wherein the at least one additional layer comprises a material that is different from a material of the first layer. [19] Method (200) according to any one of claims 11 to 18, wherein the formation (230) of the at least one additional layer comprises: Forming a third layer above the second layer, wherein at least one of the second and third layers fills any remaining space between adjacent structural elements of the multiple structural elements.

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