Semiconductor device and semiconductor device manufacturing processes

Abstract

Semiconductor device (100; 200) comprising the following: a layered substrate (140) comprising an insulating substrate (141) and a circuit board (142a, 142b) arranged over a front surface of the insulating substrate (141); a semiconductor chip (144a-c, 146a-c) that is arranged above the circuit board (142a, 142b); a housing (110) with a storage area (112a) for housing the layer substrate (140) and the semiconductor chip (144a-c, 146a-c); a terminal block (120, 130) having a first surface and a second surface opposite the first surface and holding external connection terminals (121, 131) projecting from the first surface and the second surface; and a printed circuit board (119a-b) having a first main plane and a second main plane opposite the first main plane is arranged over a perimeter of the accommodation area (112a), is held on the second surface side of the terminal block (120, 130), is electrically connected by a connecting element (148) to a control electrode (144ac, 144bc, 144cc, 146ac, 146bc, 146cc) of the semiconductor chip (144a-c, 146a-c) and is connected to the external connection terminals (121, 131), wherein the printed circuit board (119a-b) is inserted between the second surface of the terminal block (120, 130) and the housing (110) in such a way that the printed circuit board (119a-b) is arranged directly on the housing (110) and the second surface of the terminal block (120, 130) is arranged on the printed circuit board (119a-b), wherein: the connecting block (120, 130) has a third surface between the first surface and the second surface, which connects to the first surface; and at least one of the second surface and the third surface is joined to the housing (110), wherein: the connecting block (120, 130) has a height difference (123, 133) on the third surface and a part of the housing (110) is arranged on a first surface side of the height difference (123, 133).

Description

GENERAL STATE OF THE ART1. Field of the invention

[0001] The embodiments discussed herein relate to a semiconductor device and a semiconductor device manufacturing process. 2. Background of the state of the art

[0002] Power semiconductor modules (semiconductor devices) contain semiconductor chips such as insulated-layer bipolar transistors (IGBTs), metal oxide semiconductor field-effect transistors (MOSFETs) and freewheeling diodes (FWDs), and are widely used as power converters.

[0003] In such semiconductor devices, a layered substrate, comprising an insulating plate and a circuit pattern made of copper foil and formed on the insulating plate, is housed within a package. The semiconductor chips are arranged over the copper foil. Furthermore, the layered substrate and the semiconductor chips are wired within the package. The electrodes of the semiconductor chips are electrically connected by wires, and the electrodes of the semiconductor chips and external electrode connections are also electrically connected by wires. These components within the package are sealed with resin (see, for example, Japanese Patent Application JP 2000-323646A).

[0004] Incidentally, the number of wires per element of a control signal system tends to increase when the functionality of a semiconductor chip contained in a semiconductor device is improved. To prevent wiring within a semiconductor device package from becoming too complex, the following method, for example, is used to simplify wiring connections. A circuit pattern is formed on a layered substrate, and this pattern is used for wiring guidance.

[0005] However, when a circuit pattern is used, an increase in the number of wires leads to more complex wiring. As a result, assembly becomes more difficult and the labor hours required for wiring increase. Furthermore, in the wiring of a control signal system, a magnetic field or similar generated during switching can affect the product's characteristics, depending on the wiring method used. This can lead to malfunctions.

[0006] DE 102 32 566 A1 describes a semiconductor component with a housing consisting of a metal base, a one-piece enclosure with terminals, and a cover. The housing contains a power circuit and a control circuit, which are mounted in two levels and encapsulated using a gel-like filler. In this semiconductor component, control terminals for the external connection of the control circuit are embedded as pin terminals in a control terminal block forming an independent component. The control terminal block is connected to the enclosure housing in such a way that it extends beyond the top surface of the enclosure near the center of the top surface.A printed circuit board of the control circuit extends and is connected between connecting leads that extend from the control terminal block into the interior of the housing, and connecting leads that extend vertically from an intermediate connection terminal block located in the housing.

[0007] Furthermore, US 2001 / 0038143A1 describes a power semiconductor module with a metal base, several wiring substrates provided on the base, and substrate-containing sections with a resin section containing one of the wiring substrates, wherein a first wiring substrate of the wiring substrates comprises a power circuit section with a power semiconductor device. The wiring substrate is positioned in self-alignment on the metal substrate based on an inner wall of the resin section of the substrate-containing section.

[0008] DE 10 2006 012 429 A1 describes a semiconductor device comprising a housing and an insulating substrate located within the housing. It also includes a plurality of semiconductor chips mounted on the insulating substrate, each having a first chip electrode for receiving a control signal, and a flexible circuit board supported by the housing. This board has a core section and a plurality of conductor sections extending from the core section. Each of the first chip electrodes is electrically connected to the corresponding conductor section. A conductor is also provided on the flexible circuit board such that the terminals of the control IC chip are connected to an external control circuit via the copper structures of the flexible circuit board and the pins of the connector.Furthermore, each of the tips of the conductor sections can be easily connected to the corresponding control electrode of the IGBT chip via any connecting agent or conductive adhesive, so that the IGBT chips as a whole can be electrically connected to the flexible circuit board in a simple manner. BRIEF SUMMARY OF THE INVENTION

[0009] The present invention was conceived under the background circumstances described above. An object of the present invention is to provide a semiconductor device and a semiconductor device manufacturing method according to the attached claims, wherein the wiring connection is simplified. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a perspective view of a semiconductor device according to a first embodiment; Fig. Figure 2 is a flowchart of a process for manufacturing the semiconductor device according to the first embodiment; Fig. Figure 3 is a perspective view showing a state in which parts are mounted over an insulating substrate of the semiconductor device according to the first embodiment; Fig. Figure 4 is a perspective view of terminal blocks of the semiconductor device according to the first embodiment; Fig. Figure 5 is a perspective view of another example of terminal blocks of the semiconductor device according to the first embodiment; Fig. Figure 6 is a perspective view of a printed circuit board and the terminal blocks of the semiconductor device according to the first embodiment (Part 1); Fig. Figure 7 is a perspective view of the printed circuit board and terminal blocks of the semiconductor device according to the first embodiment (part 2); Fig. Figure 8 is an incomplete sectional view of the printed circuit board and a layer substrate of the semiconductor device according to the first embodiment; Fig. Figure 9 is a top view of a housing of the semiconductor device according to the first embodiment; Fig. Figure 10 is a rear view of the housing of the semiconductor device according to the first embodiment; Fig. Figure 11 is a circuit diagram representing a circuit structure in the semiconductor device according to the first embodiment; Fig. 12 is a top view of a semiconductor device, which is taken as a reference example; Fig. Figure 13 is a perspective view of a semiconductor device according to a second embodiment; Fig. 14 is a flowchart of a process for manufacturing the semiconductor device according to the second embodiment; Fig. 15 is a top view of a busbar block of the semiconductor device according to the second embodiment and Fig. Figure 16 is a top view of a housing of the semiconductor device according to the second embodiment,

[0010] in which the insulating substrates are housed. DETAILED DESCRIPTION OF THE INVENTION

[0011] The following descriptions of embodiments are provided with reference to the accompanying drawings, in which the same reference numerals refer to the same elements throughout the text. (First embodiment)

[0012] First, a semiconductor device according to a first embodiment is created by using Fig. 1 described.

[0013] Fig. Figure 1 is a perspective view of a semiconductor device according to a first embodiment.

[0014] A semiconductor device 100 includes a package 110 and layer substrates 140, which are housed in accommodation sections 112a, 112b and 112c of the package 110.

[0015] In the semiconductor device 100, a positive electrode is connected to P terminals 113a, 113b, and 113c, and a negative electrode is connected to N terminals 114a, 114b, and 114c. A control signal is applied to each of control terminals 121 and 131. An output corresponding to a control signal is received from each of a U terminal 115a, a V terminal 115b, and a W terminal 115c.

[0016] The details of the housing 110, which is incorporated into the above semiconductor device 100, and the layer substrates 140, which are housed in the housing 110, will be described later.

[0017] A method for manufacturing the semiconductor device 100 is now being developed using Fig. 2 described.

[0018] Fig. Figure 2 is a flowchart of a process for manufacturing the semiconductor device according to the first embodiment.

[0019] (Step S11) Printed circuit boards 119a and 119b and terminal blocks 120 and 130 are manufactured (step S11a). Furthermore, the layer substrates 140 are manufactured (step S11b). In step S11a, control pins 121 and 131 of terminal block 120 and 130, respectively, are pressed into printed circuit boards 119a and 119b to hold the printed circuit boards 119a and 119b to a bottom surface of terminal blocks 120 and 130.

[0020] The layered substrate 140 is now produced by using Fig. 3 described.

[0021] Fig. Figure 3 is a perspective view showing a state in which parts are mounted over an insulating substrate of the semiconductor device according to the first embodiment.

[0022] The layered substrate 140 includes a radiation plate (not shown) made of copper or the like and arranged over a bottom surface of an insulating substrate 141, and circuit boards 142a and 142b made of copper foil or the like and arranged over a top surface of the insulating substrate 141.

[0023] For example, a conductive connection 143a, made of copper, is located on the underside of circuit board 142a in Fig. 3. The emitter electrodes of semiconductor chips 144a, 144b, and 144c are arranged and aligned over circuit board 142a with solder between them. Furthermore, a straight circuit board 145a is arranged over the emitter electrodes of the aligned semiconductor chips 144a, 144b, and 144c with solder between them. As a result, the emitter electrodes of the semiconductor chips 144a, 144b, and 144c are electrically connected to each other.

[0024] For example, a conductive connection 143b, made of copper, is located on the upper side of circuit board 142b in Fig. 3. The emitter electrodes of semiconductor chips 146a, 146b, and 146c are arranged and aligned over circuit board 142b with solder between them. Furthermore, a straight circuit board 145b is arranged over the emitter electrodes of the aligned semiconductor chips 146a, 146b, and 146c with solder between them. As a result, the emitter electrodes of the semiconductor chips 146a, 146b, and 146c are electrically connected to each other.

[0025] An IGBT, a MOSFET, an FWD, or the like is used as the semiconductor chip 144a, 144b, 144c, 146a, 146b, or 146c. In the example of Fig. 3. A reverse-conducting IGBT (RC-IGBT) is used, for example, the semiconductor chip 144a. In addition to main electrodes (emitter electrodes and collector electrodes), the semiconductor chips 144a, 144b, 144c, 146a, 146b and 146c have several control electrodes 144ac, 144bc, 144cc, 146ac, 146bc and 146cc respectively, which are connected to gate terminals, sense terminals and chip temperature measurement terminals.

[0026] In the example of Fig. 3. The emitter electrodes of semiconductor chips 144a, 144b, and 144c are connected by the circuit board 145a. However, the emitter electrodes of semiconductor chips 144a, 144b, and 144c can be connected by a different method. That is, the emitter electrodes of semiconductor chips 144a, 144b, and 144c can be connected by a wire made of aluminum or the like. Similarly, the emitter electrodes of semiconductor chips 146a, 146b, and 164c can be connected by a wire.

[0027] Next, terminal blocks 120 and 130 will be connected using the Fig. 4 to 7 described.

[0028] Fig. Figure 4 is a perspective view of the terminal blocks of the semiconductor device according to the first embodiment. Fig. Figure 5 is a perspective view of another example of terminal blocks of the semiconductor device according to the first embodiment.

[0029] Furthermore, each of the Fig. 6 and Fig. 7 A perspective view of the printed circuit board and the terminal blocks of the semiconductor device according to the first embodiment. In the Fig. 6 and Fig. 7. The connection blocks 120 and 130 are arranged above the circuit board 119a.

[0030] As in Fig. As shown in Figure 4, terminal blocks 120 and 130 are formed by integrally shaping the control terminal (external connection terminal) 121 and 131, respectively, using resin, and are almost cuboid in shape. There are spaces 122 and 132, each defined by two projections, on the underside (second surface) of terminal block 120 and 130, respectively. The undersides of terminal blocks 120 and 130 face the printed circuit board 119a. Spaces 122 and 132 extend through terminal block 120 and 130 from a front to a back side. Fig. 4. Furthermore, height difference sections 123 and 133 are formed on mutually facing surfaces of the connecting block 120 and 130, respectively. A connecting block 150, which is in Fig. As shown in Figure 5, the control terminals 151 are formed by integrally forming them, and the control terminals 151 project from a top surface and a bottom surface of the terminal block 150. Each of the terminal blocks 120 and 130 can have a resin body like that of the terminal block 150 with a simple cuboid shape.

[0031] The terminal blocks 120 and 130 above hold several control terminals 121 and 131, respectively. Each control terminal 121 or control terminal 131 has a structure in which both end sections are thicker than one body section. The terminal blocks 120 and 130 hold the body sections of the control terminals 121 and 131 above. Both end sections of the control terminals 121 and 131, which are thicker than the body sections, project from the upper surfaces (first surfaces) and the lower surfaces (second surfaces) of the terminal block 120 and 130, respectively, which are located in Fig. 4 are shown. As will be described later, the lower end sections of the control connections 121 and 131, which protrude on the underside of the terminal block 120 and 130 respectively, are connected to the Fig. 4 are shown, pressed into through holes produced in the circuit board 119a. Fig. In Figure 6, control terminals 121 and 131 are arranged in two rows in terminal block 120 and 130, respectively. Consequently, the number of control terminals 121 and 131 held by terminal block 120 and 130 is high compared to a case where control terminals 121 and 131 are arranged in a single row. Furthermore, control terminals 121 and 131 can be arranged in three or more rows in terminal block 120 and 130, respectively. This further increases the number of control terminals 121 and 131 held by terminal block 120 and 130. Terminal blocks 120 and 130 are located above an end section of printed circuit board 119a.

[0032] The printed circuit board (PCB) 119a, used to form the housing 110, comprises a wiring layer made of a conductive material and a base plate made of a highly heat-resistant material. Several electrodes 119a1, electrically connected to the wiring layer, are arranged over a front surface of the PCB 119a. The wiring layer can be a single layer, extend over both surfaces of the PCB 119a, or have a multilayer structure. Furthermore, several through-holes 119a2, penetrating from a top surface (first main plane) to a bottom surface (second main plane), are provided in the PCB 119a. As described later, the PCB 119a is integrally formed with the housing 110. At this point, resin used to form the housing 110 enters the through-holes 119a2.As a result, the circuit board 119a adheres easily to the housing 110. The multiple through-holes 119a2 are preferably arranged such that the multiple aligned electrodes 119a1 will be inserted between them. The areas surrounding the multiple electrodes 119a1 are fixed with resin in the multiple through-holes 119a2. This improves the reliability of the connection of wires 148 in a subsequent step.

[0033] Furthermore, a pattern made of copper can be formed on the back surface of the printed circuit board 119a, and irregularities can be intentionally created by blackening treatment on one area of ​​the pattern. When the printed circuit board 119a is integrally formed with the housing 110, the irregularities on the back surface of the printed circuit board 119a consequently align with the housing 110, and the printed circuit board 119a adheres easily to the housing 110. A continuous pattern of a wiring layer on one underside can be used as a shield. A residue, such as a resist, is preferably not left on the underside of the printed circuit board 119a.

[0034] The lower end sections of the control terminals 121 and 131, which protrude from the undersides of the terminal block 120 and 130 respectively, are connected to the circuit board 119a above by press-fitting, and the terminal blocks 120 and 130 are positioned. As a result, the circuit board 119a and the control terminals 121 and 131 are electrically connected. As shown in Fig. As shown in Figure 7, the lower end sections of the control terminals 121 and 131 may be exposed or protrude from a bottom surface of the circuit board 119a.

[0035] If the lower end sections of the control connectors 121 and 131 are the same thickness as the body sections of the control connectors 121 and 131, the lower end sections of the control connectors 121 and 131 cannot be pressed into the printed circuit board 119a, but must be soldered. In this case, the lower end sections of the control connectors 121 and 131 that penetrate the printed circuit board 119a (from the front surface of the printed circuit board 119a) are soldered to a rear surface of the printed circuit board 119a. However, solder melts depending on the temperature, and molten solder can enter the resin. To prevent molten solder from entering the resin, it is desirable to cover the soldered sections of the control connectors 121 and 131 on the rear surface of the printed circuit board 119a with epoxy resin and allow the epoxy resin to cure.When the control connections 121 and 131 are fitted into the circuit board 119a, it is therefore desirable to press them in instead of soldering them.

[0036] Furthermore, a control circuit can be implemented on the circuit board 119a, and electronic components or the like, electrically connected to the control terminals 121 and 131, can be mounted on the circuit board 119a. The circuit board 119b, described later, has the same structure as the circuit board 119a and is handled in the same way.

[0037] The above layer substrate 140, the above printed circuit boards 119a and 119b and the above terminal blocks 120 and 130 are manufactured.

[0038] (Step S12) The housing 110 is formed by integrally forming the printed circuit boards 119a and 119b, over which the terminal blocks 120 and 130, wiring terminals 116, 117 and 118, the P terminals 113a, 113b and 113c, the N terminals 114a, 114b and 114c, the U terminal 115a, the V terminal 115b, the W terminal 115c and the like are arranged by using resin.

[0039] The housing 110 formed in this way is constructed by using the Fig. 9 and Fig. 10 described.

[0040] Fig. Figure 9 is a top view of the housing of the semiconductor device according to the first embodiment. Fig. Figure 10 is a rear view of the housing of the semiconductor device according to the first embodiment.

[0041] The housing 110 is formed, for example, by injection molding using resin and has the shape of a frame with a concave area in its central region. The housing sections 112a, 112b, and 112c, in which the aforementioned layer substrates 140 are housed, are formed within the concavity of the central region. The printed circuit boards 119a and 119b are arranged (in the lateral direction of the housing 110) in circumferential sections of housing section 112a. A pair of printed circuit boards 119a is arranged (in the lateral direction of the housing 110) in circumferential sections of housing section 112b. The printed circuit boards 119a and 119b are arranged (in the lateral direction of the housing 110) in circumferential sections of housing section 112c. Furthermore, each printed circuit board 119a or each printed circuit board 119b is integrally formed with the housing 110 and arranged.A resin beam 111a or 111b, made of resin, is formed over a printed circuit board 119a arranged in this manner. The housing 110 withstands pressure exerted laterally on the housing 110 by the resin beams 111a and 111b.

[0042] In the accommodation section 112a of the above housing 110, the P-terminal 113a and the N-terminal 114a are located on one side in the longitudinal direction of the housing 110 (on the lower side of the housing 110 in Fig. 9) formed and the U-connection 115a is located on the side of the other side in the longitudinal direction of the housing 110 (on the upper side of the housing 110 in Fig. 9). Similarly, in the housing section 112b of the above housing 110, the P-terminal 113b and the N-terminal 114b are formed on one side in the longitudinal direction of the housing 110 (on the lower side of the housing 110 in Fig. 9) formed and the V-connection 115b is located on the side of the other side in the longitudinal direction of the housing 110 (on the upper side of the housing 110 in Fig. 9). Furthermore, in the housing section 112c of the above housing 110, the P-terminal 113c and the N-terminal 114c are formed on one side in the longitudinal direction of the housing 110 (on the lower side of the housing 110 in Fig. 9) formed and the W-terminal 115c is located on the side of the other side in the longitudinal direction of the housing 110 (on the upper side of the housing 110 in Fig. 9) trained.

[0043] The wiring terminals 116, which are electrically connected to the U terminal 115a, the V terminal 115b, and the W terminal 115c, are arranged in the housing sections 112a, 112b, and 112c, respectively. The wiring terminals 116 extend parallel to the circuit boards 119a and 119b to this side of the wiring terminals 118 described later. Furthermore, the wiring terminals 117, which are electrically connected to the N terminals 114a, 114b, and 114c, are arranged in the housing sections 112a, 112b, and 112c, respectively. The wiring connections 117 extend parallel to the circuit boards 119a and 119b from the N terminals 114a, 114b and 114c to this side of the wiring connections 116. Furthermore, the wiring connections 118, which are electrically connected to the P terminals 113a, 113b and 113c, are arranged in the housing section 112a, 112b and 112c respectively.The wiring terminals 118 protrude from the P terminals 113a, 113b and 113c.

[0044] Furthermore, terminal blocks 120 and 130 are arranged above circuit boards 119b and 119a, respectively, on one side of the U-terminal 115a of the housing section 112a, and control terminals 121 and 131 are electrically connected to circuit boards 119b and 119a, respectively. Terminal blocks 120 and 130 are arranged near U-terminal 115a, V-terminal 115b, and W-terminal 115c on the longitudinal side of the housing 110.

[0045] The terminal blocks 120 and 130 are integrated with the housing 110 using resin by integral molding. During a secondary molding process, the top surfaces, bottom surfaces, or side surfaces (third surfaces) between the top and bottom surfaces of the terminal blocks 120 and 130 are welded together with the heated resin. As a result, the terminal blocks 120 and 130 are joined to the housing 110. In the example of Fig. 9. The side surfaces of terminal blocks 120 and 130 are joined to the upper and lower surfaces of terminal block 120 and 130, respectively. Thermoplastic resin, such as polyphenylene sulfide (PPS), can be used as the resin. When the terminal blocks 120 and 130, which hold the control terminal 121 and 131, respectively, are formed (primary forming), it is desirable to form the bodies of the terminal blocks 120 and 130 using a resin that is the same type as, or identical to, the resin used to form the housing 110. Forming the bodies of the terminal blocks 120 and 130 and the housing 110 using resin materials of the same type facilitates secondary forming.

[0046] To position part of the housing 110 on an upper surface of the height-difference sections 123 and 133, the height-difference sections 123 and 133 are coated with resin during a secondary forming process, and integral forming is performed. This allows the terminal blocks 120 and 130 and the housing 110 to be firmly joined together. The terminal blocks 120 and 130 and the housing 110 are integrally formed so that the end sections of the control terminals 121 and 131, which are exposed or protrude on an underside (second main plane) of the printed circuit boards 119a and 119b, will be in contact with the housing 110. This holds (inserts) the printed circuit boards 119a and 119b between the undersides (second surfaces) of the terminal blocks 120 and 130 and the housing 110. As a result, the circuit boards 119a and 119b can be firmly fixed to the housing 110. Furthermore, the following procedure can be used.Resin is poured into spaces 122 and 132 of terminal blocks 120 and 130, respectively. Part of the housing 110 is positioned in spaces 122 and 132, joined to terminal blocks 120 and 130, and makes contact with control terminals 121 and 131. A sandwich structure ensures that circuit boards 119a and 119b adhere reliably to the housing 110.

[0047] The circuit board 119a, which is integrally formed with the housing 110 by primary forming, is now formed by using Fig. 8 described.

[0048] Fig. Figure 8 is an incomplete sectional view of the printed circuit board and a layered substrate of the semiconductor device according to the first embodiment.

[0049] Fig. Figure 8 is an incomplete sectional view, taken along the dashed line XX from Fig. 1 was taken. As in Fig. As shown in Figure 8, an end section of the printed circuit board 119a projects from the housing 110 into the interior of the housing section (housing area) 112a, that is, to one side of the layer substrate 140. The projecting end section is formed during a secondary forming process by inserting the printed circuit board 119a through a metal mold. Furthermore, as shown in the Fig. 6 and Fig. As shown in Figure 7, the aligned electrodes 119a1 and the through holes 119a2 of the circuit board 119a are arranged along the projecting end section.

[0050] Step S12 takes as an example a case in which the wiring terminals 116 and 117 are integrally formed during the formation of the housing 110. However, the housing 110 can also be formed by integrally forming the components other than the wiring terminals 116 and 117. In this case, the wiring terminals 116 and 117 are joined at specific positions by welding after the housing 110 has been formed.

[0051] (Step S13) The layer substrates 140 produced in step S11b are placed in the housing 110 formed in step S12. The resin beams 111a and 111b are then attached over the printed circuit boards 119a.

[0052] To be precise, that in Fig. 3. The layered substrate 140 described in section 3 is placed over a copper plate or a heat sink. The housing 110 is adhered to the layered substrate 140, which is placed over the copper plate or heat sink, such that the layered substrate 140, which is placed over the copper plate or heat sink, is housed in each of the housing sections 112a, 112b and 112c of the housing 110, which are located in the Fig. 9 and Fig. As described in section 10, during the assembly process, the conductive connection 143b and the circuit board 145a of the layered substrate 140 are joined to (the back surface) the wiring connection 116 of the housing 110. Furthermore, the circuit board 145b of the layered substrate 140 is joined to (the back surface) the wiring connection 117 of the housing 110. In addition, the conductive connection 143a of the layered substrate 140 is joined to (the back surface) the wiring connection 118 of the housing 110. Afterward, the resin beams 111a and 111b are placed over the circuit boards 119a.

[0053] (Step S14) The control electrodes, such as gate electrodes, of the semiconductor chips 144a, 144b and 144c and the circuit board 119a are connected by wires 148 and the control electrodes, such as gate electrodes, of the semiconductor chips 146a, 146b and 146c and the circuit board 119b are connected by wires 148.

[0054] As a result, the structure of the semiconductor device 100, which is in Fig. 1 is shown, received.

[0055] It is desirable to arrange the semiconductor chips 144a, 144b, and 144c such that each control electrode will be aligned along the circuit board 119a. The same applies to the semiconductor chips 146a, 146b, and 146c. This arrangement simplifies connection via the wires 148. As shown in Fig. As shown in Figure 3, the use of RC-IGBTs as the semiconductor chips 144a, 144b, 144c, 146a, 146b and 146c simplifies the alignment of the control electrodes.

[0056] (Step S15) The layer substrates 140, the printed circuit boards 119a and 119b, the resin beams 111a and 111b, the wiring terminals 116, 117 and 118, the wires 148 and the like in the concavity of the housing 110 are sealed by using sealing resin and the sealing resin is cured. As a result, the semiconductor device 100 is completed.

[0057] At this point, resin can be poured into cavities 122 and 132 of terminal blocks 120 and 130, respectively, to seal the control terminals 121 and 131 within these cavities. Sealing in this manner improves the adhesion of the control terminals 121 and 131 to the printed circuit boards 119a and 119b. Furthermore, when terminal blocks 120 and 130 are sealed, the height difference sections 123 and 133 of terminal blocks 120 and 130 can also be coated with resin. This presses the terminal blocks 120 and 130 against the printed circuit boards 119a and 119b, further increasing the reliability of the adhesion of the control terminals 121 and 131 to the printed circuit boards 119a and 119b. Accordingly, the positions of elevation difference sections 123 and 133 are not based on those in Fig. The options shown in Figure 4 are limited. There is no restriction on the positions of the height difference sections 123 and 133, as long as they are formed on surfaces perpendicular to the surfaces of the terminal blocks 120 and 130, which are opposite the circuit board 119a. Furthermore, each of the height difference sections 123 and 133 can be formed on multiple surfaces, not just one. Epoxy resin, for example, can be used as the sealing resin.

[0058] A circuit structure in the above semiconductor device 100 is now implemented by using the Fig. 1, Fig. 3 and Fig. 11 described.

[0059] Fig. Figure 11 is a circuit diagram that represents a circuit structure in the semiconductor device according to the first embodiment.

[0060] In the layer substrate 140 in the accommodation section 112a of the semiconductor device 100 ( Fig. 1 and Fig. 3) The conductive terminal 143a, which is electrically connected to the P terminal 113a via the wiring terminal 118, is electrically connected to the collector electrodes of the semiconductor chips 144a, 144b and 144c via the circuit board 142a. The wiring terminal 116 is electrically wired to the circuit board 145a, which is electrically connected to the emitter electrodes of the semiconductor chips 144a, 144b and 144c, and is electrically connected to the U terminal 115a.

[0061] The conductive terminal 143b is electrically connected to the wiring terminal 116, which is electrically connected to the U terminal 115a, and is electrically connected to the collector electrodes of the semiconductor chips 146a, 146b, and 146c via the circuit board 142b. The wiring terminal 117 is electrically wired to the circuit board 145b, which is electrically connected to the emitter electrodes of the semiconductor chips 146a, 146b, and 146c, and is electrically connected to the N terminal 114a.

[0062] Furthermore, in the layer substrate 140 in the accommodation section 112b of the semiconductor device 100 ( Fig. 1 and Fig. 3) The conductive terminal 143a, which is electrically connected to the P terminal 113b via the wiring terminal 118, is electrically connected to the collector electrodes of the semiconductor chips 144a, 144b and 144c via the circuit board 142a. The wiring terminal 116 is electrically wired to the circuit board 145a, which is electrically connected to the emitter electrodes of the semiconductor chips 144a, 144b and 144c, and is electrically connected to the V terminal 115b.

[0063] The conductive terminal 143b is electrically connected to the wiring terminal 116, which is electrically connected to the V terminal 115b, and is electrically connected to the collector electrodes of the semiconductor chips 146a, 146b, and 146c via the circuit board 142b. The wiring terminal 117 is electrically wired to the circuit board 145b, which is electrically connected to the emitter electrodes of the semiconductor chips 146a, 146b, and 146c, and is electrically connected to the N terminal 114b.

[0064] Furthermore, in the layer substrate 140 in the accommodation section 112c of the semiconductor device 100 ( Fig. 1 and Fig. 3) The conductive terminal 143a, which is electrically connected to the P terminal 113c via the wiring terminal 118, is electrically connected to the collector electrodes of the semiconductor chips 144a, 144b and 144c via the circuit board 142a. The wiring terminal 116 is electrically wired to the circuit board 145a, which is electrically connected to the emitter electrodes of the semiconductor chips 144a, 144b and 144c, and is electrically connected to the W terminal 115c.

[0065] The conductive terminal 143b is electrically connected to the wiring terminal 116, which is electrically connected to the W terminal 115c, and is electrically connected to the collector electrodes of the semiconductor chips 146a, 146b, and 146c via the circuit board 142b. The wiring terminal 117 is electrically wired to the circuit board 145b, which is electrically connected to the emitter electrodes of the semiconductor chips 146a, 146b, and 146c, and is electrically connected to the N terminal 114c.

[0066] By applying the above structure, the in Fig. The circuit shown in 11 is formed in the semiconductor device 100.

[0067] In a state where the positive electrode is connected to the P terminal 113a and the negative electrode is connected to the N terminal 114a, control signals are input to or output from external circuits via control terminals 121 and 131 and circuit boards 119a and 119b. These control signals are output via circuit boards 119a and 119b and wires 148 to the gate electrodes of semiconductor chips 144a, 144b, and 144c, and semiconductor chips 146a, 146b, and 146c. An output is received from terminal 115a in accordance with the control signals.

[0068] In a state where the positive electrode is connected to the P terminal 113b and the negative electrode is connected to the N terminal 114b, control signals are input or output via control terminals 121 and 131 and circuit boards 119a and 119b. These control signals are output via circuit boards 119a and 119b and wires 148 to the gate electrodes of semiconductor chips 144a, 144b, and 144c, and semiconductor chips 146a, 146b, and 146c. An output is received from V terminal 115b in accordance with the control signals.

[0069] In a state where the positive electrode is connected to the P terminal 113c and the negative electrode is connected to the N terminal 114c, control signals are input or output via control terminals 121 and 131 and circuit boards 119a and 119b. Based on these control signals, control signals are output via circuit boards 119a and 119b and wires 148 to the gate electrodes of semiconductor chips 144a, 144b, and 144c and semiconductor chips 146a, 146b, and 146c. An output is received from the W terminal 115c based on the control signals.

[0070] A semiconductor device other than semiconductor device 100 is now used as a reference example by means of Fig. 12 described.

[0071] Fig. Figure 12 is a top view of a semiconductor device, which is taken as a reference example.

[0072] A semiconductor device 300 includes a housing 310 and three layer substrates 320, which are housed in a housing section 330 formed in a central area of ​​the housing 310.

[0073] The housing 310 is formed by injection molding using resin. Control terminals 311, control electrodes 312, which are electrically connected to the control terminals 311, P terminals 313a, 313b and 313c, N terminals 314a, 314b and 314c, a U terminal 315a, a V terminal 315b and a W terminal 315c are integrally formed.

[0074] The layered substrate 320 includes a radiation plate (not shown) formed over a bottom surface of an insulating substrate 321, and circuit boards 322a, 322b, 322c, 322d, 322e, and 322f formed over a top surface of the insulating substrate 321. Furthermore, semiconductor chips 323a and 323c and semiconductor chips 323b and 323d are arranged over circuit boards 322b and 322f, respectively, with solder between them.

[0075] The above layer substrate 320 is housed in the accommodation section 330 of the housing 310. The control electrodes 312, the circuit boards 322a, 322c and 322d and main terminals of the semiconductor chips 323a, 323b, 323c and 323d are connected by wires 324.

[0076] As in Fig. As shown in Figure 12, in the semiconductor device 300 above, the wiring is routed from the control electrodes 312, which are electrically connected to the control terminals 311, to the circuit boards 322c and 322d to input control signals to the semiconductor chips 323a, 323b, 323c, and 323d. Furthermore, ten wires 324 are connected to each of the semiconductor chips 323a, 323b, 323c, and 323d. This wiring is complex. Such wiring impairs assembly and increases the labor hours required for wiring. Additionally, in the wiring of a control signal system, a magnetic field or similar generated during switching can, depending on the routing method, affect the product characteristics. Consequently, a malfunction may occur.

[0077] In the semiconductor device 100, the circuit boards 119a and 119b are arranged in the circumferential sections of the housing sections 112a, 112b, and 112c of the housing 110, in which the layer substrates 140 are housed. The terminal blocks 120 and 130, which hold the control terminals 121 and 131 respectively and output control signals to the circuit boards 119a and 119b, are arranged above the circuit boards 119a and 119b. The gate electrodes of the semiconductor chips 144a, 144b, and 144c and the semiconductor chips 146a, 146b, and 146c and the circuit board 119a and 119b, respectively, are electrically connected by the wires 148.

[0078] This leads to a simplification of the wiring in the control signal system of the semiconductor device 100. Accordingly, the wiring routing and bundling are easily controlled. As a result, assembly is improved, and the number of man-hours required for wiring is reduced. Furthermore, complicated routing is avoided, incorrect wiring is prevented, and the number of parts, such as circuit diagrams and electrode pads, is reduced. Consequently, the semiconductor device 100 is miniaturized. Since wiring simplification and uniformity are implemented in the control signal system of the semiconductor device 100, the influence of a magnetic field or similar, generated during switching, on the product characteristics is mitigated, and the occurrence of malfunctions is prevented. (Second embodiment)

[0079] In a second embodiment, a different semiconductor device is used by means of Fig. 13 described.

[0080] Fig. Figure 13 is a perspective view of a semiconductor device according to a second embodiment.

[0081] In a semiconductor device 200, a busbar block 210 is formed by integrally forming the wiring connections 116 and 117 of the semiconductor device 100 according to the first embodiment ( Fig. 1) is formed, mounted in a concavity in the central area.

[0082] The structure, with the exception of the wiring connections 116 and 117, of a package 110 of the semiconductor device 200 is identical to that of the package 110 of the semiconductor device 100. The layer substrates 140 in the semiconductor device 200 are structurally identical to the layer substrates 140 in the semiconductor device 100.

[0083] Furthermore, the circuit structure in the semiconductor device 200 is identical to the circuit structure in the semiconductor device 100 according to the first embodiment ( Fig. 11).

[0084] A method for manufacturing the above semiconductor device 200 is described by using Fig. 14 described.

[0085] Fig. Figure 14 is a flowchart of a process for manufacturing the semiconductor device according to the second embodiment.

[0086] (Step S21) Printed circuit boards 119a and 119b and terminal blocks 120 and 130 are manufactured (step S21a). Furthermore, the layer substrates 140 are manufactured (step S21b). Additionally, the busbar block 210 is manufactured (step S21c). In step S21a, control terminals 121 and 131 of terminal block 120 and 130, respectively, are pressed into printed circuit boards 119a and 119b to hold the printed circuit boards 119a and 119b to one underside of terminal blocks 120 and 130.

[0087] The structure of the layer substrates 140 ( Fig. 3) and the structure of connection blocks 120 and 130 ( Fig. 4 to 7) are described in the first embodiment.

[0088] Busbar block 210 is operated using Fig. 15 described.

[0089] Fig. Figure 15 is a top view of the busbar block of the semiconductor device according to the second embodiment.

[0090] The busbar block 210 is formed using resin. For example, more than one frame is combined to form a framework so that it fits into the concavity in the central area of ​​the semiconductor device 200. Furthermore, the wiring connections 116 and 117, corresponding to the housing sections 112a, 112b and 112c, are integrally formed, for example, on a rear surface of the frames combined in this way.

[0091] (Step S22) The housing 110 is formed by integrally forming the printed circuit boards 119a and 119b, the terminal blocks 120 and 130, wiring terminals 118, P terminals 113a, 113b and 113c, N terminals 114a, 114b and 114c, a U terminal 115a, a V terminal 115b and a W terminal 115c using resin.

[0092] That is, the housing 110 formed in step S22 corresponds to the housing 110 in the first embodiment, which is described in the Fig. 9 and Fig. 10 is shown and from which the wiring connections 116 and 117 and the resin beams 111a and 111b have been removed.

[0093] (Step S23) The layer substrates 140 produced in step S21b are placed in the housing 110 formed in step S22.

[0094] To be precise, that in Fig. 3. The layered substrate 140 described in step 2 is placed over a copper plate or a heat sink. The housing 110 is adhered to the layered substrate 140, which is placed over the copper plate or heat sink, so that the layered substrate 140, which is placed over the copper plate or heat sink, is housed in each of the housing sections 112a, 112b and 112c of the housing 110 formed in step 22. At this point, a conductive terminal 143a of the layered substrate 140 in the housing section 112a is joined to the wiring terminal 118, which is electrically connected to the P terminal 113a. A conductive connection 143a of the layer substrate 140 in the accommodation section 112b is joined to the wiring connection 118, which is electrically connected to the P connection 113b.A conductive connection 143a of the layer substrate 140 in the accommodation section 112c is joined to the wiring connection 118, which is electrically connected to the P connection 113c.

[0095] (Step S24) Semiconductor chips 144a, 144b and 144c and semiconductor chips 146a, 146b and 146c and the circuit board 119a or 119b are connected by wires 148.

[0096] The connection through wires 148 is now made by using Fig. 16 described.

[0097] Fig. Figure 16 is a top view of the housing of the semiconductor device according to the second embodiment, in which insulating substrates are housed.

[0098] As in Fig. As shown in Figure 16, the gate electrodes of the semiconductor chips 144a, 144b and 144c and the circuit board 119a are connected by the wires 148 and the gate electrodes of the semiconductor chips 146a, 146b and 146c and the circuit board 119b are connected by the wires 148.

[0099] (Step S25) The busbar block 210 produced in step S21c ( Fig. 15) is mounted in the concavity in the central area of ​​the housing 110 obtained in this way. The layer substrates 140 are housed in the housing 110, and the semiconductor chips 144a, 144b, and 144c, and the semiconductor chips 146a, 146b, and 146c, and the printed circuit board 119a or 119b, are connected by the wires 148. Next, the wiring terminals 116 are joined to conductive terminals 143b and printed circuit boards 145a by welding, and the wiring terminals 117 are joined to printed circuit boards 145b by welding.

[0100] At this point, in housing section 112a, the wiring terminal 116 of the busbar block 210 is electrically connected to the conductive terminal 143b and the circuit board 145a of the layered substrate 140, and is electrically connected to the U-terminal 115a. Furthermore, the wiring terminal 117 of the busbar block 210 is electrically connected to the circuit board 145b of the layered substrate 140.

[0101] Furthermore, in housing section 112b, the wiring connection 116 of the busbar block 210 is electrically connected to the conductive connection 143b and the circuit board 145a of the layered substrate 140, and is electrically connected to the V-connection 115b. Additionally, the wiring connection 117 of the busbar block 210 is electrically connected to the circuit board 145b of the layered substrate 140.

[0102] Furthermore, in housing section 112c, the wiring terminal 116 of the busbar block 210 is electrically connected to the conductive terminal 143b and the circuit board 145a of the layered substrate 140, and is electrically connected to the W terminal 115c. Additionally, the wiring terminal 117 of the busbar block 210 is electrically connected to the circuit board 145b of the layered substrate 140.

[0103] The structure of the semiconductor device 200, which is in Fig. The figure shown in 13 is obtained in this way.

[0104] (Step S26) The layer substrates 140, the printed circuit boards 119a and 119b, the wires 148, the busbar block 210, and the like in the concavity of the housing 110 are sealed using sealing resin, and the sealing resin is cured. As a result, the semiconductor device 200 is completed.

[0105] As described, in the semiconductor device 200, the printed circuit boards 119a and 119b are arranged in the circumferential sections of the housing sections 112a, 112b, and 112c of the housing 110, in which the layer substrates 140 are housed. The terminal blocks 120 and 130, which hold the control terminals 121 and 131 respectively and output control signals to the printed circuit boards 119a and 119b, are arranged above the printed circuit boards 119a and 119b. The gate electrodes of the semiconductor chips 144a, 144b, and 144c and the printed circuit board 119a are electrically connected by the wires 148, and the gate electrodes of the semiconductor chips 146a, 146b, and 146c and the printed circuit board 119b are electrically connected by the wires 148.

[0106] This leads to a simplification of the wiring in the control signal system of the semiconductor device 200. Accordingly, the wiring routing and bundling are easily controlled. As a result, assembly is improved, and the number of man-hours required for wiring is reduced. Furthermore, complicated routing is avoided, incorrect wiring is prevented, and the number of parts, such as circuit diagrams and electrode pads, is reduced. Consequently, the semiconductor device 200 is miniaturized. Since wiring simplification and uniformity are implemented in the control signal system of the semiconductor device 200, the influence of a magnetic field or similar, generated during switching, on the product characteristics is mitigated, and the occurrence of malfunctions is prevented.

[0107] Furthermore, in the semiconductor device 200, the wiring connections 116 and 117 are fitted into the housing sections 112a, 112b, and 112c simply by mounting the busbar block 210 with the wiring connections 116 and 117 in the concavity in the central area of ​​the semiconductor device 200. Consequently, the assembly of the wiring connections 116 and 117 is improved, and the labor hours required for assembly are reduced. Since the semiconductor device 200 incorporates the busbar block 210, its rigidity is also improved, and deformation of the semiconductor device 200 due to bending or twisting caused by external vibrations or similar factors is minimized. This prevents shock, damage or the like of the semiconductor chips 144a, 144b and 144c and the semiconductor chips 146a, 146b and 146c in the semiconductor device 200.

[0108] According to the disclosed techniques, a wiring connection is simplified.

Claims

[1] Semiconductor device (100; 200) comprising the following: a layered substrate (140) comprising an insulating substrate (141) and a circuit board (142a, 142b) arranged over a front surface of the insulating substrate (141); a semiconductor chip (144a-c, 146a-c) that is arranged above the circuit board (142a, 142b); a housing (110) with a storage area (112a) for housing the layer substrate (140) and the semiconductor chip (144a-c, 146a-c); a terminal block (120, 130) having a first surface and a second surface opposite the first surface and holding external connection terminals (121, 131) projecting from the first surface and the second surface; and a printed circuit board (119a-b) having a first main plane and a second main plane opposite the first main plane is arranged over a perimeter of the accommodation area (112a), is held on the second surface side of the terminal block (120, 130), is electrically connected by a connecting element (148) to a control electrode (144ac, 144bc, 144cc, 146ac, 146bc, 146cc) of the semiconductor chip (144a-c, 146a-c) and is connected to the external connection terminals (121, 131), wherein the printed circuit board (119a-b) is inserted between the second surface of the terminal block (120, 130) and the housing (110) in such a way that the printed circuit board (119a-b) is arranged directly on the housing (110) and the second surface of the terminal block (120, 130) is arranged on the printed circuit board (119a-b), wherein: the connecting block (120, 130) has a third surface between the first surface and the second surface, which connects to the first surface; and at least one of the second surface and the third surface is joined to the housing (110), wherein: the connecting block (120, 130) has a height difference (123, 133) on the third surface and a part of the housing (110) is arranged on a first surface side of the height difference (123, 133). [2] Semiconductor device (100) according to claim 1, wherein the printed circuit board (119a) is held on the second surface side of the terminal block (120, 130) by pressing the external connection terminals (121, 131) into the printed circuit board (119a). [3] Semiconductor device (100) according to claim 2, wherein the circuit board (119a) has several through holes (119a2) and is joined to the housing at the several through holes (119a2). [4] Semiconductor device (100) according to claim 3, wherein an end section of the printed circuit board (119a) protrudes from the housing (110) into an interior of the accommodation area (112a). [5] Semiconductor device (100) according to claim 2, wherein: the terminal block (120, 130) is arranged on a first main plane side of the printed circuit board (119a-b); End sections of the external connection terminals (121, 131) are exposed or protrude on a second main plane side of the printed circuit board (119a-b) and are in contact with the housing (110). [6] Semiconductor device (100) according to claim 2, wherein: the terminal block (120, 130) has projections on the second surface side that define a space (122, 132) between the terminal block (120, 130) and the printed circuit board (119a); and / or a part of the housing (110) is arranged in the space (122, 132), is joined to the terminal block (120, 130) and is in contact with the external connection terminals (121, 131). [7] Semiconductor device (100) according to claim 1, wherein: the semiconductor chip (144a-c, 146a-c) which is included in the semiconductor device is provided several times; the semiconductor chips (144a-c, 146a-c) are arranged above the circuit board (142a, 142b) of the layered substrate (140) along the circuit board (119a-b) and Control electrodes (144ac, 144bc, 144cc, 146ac, 146bc, 146cc) of the semiconductor chips (144a-c, 146a-c) are arranged along the circuit board (119a-b) and are electrically connected to the circuit board (119a-b). [8] Semiconductor device (100) according to claim 7, further comprising wiring connections (116-118) arranged along the circuit board (119a-b) and connected to main electrodes of each of the semiconductor chips (144a-c, 146a-c). [9] Semiconductor device (200) according to claim 8, further comprising a busbar block (210) that fits within the circumference covering the accommodation area (112a) and having the wiring connections (116-118). [10] Semiconductor device manufacturing process comprising the following: Produce: a terminal block (120, 130) having a first surface and a second surface opposite the first surface and holding external connection terminals (121, 131) projecting from the first surface and the second surface; and a printed circuit board (119a, b) having a first principal plane and a second principal plane opposite the first principal plane; and Pressing the external connection terminals (121, 131) into the printed circuit board (119a, b), arranging heated resin around the terminal block (120, 130) while holding the printed circuit board (119a-b) on the second face side of the terminal block (120, 130), and integrally forming the terminal block (120, 130) and the printed circuit board (119a-b) to form a housing (110; 130). [11] Semiconductor device manufacturing method according to claim 10, wherein the printed circuit board (119a-b) is held on the second surface side of the terminal block (120, 130) by pressing the external connection terminals (121, 131) into the printed circuit board (119a-b). [12] Semiconductor device manufacturing method according to claim 11, wherein, during integral forming of the terminal block (120, 130) and the printed circuit board (119a-b), the terminal block (120, 130) is arranged on a first main plane side of the printed circuit board (119a-b) and end sections of the external connection terminals (121, 131) are exposed or protrude on a second main plane side of the printed circuit board (119a-b) and are in contact with the resin. [13] Semiconductor device manufacturing process according to claim 11, further comprising: Produce: a layered substrate (140) comprising an insulating substrate (141) and a circuit board (142a-b) formed over a front surface of the insulating substrate (141); and a semiconductor chip (144a-c, 146a-c); placing the layer substrate (140) in a placement area (112a) of the housing (110); arranging the semiconductor chip (144a-c, 146a-c) over the circuit board (119a-b) and Connecting a control electrode (144ac, 144bc, 144cc, 146ac, 146bc, 146cc) of the semiconductor chip (144a-c, 146a-c) and the circuit board (119a-b) by means of a conductive connecting element (148). [14] Semiconductor device (100; 200) comprising the following: a layered substrate (140) comprising an insulating substrate (141) and a circuit board (142a, 142b) arranged over a front surface of the insulating substrate (141); a semiconductor chip (144a-c, 146a-c) that is arranged above the circuit board (142a, 142b); a housing (110) with a storage area (112a) for housing the layer substrate (140) and the semiconductor chip (144a-c, 146a-c); a terminal block (120, 130) having a first surface and a second surface opposite the first surface and holding external connection terminals (121, 131) projecting from the first surface and the second surface; and a printed circuit board (119a-b) having a first main plane and a second main plane opposite the first main plane is arranged over a perimeter of the accommodation area (112a), is held on the second surface side of the terminal block (120, 130), is electrically connected by a connecting element (148) to a control electrode (144ac, 144bc, 144cc, 146ac, 146bc, 146cc) of the semiconductor chip (144a-c, 146a-c) and is connected to the external connection terminals (121, 131), wherein the printed circuit board (119a-b) is inserted between the second surface of the terminal block (120, 130) and the housing (110) in such a way that the printed circuit board (119a-b) is arranged directly on the housing (110) and the second surface of the terminal block (120, 130) is arranged on the printed circuit board (119a-b), wherein: the terminal block (120, 130) has projections on the second surface side that define a space (122, 132) between the terminal block (120, 130) and the printed circuit board (119a); and / or a part of the housing (110) is arranged in the space (122, 132), is joined to the terminal block (120, 130) and is in contact with the external connection terminals (121, 131).

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