FINFET device with carbon-doped regions under gate spacers and formation method

Abstract

Method comprising: Depositing a dummy gate (70, 76) over and along sidewalls of a fin (36, 56) extending upwardly from a semiconductor substrate (32, 50); Forming a first gate spacer (80) along a sidewall of the dummy gate (70, 76); plasma doping the first gate spacer (80) with carbon to form a carbon-doped gate spacer (80B); Forming a source / drain region (42, 44, 82, 84) adjacent to a channel region (108, 112) of the fin (36, 56); and Diffusing carbon from the carbon-doped gate spacer (80B) into a first region of the fin (36, 56) to provide a first carbon-doped region (106, 110), the first carbon-doped region (106, 110) being disposed between at least a portion of the source / drain region (42, 44, 82, 84) and the channel region (108, 112) of the fin (36, 56); wherein forming the source / drain region (42, 44, 82, 84) comprises etching a second portion of the rib (36, 56) to provide a recess (102, 104) adjacent to the first portion of the rib (36, 56), the method further comprising plasma doping the recess (102, 104) with carbon to form a second carbon-doped region (107, 111) along sidewalls and a bottom surface of the recess (102, 104).

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by depositing insulating or dielectric layers, conductive layers, and semiconductor layers of various materials one after the other over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0002] The semiconductor industry is improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, reducing the minimum feature size creates additional problems that need to be addressed.

[0003] The publication US 2016 / 0 042 952 A1 discloses a manufacturing method for producing a semiconductor component, wherein spacers are doped with carbon to increase the etch resistance.

[0004] The publication US 2015 / 0 102 393 A1 discloses a manufacturing method for producing a semiconductor device, wherein a carbon-doped silicon layer is grown epitaxially in a source / drain trench in order to interrupt a crystal structure of the fin for the growth of the source / drain regions and to prevent the epitaxial growth of structures with multiple facets.

[0005] The patent US 9 202 920 B1 discloses a manufacturing method for producing a semiconductor device, wherein a delta-doped buffer is formed in a source / drain recess, which buffer may have a large amount of boron atoms and a smaller amount of carbon atoms.

[0006] The publication US 2009 / 0 273 034 A1 discloses a manufacturing method for producing a semiconductor device, wherein source / drain regions are carbon-doped in order to reduce diffusion of boron from the source / drain regions into the channel region.

[0007] US 2005 / 0164461 A1 discloses a method for forming a junction region of a semiconductor device. A gate structure is formed on a semiconductor substrate, and a dopant is implanted into the semiconductor substrate to form the junction region. An insulating layer is formed on the gate structure and the semiconductor substrate, and a carbon-containing plasma treatment is performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 is a perspective view of a fin field effect transistor ("FinFET") device according to some embodiments. The Fig. 2-5 are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 6A and Fig. 6B are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 7A, Fig. 7B and Fig. 7C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 8A, Fig. 8B and Fig. 8C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 9A, Fig. 9B and Fig. 9C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 10A, Fig. 10B and Fig. 10C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. Fig. 10D is a cross-sectional view of a FinFET device in a process chamber according to some embodiments. The Fig. 11A, Fig. 11B and Fig. 11C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 12A, Fig. 12B and Fig. 12C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 13A, Fig. 13B and Fig. 13C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 14A, Fig. 14B and Fig. 14C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 15A, Fig. 15B and Fig. 15C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 16A, Fig. 16B and Fig. 16C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. Fig. 17 is a cross-sectional view of an intermediate stage in the fabrication of a FinFET device according to some embodiments. The Fig. 18A, Fig. 18B and Fig. 18C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 19A, Fig. 19B and Fig. 19C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 20A, Fig. 20B and Fig. 20C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 21A, Fig. 21B and Fig. 21C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. Fig. 22 is a cross-sectional view of an intermediate stage in the fabrication of a FinFET device according to some embodiments. The Fig. 23A, Fig. 23B and Fig. 23C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 24A, Fig. 24B and Fig. 24C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 25A, Fig. 25B and Fig. 25C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 26A, Fig. 26B and Fig. 26C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 27A and Fig. 27B are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 28 and Fig. 29 are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments DETAILED DESCRIPTION

[0009] Semiconductor methods and a corresponding semiconductor device that address the above-mentioned problems are provided by claims 1, 8, and 15. The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, forming a first element over or on top of a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first element and the second element such that the first and second elements need not be in direct contact.Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, impose any relationship between the various described embodiments and / or configurations.

[0010] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to other element(s) or feature(s) as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0011] Fig. 1 shows an example of a fin field-effect transistor (FinFET) 30 in a three-dimensional view. The FinFET 30 includes a fin 36 on a substrate 32. The substrate 32 has isolation regions 34, and the fin 36 protrudes above and lies between adjacent isolation regions 34. A gate dielectric 38 is disposed along sidewalls and above a top surface of the fin 36, and a gate electrode 40 is disposed above the gate dielectric 38. Source / drain regions 42 and 44 are disposed on opposite sides of the fin 36 with respect to the gate dielectric 38 and the gate electrode 40. Fig. 1 further shows reference cross-sections used in later figures. Cross-section AA lies over a channel, the gate dielectric 38, and the gate electrode 40 of the FinFET 30. Cross-section CC lies in a plane parallel to cross-section AA and is located outside the channel by the fin 36. Cross-section BB is perpendicular to cross-section AA and lies along a longitudinal axis of the fin 36 and in the direction of, for example, a current flow between the source / drain regions 42 and 44. The subsequent figures refer to these reference cross-sections for clarity.

[0012] Some embodiments described herein are described in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects used in planar devices, such as planar FETs.

[0013] The fins can be patterned by any suitable method. For example, the fins can be patterned using one or more photolithography techniques, such as double-patterning or multiple-patterning techniques. Generally, double-patterning or multiple-patterning techniques combine photolithography and self-aligned techniques so that structures can be created that have, for example, center-to-center pitches that are smaller than those otherwise obtained with a single, direct photolithography technique. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography technique. Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned technique.The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to structure the ribs.

[0014] The Fig. 2 to 29 are cross-sectional views of intermediate stages in the fabrication of FinFETs according to an exemplary embodiment. Fig. 2 to 5, 28 and 29 show the Fig. 1 shown reference cross-section AA, but with multiple FinFETs. In the Fig. 6 to 27B, figures ending with an "A" designation are shown along a similar cross-section to AA; figures ending with a "B" designation are shown along a similar cross-section to BB; and figures ending with a "C" designation are shown along a similar cross-section to CC. Fig. 17 and Fig. 22 show the Fig. 1 shown reference cross-section CC.

[0015] Fig. 2 shows a substrate 50. The substrate 50 may be a semiconductor substrate, for example, a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate comprises a layer of a semiconductor material formed on an insulator layer. The insulator layer may, for example, be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0016] The substrate 50 has a first region 100A and a second region 100B. The first region 100A may be used to form n-type devices, such as NMOS transistors, e.g., n-FinFETs. The second region 100B may be used to form p-type devices, such as PMOS transistors, e.g., p-FinFETs. The divider 15 between the first region 100A and the second region 100B indicates a physical separation between the first region 100A and the second region 100B. Components of the first region 100A may be physically separated from components of the second region 100B, but are shown side by side in the following figures for illustrative purposes.

[0017] Fig. 2 also shows the formation of a mask 53 over the substrate 50. In some embodiments, the mask 53 may be used in a subsequent etching step to pattern the substrate 50 (see Fig. 3). As in Fig. 2, the mask 53 may include a first mask layer 53A and a second mask layer 53B. The mask layer 53A may be a hard mask layer such as silicon nitride or the like and may be formed using any suitable method, such as deposition, atomic layer deposition (ALD), or physical vapor deposition (PVD). The mask layer 53A may be used to prevent or minimize etching of the substrate 50 underlying the mask layer 53A in the subsequent etching step (see Fig. 3). Mask layer 53B may include photoresist and, in some embodiments, may be used to pattern mask layer 53A for use in the subsequent etching step described above. Mask layer 53B may be formed using a spin-coating technique and may be patterned using suitable photolithography techniques. In some embodiments, three or more masks 53 may be used.

[0018] Fig. 3 shows the formation of semiconductor stripes 52 in the substrate 50. First, the mask layers 53A and 53B may be patterned, with openings in the mask layers 53A and 53B exposing regions of the substrate 50 where trenches will be formed. Next, an etching process may be performed, in which the etching process creates trenches in the substrate 50 through openings in the mask 53. The remaining portions of the substrate 50 underlying the patterned mask 53 form a plurality of semiconductor stripes 52. The etching may be any suitable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching may be anisotropic.

[0019] In Fig. 4, an insulating material is formed between adjacent semiconductor strips 52 to form insulating regions 54. The insulating material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-bake to convert it to another material, such as an oxide), the like, or a combination thereof. Other insulating materials formed by any suitable method may be used.

[0020] Furthermore, in some embodiments, the isolation regions 54 may include a conformal liner (not shown) formed on sidewalls and a bottom surface of the trenches 55 (see Fig. 3) before the trenches 55 are filled with an insulating material of the isolation regions 54. In some embodiments, the liner may comprise a semiconductor nitride (e.g., a silicon nitride), a semiconductor oxide (e.g., a silicon oxide), a thermal semiconductor oxide (e.g., a thermal silicon oxide), a semiconductor oxynitride (e.g., a silicon oxynitride), a polymer dielectric, combinations thereof, and the like. Forming the liner may comprise any suitable method, such as ALD, CVD, high-density plasma (HDP) CVD, PVD, and the like. In such embodiments, the liner may prevent (or at least reduce) the diffusion of semiconductor material of the semiconductor stripes 52 (e.g., Si and / or Ge) into the surrounding isolation regions 54 during the subsequent annealing of the isolation regions 54.For example, after the deposition of the insulation regions 54, an annealing process may be applied to the insulation material of the insulation regions 54.

[0021] Furthermore, in Fig. 4, a planarization process, such as chemical mechanical polishing (CMP), may remove any excess insulation material and form coplanar upper surfaces of the isolation regions 54 and the upper surface of the semiconductor stripes 52. In some embodiments, the CMP may also remove the mask 53. In other embodiments, the mask 53 may be removed using a wet cleaning process separate from the CMP.

[0022] Fig. 5 shows the deepening of the isolation regions 54 to form shallow trench isolation (STI) regions 54. The isolation regions 54 are deepened such that ridges 56 protrude between adjacent isolation regions 54 in the first region 100A and the second region 100B. Furthermore, the upper surfaces of the isolation regions 54 may have a flat surface as shown, a convex surface, a concave surface (such as concavities), or a combination thereof. The upper surfaces of the isolation regions 54 may be formed flat, convex, and / or concave by a suitable etching. The isolation regions 54 may be deepened using a suitable etching process that is, for example, selective for the material of the isolation regions 54. For example, chemical removal of the oxide can be used using a CERTAS® etch or a SICONI tool from Applied Materials or dilute hydrofluoric acid (dHF).

[0023] A person skilled in the field will easily understand that with reference to the Fig. 2 to 5 is only one example of how the fins 56 may be formed. In further embodiments, a dielectric layer may be formed over a top surface of the substrate 50; trenches may be etched through the dielectric layer; homoepitaxial structures may be grown epitaxially in the trenches; and the dielectric layer may be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. In still further embodiments, heteroepitaxial structures may be used for the fins. For example, the semiconductor stripes 52 in Fig. 4, and a material different from the semiconductor stripes 52 may be epitaxially grown in their place. In yet another embodiment, a dielectric layer may be formed over a top surface of the substrate 50; trenches may be etched through the dielectric layer; heteroepitaxial structures may be epitaxially grown in the trenches using a material different from the substrate 50; and the dielectric layer may be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the ridges 56. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the grown materials may be doped in situ during growth, which may eliminate the need for prior and subsequent implantations, although in situ and implantation doping may be used together.Furthermore, it may be advantageous to epitaxially grow a material in an NMOS region that differs from the material in a PMOS region. In various embodiments, the fins 56 may be silicon germanium (Si. x Ge 1-x , where x can be between about 0 and 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, available materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0024] In the Fig. 6A and Fig. 6B, a dummy dielectric layer 58 is formed on the fins 56. The dummy dielectric layer 58 may, for example, be made of silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited according to suitable techniques (e.g., using CVD, PVD, or the like) or thermally grown (e.g., using thermal oxidation or the like). A dummy gate layer 60 is formed over the dummy dielectric layer 58, and a mask layer 62 is formed over the dummy gate layer 60. The dummy gate layer 60 may be deposited over the dummy dielectric layer 58 and then planarized, for example, by a CMP. The mask layer 62 may be deposited over the dummy gate layer 60.The dummy gate layer 60 may be made of polysilicon, for example, although other materials that exhibit high etch selectivity with respect to the etching of the isolation regions 54 may also be used. The mask layer 62 may, for example, comprise silicon nitride or the like. In this example, a single dummy gate layer 60 and a single mask layer 62 are formed over the first region 100A and the second region 100B. In other embodiments, separate dummy gate layers may be formed in the first region 100A and the second region 100B, and separate mask layers may be formed in the first region 100A and the second region 100B.

[0025] In the Fig. 7A, Fig. 7B and Fig. 7C, the mask layer 62 may be patterned using suitable photolithography and etching techniques to form a mask 72 in the first region 100A and a mask 78 in the second region 100B. The pattern of the masks 72 and 78 may then be transferred to the dummy gate layer 60 using a suitable etching technique to form dummy gates 70 in the first region 100A and dummy gates 76 in the second region 100B. Optionally, the pattern of the masks 72 and 78 may be transferred to the dummy dielectric layer 58 in a similar manner. The pattern of the dummy gates 70 and 76 covers corresponding channel regions of the fins 56, while the source / drain regions of the fins 56 are exposed. The dummy gates 70 and 76 may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the respective epitaxial fins.

[0026] Furthermore, although not explicitly shown, the masks 72 and 78 may be used to form the dummy gate layer 60 and the optional dummy dielectric layer 58 in cross section AA of the Fig. 1 and Fig. 7A. In particular, the dummy gate layer 60 may be structured such that dummy gates of adjacent FinFET devices in the two regions 100A and 100B are physically separated. For example, the dummy gates 70 and 76 may be physically separated from each other, as may dummy gates of adjacent FinFET devices (not explicitly shown). In other embodiments, other masks (e.g., other than masks 72 and 78) may be used to pattern the dummy gate layer 60 in other cross sections (e.g., cross section AA instead of cross section BB of the Fig. 1, Fig. 7A and Fig. 7B). A size of the dummy gates 70 and 76 and a pitch between the dummy gates 70 and 76 may depend on a region of a die in which the dummy gates are formed. In some embodiments, the dummy gates 70 and 76 may be larger and have a larger pitch when located in an input / output region of a die (where, for example, input / output circuits are arranged) than when located in a logic region of a die (where, for example, logic circuits are arranged).

[0027] In the Fig. 7A, Fig. 7B and Fig. 7C, suitable recesses (not shown) may be formed in the ribs 56, the semiconductor stripes 52, and / or the substrate 50. For example, a p-well may be formed in the first region 100A and an n-well may be formed in the second region 100B.

[0028] The various implantation steps for the various regions 100A and 100B may be performed using photoresist or other masks (not shown). For example, a photoresist is formed over the ridges 56 and the isolation regions 54 in the second region 100B. The photoresist is patterned to expose the second region 100B of the substrate 50, such as a PMOS region. The photoresist may be formed using a spin-coating technique and may be patterned using suitable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is applied to the second region 100B, and the photoresist may serve as a mask to substantially prevent n-type impurities from being implanted into the first region 100A, such as an NMOS region.The n-impurities may be phosphorus, arsenic or the like, which is present at a concentration of 10. 18 cm -3 or less, for example in a range of about 10 17 cm -3 up to about 10 18 cm -3 , is implanted into the first region. After implantation, the photoresist is removed, e.g., by a suitable ashing process.

[0029] After implanting the second region 100B, a photoresist is formed over the ribs 56 and the isolation regions 54 in the second region 100B. The photoresist is patterned to expose the first region 100A of the substrate 50, such as the NMOS region. The photoresist may be formed using a spin-coating technique and may be patterned using suitable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be applied to the first region 100A, and the photoresist may serve as a mask to substantially prevent p-type impurities from being implanted into the second region, such as the PMOS region. The p-type impurities may be boron, BF2, or the like, which may be implanted into the first region to a concentration of 10 18 cm -3 , for example in a range of about 10 17 cm -3 up to about 1018 cm -3 , implanted. After implantation, the photoresist can be removed, for example, by a suitable ashing process.

[0030] After implanting the first region 100A and the second region 100B, an anneal may be performed to activate the implanted p- and n-type impurities. The implants may form a p-well in the first region 50B, e.g., the NMOS region, and an n-well in the second region, e.g., the PMOS region. In some embodiments, the grown materials of the epitaxial fins may be doped in situ during growth, which may obviate the need for implants, although in situ and implant doping may be used together.

[0031] In the Fig. 8A, Fig. 8B and Fig. 8C, a first gate spacer 80 is formed on exposed surfaces of the respective dummy gates 70 and 76 ( Fig. 8A and Fig. 8B) and / or the dummy dielectric layer 58 over the ribs 56 ( Fig. 8C). Any suitable methods may be used to form the first gate spacer 80. In some embodiments, deposition (such as CVD, ALD, or the like) may be used to form the first gate spacer 80. In some embodiments, as shown in Fig. 8A, the first gate spacer may have a thickness T1 of approximately 3 nm. The first gate spacer 80 may comprise any suitable material. In some embodiments, the first gate spacer 80 may comprise a combination of silicon, oxygen, carbon, and nitrogen (e.g., SiOCN).

[0032] In the Fig. 9A, Fig. 9B and Fig. 9C, implantations for lightly doped source / drain (LDD) regions 77 and 79 can be performed. Similar to the above-mentioned Fig. 7A, Fig. 7B and Fig. 7C, a mask (not shown), such as a photoresist, may be formed over the first region 100A, e.g., the NMOS region, while the second region 100B, e.g., the PMOS region, is exposed, and p-type impurities may be implanted into the exposed fins 56 in the second region 100B to form the LDD regions 79. During the implantation of the LDD regions 79, the dummy gate 76 may serve as a mask to prevent (or at least reduce) implantation of the dopants into a channel region of the exposed fins 56. Thus, the LDD regions 79 may be formed substantially in source / drain regions of the exposed fins 56. The mask may then be removed.Subsequently, a mask (not shown), such as a photoresist, may be formed over the second region 100B while the first region 100A is exposed, and n-type impurities may be implanted into the exposed fins 56 in the first region 100A to form the LDD regions 77. During the implantation of the LDD regions 77, the dummy gate 70 may serve as a mask to prevent (or at least reduce) implantation of the dopants into a channel region of the exposed fins 56. Thus, the LDD regions 77 may be formed substantially in source / drain regions of the exposed fins 56. The mask may then be removed. The n-type impurities may be any of the previously described n-type impurities, and the p-type impurities may be any of the p-type impurities described above. The LDD regions 77 and 79 can each have an impurity concentration of about 10. 15 cm -3 up to about 1016 cm -3 Annealing can be used to activate the implanted impurities.

[0033] Next, with reference to the Fig. 10A, Fig. 10B, Fig. 10C and Fig. 10D, a carbon treatment 101 may be applied to the first gate spacer 80. The carbon treatment 101 may incorporate carbon into the first gate spacer 80 (see Fig. 8A-8C), thereby forming a carbon-doped gate spacer 80B. The carbon treatment 101 may contribute to strengthening the first gate spacer 80 by providing the carbon-doped gate spacer 80B with increased etch resistance. Thus, defects on the carbon-doped gate spacer 80B may be removed during subsequent etching processes (e.g., during a replacement gate process to replace the dummy gates 70 / 76 with a functional gate stack, see the Fig. 25A to 26C). In some embodiments, the carbon treatment 101 may further cause the doping of the dummy dielectric 58 with carbon and also reduce an etch rate of the dummy dielectric 58 in subsequent process steps (e.g., during a replacement gate process).

[0034] Referring to FIG. 10D, in some embodiments, the carbon treatment 101 includes placing the wafer on which the FinFET 30 will be formed in a plasma chamber 202 on a wafer chuck 204 beneath an RF coil 206. Any suitable plasma chamber 202 may be used. For example, the VARIAN VIISTA® PLAD from Applied Materials may be suitable for some embodiments. A conformal carbon plasma doping may be applied to the FinFET 30 in the plasma chamber 202 using a gas source and an RF coil configured to generate carbon plasma in the plasma chamber 202. In some embodiments, the gas source generates a gas during the conformal carbon plasma doping. The gas may, in some embodiments, be a hydrocarbon, such as CH4, C2H2, C2H4, or C2H6, delivered at a rate of about 40 standard cubic centimeters per minute (sccm) to about 60 sccm and a dosage of about 1 × 1014 cm -2 up to about 1 × 10 15 cm -2 introduced into the plasma chamber 202 during the carbon treatment 101. In some embodiments, an RF power of about 800 W, a DC bias of about 1 kV to about 3 kV, a pulse width (PW) of about 30 µs to about 60 µs, and a pressure of about 27 mbar (20 mTorr) to about 40 mbar (30 mTorr) may be used in the plasma chamber during the carbon treatment 101. In one embodiment of a conformal carbon plasma doping process, plasma containing carbon ions is generated in the plasma chamber 202. The carbon ions are directed onto the FinFET 30 and implanted into exposed surfaces of the FinFET 30 according to the process parameters of the plasma chamber 202.

[0035] In some embodiments, the use of a conformal carbon plasma doping of the gate spacers 80 may enable more uniform doping in the resulting carbon-doped gate spacer 80B. For example, it may be possible to dope the first gate spacer 80 (see Fig. 8A-8C) using a beam delivery implantation. However, due to the high aspect ratios of some dummy gates and / or fins, a line of sight from the beam delivery to all regions of the first gate spacer 80 may not be available. Therefore, a beam delivery implantation may result in some portions of the first gate spacer 80 remaining undoped, resulting in non-uniform doping of the carbon-doped gate spacer 80B, particularly for aspect ratios (e.g., a height-to-pitch ratio) greater than about 10:1 for the dummy gates and / or fins. Using a conformal carbon plasma doping of the first gate spacer 80 may enable more uniform doping of the first gate spacer 80.For example, after the carbon treatment 101 of the first gate spacer 80, a carbon concentration in the carbon-doped gate spacer 80B may be substantially similar in different portions of the carbon-doped gate spacer 80B. In some embodiments, a carbon concentration in portions of the carbon-doped gate spacer 80B that extend along top surfaces of the dummy gates 70 and 76 may be substantially the same as a carbon concentration of portions of the carbon-doped gate spacer 80B that extend along sidewalls of the dummy gates 70 and 76 and the fin 56.

[0036] In some embodiments, the use of conformal carbon plasma doping of the carbon-doped gate spacer 80B may further provide a high carbon concentration with reduced surface damage to the underlying substrate 50, the semiconductor stripes 52, and / or the fins 56 compared to the beam delivery doping method embodiment. Furthermore, the conformal carbon plasma doping method may not require additional cleaning and / or annealing processes to drive the carbon into the first gate spacer 80, thereby reducing manufacturing costs compared to other embodiments of the method. After the carbon treatment 101, the carbon-doped gate spacer 80B may have increased amounts of carbon compared to the first gate spacer 80.For example, in some embodiments, the carbon concentration in the carbon-doped gate spacer 80B may be about 3 × 10 . 20 cm -3 or more, such as 4 × 10 20 cm -3 up to about 3 × 10 21 cm -3 .

[0037] After the carbon treatment 101, a thin film of carbon 80A may have formed on a surface of the carbon-doped gate spacer 80B, onto which the carbon plasma was incident during the carbon treatment 101. The carbon layer 80A may have a thickness T2 of about 0.5 nm to about 2 nm, as shown in Fig. 10A. In some embodiments, the first gate spacer 80 may have a carbon density gradient after the carbon treatment 101, with a greatest density of carbon present at the surface of the carbon-doped gate spacer 80B into which carbon plasma was incident during the carbon treatment 101, and a smallest density of carbon present at the surface of the carbon-doped gate spacer 80B opposite the surface onto which the carbon plasma was incident during the carbon treatment 101. In some embodiments, the carbon treatment 101 may also result in an increased carbon concentration in the dummy dielectric layer 58.

[0038] The Fig. 10A to 10D show embodiments in which the carbon treatment 101 is performed after the LDD regions 77 and 79 have been formed (see Fig. 9A to 9C). In some embodiments, the carbon treatment 101 may be performed after forming the first gate spacer 80 (see Fig. 8A-C), but before the formation of the LDD regions 77 and 79.

[0039] With reference to the Fig. 11A to 11C, additional gate spacers may be formed over the carbon-doped gate spacer 80B and the carbon film 80A. First, a second gate spacer 83 may be formed over the carbon-doped gate spacer 80B and the carbon film 80A. Any suitable methods may be used to form the second gate spacer 83. In some embodiments, deposition (such as ALD, CVD, or the like) may be used to form the second gate spacer 83. Any suitable material may be used to form the second gate spacer 83. In some embodiments, the second gate spacer 83 may comprise SiOCN. As shown in Fig. 11A, in some embodiments, the second gate spacer 83 may have a thickness T3 of about 3 nm. After the second gate spacer 83 is formed, a third gate spacer 85 is formed over the second gate spacers 83. Any suitable methods for forming the third gate spacer 85 may be used. In some embodiments, deposition (such as ALD, CVD, or the like) may be used to form the third gate spacers 85. Any suitable material may be used to form the third gate spacer 85. In some embodiments, the third gate spacer 85 may comprise silicon nitride (SiN) or the like. The third gate spacer 85 may, in some embodiments, have a thickness T4 of about 4 nm, as shown in Fig. 11A shown.

[0040] Next, a patterning process is performed to remove unnecessary portions of the carbon-doped gate spacer 80B, the carbon film 80A, the second gate spacer 83, and the third gate spacer 85. Any suitable patterning process may be used. In some embodiments, a photoresist (not shown) may be deposited and patterned using suitable lithography techniques, with openings in the photoresist exposing portions of the carbon-doped gate spacer 80B, the carbon film 80A, the second gate spacer 83, and the third gate spacer 85. An etching process may be performed using the photoresist as a mask. The etching process may be anisotropic.After etching, lateral portions of the carbon-doped gate spacer 80B, the carbon film 80A, the second gate spacer 83, and the third gate spacer 85 may be removed over the LDD regions and over the isolation regions 54 to expose portions of the fins 56 and the hard masks 72 / 78 over the dummy gate stacks 70 / 76. Portions of the carbon-doped gate spacer 80B, the carbon film 80A, the second gate spacer 83, and the third gate spacer 85 along the sidewalls of the dummy gates 70 / 76 may remain after etching. The resulting structure is shown in FIGS. Fig. 12A to 12C shown.

[0041] The Fig. 13A to 22 illustrate the formation of epitaxial source / drain regions 82 and 84 in the first region 100A and the second region 100B. In some embodiments, the epitaxial source / drain regions 82 may be formed in the first region 100A before the epitaxial source / drain regions 84 are formed in the second region 100B. It is also possible to form the epitaxial source / drain regions 84 in the second region 100B before the epitaxial source / drain regions 82 are formed in the first region 100A.

[0042] The Fig. 13A to 17 illustrate the formation of an epitaxial source / drain region in the first region 100A. During the formation of the epitaxial source / drain region in the first region 100A, e.g., the NMOS region, the second region 100B, e.g., the PMOS region, may be masked (not shown).

[0043] With reference to the Fig. 13A to 13C, the source / drain regions of the fins 56 in the first region 100A are etched to form recesses 102. The etching may be performed to form a recess 102 between adjacent dummy gates 70. Any suitable etching technique may be used. In some embodiments, the recesses 102 may be etched to extend at least partially beneath a portion of the dummy gate dielectric 58, the carbon-doped gate spacer 80B, the carbon film 80A, the second gate spacer 83, and the third gate spacer 85. In other embodiments, the recesses 102 need not extend under any portions of the dummy gate dielectric 58, the carbon-doped gate spacer 80B, the carbon film 80A, the second gate spacer 83, and the third gate spacer 85. A portion of the ribs 56 (see Fig. 13B) between adjacent ones of the recesses 102 and directly below the dummy gate 70 may provide a channel region of a FinFET device.

[0044] Next, as shown in the Fig. 14A to 14C, a carbon treatment 121 may be applied to the recesses 102. The carbon treatment 121 may implant carbon dopants along sidewalls and a bottom surface of the recesses 102, thereby forming carbon-doped regions 107 in the recesses 102 along the ridges 56, the semiconductor stripes 52, and the substrate 50. In another embodiment, the carbon treatment 101 described above and / or the carbon treatment 121 may implant carbon dopants into various gate spacers (e.g., the carbon-doped gate spacer 80B, the carbon film 80A, the second gate spacer 83, and the third gate spacer 85), which may diffuse into channel regions of the FinFET without forming the carbon-doped regions 107 along the sidewalls and bottom surface of the recesses 102.In one embodiment, the carbon treatment 121 may simultaneously implant carbon dopants along sidewalls and a bottom surface of the recesses 102 to form the carbon-doped regions 107 and various gate spacers that may diffuse into channel regions of the FinFET. In one embodiment, the carbon treatment 121 forms the carbon-doped regions 107 without implanting carbon dopants into various gate spacers. For example, the carbon treatment 121 may be performed without performing the carbon treatment 101 described above. The carbon-doped region 107 may include both carbon and a material of the fins 56, the semiconductor stripes 52, and the substrate 50 (e.g., Si, SiGe, combinations thereof, or the like).The carbon-doped regions 107 on sidewalls and a bottom surface of the recesses 102 can be used to reduce the diffusion of dopants from subsequently formed epitaxial source / drain regions into the recesses 102 (see, e.g., FIG. Fig. 16A to 16C). In some embodiments, the reduction in dopant diffusion may be a result of a reduction in interstitial atoms provided by the carbon-doped regions 107.

[0045] In some embodiments, the carbon treatment 121 may be similar to the carbon treatment 101 (see Fig. 10A to 10D). For example, the carbon treatment 121 may include placing a wafer on which the FinFET 30 will be formed in a plasma chamber 202 on a wafer chuck under an RF coil. Any suitable plasma chamber may be used. For example, the VARIAN VIISTA® PLAD from Applied Materials may be suitable for some embodiments. Conformal carbon plasma doping may be applied to the FinFET 30 in the plasma chamber using a gas source and an RF coil configured to generate carbon plasma in the plasma chamber. In some embodiments, the gas source generates a gas during the conformal carbon plasma doping. The gas, in some embodiments, may be a hydrocarbon, such as CH4, C2H2, C2H4, or C2H6, which at a dosage of about 5 × 10 13 cm -2 up to about 5 × 10 14 cm -2can be introduced into the plasma chamber during carbon treatment 121. In some embodiments, a DC bias of about 0.5 kV to about 2 kV, a power range of about 650 W to about 900 W, a pressure of about 27 mbar (20 mTorr) to about 107 mbar (80 mTorr), and a pulse width of about 20 µs to about 60 µs can be used in the plasma chamber during carbon treatment 121. In one embodiment of a conformal carbon plasma doping process, plasma containing carbon ions is generated in the plasma chamber 202. The carbon ions are directed onto the FinFET 30 and implanted into exposed surfaces of the FinFET 30 according to the process parameters of the plasma chamber 202.

[0046] In some embodiments, the use of conformal carbon plasma doping of the recesses 102 may enable more uniform doping in the resulting carbon-doped regions 107. For example, it may be possible to dope the recesses 102 using beam delivery implantation. However, due to the high aspect ratios of some ridges, a line of sight from the beam delivery to all regions of the recesses 102 may not be available. Therefore, beam delivery implantation may result in some portions of the recesses 102 not being doped, resulting in non-uniform doping of the carbon-doped regions 107, particularly for aspect ratios greater than about 10:1 for the ridges 56. The use of conformal carbon plasma doping of the recesses 102 may enable more uniform doping of the carbon-doped regions 107.For example, after the carbon treatment 121 of the recesses 102, a carbon concentration in the recesses 102 in different portions of the carbon-doped regions 107 may be substantially similar. For example, in one embodiment, a ratio of the carbon concentration of the carbon-doped regions 107 at the top of the ribs 56 to the carbon concentration of the carbon-doped regions 107 at the sidewalls of the ribs 56 to the carbon concentration of the carbon-doped regions 107 at the bottom of the ribs 56 may range from about 1:0.65:0.65 to about 1:0.9:0.9.

[0047] In some embodiments, the use of conformal carbon plasma doping of the carbon-doped region 107 may further provide a high carbon concentration with reduced surface damage to the underlying substrate 50, the semiconductor stripes 52, and / or the fins 56. After the carbon treatment 121, the carbon-doped regions 107 may have increased amounts of carbon. For example, in some embodiments, the carbon concentration in the carbon-doped region 107 may be approximately 3 × 10 20 cm -3 or more. It has been observed that a carbon concentration in this range is sufficient to reduce the diffusion of impurities from the epitaxial source / drain regions 82 into the fins 56.

[0048] After the carbon treatment 121, a thin film of carbon 105 may have formed on a surface of the recesses 102 onto which the carbon plasma was incident during the carbon treatment 121. In some embodiments, the carbon thin film 105 may be further deposited over the dummy gate stacks 70 and along exposed surfaces of the carbon-doped gate spacer 80B, the carbon film 80A, the second gate spacer 83, and the third gate spacer 85.

[0049] Afterwards, as described in the Fig. 15A to 15C, a cleaning process may be used to remove the carbon thin film 105. Any suitable cleaning process may be used. For example, a high-temperature sulfur peroxide mixture (SPM) etch may be used to remove the carbon thin film 105. The cleaning process may be performed for any suitable length, such as about 10 seconds to about 45 seconds, in some embodiments. In other embodiments, the cleaning process may take a longer or shorter time. In various embodiments, the carbon thin film 105 may be removed without removing the carbon-doped regions 107 in the recesses 102.

[0050] In the Fig. 16A to 16C, epitaxial source / drain regions 82 are epitaxially grown in the first region 100A in the recesses 102. The epitaxial source / drain regions 82 may comprise any suitable material, such as any material suitable for n-type FinFETs. For example, if the fin 56 is made of silicon, the epitaxial source / drain regions 82 may comprise silicon, SiC, SiCP, SiP, or the like. The epitaxial source / drain regions 82 may have surfaces raised from respective surfaces of the fins 56 and may have facets. The epitaxial source / drain regions 82 are formed in the fins 56 such that each dummy gate 70 is disposed between corresponding adjacent pairs of the epitaxial source / drain regions 82 (as in Fig. 16B). In some embodiments, the epitaxial source / drain regions 82 may extend beyond the fins 56 and into the semiconductor stripes 52.

[0051] The epitaxial source / drain regions 82 in the first region 100A may be implanted with dopants to form source / drain regions, similar to the previously described method for forming the lightly doped source / drain regions. The epitaxial source / drain regions 82 may have an impurity concentration in a range of approximately 10 19 cm -3 up to about 10 21 cm -3 The n-type impurities for the source / drain regions in the first region 100A, e.g., the NMOS region, may be any of the previously described n-type impurities. In other embodiments, the epitaxial source / drain regions 82 may be doped in situ during growth.

[0052] The carbon-doped regions 107 may be arranged along sidewalls and a bottom surface of the source / drain regions 82 and may provide a barrier between the epitaxial source / drain regions 82 and the underlying substrate (e.g., the fins 56, the semiconductor stripes 52, and the substrate 50). Furthermore, the carbon-doped regions 107 may completely cover a bottom surface of the epitaxial source / drain regions 82, and the carbon-doped regions 107 may completely enclose a bottom portion of the epitaxial source / drain regions 82 (e.g., portions of the epitaxial source / drain regions 82 in the recesses 102) in a top view (not shown).

[0053] After the epitaxial source / drain regions 82 are implanted with dopants, an anneal may be performed. In some embodiments, the annealing may be performed at a temperature of about 1150°C for about 1.4 ms to about 20 ms, such as about 3 ms, using a suitable millisecond annealing (MSA) process (e.g., using a microsecond annealing (µSSA) tool). The annealing may be part of the formation process of the epitaxial source / drain regions 82 to provide a more uniform distribution of dopants within the epitaxial source / drain regions 82. In some embodiments, the annealing may further cause carbon from the carbon-doped gate spacer 80B and / or the carbon thin film 80A to diffuse into edge regions of the fins 56 (e.g., into the LDD regions 77 and / or into the vicinity of the channel regions of the fins 56) to form carbon-doped regions 106, as shown in Fig. 16B. In some embodiments, the annealing may be performed to form carbon-doped regions 106 together with the formation of the carbon-doped regions 107 or without the formation of the carbon-doped regions 107.

[0054] The carbon-doped regions 106 may be disposed between the epitaxial source / drain regions 82 and the channel regions 108 (e.g., the regions directly below the dummy gates 70) of the fins 56. In some embodiments, the dummy gates 70 may extend further along sidewalls of the channel regions 108, as shown in Fig. 16A. The carbon-doped regions 107 may also be arranged between the channel regions 108 of the fins 56 and the epitaxial source / drain regions 82. In some embodiments, a carbon concentration of the carbon-doped regions 106 may be equal to a carbon concentration of the carbon-doped regions 107, but this need not be the case. For example, in one embodiment, a carbon concentration of the carbon-doped regions 106 may be less than a carbon concentration of the carbon-doped regions 107. In some embodiments, a carbon concentration in the carbon-doped regions 106 may be approximately 1 × 10 19 cm -3 up to about 5 × 10 19 cm -3 while a carbon concentration in the carbon-doped region 107 is about 3 × 10 20 cm -3 or more.

[0055] The distribution of carbon in the carbon-doped regions 106 / 107 may be substantially uniform along a top surface, sidewalls, and bottoms of the fins 56 due to the conformal plasma doping techniques used to form the carbon-doped regions 106 / 107 as described above. For example, in one embodiment, a ratio of the carbon concentration of the carbon-doped regions 107 at the top of the fins 56 to the carbon concentration of the carbon-doped regions 107 at the sidewalls of the fins 56 to the carbon concentration of the carbon-doped regions 107 at the bottom of the fins 56 may be in the range of approximately 1:0.65:0.65 to approximately 1:0.9:0.9.

[0056] It has been observed that carbon dopants prevent (or at least reduce) the diffusion of dopants (e.g., n-type impurities) from the epitaxial source / drain regions 82 into the channel regions 108 of the fins 56. Thus, in various embodiments, by disposing one or more carbon-doped regions (e.g., regions 106 and 107) between the epitaxial source / drain regions 82 and the channel regions 108 of the fins 56, undesirable diffusion of dopants (e.g., n-type impurities) from the epitaxial source / drain regions 82 can be reduced. For example, in experimental data comparing embodiments with carbon-doped regions 106 and / or 107 with embodiments without carbon-doped regions 106 and / or 107, it has been observed that the diffusion distance of dopants from the epitaxial source / drain regions 82 can be reduced by at least about 1 nm.Furthermore, by reducing diffusion from the epitaxial source / drain regions 82, one or more of the following non-limiting benefits may be achieved: reducing short-channel effects, reducing parasitic capacitance (e.g., reducing parasitic gate-source capacitance and / or parasitic gate-drain capacitance), reducing leakage current, and improving the switching speed of the resulting FinFET device. For example, an improvement of about 3% to about 6% in switching speed has been observed for devices with carbon-doped regions separating the source / drain and channel regions compared to devices without such carbon-doped regions.

[0057] The Fig. 16A to 16C show embodiments of epitaxial source / drain regions 82 in which each source / drain region 82 is physically separated from adjacent source / drain regions 82. In some embodiments, two or more adjacent source / drain regions 82 may be merged. An embodiment of a FinFET with merged source / drain regions is shown in Fig. 17, which is shown along the CC cross-section of Fig. 1 is taken. In Fig. 17, two adjacent source / drain regions 82 are merged. In some embodiments, more than two adjacent source / drain regions 82 may be merged.

[0058] The Fig. 18A to 22 illustrate the formation of epitaxial source / drain regions in the second region 100B. During the formation of the epitaxial source / drain region in the second region 100B, e.g., the PMOS region, the first region 100A, e.g., the NMOS region, may be masked (not shown).

[0059] With reference to the Fig. 18A to 18C, the source / drain regions of the fins 56 in the second region 100B are etched to form recesses 104. The etching may be performed to form a recess 104 between adjacent dummy gates 76. Any suitable etching technique may be used. In some embodiments, the recesses 104 may be etched to extend at least partially beneath a portion of the dummy gate dielectric 58, the carbon-doped gate spacer 80B, the carbon film 80A, the second gate spacer 83, and the third gate spacer 85. In other embodiments, the recesses 104 need not extend under any portions of the dummy gate dielectric 58, the carbon-doped gate spacer 80B, the carbon film 80A, the second gate spacer 83, and the third gate spacer 85. A portion of the ribs 56 (see Fig. 18B) between adjacent ones of the recesses 102 and directly below the dummy gate 76 may provide a channel region of a FinFET device.

[0060] Next, as shown in the Fig. 19A to 19C, a carbon treatment 131 may be applied to the recesses 104. The carbon treatment 131 may implant carbon dopants along sidewalls and a bottom surface of the recesses 104, thereby forming carbon-doped regions 111 in the recesses 104 along the ridges 56, the semiconductor stripes 52, and the substrate 50. In another embodiment, the carbon treatment 101 described above and / or the carbon treatment 131 may implant carbon dopants into various gate spacers (e.g., the carbon-doped gate spacer 80B, the carbon film 80A, the second gate spacer 83, and the third gate spacer 85), which may diffuse into channel regions of the FinFET without forming the carbon-doped regions 111 along sidewalls and the bottom surface of the recesses 104.In one embodiment, the carbon treatment 131 may simultaneously implant carbon dopants along sidewalls and a bottom surface of the recesses 104 to form the carbon-doped regions 111 and the various gate spacers that may diffuse into channel regions of the FinFET. In one embodiment, the carbon treatment 131 forms the carbon-doped regions 111 without implanting carbon dopants into the various gate spacers. For example, the carbon treatment 131 may be performed without performing the carbon treatment 101 as described above. The carbon-doped region 111 may include both carbon and a material of the fins 56, the semiconductor stripes 52, and the substrate 50 (e.g., Si, SiGe, combinations thereof, or the like).The carbon-doped regions 111 on sidewalls and a bottom surface of the recesses 104 can be used to reduce the diffusion of dopants from subsequently formed epitaxial source / drain regions into the recesses 104 (see, e.g., FIG. Fig. 21A to 21C). In some embodiments, the reduction in dopant diffusion may be a result of a reduction in interstitial atoms provided by the carbon-doped regions 111.

[0061] In some embodiments, the carbon treatment 131 may be the carbon treatment 101 (see Fig. 10A to 10D) and carbon treatment 121 (see Fig. 14A to 14C). For example, the carbon treatment 131 may include placing a wafer on which the FinFET 30 will be formed in a plasma chamber 202 on a wafer chuck under an RF coil. Any suitable plasma chamber may be used. For example, the VARIAN VIISTA® PLAD from Applied Materials may be suitable for some embodiments. Conformal carbon plasma doping may be applied to the FinFET 30 in the plasma chamber using a gas source and an RF coil configured to generate carbon plasma in the plasma chamber. In some embodiments, the gas source generates a gas during the conformal carbon plasma doping. The gas, in some embodiments, may be a hydrocarbon, such as CH4, C2H2, C2H4, or C2H6, applied at a dosage of about 5 × 10 13 cm -2 up to about 5 × 10 14 cm -2can be introduced into the plasma chamber during carbon treatment 131. In some embodiments, a DC bias of about 0.5 kV to about 2 kV, a power range of about 650 W to about 900 W, a pressure of about 27 mbar (20 mTorr) to about 107 mbar (80 mTorr), and a pulse width of about 20 µs to about 60 µs can be used in the plasma chamber during carbon treatment 131. In one embodiment of a conformal carbon plasma doping process, plasma containing carbon ions is generated in the plasma chamber 202. The carbon ions are directed onto the FinFET 30 and implanted into exposed surfaces of the FinFET 30 according to the process parameters of the plasma chamber 202.

[0062] In some embodiments, the use of conformal carbon plasma doping of the recesses 104 may enable more uniform doping in the resulting carbon-doped regions 111. For example, it may be possible to dope the recesses 104 using beam delivery implantation. However, due to the high aspect ratios of some ridges, a line of sight from the beam line to all regions of the recesses 104 may not be available. Therefore, beam delivery implantation may result in some portions of the recesses 104 not being doped, resulting in non-uniform doping of the carbon-doped regions 111, particularly for aspect ratios greater than about 10:1 for the ridges 56. The use of conformal carbon plasma doping of the recesses 104 may enable more uniform doping of the carbon-doped regions 111.For example, after the carbon treatment 131 of the recesses 104, a carbon concentration in the recesses 104 in different portions of the carbon-doped regions 111 may be substantially similar. For example, in one embodiment, a ratio of the carbon concentration of the carbon-doped regions 111 at the top of the ribs 56 to the carbon concentration of the carbon-doped regions 111 at the sidewalls of the ribs 56 to the carbon concentration of the carbon-doped regions 111 at the bottom of the ribs 56 may range from about 1:0.65:0.65 to about 1:0.9:0.9.

[0063] In some embodiments, the use of conformal carbon plasma doping of the carbon-doped regions 111 may further provide a high carbon concentration with reduced surface damage to the underlying substrate 50, the semiconductor stripes 52, and / or the fins 56. After the carbon treatment 131, the carbon-doped regions 111 may have increased amounts of carbon. For example, in some embodiments, the carbon concentration in the carbon-doped region 111 may be approximately 3 × 10 20 cm -3 or more. It has been observed that a carbon concentration in this range is sufficient to reduce the diffusion of impurities from the epitaxial source / drain regions 84 into the fins 56.

[0064] After the carbon treatment 131, a thin film of carbon 109 may have formed on a surface of the recesses 104 onto which the carbon plasma was incident during the carbon treatment 131. In some embodiments, the carbon thin film 109 may be further deposited over the dummy gate stacks 70 and along the exposed surfaces of the carbon-doped gate spacer 80B, the carbon film 80A, the second gate spacer 83, and the third gate spacer 85 in the second region 100B.

[0065] Afterwards, as described in the Fig. 20A to 20C, a cleaning process may be used to remove the carbon thin film 109. Any suitable cleaning process may be used. For example, a high-temperature sulfur peroxide mixture (SPM) etch may be used to remove the carbon thin film 109. The cleaning process may be performed for any suitable length, such as about 10 seconds to about 45 seconds, in some embodiments. In other embodiments, the cleaning process may take a longer or shorter time. In various embodiments, the carbon thin film 109 may be removed without removing the carbon-doped regions 111 in the recesses 104.

[0066] In the Fig. 21A to 21C, epitaxial source / drain regions 84 are epitaxially grown in the recesses 104 in the second region 100B. The epitaxial source / drain regions 84 may comprise any suitable material, such as material suitable for p-type FinFETs. For example, if the fin 56 is made of silicon, the epitaxial source / drain regions 84 may comprise SiGe, SiGeB, Ge, GeSn, or the like. The epitaxial source / drain regions 84 may have surfaces raised from respective surfaces of the fins 56 and may have facets. In the second region 100B, epitaxial source / drain regions 84 are formed in the fins 56 such that each dummy gate 76 is disposed between corresponding adjacent pairs of the epitaxial source / drain regions 84. In some embodiments, the epitaxial source / drain regions 84 may extend beyond the fins 56 and into the semiconductor stripes 52.

[0067] The epitaxial source / drain regions 84 in the second region 100B may be implanted with dopants to form source / drain regions, similar to the previously described method for forming the lightly doped source / drain regions. The epitaxial source / drain regions 84 may have an impurity concentration in a range of approximately 10 19 cm -3 up to about 10 21 cm -3 The p-type impurities for source / drain regions in the second region 50C, e.g., the PMOS region, may be any of the previously described p-type impurities. In other embodiments, the epitaxial source / drain regions 84 may be doped in situ during growth.

[0068] The carbon-doped regions 111 may be arranged along sidewalls and a bottom surface of the source / drain regions 84 and may provide a barrier between the epitaxial source / drain regions 84 and the underlying substrate (e.g., the fins 56, the semiconductor stripes 52, and the substrate 50). Furthermore, the carbon-doped regions 111 may completely cover a bottom surface of the epitaxial source / drain regions 84, and the carbon-doped regions 111 may completely enclose a bottom portion of the epitaxial source / drain regions 84 (e.g., portions of the epitaxial source / drain regions 84 in the recesses 104) in a top view (not shown).

[0069] After the epitaxial source / drain regions 84 are implanted with dopants, an anneal may be performed. In some embodiments, the annealing may be performed at a temperature of about 1150°C for about 1.4 ms to about 20 ms, such as about 3 ms, using a suitable MSA process (e.g., using a μSSA tool). The annealing may be part of the formation process of the epitaxial source / drain regions 84 to provide a more uniform distribution of dopants within the epitaxial source / drain regions 84. In some embodiments, the annealing may further cause carbon to diffuse from the carbon-doped gate spacer 80B and / or the carbon thin film 80A into the exterior region of the fins 56 to form the carbon-doped regions 110, as shown in Fig. 24B. In some embodiments, the annealing may be performed to form carbon-doped regions 110 together with the formation of the carbon-doped regions 111 or without the formation of the carbon-doped regions 111.

[0070] The carbon-doped regions 110 may be arranged between the epitaxial source / drain regions 84 and the channel regions 112 of the fins 56 (e.g., the regions of the fins 56 directly below the dummy gates 76). The carbon-doped regions 111 may also be arranged between the channel regions 112 of the fins 56 and the epitaxial source / drain regions 84. In some embodiments, a carbon concentration of the carbon-doped regions 110 may be equal to a carbon concentration of the carbon-doped regions 111, but this need not be the case. For example, in one embodiment, a carbon concentration of the carbon-doped regions 110 may be less than a carbon concentration of the carbon-doped regions 111. In some embodiments, a carbon concentration in the carbon-doped regions 110 may be approximately 1 × 10 19 cm -3 up to about 5 × 10 19 cm -3while a carbon concentration in the carbon-doped region 111 is about 3 × 10 20 cm -3 or more.

[0071] In some embodiments, the dummy gates 76 may extend further along sidewalls of the channel regions 112, as shown in the Fig. 21A. The distribution of carbon in the carbon-doped regions 111 / 110 may be substantially uniform along a top surface, sidewalls, and bottoms of the fins 56 due to the conformal plasma doping techniques used to form the carbon-doped regions 111 / 110 as described above. For example, in one embodiment, a ratio of the carbon concentration of the carbon-doped regions 111 / 110 at the top of the fins 56 to the carbon concentration of the carbon-doped regions 111 / 110 at the sidewalls of the fins 56 to the carbon concentration of the carbon-doped regions 111 / 110 at the bottom of the fins 56 may range from about 1:0.65:0.65 to about 1:0.9:0.9.

[0072] Carbon dopants have been observed to prevent (or at least reduce) the diffusion of dopants (e.g., p-type impurities) from the epitaxial source / drain regions 84 into the channel regions 112 of the fins 56. Thus, in various embodiments, by disposing one or more carbon-doped regions (e.g., regions 110 and 111) between the epitaxial source / drain regions 84 and the channel regions 112 of the fins 56, undesirable diffusion of dopants (e.g., p-type impurities) from the epitaxial source / drain regions 84 can be reduced. For example, in experimental data comparing embodiments with carbon-doped regions 110 and / or 111 with embodiments without carbon-doped regions 110 and / or 111, it has been observed that the diffusion distance of dopants from the epitaxial source / drain regions 84 can be reduced by at least about 1 nm.Furthermore, by reducing diffusion from the epitaxial source / drain regions 84, one or more of the following non-limiting benefits may be achieved: reducing short-channel effects, reducing parasitic capacitance (e.g., reducing parasitic gate-source capacitance and / or parasitic gate-drain capacitance), reducing leakage current, and improving the switching speed of the resulting FinFET device. For example, an improvement of about 3% to about 6% in switching speed has been observed for devices with carbon-doped regions separating the source / drain and channel regions compared to devices without such carbon-doped regions.

[0073] Although the annealing process for forming carbon-doped regions 110 is shown as separate from the annealing process for forming carbon-doped regions 106, in further embodiments, a single anneal may be performed to simultaneously form carbon-doped regions 110 and 106. For example, in one embodiment, a single annealing process is performed after epitaxial source / drain regions 82 and 84 have been formed. In such embodiments, the single annealing may cause carbon to diffuse from carbon-doped gate spacer 80B into underlying fins 56 to simultaneously form carbon-doped regions 106 in first region 100A and carbon-doped regions 110 in second region 100B.

[0074] The Fig. 21A to 21C show embodiments of epitaxial source / drain regions 84 in which each source / drain region 84 is physically separated from adjacent source / drain regions 84. In some embodiments, two or more adjacent source / drain regions 84 may be merged. One embodiment of a FinFET with merged source / drain regions is shown in Fig. 22, which is shown along the CC cross-section of Fig. 1 is taken. In Fig. 22, two adjacent source / drain regions 84 are merged. In some embodiments, more than two adjacent source / drain regions 84 may be merged.

[0075] In the Fig. 23A to 23C, an etch stop layer 87 and an interlayer dielectric (ILD) 88 are formed over the Fig. 13A-C through 18. In one embodiment, the ILD 88 is a flowable film formed by flowable CVD. In some embodiments, the ILD 88 is formed from a dielectric material such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like, and may be deposited by any suitable method, such as CVD or PECVD.

[0076] In the Fig. 24A to 24C, a planarization process such as CMP may be performed to level the top surface of the ILD 88 with the top surfaces of the dummy gates 70 and 76. After the planarization process, the top surfaces of the dummy gates 70 and 76 are exposed through the ILD 88. In some embodiments, the CMP may remove all or portions of the masks 72 and 78. In other embodiments, the masks 72 and 78 may be removed before the ILD 88 is deposited.

[0077] In the Fig. 25A to 25C, the remaining portions of the masks 72 and 78 and the dummy gates 70 and 76 are removed in one or more etching steps to form recesses 90. Each recess 90 exposes a channel region (e.g., channel regions 108 and 112) of a corresponding fin 56. Each channel region is disposed between adjacent pairs of epitaxial source / drain regions 82 and 84. During removal, the dummy dielectric layer 58 may be used as an etch stop layer when the dummy gates 70 and 76 are etched. The dummy dielectric layer 58 may then be removed after the removal of the dummy gates 70 and 76.

[0078] As described above, the carbon treatment 101 applied to the first gate spacer 80 may reinforce the carbon-doped first gate spacer 80 and form a carbon thin film 80A over the first gate spacer 80. The carbon treatment 101 may help protect the epitaxial source / drain regions 82 and 84 during the removal of the dummy gates 70 and 76, which may be Fig. 24A to 24C. For example, in some embodiments, the dummy gates 70 and 76 are removed using wet cleaning that uses a wet cleaning chemical such as NH4OH. Without the carbon treatment 101, the wet cleaning chemical may penetrate the first gate spacer 80, the second gate spacer 83, and the third gate spacer 85 and damage the epitaxial source / drain regions 82 and 84. The carbon treatment 101 may prevent or mitigate damage to the epitaxial source / drain regions 82 and 84 caused by wet cleaning chemical penetration through the gate spacers. Therefore, in some embodiments, the source / drain regions may be free of defects or may have reduced defects compared to a FinFET formed using similar methods but without carbon treatment 101 of a gate spacer.

[0079] In the Fig. 26A to 26C, gate dielectric layers 92 and 96 and gate electrodes 94 and 98 for the replacement gates are formed. The gate dielectric layers 92 and 96 are conformally deposited in the recesses 90, such as on the top surfaces and sidewalls of the fins 56 and on sidewalls of the gate spacers 86, and on a top surface of the ILD 88. According to some embodiments, the gate dielectric layers 92 and 96 comprise silicon oxide, silicon nitride, or multilayers thereof. In other embodiments, the gate dielectric layers 92 and 96 comprise a high-k dielectric material, and in these embodiments, the gate dielectric layers 92 and 96 may have a k value greater than about 7.0 and may comprise a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof.The formation processes of the gate dielectric layers 92 and 96 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like.

[0080] Next, gate electrodes 94 and 98 are deposited over gate dielectric layers 92 and 96, respectively, and the remaining portions of recesses 90 are filled. Gate electrodes 94 and 98 may be made of a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multilayers thereof. In some embodiments, gate electrodes 94 and 98 may each include one or more barrier layers, work function layers, and / or work function adjustment layers to adjust the work function of gate electrodes 94 and 98. After filling gate electrodes 94 and 98, a planarization process, such as CMP, may be performed to remove the excess portions of gate dielectric layers 92 and 96 and the excess portions of the gate electrode material 94 and 98 that overlie the top surface of ILD 88.The resulting remaining portions of the material of the gate electrodes 94 and 98 and the gate dielectric layers 92 and 96 then form replacement gates of the resulting FinFETs.

[0081] The formation of the gate dielectric layers 92 and 96 may occur simultaneously, such that the gate dielectric layers 92 and 96 are made of the same materials, and the formation of the gate electrodes 94 and 98 may occur simultaneously, such that the gate electrodes 94 and 98 are made of the same materials. However, in other embodiments, the gate dielectric layers 92 and 96 may be formed by different processes, such that the gate dielectric layers 92 and 96 may be made of different materials, and the gate electrodes 94 and 98 may be formed by different processes, such that the gate electrodes 94 and 98 may be made of different materials. Different masking steps may be used to mask and expose appropriate areas if separate processes are used.

[0082] Furthermore, the gate electrode 94 and the gate dielectric layer 92 may be physically separated from gate stacks of adjacent FinFET devices in the region 100A (see, e.g., Fig. 28). Similarly, the gate electrode 98 and the gate dielectric layer 96 may be physically separated from gate stacks of adjacent FinFET devices in the region 100B (see, e.g., Fig. 29). In some embodiments, the gate electrodes 94 / 98 and the gate dielectric layers 92 / 96 may be formed to have the same structure as the dummy gate stacks 70 / 76 (see Fig. 7A). In such embodiments, the gate electrodes 94 / 98 and the gate dielectric layers 92 / 96 may be physically separated from adjacent gate stacks because the dummy gate stacks 70 / 76 have previously been patterned to be physically separated from adjacent dummy gate stacks, as described above with reference to Fig. 7A. In other embodiments, a combination of photolithography and etching may be used to pattern the gate electrodes 94 / 98 and the gate dielectric layers 92 / 96 after deposition.

[0083] In the Fig. 27A to 27B, an ILD 150 is deposited over the ILD 88. Furthermore, in the Fig. 27A to 27C, contacts 152 and 154 are formed by the ILD 150 and the ILD 88, and contacts 156 and 158 are formed by the ILD 150. In one embodiment, the ILD 150 is a flowable film formed by a flowable CVD process. In some embodiments, the ILD 150 is formed from a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable process, such as CVD and PECVD. Openings for contacts 152 and 154 are formed by the ILDs 88 and 100. Openings for contacts 156 and 158 are formed by the ILD 150. These openings may all be formed simultaneously in a same process or in separate processes. The openings may be formed using suitable photolithography and etching techniques. A lining, such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are formed in the openings.The liner may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, aluminum, nickel, or the like. A planarization process, such as a CMP process, may be performed to remove excess material from a top surface of the second ILD 150. The remaining portions of the liner and conductive material form the contacts 152 and 154 in the openings. An annealing process may be performed to form a silicide at the interface between the epitaxial source / drain regions 82 and 84 and the contacts 152 and 154, respectively.Contacts 152 are physically and electrically connected to epitaxial source / drain regions 82, contacts 154 are physically and electrically connected to epitaxial source / drain regions 84, contact 156 is physically and electrically connected to gate electrode 94, and contact 158 ​​is physically and electrically connected to gate electrode 98.

[0084] While contacts 152 and 154 in Fig. 27B are shown in the same cross-section as contacts 156 and 158, this illustration is for descriptive purposes, and in some embodiments, contacts 152, 154 are arranged in different cross-sections than contacts 156 and 158.

[0085] As described herein, a carbon treatment is applied to a gate spacer and / or along sidewalls and a bottom surface of one or more source / drain recesses. The carbon treatment may include conformal carbon plasma doping of the one or more gate spacers and / or along sidewalls and a bottom surface of one or more source / drain recesses. Thus, various embodiments may help provide carbon-doped regions disposed between and separating a channel region of a FinFET device and an epitaxial source / drain region. The carbon-doped region may help prevent the diffusion of impurities (e.g., n- or p-type dopants) from the source / drain regions into the channel region and / or the underlying bulk substrate. Thus, device performance (e.g.,AC electrical performance, such as switching speed, parasitic capacitance, reduced short-channel effects, reduced leakage currents, or the like, can be improved. For example, by preventing impurity diffusion, defects at source / drain and channel junctions can be reduced, reducing the likelihood of leakage current, particularly in devices with a small pitch. Furthermore, carbon doping of the gate spacers can further increase the etch selectivity of the spacers relative to a dummy gate during gate replacement processes, which can lead to fewer spacer defects and increased yield.

[0086] According to one embodiment, a method comprises depositing a dummy gate over and along sidewalls of a fin extending upward from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further comprises forming a source / drain region adjacent to a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source / drain region and the channel region of the fin.

[0087] According to one embodiment, a method includes forming a dummy gate stack over and along sidewalls of a channel region of a semiconductor fin, depositing a spacer over and along sidewalls of the dummy gate stack, carbon plasma doping the spacer to form a carbon-doped spacer along sidewalls of the dummy gate stack and over the semiconductor fin, etching a recess in the semiconductor fin, carbon doping sidewalls and a bottom surface of the recess to provide a first carbon-doped region in the semiconductor fin, and epitaxially growing an epitaxial source / drain region in the recess. The first carbon-doped region is disposed between a sidewall of the epitaxial source / drain region in the recess and the channel region of the semiconductor fin.

[0088] According to one embodiment, a fin field-effect transistor (FinFET) device comprises a fin extending upward from a semiconductor substrate, a gate stack above and along sidewalls of a channel region of the fin, a source / drain region adjacent to the fin, and a gate spacer disposed along a sidewall of the gate stack. The gate spacer comprises carbon dopants, wherein a carbon concentration of the gate spacer is 3 10 20 cm -3 or more. The FinFET device further comprises a first carbon-doped region disposed along a bottom surface and a sidewall of the source / drain region, and a second carbon-doped region below the gate spacer and between the first carbon-doped region and the channel region.

[0089] The foregoing describes features of several embodiments so that one skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should recognize that they can readily use the present disclosure as a basis to design or modify other methods and structures to achieve the same objectives and / or realize the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit of the present disclosure and that they may make various changes, substitutions, and modifications herein without departing from the spirit of the present disclosure.

Claims

[1] Method comprising: Depositing a dummy gate (70, 76) over and along sidewalls of a fin (36, 56) extending upwardly from a semiconductor substrate (32, 50); Forming a first gate spacer (80) along a sidewall of the dummy gate (70, 76); plasma doping the first gate spacer (80) with carbon to form a carbon-doped gate spacer (80B); Forming a source / drain region (42, 44, 82, 84) adjacent to a channel region (108, 112) of the fin (36, 56); and Diffusing carbon from the carbon-doped gate spacer (80B) into a first region of the fin (36, 56) to provide a first carbon-doped region (106, 110), the first carbon-doped region (106, 110) being disposed between at least a portion of the source / drain region (42, 44, 82, 84) and the channel region (108, 112) of the fin (36, 56); wherein forming the source / drain region (42, 44, 82, 84) comprises etching a second portion of the rib (36, 56) to provide a recess (102, 104) adjacent to the first portion of the rib (36, 56), the method further comprising plasma doping the recess (102, 104) with carbon to form a second carbon-doped region (107, 111) along sidewalls and a bottom surface of the recess (102, 104). [2] The method of claim 1, wherein plasma doping the recess (102, 104) with carbon further deposits a carbon thin film (105, 109) along the sidewalls and over the bottom surface of the recess (102, 104), and wherein the method further comprises removing the carbon thin film (105, 109) using a cleaning process. [3] The method of claim 1 or 2, further comprising, after plasma doping the recess (102, 104), epitaxially growing the source / drain region (42, 44, 82, 84) in the recess (102, 104), wherein the second carbon-doped region (107, 111) is arranged along sidewalls and a bottom surface of the source / drain region (42, 44, 82, 84). [4] The method of any preceding claim, wherein diffusing carbon from the carbon-doped gate spacer (80B) into the first region (106, 110) comprises annealing the carbon-doped gate spacer (80B). [5] The method of claim 4, wherein diffusing carbon from the carbon-doped gate spacer (80B) into the first region (106, 110) comprises annealing the carbon-doped gate spacer (80B) after forming the source / drain region (42, 44, 82, 84). [6] The method of any preceding claim, further comprising replacing the dummy gate (70, 76) with a functional gate stack (92-98) disposed over and along sidewalls of the channel region (108, 112) of the fin (36, 56). [7] The method of any preceding claim, further comprising forming a lightly doped drain region (42, 44, 82, 84) on an upper surface of the first region (100A), the method further comprising diffusing the carbon from the carbon-doped gate spacer (80B) into the lightly doped drain region (42, 44, 82, 84) such that the first carbon-doped region (107, 111) is at least partially disposed in the lightly doped drain region (42, 44, 82, 84). [8] Method comprising: Forming a dummy gate stack (70, 76) over and along sidewalls of a channel region (108, 112) of a semiconductor fin (36, 56); Depositing a spacer (80) over and along sidewalls of the dummy gate stack (70, 76); Carbon plasma doping the spacer (80) to form a carbon-doped spacer (80B) along sidewalls of the dummy gate stack (70, 76) and above the semiconductor fin (36, 56); Etching a recess (102, 104) in the semiconductor fin (36, 56); Carbon doping sidewalls and a bottom surface of the recess (102, 104) to provide a first carbon-doped region (107, 111) in the semiconductor fin (36, 56); and epitaxially growing an epitaxial source / drain region (42, 44, 82, 84) in the recess (102, 104), wherein the first carbon-doped region (107, 111) is arranged between a sidewall of the epitaxial source / drain region (42, 44, 82, 84) in the recess (102, 104) and the channel region (108, 112) of the semiconductor fin (36, 56). [9] The method of claim 8, wherein the first carbon-doped region (107, 111) is disposed along the sidewall and a bottom surface of the source / drain region (42, 44, 82, 84). [10] The method of claim 8 or 9, wherein carbon doping the sidewalls and bottom surface of the recess (102, 104) deposits a carbon film (80A) along the sidewalls and bottom surface of the recess (102, 104). [11] The method of claim 10, further comprising removing the carbon film (80A) prior to epitaxially growing the source / drain region (42, 44, 82, 84) in the recess (102, 104). [12] The method of claims 8 to 11, further comprising annealing the carbon-doped spacer (80B) to diffuse carbon into the semiconductor fin (36, 56) and provide a second carbon-doped region (106, 110), the second carbon-doped region (106, 110) being disposed between the channel region (108, 112) and the sidewall of the source / drain region (42, 44, 82, 84). [13] The method of claim 12, wherein annealing the carbon-doped spacer (80B) occurs after epitaxially growing the source / drain region (42, 44, 82, 84), wherein the second carbon-doped region (106, 110) is further disposed between the first carbon-doped region (107, 111) and the channel region (108, 112). [14] The method of any one of claims 8 to 13, wherein carbon doping of the side walls and bottom surface of the recess (102, 104) comprises a carbon plasma doping process. [15] Fin field effect transistor device, hereinafter referred to as FinFET device, comprising a rib (36, 56) extending upwardly from a semiconductor substrate (32, 50); a gate stack over and along sidewalls of a channel region (108, 112) of the fin (36, 56); a source / drain region (42, 44, 82, 84) adjacent to the fin (36, 56); a gate spacer (80, 80B) disposed along a sidewall of the gate stack wherein the gate spacer (80, 80B) comprises carbon dopants, wherein a carbon concentration of the gate spacer (80, 80B) is 3·10 20 cm -3 or more; a first carbon-doped region (107, 111) disposed along a bottom surface and a sidewall of the source / drain region (42, 44, 82, 84); and a second carbon-doped region (106, 110) beneath the gate spacer (80, 80B) and between the first carbon-doped region (107, 111) and the channel region (108, 112). [16] The FinFET device of claim 15, wherein the first carbon-doped region (107, 111) is disposed between at least a portion of the source / drain region (42, 44, 82, 84) and a channel region (108, 112) of the fin (36, 56). [17] The FinFET device of claim 15 or 16, wherein a carbon concentration in different portions of the carbon-doped gate spacer (80, 80B) is substantially the same during a carbon plasma doping process for doping the gate spacers (80, 80B). [18] The FinFET device of any one of the preceding claims 15 to 17, further comprising a second gate spacer (83, 85) above the gate spacer (80, 80B), wherein a carbon concentration in the second gate spacer (83, 85) is smaller than in the gate spacer (80, 80B). [19] The FinFET device of claim 18, wherein a carbon film (80A) is laterally disposed between the gate spacer (80, 80B) and the second gate spacer (83, 85).

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