NEW IMAGE SENSOR

Abstract

Semiconductor device (200), comprising: a photodiode formed in a substrate (202), the photodiode having a first semiconductor region (212) in the substrate (202) doped with a first type of dopant, and a second semiconductor region (214) above the first semiconductor region (212) doped with a second type of dopant; and at least one transistor with a gate element (226) extending at least partially from a main surface of the substrate (202) into the substrate (202), wherein the gate element (226) of the at least one transistor comprises a first section (226-1) extending over the main surface of the substrate (202) and a second section (226-2) extending from the main surface of the substrate (202) into the substrate (202), wherein the semiconductor device (200) has an insulating element (210) extending into the substrate (202) surrounding the photodiode and the at least one transistor, wherein the second section (226-2) fills a recessed part of the insulating element (210), where the photodiode and the at least one transistor at least partially form a pixel.

Description

[0001] The present application relates to semiconductor devices and a method for manufacturing a semiconductor device. BACKGROUND

[0002] Integrated circuit (IC) technologies are continually being improved. Such improvements often involve shrinking device geometries to achieve lower manufacturing costs, higher device integration density, higher speed, and better performance. Along with various benefits resulting from such a reduction in geometry size, improvements are being made directly to IC devices, such as an image sensor device.

[0003] Generally, an image sensor device comprises an array (or grid) of pixels for detecting incident light and recording the intensity (or brightness) of the incident light. Each pixel includes at least one light-sensitive diode (hereinafter "photodiode") configured to detect the incident light and convert the detected incident light into an electrical signal (e.g., a photocurrent / current signal), and a plurality of transistors (hereinafter "pixel transistors") connected to the photodiode and collectively configured to process the one or more electrical signals to record the intensity or brightness of the detected incident light. Corresponding semiconductor devices and manufacturing methods are known from US 9 281 331 B2, US 2006 / 0 124 976 A1, US 2008 / 0 121 952 A1 and US 2006 / 0 138 493 A1.

[0004] To evaluate the performance of the image sensor device, various properties of the image sensor device are generally considered, an important one of which is a quantum efficiency of the image sensor device. Such a quantum efficiency is typically determined by a "fill factor" of the image sensor device. The fill factor is calculated as a ratio of a chip area occupied by the one or more photodiodes divided by a total chip area of ​​the respective pixel. In conventional image sensor devices, however, at least one of the aforementioned pixel transistors is planar. This means that a respective gate element of the at least one pixel transistor extends only laterally along a main surface of the pixel.When the gate element is formed in such a fully lateral shape, the fill factor may be disadvantageously reduced because, over a given chip area, a chip area available for arranging the photodiodes may be significantly reduced.

[0005] Thus, existing image sensor devices and methods for manufacturing the same are not entirely satisfactory. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that various elements are not necessarily drawn to scale. Indeed, the dimensions and geometries of the various elements may be arbitrarily exaggerated or reduced for clarity of description. Fig. 1 shows a flowchart of an example method for forming a semiconductor device according to some embodiments. The Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H, Fig. 2I and Fig. 2J show cross-sectional views of an exemplary semiconductor device during various stages of manufacture produced by the method of Fig. 1, according to some embodiments. Fig. 3 shows an exemplary plan view of an exemplary semiconductor device manufactured by the method of Fig. 1, according to some embodiments. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0007] The following disclosure describes various example embodiments for implementing various elements of the subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, forming a first element over or on top of a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first element and the second element such that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.

[0008] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or device to one or more other elements or devices, as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0009] The present disclosure provides various embodiments of an image sensor device and methods for forming the same. In some embodiments, the disclosed image sensor device comprises a plurality of pixels formed on a semiconductor substrate, each of which comprises at least one photodiode formed in the semiconductor substrate and at least one pixel transistor at least partially having a gate element and extending into the semiconductor substrate. By forming at least one pixel transistor in each of the plurality of pixels in this manner, a corresponding fill factor of the disclosed image sensor device can be significantly increased because a lateral distance by which the pixel transistor extends can be reduced, allowing more photodiodes arranged over a given chip area. Thus, the performance (e.g.,The quantum efficiency (QE) of the disclosed image sensor device can be significantly improved over existing image sensor devices, while the area in which the disclosed image sensor device is formed remains unchanged.

[0010] Fig. 1 shows a flowchart of a method 100 for forming a semiconductor device according to one or more embodiments of the present disclosure. Note that the method 100 is merely an example and is not intended to limit the present disclosure. In some embodiments, the semiconductor device is at least part of an image sensor device. As used in the present disclosure, the image sensor device refers to any device that can detect an optical signal (e.g., photons), convert it into an electrical signal, and process the electrical signal. For example, the image sensor device may be a CMOS (complementary metal oxide semiconductor) image sensor (CIS) device, an active pixel sensor device, a charge-coupled device (CCD), or a passive pixel sensor device. Note that the method 100 of Fig. 1 does not manufacture a complete image sensor device. A complete image sensor device may be manufactured using complementary metal oxide semiconductor (CMOS) technology processing. Accordingly, it is understood that additional operations may be performed before, during, and after the method 100 of Fig. 1 may be provided and that some further processes can only be described briefly here.

[0011] In some embodiments, the method 100 begins with operation 102, in which a substrate is provided. In some embodiments, the substrate is intrinsically or extrinsically doped with a first doping type (e.g., p-type). The method 100 proceeds to operation 104, in which a recessed region is formed over the substrate. In some embodiments, the recessed region, formed as a ring-like structure, extends into the substrate from its front surface. The method 100 proceeds to operation 106, in which an insulating dielectric is deposited over the substrate. In some embodiments, the insulating dielectric overlies the front surface of the substrate and accordingly fills the recessed region. The method 100 proceeds to operation 108, in which an insulating element is formed. In some embodiments, the insulating element is formed by a polishing process (e.g.,a chemical mechanical polishing (CMP) process) is performed on the insulating dielectric until the front surface of the substrate is exposed again. Thus, the isolation element can follow the profile of the recessed region (e.g., the ring-like structure). In other words, the isolation element defines (e.g., surrounds) an active region in which at least one pixel is to be formed. The method 100 proceeds to operation 110, in which a first semiconductor region is formed over the substrate. In some embodiments, the first semiconductor region is doped with a second doping type (e.g., n-type) that is opposite to the first doping type. Furthermore, the first semiconductor region is laterally surrounded by the isolation element (i.e., it lies in the above-mentioned active region) and extends inward into the substrate to a first depth.The method 100 proceeds to operation 112, in which a second semiconductor region is formed over the first semiconductor region. In some embodiments, the second semiconductor region is doped with the first doping type (e.g., p-type). Furthermore, the second semiconductor region extends inward into the substrate (or the first semiconductor region) to a second depth that is less than the first depth. Thus, a junction associated with two different doping types (two different conductivity types) may be formed in the substrate and surrounded by the isolation element.

[0012] Next, the method 100 proceeds to operation 114, in which at least a portion of the isolation element is recessed. In some embodiments, after the at least a portion of the isolation element is recessed, a portion of the recessed area (formed in operation 104) that was filled by the insulating dielectric may be re-exposed. The method 100 proceeds to operation 116, in which a gate dielectric layer is formed. In some embodiments, the gate dielectric layer is formed over the front surface of the substrate, which accordingly lines the recessed portion of the isolation element. The method 100 proceeds to operation 118, in which a gate material is formed over the gate dielectric layer. Such a gate material may, for example, comprise a polysilicon material.Because the gate material layer (formed in operation 116) is substantially thin, in some embodiments, a "trench" may still be present after the gate dielectric layer is formed. Therefore, the gate material, typically formed as a relatively thick layer, may refill the trench and overlie the front surface of the substrate. In other words, a portion of the gate material, lined by a portion of the gate material layer, extends inward into the substrate through the isolation element, which is described in more detail below. The method 100 proceeds to operation 120, in which a gate stack is formed over the substrate. In some embodiments, the gate stack includes a patterned gate dielectric layer and a gate material extending into the substrate and protruding from the front surface of the substrate.

[0013] In some embodiments, operations of the method 100 may be associated with cross-sectional views of a semiconductor device 200 at various stages of manufacture, as shown in the Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H, Fig. 2I and 2J, respectively. In some embodiments, the semiconductor device 200 may comprise only one of a plurality of pixels of an image sensor device. The image sensor device 200 may be provided in a microprocessor, a memory cell, and / or another integrated circuit (IC). In addition, the Fig. 2A to 2J are simplified to better understand the concepts of the present disclosure. For example, it should be understood that although the figures show the image sensor device 200, the IC in which the image sensor device 200 is formed may include any desired number of additional devices, including resistors, capacitors, inductors, fuses, etc., as well as additional pixels, each substantially similar to the pixel shown, that are shown in the Fig. 2A to 2J are not shown for the purpose of clarity of illustration.

[0014] According to process 102 of Fig. 1 is Fig. 2A shows a cross-sectional view of the image sensor device 200, which includes a substrate 202 provided at one of the various manufacturing stages according to some embodiments. As shown, the substrate 202 includes a front surface 203 (also referred to as the front side) and a back surface 205 (also referred to as the back side). The substrate 202 includes a silicon substrate doped with a dopant of the first doping type (e.g., a p-type dopant), such as boron, in which case the substrate 202 is a p-type substrate. In some further embodiments, the substrate 202 may include another suitable semiconductor material. For example, the substrate 202 may be a silicon substrate doped with a dopant of a different doping type (e.g., an n-type dopant), such as phosphorus or arsenic, in which case the substrate 202 is an n-type substrate.For consistency, the p-type dopant and the n-type dopant are referred to herein as "first-type dopant" and "second-type dopant," respectively, in the following descriptions. In still some other embodiments, the substrate 202 may comprise other elemental semiconductors such as germanium and diamond. The substrate 202 may optionally comprise a compound semiconductor and / or an alloy semiconductor. Further, in some alternative embodiments, the substrate 202 may comprise an epitaxial (epi) layer, may be strained to improve performance, and may comprise a silicon-on-insulator (SOI) structure.

[0015] According to process 104 of Fig. 1 is Fig. 2B is a cross-sectional view of the image sensor device 200 including a recessed region 206 formed at one of the various manufacturing stages according to some embodiments. As shown, the recessed region 206 is formed to extend inward from the front surface 203 into the substrate 202. In some embodiments, when viewed from above, the recessed region 206 may be formed as a ring-like structure surrounding an active region 207, wherein such an active region 207 may be used to form at least one pixel of the image sensor device 200, which may include at least one photodiode and one pixel transistor, as described below.

[0016] In some embodiments, the recessed region 206 may be formed by performing at least some of the following processes: using chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, and / or other suitable techniques to deposit one or more removable layers (e.g., a photoresist layer, a hard mask layer, etc.) over the front surface 203 of the substrate 202; performing one or more patterning processes (e.g., a lithography process, a dry / wet etch process, a cleaning process, a soft / hard bake process, etc.)) to form an opening through the one or more removable layers; using one or more (dry and / or wet) etching processes, wherein the one or more patterned removable layers serve as a mask, to recess a top portion of the substrate 202; and removing the one or more removable layers.

[0017] According to process 106 of Fig. 1 is Fig. 2C shows a cross-sectional view of the image sensor device 200 including an insulating dielectric 208 deposited at one of the various manufacturing stages according to some embodiments. As shown, the insulating dielectric 208 is formed to overlie the front surface 203 of the substrate 202 and thus fill the recessed region 206. In some embodiments, the insulating dielectric 208 may comprise any of a variety of oxide materials, for example, silicon oxide. In some embodiments, the recessed region 206 is filled by the insulating dielectric 208 using CVD, PVD, and / or other suitable deposition techniques to overlie the front surface 203 of the substrate 202.

[0018] According to process 108 of Fig. 1 is Fig. 2D shows a cross-sectional view of the image sensor device 200 including an isolation element 210 formed in one of the various manufacturing stages according to some embodiments. In some embodiments, the isolation element 210 is the insulating dielectric filling the recessed region 206. Accordingly, the isolation element 210 may follow the same profile as the recessed region 206, i.e., the ring-like structure surrounding the active region 207. The isolation element 210 is typically referred to as a shallow trench isolation (STI) element. Although in the embodiment shown by Fig. 2D (and the following figures), it is understood that one or more further isolation elements (e.g., a deep trench isolation element) may be formed around the isolation element 210 to further improve the isolation capability of the isolation element 210 (e.g., reducing the overlaps between neighboring pixels). In some embodiments, the isolation element 210 may be formed by performing a polishing process (e.g., a chemical mechanical polishing (CMP) process) on the insulating dielectric ( Fig. 2C) until the front surface 203 of the substrate 202 is exposed again.

[0019] According to process 110 of Fig. 1 is Fig. 2E shows a cross-sectional view of the image sensor device 200 including a first semiconductor region 212 formed at one of the various manufacturing stages according to some embodiments. As shown, the first semiconductor region 212 is formed along the front surface 203 of the substrate 202 so as to partially overlie the substrate 202, with a portion 213 of the substrate 202 exposed, and extends from the front surface 203 inward into the substrate 202 by a depth 212'. In some embodiments, the first semiconductor region 212 is doped with the second doping type (the n-type) that is opposite to the doping type of the substrate 202. In some alternative embodiments, the first semiconductor region 212 may be formed along the front surface 203 of the substrate 202 so as to completely overlie the substrate 202 (i.e., there is no such exposed portion 213).

[0020] In some embodiments, the first semiconductor region 212 may be formed by at least some of the following methods: using chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, and / or other suitable techniques to deposit a removable layer (e.g., a photoresist layer, a hard mask layer, etc.) over the substrate 202; performing one or more patterning processes (e.g., a lithography process, a dry / wet etch process, a cleaning process, a soft / hard bake process, etc.) to form an opening through the removable layer, wherein the opening is surrounded by the isolation element 210; performing a doping process (e.g., an ion implantation process, a diffusion process, etc.), wherein the patterned removable layer serves as a mask to incorporate a plurality of dopants having the second doping type (the n-type) into the substrate 202; removing the removable layer; and performing an optional annealing process to activate the incorporated dopants.

[0021] According to process 112 of Fig. 1 is Fig. 2F shows a cross-sectional view of the image sensor device 200 including a second semiconductor region 214 formed at one of the various manufacturing stages according to some embodiments. As shown, the second semiconductor region 214 is formed along the front surface 203 of the substrate 202 so as to overlie the first semiconductor region 212, exposing a portion 215 of the first semiconductor region 212, and extending inward into the first semiconductor region 212 by a depth 214' that is less than the depth 212' of the first semiconductor region 212.

[0022] In some embodiments, the second semiconductor region 214 is also doped with the first doping type (the p-type), similar to the substrate 202, but at an increased concentration. Thus, a pn junction 215 may be formed at the interface between the first semiconductor region 212 and the second semiconductor region 214, and in some embodiments, the first semiconductor region 212 and the second semiconductor region 214 (with the pn junction 215) may serve as the pixel's photodiode surrounded by the isolation element 210. According to the present disclosure, such a photodiode may be configured to convert a radiation source (e.g., light) incident from either the front surface 203 or the back surface 205 into an electrical current signal, which will be described in more detail below.Furthermore, according to some embodiments, the second semiconductor region 214, typically referred to as a “pinned layer,” may be configured to provide an isolation element for the first semiconductor region 212, at least in part due to the increased doping concentration.

[0023] In some embodiments, the second semiconductor region 214 may be formed by at least some of the following methods: using chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, and / or other suitable techniques to deposit a removable layer (e.g., a photoresist layer, a hard mask layer, etc.) over the substrate 202; performing one or more patterning processes (e.g., a lithography process, a dry / wet etch process, a cleaning process, a soft / hard bake process, etc.) to form an opening through the removable layer, wherein the opening is aligned with the first semiconductor region 206 (e.g., laterally included within the area defined by the first semiconductor region 206); performing a doping process (e.g., an ion implantation process, a diffusion process, etc.), wherein the patterned removable layer serves as a mask to incorporate a plurality of dopants having the first doping type (the p-type) into the first semiconductor region 206; removing the removable layer; and performing an optional annealing process to activate the incorporated dopants.

[0024] According to process 114 of Fig. 1 is Fig. 2G shows a cross-sectional view of the image sensor device 200 in which a portion of the isolation element 210 is recessed in one of the various manufacturing stages according to some embodiments. As in the embodiment shown in Fig. 2G (and the following figures), the recessed portion of the insulation element 210 is arranged laterally adjacent to the exposed portion 213 of the front surface 203, forming a trench 218 laterally adjacent to the exposed portion 213 of the front surface 203. Note that the trench 218 is part of the recessed area 206 ( Fig. 2B). More specifically, in some embodiments, after forming the trench 218, at least corresponding upper portions of the sidewalls of the recessed region 206 (also referred to as sidewalls 218-1 of the trench 218) and / or at least a portion of a lower edge of the recessed region 206 (also referred to as lower edge 218-2 of the trench 218) are each re-exposed.

[0025] In some embodiments, the trench 218 may be formed by performing at least some of the following processes: using chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, and / or other suitable techniques to deposit one or more removable layers (e.g., a photoresist layer, a hard mask layer, etc.) over the front surface 203 of the substrate 202; performing one or more patterning processes (e.g., a lithography process, a dry / wet etch process, a cleaning process, a soft / hard bake process, etc.)) to form an opening through the one or more removable layers, the opening aligned with a region in which the trench 218 is to be formed; using one or more (dry and / or wet) etching processes, with the one or more patterned removable layers serving as a mask, to recess a portion of the isolation element 210; and removing the one or more removable layers.

[0026] According to process 116 of Fig. 1 is Fig. 2H shows a cross-sectional view of the image sensor device 200 including a gate dielectric layer 220 formed at one of the various manufacturing stages according to some embodiments. As shown, the gate dielectric layer 220 is formed to overlie the substrate 202. More specifically, the gate dielectric layer 220 overlies the isolation element 210, the first and second semiconductor regions 212 and 214, the exposed portion 213 of the front surface 203 of the substrate 202, and the trench 218. In some embodiments, since the gate dielectric layer 220 is substantially thin and conformal, the gate dielectric layer 220 may be formed to line the trench 218, i.e., extend along the sidewalls 218-1 and the bottom edge 218-2, while not completely filling the trench 218.

[0027] In some embodiments, the gate dielectric layer 220 is formed from a high-k dielectric constant (hereinafter "high-k" or "HK") material. The high-k material may comprise a metal oxide, a metal nitride, a metal silicate, a transition metal oxide, a transition metal nitride, a transition metal silicate, an oxynitride of metals, a metal aluminate, a zirconium silicate, a zirconium aluminate, combinations thereof, or other suitable compositions. Example high-k materials further include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), combinations thereof, and / or other suitable materials.Alternatively, the high-k materials may include other high-k dielectrics, such as LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfLaO, HfSiO, LaSiO, AlSiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, and / or other suitable materials. Although described herein as an embodiment including high-k materials, other dielectrics (e.g., SiO2) are possible. In some embodiments, the gate dielectric layer 220 may be formed using an atomic layer deposition (ALD), CVD, or PVD technique to deposit at least one of the above-mentioned dielectrics over the substrate 202.

[0028] According to process 118 of Fig. 1 is Fig. 2I illustrates a cross-sectional view of the image sensor device 200 including a gate material 222 formed at one of the various manufacturing stages, according to some embodiments. As shown, the gate material 222 overlies the substrate 202, and since the gate material 222 is formed to be substantially thick, the trench 218 is refilled with the gate material 222. According to some embodiments, the gate material 222, which may comprise, for example, a polysilicon material, may be formed using a CVD or PVD technique to deposit the polysilicon over the substrate 202.

[0029] According to process 120 of Fig. 1 is Fig. 2J shows a cross-sectional view of the image sensor device 200 including a gate stack 226 formed in one of the various manufacturing stages according to some embodiments. According to some embodiments, the gate stack 226 includes a patterned gate dielectric layer 220' and a patterned gate material 222'. In the illustrated embodiment of Fig. 2J, the gate stack 226 includes at least two portions: a first portion 226-1 extending laterally along the front surface 203 of the substrate 202; and a second portion 226-2 extending from the front surface 203 inward into the substrate 202. Further, in some embodiments, the first portion 226-1 extends laterally along the front surface 203 of the substrate 202 to at least partially overlie the portion 215 of the first semiconductor region 212.

[0030] In some embodiments, the gate stack 226 may be formed by performing at least some of the following processes: using chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, and / or other suitable techniques to deposit one or more removable layers (e.g., a photoresist layer, a hard mask layer, etc.) over the gate material 222; performing one or more patterning processes (e.g., a lithography process, a dry / wet etch process, a cleaning process, a soft / hard bake process, etc.) to form an opening through the one or more removable layers, the opening aligned with a region in which the gate stack 226 is not to be formed; using one or more (dry and / or wet) etching processes, with the one or more patterned removable layers serving as a mask, to recess respective portions of the gate material 222 and the gate dielectric layer 220; and removing the one or more removable layers.

[0031] As mentioned above, the first and second semiconductor regions 212 and 214 form the photodiode of the pixel surrounded by the isolation element 210. In some embodiments, the gate stack 226 may be formed as a "transfer gate" of a transfer transistor of the pixel. In operation, the photodiode first absorbs a radiation source incident from either the front surface 203 or the back surface 205 and converts the radiation source into a plurality of electron-hole pairs in the first semiconductor region 212 (e.g., near the portion 215). Then, in some embodiments, the gate stack 226 is configured to serve as a gate to allow a "flow" of the generated electron-hole pairs (i.e., an electrical current signal) into a floating diffusion region (in the cross-sectional view of Fig. 2J not shown). Such a diffusion region is further coupled to one or more other transistors (e.g., a reset transistor, a source follower transistor, a select transistor, etc.) of the pixel to enable the one or more other transistors to further process the generated electrical current signal.

[0032] In the conventional image sensor device, the above-described gate stack of the transfer transistor is typically formed to extend only along the front surface 203 (i.e., it does not have a second portion 226-2). Various problems may arise when forming the gate stack of the transfer transistor in such a fully lateral configuration. For example, since the gate stack of the transfer transistor in each of a plurality of pixels of the conventional image sensor device extends only along a single direction, the above-mentioned floating diffusion region can only be formed along this single direction. Thus, respective center-to-center pitches available for forming the photodiodes across the plurality of pixels are significantly limited over a given length along this direction.Accordingly, an area available for forming the photodiode is reduced, which disadvantageously lowers the fill factor, which in turn degrades the performance of the conventional image sensor devices.

[0033] Fig. 3 shows an exemplary top view 300 of the image sensor device 200 according to various embodiments. Note that the Fig. 2A-2J are each taken along line AA of the plan view 300. Accordingly, the gate stack 226 may include, in addition to the first and second sections 226-1 and 226-2, as shown in Fig. 2J, further comprise a portion 226-3 extending laterally from the first portion 226-1 and, in particular, inclined relative to the first portion 226-1. In some embodiments, such an inclined portion 226-3 may be disposed above the front surface 203 ( Fig. 2J), ie it does not extend into the substrate 202, which allows the photodiode (formed by the first and second semiconductor regions 212 and 214) to be arranged on one side 301 of the inclined section 226-3, and the above-described floating diffusion region (305 in the embodiment shown in Fig. 3) is arranged on another side 303 of the inclined portion 226-3, which is opposite to side 301. Thus, additional spacing along line AA can be eliminated, which can significantly increase the respective center-to-center distances available for forming the photodiodes across the majority of pixels of the disclosed image sensor device 200. Thus, the performance of the disclosed image sensor device 200 can be advantageously improved compared to conventional image sensor devices.

[0034] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims.

Claims

[1] A semiconductor device (200) comprising: a photodiode formed in a substrate (202), the photodiode comprising a first semiconductor region (212) in the substrate (202) doped with a first doping type and a second semiconductor region (214) over the first semiconductor region (212) doped with a second doping type; and at least one transistor having a gate element (226) extending at least partially from a main surface of the substrate (202) into the substrate (202), wherein the gate element (226) of the at least one transistor comprises a first portion (226-1) extending over the main surface of the substrate (202) and a second portion (226-2) extending from the main surface of the substrate (202) into the substrate (202), wherein the semiconductor device (200) comprises an insulating element (210) extending into the substrate (202) surrounding the photodiode and the at least one transistor, wherein the second portion (226-2) fills a recessed part of the insulating element (210), wherein the photodiode and the at least one transistor at least partially form a pixel. [2] The semiconductor device (200) of claim 1, wherein the first and second doping types are different from each other. [3] The semiconductor device (200) of claim 1, wherein the first portion (226-1) of the gate element (226) of the at least one transistor is laterally connected to the first semiconductor region (212) and the second portion (226-2) of the gate element (226) of the at least one transistor is laterally spaced from the first semiconductor region (212). [4] A semiconductor device (200) according to any one of the preceding claims, wherein the gate element (226) of the at least one transistor comprises a gate oxide layer and a polysilicon layer, each comprising a lateral portion extending along the main surface of the substrate (202) and a vertical portion extending into the substrate (202). [5] A semiconductor device (200) according to any one of the preceding claims, wherein the at least one transistor is a transfer gate transistor of the pixel. [6] Semiconductor device (200) according to one of the preceding claims, wherein the second semiconductor region (214) is formed such that a part of the first semiconductor region (212) is not overlaid by the second semiconductor region (214). [7] The semiconductor device (200) of any preceding claim, wherein the first portion (226-1) extends to at least partially overlie the first semiconductor region (212). [8] A semiconductor device (200) comprising: a photodiode formed in a substrate (202); and at least one transistor having a gate stack (226) comprising a first portion (226-1) and a second portion (226-2) connected to one end of the first portion (226-1), wherein the first portion (226-1) is arranged over and extends along a main surface of the substrate (202) and the second portion (226-2) extends from the main surface of the substrate (202) into the substrate (202), wherein the gate stack (226) comprises a third portion (226-3) extending laterally from the first portion (226-1) and is inclined relative to the first portion (226-1), wherein the photodiode and the at least one transistor at least partially form a pixel. [9] The semiconductor device (200) of claim 8, wherein the photodiode comprises: a first semiconductor region (212) in the substrate (202) doped with a first doping type; and a second semiconductor region (214) over the first semiconductor region (212) doped with a second doping type. [10] The semiconductor device (200) according to claim 9, wherein the second semiconductor region (214) is formed such that a part of the first semiconductor region (212) is not overlaid by the second semiconductor region (214). [11] The semiconductor device (200) of claim 9 or 10, wherein the first and second doping types are different from each other. [12] The semiconductor device (200) of any one of claims 8 to 11, wherein the first portion (226-1) of the gate stack (226) of the at least one transistor is laterally connected to the first semiconductor region (212) and the second portion (226-2) of the gate stack (226) of the at least one transistor is laterally spaced from the first semiconductor region (212). [13] The semiconductor device (200) of any one of claims 8 to 12, wherein the gate stack (226)l of the at least one transistor comprises a gate oxide layer and a polysilicon layer, each comprising a lateral portion extending along the main surface of the substrate (202) and a vertical portion extending into the substrate (202). [14] The semiconductor device (200) of any one of claims 8 to 13, wherein the at least one transistor is a transfer gate transistor of the pixel. [15] A semiconductor device (200) according to any one of claims 8 to 14, further comprising: an insulation element (210) extending into the substrate (202) surrounding the photodiode and the at least one transistor. [16] The semiconductor device (200) of claim 15, wherein at least a portion of the isolation element (210) directly contacts the second portion (226-2) of the gate stack (226) of the at least one transistor. [17] Method comprising: Forming an insulating element (210) extending into a substrate (202); Forming a first semiconductor region (212) and a second semiconductor region (214) in the substrate (202) which are surrounded by the insulating element (210), wherein the first and second semiconductor regions (212, 214) form a photodiode of a pixel of an image sensor device (200); Deepening a portion of the insulation element (210) to expose a sidewall (218-1) of the insulation element (210) facing the first and second semiconductor regions (214) but laterally spaced therefrom; and Forming a gate element (226) extending along a main surface of the substrate (202) and filling the recessed part (218) of the insulation element (210), wherein the gate element (226) is part of a transistor of the image sensor device (200), wherein the photodiode and the transistor at least partially form a pixel, wherein the gate element (226) comprises a first portion (226-1) and a second portion (226-2), wherein the first portion (226-1) extends over the main surface of the substrate (202) and wherein the second portion (226-2) fills the recessed part (218). [18] The method of claim 17, wherein the gate element (226) is part of a transfer gate transistor of the pixel of the image sensor device (200) connected to the photodiode. [19] The method of claim 17 or 18, wherein the gate element (226) comprises a gate oxide layer (220') and a polysilicon layer (222'), each comprising a lateral portion extending along the major surface of the substrate (202) and a vertical portion extending into the substrate (202). [20] The method of any one of claims 17 to 19, wherein the first portion (226-1) extends to at least partially overlie the first semiconductor region (212).

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