Semiconductor chip with a silicon carbide substrate

Abstract

The invention relates to a semiconductor chip (1) with a semiconductor device (100) in a semiconductor body (10), wherein the semiconductor body (10) is a silicon carbide substrate (11); an epitaxial silicon carbide layer system (12) on a first side (11.1) of the silicon carbide substrate (11); a discontinuity layer (13); wherein the discontinuity layer (13) is embedded either in the silicon carbide substrate (11) or in the epitaxial silicon carbide layer system (12), each at a vertical distance (20) from the first side (11.1) of the silicon carbide substrate (11).

Description

TECHNICAL AREA

[0001] The invention relates to a semiconductor chip with a semiconductor component in a semiconductor body which has a silicon carbide substrate. BACKGROUND

[0002] Silicon carbide (SiC) exhibits a comparatively wide bandgap, for example, compared to silicon. This can enable high-voltage and / or high-current capabilities and is of particular interest for power semiconductor devices. These find applications in various fields such as high-voltage direct current transmission, for example in offshore wind farms or similar applications. SUMMARY

[0003] Examples in the present application relate to an advantageous semiconductor chip with a silicon carbide substrate.

[0004] In one embodiment, a semiconductor chip comprises a semiconductor device within a semiconductor body. The semiconductor body includes, in addition to a silicon carbide (SiC) substrate, an epitaxial SiC layer system and a discontinuity layer. The epitaxial SiC layer system is arranged on a first face of the SiC substrate. The discontinuity layer is embedded either in the SiC substrate or in the epitaxial SiC layer system, each at a vertical distance from the first face of the SiC substrate. In other words, the discontinuity layer can be located below the first face in the SiC substrate or above the first face in the epitaxial SiC layer system, but in both cases, it is vertically spaced from the first face.

[0005] The interruption layer can be an amorphous and / or porous layer, as well as a highly doped layer. It can form or serve as an interruption in the crystal structure, or it can interrupt (e.g., significantly reduce) electron-hole (eh) recombination, for example, by shielding the interface between the substrate and the epitaxial layer system from eh recombination. At this interface ("first side" of the SiC substrate) between the SiC substrate and the epitaxial SiC layer system, so-called conversion points can be found, which can result from the conversion of basal plane dislocations (BPD) in the substrate to thread-edge dislocations (TED) in the epitaxial layer system.

[0006] While TEDs may be less critical, stacking fault growth can occur once eh recombination reaches the conversion points. Although this bipolar degradation occurs in bipolar mode, the resulting stacking faults remain in unipolar mode and can, for example, affect the electrical properties of the device. A disruption layer embedded in the substrate or epitaxial layer system can, for example, "interrupt" stacking fault growth due to the "disrupted" crystal structure and / or "interrupt" it, for example, significantly reduce eh recombination across the interface.

[0007] Specific embodiments and features are provided in this description, the figures, and the dependent claims. The individual features are disclosed independently of any specific claim category; the disclosure relates to aspects of the device and components, as well as to aspects of the process and use. For example, if a chip manufactured in a specific way is described, this also constitutes a disclosure of the corresponding manufacturing process, and vice versa. In general terms, one approach of this application is to introduce a discontinuity layer into a semiconductor body comprising a SiC substrate and an epitaxial SiC layer system, particularly at a vertical distance from the interface between the substrate and the epitaxial layer system.

[0008] The SiC substrate can have a principal plane of extension spanned by lateral directions (also referred to as "horizontal directions"). The vertical direction can be essentially perpendicular to the lateral directions, and the vertical extension of the SiC substrate can be small compared to its lateral extension. In some examples, the SiC substrate can comprise or consist essentially of 2H-SiC (SiC of the 2H polytype), 6H-SiC, 3C-SiC, or 15R-SiC. In one example, the semiconductor material is silicon carbide of the hexagonal 4H polytype (4H-SiC). An angle off-axis of the SiC substrate can range from 2° to 8°, typically 4°. The first side of the SiC substrate can then be ribbed, so that sections of the first side can be inclined with respect to the lateral directions and / or the horizontal direction.For example, a principal crystal axis (e.g., the <0001> -axis) of the SiC substrate enclose an angle (e.g. the angle outside the axis) with the vertical direction.

[0009] The "vertical distance" is measured in the vertical direction. More precisely, it is defined as the smallest distance, namely the distance (not center-to-center). By definition, all layers or layer systems of the semiconductor body have a first side and a vertically opposite second side, with the first sides oriented in the same vertical upward direction and the second sides oriented in the same vertical downward direction. For example, the first side of the epitaxial SiC layer system faces away from the SiC substrate and / or the second side of the SiC substrate faces away from the epitaxial SiC layer system. "Above" means closer to the first side of the semiconductor body, and "below" means closer to the second side of the semiconductor body.

[0010] The epitaxial SiC layer system comprises at least one epitaxial SiC layer. In particular, it can comprise a plurality of stacked layers, for example, a device layer or layers, especially with a buffer layer underneath. An active region or regions of the device can be arranged in the device layer(s). Alternatively or additionally to an n-region, the device can, in particular, comprise a p-region, e.g., depending on the device type, an anode contact in the case of a diode or a body region in the case of an nFET.

[0011] Since it is a "layer," the interruption layer can have a greater lateral extent than its thickness, e.g., a greater extent in each lateral direction compared to its extent in the vertical direction. Relative to the area of ​​the chip, the interruption layer can, for example, extend over at least 50%, 70%, or 90% of the chip's area. In one embodiment, the interruption layer extends over the entire area of ​​the chip.

[0012] In general, the semiconductor body can include an additional ("second") disruption layer in addition to the ("first") disruption layer discussed so far. For example, one disruption layer can be embedded in the SiC substrate, while the other is embedded in the epitaxial SiC layer system. Alternatively, the semiconductor body can include only a single disruption layer, and the disclosure is intended to cover both options unless otherwise stated. In other words, "the disruption layer" can be the only disruption layer in the semiconductor body, or it can be a first disruption layer combined with a second disruption layer.

[0013] In one embodiment, the vertical distance between the first side of the SiC substrate and the interruption layer is at least 0.1 µm, and in particular at least 0.2 µm. Upper limits of the vertical distance can be, for example, 1 µm, 0.7 µm, or 0.5 µm. The interruption layer is positioned at a vertical distance, but not too far, from the interface / first side of the SiC substrate.

[0014] As described above, the interruption layer is embedded in the SiC substrate or in the epitaxial SiC layer system. "Embedded" can refer to the vertical direction, so that, for example, in the case of the SiC substrate, an upper end (first side) of the interruption layer may be located below the first side of the SiC substrate, and a lower end (second side) of the interruption layer may be located above the second side of the SiC substrate. In the case of the epitaxial SiC layer system, for example, an upper end (first side) of the interruption layer may be located below the first side of the epitaxial SiC layer system, and a lower end (second side) of the interruption layer may be located above the second side of the epitaxial SiC layer system. In other words, in the case of embedding in the SiC substrate, a corresponding portion of the SiC substrate is located above and below the interruption layer.In the case of embedding in the epitaxial SiC layer system, a corresponding part of the epitaxial SiC layer system is arranged above and below the interruption layer.

[0015] In one embodiment, the interruption layer has a vertical thickness of at least 0.1 µm (or at least 0.2 µm, or at least 0.3 µm, or at least 0.5 µm) and / or not more than 5 µm. Regarding the vertical spacing, the thickness is measured in the vertical direction. Depending on, for example, the specific interruption layer type and its manufacturing process, limiting the thickness can offer economic advantages.

[0016] In one embodiment, the interruption layer is a highly doped layer. In the epitaxial SiC layer system with a buffer layer, the highly doped interruption layer can, in particular, have a higher doping concentration than the buffer layer. When positioned above the interface, i.e., embedded in the epitaxial SiC layer system, the shielding properties of the highly doped interruption layer can significantly reduce eh recombination across the interface with the conversion points. Alternatively or additionally, the high-dose implantation can disrupt the crystal structure. Thus, high-dose implantation can also be a means of producing an amorphous and / or porous layer, which is deposited solely for this reason, or in combination with the shielding properties, due to the physical disruption of the crystal structure.

[0017] In one embodiment, the disruption layer is an amorphous and / or porous layer. When embedded in the epitaxial SiC layer system, the amorphous / porous disruption layer can, for example, halt or interrupt the dislocations themselves, namely the stacking fault growth from the interface to the first face of the semiconductor body. This growth to the first face can also be interrupted, however, if the amorphous / porous disruption layer is embedded in the SiC substrate, as detailed below. As an alternative to high-dose implantation, the amorphous / porous layer can be formed, for example, by laser irradiation and / or porosification.

[0018] In one embodiment, the epitaxial SiC layer system comprises a device layer and a buffer layer positioned between the device layer and the SiC substrate. Specifically, the buffer layer can be directly adjacent to the first side of the SiC substrate, and / or the device layer can be directly adjacent to the first side of the buffer layer. The doping concentration of the buffer layer can be higher than that in the device layer, for example, higher than in a region of the device layer directly adjacent to the buffer layer. In other words, the doping concentration in the buffer layer can be higher, for example, than in a drift region formed in the device layer. Regarding a highly doped interruption layer, its doping concentration can be higher than that of the buffer layer.

[0019] Regardless of these details, the buffer layer positioned above the interface can, for example, shield the conversion points from the device layer. The hole density can become particularly high in the drift region, with the holes reaching the conversion points, for instance, with increasing current density. Although this could be counteracted by increasing the thickness and doping concentration of the buffer layer, there may be limitations for economic and technical reasons. In this respect, one approach of this application is to combine the buffer layer with the interruption layer.

[0020] In one embodiment, the disruption layer is embedded in the buffer layer, such that a lower section of the buffer layer is located below the disruption layer and an upper section of the buffer layer is located above it. In the case of an amorphous / porous disruption layer, the disruption of the crystal structure can, for example, stop further dislocation or stacking fault growth if eh recombination reaches the conversion points despite the buffer layer. Alternatively or additionally, if the disruption layer has a higher doping concentration compared to the buffer layer, it can, for example, provide some separation of eh recombination and the conversion points at the interface, thus significantly reducing eh recombination and dislocation growth.

[0021] In one embodiment relating to the amorphous and / or porous interruption layer, this layer is embedded in the SiC substrate. In other words, the interruption layer is located at a vertical distance below the interface / first side of the substrate. For example, the upward growth of a dislocation from the interface may, for geometric reasons, result in or require a "mirror image" dislocation that propagates downwards within the substrate. This downward propagation can be stopped by the amorphous / porous layer embedded in the substrate, which conversely can also stop the upward propagation.

[0022] In one embodiment, a metallization layer is arranged on the second side of the SiC substrate, which is the second side of the semiconductor body. In other words, the chip has a backside metallization, for example, in combination with a frontside metallization on the first side of the semiconductor body. The backside metallization layer can serve, for example, for mounting the chip in a package and / or, in particular, as an electrical contact for the component. This applies especially to a vertical component with its load contacts on opposite sides of the semiconductor body.

[0023] In one embodiment, the device is a FET with a source region and a drain region. In particular, it can be a vertical FET with its source region and drain region on opposite sides of the semiconductor body, e.g., the source region on the first side and the drain region on the second side. Then, the backside metallization can be, in particular, the drain metallization of the vertical FET or be encompassed by it.

[0024] In one embodiment, the chip comprises an additional (“second”) interruption layer, which may be arranged, in particular, “complementary” to the first interruption layer. For example, one interruption layer may be embedded in the SiC substrate, while the other interruption layer is embedded in the epitaxial SiC layer system. The additional or “second” interruption layer is not necessarily arranged at a vertical distance from the interface between the substrate and the epitaxial layer system, but may generally be directly adjacent to the interface. Such an interruption layer, which is arranged, in particular, between the SiC substrate and a buffer layer (see above), is also disclosed regardless of a vertical distance from the interface and regardless of whether only one or two interruption layers are present.In other words, a semiconductor chip comprising a semiconductor device in a semiconductor body is disclosed, wherein the semiconductor body comprises: a silicon carbide substrate; an epitaxial silicon carbide layer system on a first side of the silicon carbide substrate; a discontinuity layer; wherein the epitaxial silicon carbide layer system comprises a buffer layer, and wherein the discontinuity layer is arranged on the first side of the silicon carbide substrate between the silicon carbide substrate and the buffer layer. In particular, this discontinuity layer can be directly adjacent to the first side of the SiC substrate.

[0025] The application also relates to a package comprising the semiconductor chip and a housing in which the chip is mounted and electrically contacted. In particular, a backside metallization (see above) of the chip can be contacted in the housing, for example, connected to a pin of the package. In the example just given, this can be the drain pin of the package.

[0026] The application further relates to a method for manufacturing a semiconductor chip or package. In addition to the epitaxial deposition of an epitaxial SiC layer system onto a SiC substrate, the method includes the formation of the interruption layer.

[0027] A disruption layer can be formed, in particular, by high-dose implantation (“highly doped layer,” see above), which can be applied due to the shielding properties and / or the associated disruption of the crystal structure. Alternatively, an amorphous / porous layer can be formed by laser irradiation, whereby SiC, for example, can be split into Si and C at the laser focus. Specifically, the laser focus plane can be chosen slightly below the irradiation surface, for example, slightly below the first face of the SiC substrate, to embed the disruption layer within it (or slightly below the first face of the buffer layer, to embed the disruption layer within it).

[0028] Alternatively, the amorphous / porous layer can be formed through porosification, specifically in an etching process. These different manufacturing methods can be combined or applied as alternatives. Depending on the position of the interruption layer, its formation can be implemented at different steps in the process. For example, the interruption layer embedded in the SiC substrate can be formed before the deposition of the epitaxial SiC layer system.

[0029] Conversely, the formation of the interruption layer embedded in the epitaxial SiC layer system can be integrated into the deposition process itself. In particular, the interruption layer can be formed after the deposition of the buffer layer, for example, at least after the deposition of its lower portion, and before the deposition of the device layer. In one embodiment, the interruption layer is produced after the deposition of the lower portion of the buffer layer and before the deposition of the upper portion of the buffer layer. In particular, a high-dose implantation step can be implemented in between to form the highly doped interruption layer embedded in the buffer layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The chip and other embodiments will be discussed in more detail below using exemplary embodiments. The individual features may also be relevant in other combinations. Fig. Figure 1 shows a chip with an epitaxial SiC layer system on a SiC substrate, in which a disruption layer is embedded; Fig. Figure 2 shows a chip with a SiC substrate and an epitaxial SiC layer system in which a disruption layer is embedded; Fig. Figure 3 shows a cross-sectional view of a component formed in the chip; Fig. Figures 4a-c show schematic views of different possibilities for producing the interruption layer; Fig. Figure 5 shows a cross-section through a package containing the chip; Fig. Figure 6 shows some of the manufacturing steps in a flowchart. SPECIAL DESIGNS

[0031] Fig. Figure 1 shows a schematic cross-section through a semiconductor chip 1 with a semiconductor body 10. The semiconductor body 10 comprises a silicon carbide (SiC) substrate 11 and an epitaxial SiC layer system 12. The epitaxial SiC layer system 12 is epitaxially deposited onto a first side 11.1 of the SiC substrate 11; in the example shown, it comprises a device layer 16 and a buffer layer 15 below it. On the second side 11.2 of the SiC substrate 11, which is the second side 10.2 of the semiconductor body 10, a metallization layer 30 is arranged, see Figure 1. Fig. 3 and Fig. 5 for more details.

[0032] Additionally, the semiconductor body 10 comprises a discontinuity layer 13. In the embodiment of Fig. 1 It is embedded in the SiC substrate 11 at a vertical distance 20 from the first side 11.1, which is the interface between the SiC substrate 11 and the epitaxial SiC layer system 12. Conversion points 40 may be located at the interface (only one is shown for clarity), which can be a starting point for the growth of a dislocation or a stacking fault 41, e.g., in bipolar mode. The interruption layer 13, provided as an amorphous / porous layer, can interrupt the crystal structure and stop a mirror stacking fault 42. Consequently, it can also interrupt further upward propagation of the stacking fault 41.

[0033] The interruption layer 13 can, for example, have a vertical thickness 25 of approximately 2.5 µm. The vertical spacing 20 can, for example, be approximately 0.5 µm. The interruption layer 13 can be produced prior to the deposition of the epitaxial SiC layer system, for example, by laser irradiation through the first side 11.1 with a focal plane that is slightly shifted downwards, see below for details.

[0034] In the embodiment of Fig. 2 The interruption layer 13 is embedded in the buffer layer 15. A lower section 15.1 of the buffer layer is arranged below the interruption layer 13 and an upper section 15.2 is arranged above it, namely between the interruption layer 13 and the component layer 16. Again, the interruption layer 13 is spaced away from the interface between the SiC substrate 11 and the epitaxial SiC layer system 12.

[0035] On the one hand, in the case of an amorphous / porous interruption layer 13, the interruption of the crystal structure can physically stop the growth of the stacking fault 41, as schematically shown. Alternatively or additionally, the interruption layer 13 can be highly doped and provide shielding of the interface from eh recombination, for example in addition to shielding by the buffer layer 15.

[0036] In summary, the disruption layer 13 can decrease eh recombination (which triggers stacking fault growth) and / or stop growth once it is initiated due to the disrupted crystal structure.

[0037] To manufacture chip 1 of Fig. 2. The interruption layer 13 can be formed, for example, after the deposition of the lower section 15.1 of the buffer layer 15 and before the deposition of its upper section 15.2, for example by high-dose implantation in between. Alternatively, the buffer layer 15 can be deposited in one step, with the interruption layer 13 being formed afterwards, for example by laser irradiation.

[0038] Fig. Figure 3 shows a schematic cross-section of chip 1 and illustrates a semiconductor device 100, in the example shown a vertical transistor device 100. In general, throughout this disclosure, the same reference numerals denote the same elements or elements with the same function, and reference is always made to the descriptions of the other figures. Naturally, every dimension or ratio in this schematic drawing is not to scale.

[0039] The vertical transistor device 101 comprises a source region 110 on the first side 10.1 of the semiconductor body 10 and a drain region 113 on the vertically opposite second side 10.2. Between these are its body region 111 and drift region 112. The drift region 112 is made of the same doping type but with a lower doping concentration compared to the drain region 113. In the case of an nFET, the source region 110, the drift region 112, and the drain region 113 are n-doped, while the body region 111 is p-doped.

[0040] A gate region 120 is arranged laterally next to the body region 111 in a groove 121. It comprises a gate electrode 122 and a gate dielectric 123, which capacitively couples the gate electrode 122 to the body region 111. On the first side 10.1, an insulating layer 130 with a front-side metallization layer 135 is arranged on it. The front-side metallization layer 135 is the source contact; it is connected to the source region 110 and the body region 111 via a contact connector 136. The metallization layer 30 on the second side 10.2 is connected to the drain region 113 and serves as the drain contact.

[0041] The source region 110, the body region 111, and the drift region 112 are formed in the component layer 16. Below, the buffer layer 15 is arranged to provide some shielding of the interface from eh recombination, as shown above. In the example shown, the interruption layer 13 is embedded in the SiC substrate, as is typical for Fig. 1 explained, but the interruption layer could also be embedded in the buffer layer 15, as in Fig. 2 shown.

[0042] Fig. Figures 4a-c illustrate different options for producing the interruption layer 13. Fig. Figure 4a shows a laser irradiation 150, namely a laser beam 151, which is focused into a focal plane 125 below the first side 11.1 of the SiC substrate 11. In the focal plane 125, the crystal structure is locally destroyed, resulting in an amorphous and / or porous layer 13a.

[0043] Fig. 4b illustrates the formation of an interrupted layer through porosification 160, namely through an etching agent 161. Fig. Figure 4c illustrates a high-dose implantation 170. In this case, the interruption layer is to be embedded in the buffer layer 15, and the doping agent 171 for the high-dose implantation 170 is introduced after the deposition of the lower section 15.1 of the buffer layer 15 and before the deposition of the upper section 15.2 thereof.

[0044] Fig. Figure 5 shows a package 200 comprising a housing 201 in which the semiconductor chip 1 is mounted. Specifically, the chip 1 is placed on a heat sink 202, with the metallization layer located on the second side (not shown here), namely the drain metallization of the chip 1, being electrically connected to the heat sink 202. The drain contact can be connected via a corresponding pin 203. The chip 1 is embedded in a molding compound 204; further connection details are not shown here.

[0045] Fig. Section 6 summarizes some of the manufacturing steps. After providing the SiC substrate 210, several options are possible. Either the formation of the interruption layer 211 can take place before the epitaxial deposition 212 of the epitaxial SiC layer system. Alternatively, as illustrated in the lower path, the formation of the interruption layer 211 can be embedded between the deposition steps 212.1 and 212.2; see also Fig. 4c.

Claims

[1] Semiconductor chip (1) with a semiconductor component (100) in a semiconductor body (10), wherein the semiconductor body (10) comprises a silicon carbide substrate (11); an epitaxial silicon carbide layer system (12) on a first side (11.1) of the silicon carbide substrate (11); an interruption layer (13); wherein the interruption layer (13) is embedded either in the silicon carbide substrate (11) or in the epitaxial silicon carbide layer system (12), each at a vertical distance (20) from the first side (11.1) of the silicon carbide substrate (11). [2] Semiconductor chip (1) according to claim 1, wherein the vertical distance (20) between the first side (11.1) of the silicon carbide substrate (11) and the interruption layer (13) is at least 0.1 µm and not more than 1 µm. [3] Semiconductor chip (1) according to claim 1 or 2, wherein the interruption layer (13) has a vertical thickness (25) of at least 0.1 µm and not more than 5 µm. [4] Semiconductor chip (1) according to one of the preceding claims, wherein the interruption layer (13) is a highly doped layer (13b). [5] Semiconductor chip (1) according to one of the preceding claims, wherein the interruption layer (13) is an amorphous and / or porous layer (13a). [6] Semiconductor chip (1) according to one of the preceding claims, wherein the epitaxial silicon carbide layer system (12) comprises a component layer (16) and a buffer layer (15), wherein the buffer layer (15) is arranged between the component layer (16) and the silicon carbide substrate (11) and is doped with a higher doping concentration than the component layer (16). [7] Semiconductor chip (1) according to claim 6, wherein the interruption layer (13) is embedded in the buffer layer (15), wherein a lower portion (15.1) of the buffer layer (15) is arranged between the interruption layer (13) and the silicon carbide substrate (11) and an upper portion (15.2) of the buffer layer (15) is arranged between the device layer (16) and the interruption layer (13). [8] Semiconductor chip (1) according to claim 5, optionally also in combination with claim 6, wherein the amorphous and / or porous layer (13a) is embedded in the silicon carbide substrate (11). [9] Semiconductor chip (1) according to one of the preceding claims, comprising a metallization layer (30) arranged on a second side (11.2) of the silicon carbide substrate (11) vertically opposite the first side (11.1). [10] Semiconductor chip (1) according to claim 9, wherein the semiconductor component (100) is a vertical transistor component (101) having a source region (110) and a drain region (113) on opposite sides (10.1, 10.2) of the semiconductor body (10). [11] Semiconductor chip (1) according to one of the preceding claims, comprising an additional interruption layer which is vertically spaced from the interruption layer (13). [12] Package (200), comprising the semiconductor chip (1) according to one of the preceding claims, and a housing (201), wherein the semiconductor chip (1) is mounted in the housing (201) and electrically contacted. [13] Method for producing the semiconductor chip (1) according to one of claims 1 to 11 or the package (200) according to claim 12, comprising the steps i) providing the silicon carbide substrate (11); ii) epitaxial deposition of the epitaxial silicon carbide layer system (12) on the first side (11.1) of the silicon carbide substrate (11); iii) forming the interruption layer (13). [14] Method according to claim 13 for producing the semiconductor chip (1) according to claim 5, wherein the interruption layer (13) is formed by laser irradiation (150) and / or porosification (160) and / or high-dose implantation (170). [15] A method according to claim 14 for producing the semiconductor chip (1) according to claim 8, wherein step iii) is carried out before step ii). [16] Method according to claim 13 for producing the semiconductor chip (1) according to claims 4 and 7, wherein the highly doped layer (13b) is produced by a high-dose implantation (170) between a deposition of the lower portion (15.1) of the buffer layer (15) and a deposition of the upper portion (15.2) of the buffer layer (15).

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