STORAGE ELEMENTS WITH CONTACT STRUCTURES AND METHOD FOR MANUFACTURING THEM

Abstract

A memory device comprises several first memory cells formed in a first region of a substrate, several first via structures formed in a second region of the substrate, the second region being arranged adjacent to the first region along a first lateral direction, a first of several front-side interconnect structures formed on a first side of the substrate, the first front-side interconnect structure being coupled to gate terminals of access transistors of the several first memory cells, and a first of several back-side interconnect structures formed on a second side of the substrate vertically opposite the first side, the first back-side interconnect structure being coupled to the first front-side interconnect structure by one or more of the several first via structures.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims priority over the preliminary US patent application No. 63 / 642,080, filed on May 3, 2024, entitled “Back-Side Global Fly WL on SRAM Array”, which is incorporated by reference into the present application. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. As ICs continue to miniaturize, more and more components are integrated into individual chips. This miniaturization process generally provides advantages by increasing production efficiency and reducing associated costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 illustrates a block diagram of an example memory device in accordance with some embodiments. Fig. Figure 2 illustrates a schematic diagram of an example circuit used in the memory element of Fig. 1 may be exhibited, in accordance with some embodiments. Fig. 3A and Fig. Figure 3B illustrates an example layout associated with an example circuit in accordance with some embodiments. Fig. Figure 4 illustrates a schematic diagram of an example circuit used in the memory component of Fig. 1 may be exhibited, in accordance with some embodiments. Fig. 5A and Fig. Figure 5B illustrates an example layout associated with an example circuit in accordance with some embodiments. Fig. 6A and Fig. 6B illustrates schematic diagrams of example circuits used in the memory device of Fig. 1 may be exhibited, in accordance with some embodiments. Fig. Figure 7 illustrates a schematic diagram of an example circuit used in the memory component of Fig. 1 may be exhibited, in accordance with some embodiments. Fig. Figure 8 illustrates an example layout associated with an example circuit in accordance with some embodiments. Fig. Figure 9 illustrates a flowchart of an example procedure for forming a memory element. Fig. Figure 10 illustrates a flowchart of an example procedure for forming a memory component. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, such that the first and second structural elements might not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves the purpose of simplification and clarity and does not itself imply any relationship between the different embodiments and / or configurations explained.

[0005] Furthermore, spatially relative terms such as "underlying", "below", "under", "overlying", "above", "above", "below", and the like may be used herein to facilitate description and to describe the relationship of one element or structural element to another element(s) or structural element(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the component in use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0006] In general, word line (WL) latency is one of the factors that significantly impacts the overall speed of a memory device (e.g., static random-access memory (SRAM)). SRAM devices retain data while power is supplied, providing faster access speeds and better reliability for high-performance applications. However, as semiconductor technology shrinks, the poly-pitch (the distance between polysilicon traces) decreases, resulting in narrower WLs with increased resistance and capacitance, which in turn worsens WL latency and slows down memory access speeds.Furthermore, in a memory device where backside metal leads are used, the backside metal leads cannot be directly connected to the frontside device gate, necessitating indirect connections that result in higher resistance and capacitance, while increasing design complexity. The present disclosure can address these problems by utilizing via-hole structures to implement a backside WL scheme, effectively improving WL delay.

[0007] The present disclosure provides various embodiments of a memory device (or IC). The memory device can comprise a memory array formed in a first region of a substrate, a first interconnect structure formed on a first side of the substrate, a second interconnect structure formed on a second side of the substrate, and a via structure formed in a second region of the substrate such that the via structure can couple the first interconnect structure to the second interconnect structure. This can achieve the backside waveguide scheme while improving waveguide delay problems without significantly impacting the device area.

[0008] Fig. Figure 1 illustrates a block diagram of an example memory device in accordance with some embodiments. The memory device 100 comprises a memory control unit 105 and a memory array 120. In one aspect, the memory array 120 comprises multiple memory circuits or memory cells 125. The memory array 120 has word lines WL0, WL1...WL1 J , each extending in a first direction (e.g., X-direction), and bit lines BL0, BL1...BL KThe word lines (WLs) and bit lines (BLs) extend in a second direction (e.g., the Y-direction). The word lines (WLs) and bit lines (BLs) can each be a conductive metal or a conductive rail. In some embodiments, each memory cell 125 is coupled to a corresponding word line (WL) and a corresponding bit line (BL) and can be operated according to voltages or currents through the corresponding word line (WL) and the corresponding bit line (BL). In some embodiments, each bit line (BL) and BLB is coupled to one or more memory cells 125 or a group of memory cells 125 arranged along the second direction (e.g., the Y-direction). The bit lines (BL) and BLB can receive and / or provide differential signals.

[0009] Each memory cell 125 can be a volatile memory cell, a non-volatile memory cell, or a combination thereof. For example, each memory cell 125 is configured as a static random access memory cell (SRAM cell). However, it should be noted that the memory cell 125 can be implemented as any of several other non-volatile memory cells, such as a resistive random access memory cell (RRAM cell, Resistive Random Access Memory), a magnetoresistive random access memory cell (MRAM cell, Magnetoresistive Random Access Memory), a phase-change random access memory cell (PCRAM cell, Phase-Change Random Access Memory), an eFuse, an antifuse, etc., while remaining within the scope of this disclosure. In some embodiments, the memory array 120 has additional lines (e.g., select lines, reference lines, reference control lines, power rails, etc.).

[0010] The memory control unit 105 is a hardware component that controls operations of the memory array 120. In some embodiments, the memory control unit 105 includes a bit line control unit (BL control unit) 112, a word line control unit (WL control unit) 114, and a voltage supply circuit 110. The BL control unit 112, the WL control unit 114, and the voltage supply circuit 110 can be configured as logic circuits, analog circuits, or a combination thereof. In one configuration, the WL control unit 114 is a circuit that supplies a voltage or current through one or more word lines (WLs) of the memory array 120, and the BL control unit 112 is a circuit that supplies or detects a voltage or current through one or more bit lines (BLs) of the memory array 120.In one configuration, the voltage supply circuit 110 is a circuit that provides a voltage signal to the BL control unit 112 and / or the WL control unit 114. The BL control unit 112 can be coupled to bit lines BLs of the memory array 120, and the WL control unit 114 can be coupled to word lines WLs of the memory array 120. In some embodiments, the memory control unit 105 has more, fewer, or different components than in the above. Fig. 1 shown on.

[0011] In various embodiments, the memory array 120 can have multiple memory cells 125 formed in a first region of a substrate. The memory array 120 can have a first interconnect structure formed on a first side of the substrate, which operatively serves as a first section of a word line for the multiple memory cells 125. The memory array 120 can have a second interconnect structure formed on a second side of the substrate, opposite the first side, which operatively serves as a second section of the word line for the multiple memory cells 125. The memory array 120 can have one or more via structures formed in a second region of the substrate adjacent to the first region along a lateral direction, and configured to couple the first interconnect structure to the second interconnect structure.The first interconnect structure and the second interconnect structure can each extend along the lateral direction to cross both the first and second areas.

[0012] In some embodiments, the memory device 100 can have several first memory cells 125 formed in a first region of a substrate. The memory device 100 can have several first via structures formed in a second region of the substrate, the second region being arranged adjacent to the first region along a first lateral direction. The memory device 100 can have a first of several front-side interconnect structures formed on a first side of the substrate. The first front-side interconnect structure can be coupled to gate terminals of access transistors of the several first memory cells 125. The memory device 100 can have a first of several back-side interconnect structures formed on a second side of the substrate, perpendicular to the first side.The first backside interconnect structure can be coupled to the first frontside interconnect structure by one or more of the multiple first via structures.

[0013] Fig. Figure 2 illustrates a schematic diagram of an example circuit 200, which is used in the memory element of Fig. 1 may be shown, in accordance with some embodiments. The circuit 200 may include multiple memory cells (e.g., memory cells 225, 226), a first word line 210, a second word line 220, first interconnect structures 230, 231, 232, 233, 234, 235, second interconnect structures 240, 241, one or more via structures 250, and one or more via structures 251. It is welcome that the schematic diagram of Fig. 2 is simplified for illustrative purposes and therefore circuit 200 can be implemented as any of several other configurations while remaining within the scope of the present disclosure.

[0014] The multiple memory cells can be of memory array 120. In some embodiments, the multiple memory cells can be arranged along a row and across multiple columns (e.g., M columns) of a memory array. In some embodiments, the multiple memory cells can be formed in a first region of a substrate. The multiple memory cells (e.g., memory cells 225, 226) can have or be coupled to access transistors (e.g., access transistors 225T, 226T). The access transistors 225T, 226T can connect memory cells 225, 226 to the corresponding bit lines BL / BLB. In some embodiments, memory cell(s) 225 can have multiple first memory cells, and memory cell(s) 226 can have multiple second memory cells. In some embodiments, each of the multiple memory cells (e.g., memory cell(s) 225, memory cell(s) 226, etc.) can have multiple second memory cells.) have a static random access memory cell (SRAM cell, Static Random Access Memory cell).

[0015] The first word line 210 and the second word line 220 can be from the memory array 120. In some embodiments, the first word line 210 can be a front-side word line. In some embodiments, the second word line 220 can be a rear-side word line. The first word line 210 and the second word line 220 can be connected in various ways. In some embodiments, the first word line 210 and the second word line 220 can be connected by the first interconnect structure 230, the second interconnect structure 240, and one or more via structures 250. In some embodiments, the one or more via structures 250 can form a through-hole via structure. In some embodiments, the first interconnect structure 230 can be formed on a first side (e.g., the front) of the substrate.For example, the first interconnect structure 230 can be a front-facing interconnect structure. In some embodiments, the first interconnect structure 230 can be configured to operatively serve as a section of the first word line 210 for the memory cell(s) 225. In some embodiments, the second interconnect structure 240 can be formed on a second side of the substrate opposite the first (e.g., the back). For example, the second interconnect structure 240 can be a back-facing interconnect structure. In some embodiments, the second interconnect structure 240 can be configured to operatively serve as a section of the word line 220 for the memory cell(s) 225.

[0016] In some embodiments, the circuit 200 can have several front-side interconnect structures (e.g., the first interconnect structure 230, interconnect structures 231, 232, 233, 234, etc.). The interconnect structures 231, 232, 233, 234 can be formed on the front side of the substrate. In some embodiments, the interconnect structures 231, 232 can be coupled to gate terminals of the memory cell(s) 225. For example, the interconnect structures 231, 232 can be coupled to gate terminals of the access transistors 225T of the memory cell(s) 225. In some embodiments, the interconnect structures 231, 232 can be configured to operatively serve as a section of the first word line 210 for the memory cell(s) 225, while being coupled to the memory cell(s) 225 through the gate terminals of the access transistors 225T. In some embodiments, the circuit 200 can include several rear-side interconnect structures (e.g.,B. the second interconnect structure 240, interconnect structure 241, etc.). As shown, the interconnect structures 240, 241 can be formed on the back side of the substrate, vertically opposite to the front side. In some embodiments, the interconnect structures 233, 234 can be coupled to gate terminals of the memory cell(s) 226. For example, the interconnect structures 233, 234 can be coupled to gate terminals of the access transistors 226T of the memory cell(s) 226. In some embodiments, the interconnect structures 233, 234 can be configured to operatively serve as a section of the first word line 210 for the memory cell(s) 226 while being coupled to the memory cell(s) 226 through the gate terminals of the access transistors 226T.

[0017] The one or more via structures 250 can be formed in a second region of the substrate. For example, the second region can be adjacent to the first region (e.g., where the multiple memory cells can be formed). In some embodiments, the one or more via structures 250 can be configured, as shown, to couple the first interconnect structure 230 (e.g., the front interconnect structure) with the second interconnect structure 240 (e.g., the rear interconnect structure).

[0018] In some embodiments, the first word line 210 and the second word line 220 can be connected by the first interconnect structure 235, the second interconnect structure 241, and one or more via structures 251. In some embodiments, the first interconnect structure 235 can be formed on the first side (e.g., the front) of the substrate. For example, the first interconnect structure 235 can be a front-facing interconnect structure. In some embodiments, the first interconnect structure 235 can be configured to serve operationally as a section of the first word line 210 for the memory cell(s) 226. In some embodiments, the second interconnect structure 241 can be formed on the second side (e.g., the back) of the substrate, opposite the first side. For example, the second interconnect structure 241 can be a back-facing interconnect structure.In some embodiments, the second interconnect structure 241 can be configured to serve operationally as a section of the word line 220 for the memory cell(s) 226.

[0019] In some embodiments, the circuit 200 can have several front-side interconnect structures (e.g., the first interconnect structure 235, the interconnect structures 233, 234, etc.) linked to a second memory cell (e.g., the memory cell(s) 226). The interconnect structures 233, 234 can be formed on the front side of the substrate. In some embodiments, the interconnect structures 233, 234 can be coupled to gate terminals of the memory cell(s) 226. For example, the interconnect structures 233, 234 can be coupled to gate terminals of the access transistors 226T of the memory cell(s) 226. In some embodiments, the interconnect structures 233, 234 can be configured to serve operationally as a section of the first word line 210 for the memory cell(s) 226, while being coupled to the memory cell(s) 226 through the gate terminals of the access transistors 226T.In some embodiments, the circuit 200 can have several rear-side interconnect structures (e.g., the second interconnect structure 240, interconnect structure 241, etc.). As shown, the interconnect structures 240, 241 can be formed on the rear side of the substrate, oriented vertically opposite to the front side.

[0020] The one or more via structures 251 can be formed in the second region of the substrate. For example, the second region can be adjacent to the first region (e.g., where the multiple memory cells can be formed). In some embodiments, the one or more via structures 251 can be configured, as shown, to couple the first interconnect structure 235 (e.g., the front interconnect structure) with the second interconnect structure 241 (e.g., the rear interconnect structure). In some embodiments, the one or more via structures 251 can be formed in an opposite section (e.g., opposite to the one or more via structures 250 with respect to the memory cells 225, 226, etc.) of the second region of the substrate.

[0021] Fig. 3A and Fig. Figure 3B illustrates an example layout 300 associated with an example circuit, in accordance with some embodiments. More details are provided in Fig. 3A a cross-sectional view of layout 300, in particular of section Y in Fig. 3B shown. Fig. Figure 3B shows a top view of layout 300. In some embodiments, layout 300 can be linked to circuit 200. The in Fig. 3A and Fig. Layout 300 shown in Figure 3B is a non-limiting example and has been simplified for illustrative purposes. It is welcome that Layout 300 can be implemented as any number of different configurations while remaining within the scope of this disclosure.

[0022] In relation to Fig. In some embodiments, the circuit 3A can have an active region (e.g., a number of transistors, gate structures, source / drain structures, etc.) and at least one section of a via 350 on a front face of a substrate. Across the front face, the circuit can have a number of source / drain interconnect structures (sometimes referred to as MDs 301), some of which are coupled to gate vias (sometimes referred to as VDs 302) formed on them and to the via 350. Across the gate structures of the transistors in the active region, the circuit can have a number of gate vias (sometimes referred to as VGs) (not shown).

[0023] The VD 302 can couple the MD 301 to a first metal conductor in the first (e.g., bottom) front-facing metallization layer (sometimes referred to as a Mo track 303). Above the first metal conductor (e.g., the M0 track 303) (and various other metal conductors in the bottom front-facing metallization layer), the circuit can have a number of via structures (sometimes referred to as Vos 304) to couple the first metal conductor (e.g., the M0 track 303) to corresponding one or more metal conductors (sometimes referred to as M1 tracks 330) in the next front-facing metallization layer furthest from the substrate.Furthermore, the circuit can have a number of vias (not shown) across the M1 tracks 330 (and various other metal conductors in the same front-facing metallization layer) to couple the M1 tracks 302 to corresponding one or more metal conductors in the next front-facing metallization layer located further away from the substrate. Although two front-facing metallization layers are shown, it is understood that the circuit can have any number of front-facing metallization layers. The metal tracks formed across such front-facing metallization layers can be configured to electrically couple different components of the circuit (to conduct signals and / or supply power) according to various embodiments.

[0024] In relation to Fig. 3A can have a number of backside vias (sometimes referred to as BVs) on the back side of the substrate, which can couple the source / drain and gate structures of the transistors in the active region to a number of metal traces in the first (e.g., uppermost) backside metallization layer (sometimes referred to as BM0 traces 306). In some embodiments, the circuit can have at least one section of the via 350 on the back side of the substrate. In some embodiments, the circuit can have a number of vias (sometimes referred to as BVos 305) above the BM0 traces 306, which can couple the BM0 traces 306 to a number of metal traces in the next backside metallization layer, which are located further away from the substrate (e.g., BM1 traces 340).Furthermore, the circuit can have a number of vias (sometimes referred to as BV1s) (not shown) across the BM1 tracks 340, which can couple the BM1 tracks 340 to a number of metal leads in the next backside metallization layer that are further away from the substrate (sometimes referred to as BM2 tracks) (not shown).

[0025] In Fig. Figure 3B shows layout 300 in a top view. In a first region of the substrate, the circuit associated with layout 300 (e.g., circuit 200) can have several memory cells (e.g., the first memory cells 325, the second memory cells 326, etc.). The circuit can have several via structures in a second region (e.g., including section Y) of the substrate. The second region can be adjacent to the first region along a lateral direction (e.g., the x-axis, as shown in Figure 3B). Fig. 3B shown).

[0026] In some embodiments, the circuit can have the multiple memory cells arranged along a row and across multiple columns of a memory array formed in the first region. In some embodiments, the second memory cells 326 can be aligned with the first memory cells 325 along the x-axis. In some embodiments, the second memory cells 326, although not shown, can also be aligned with the first memory cells 325 along the y-axis.

[0027] In some embodiments, the circuit may have via-hole and interconnect structures (e.g., the BM0 306, M0 303, etc.) formed in various sections of the second area. For example, the circuit may be structured as shown in Fig. Figure 3B shows a first set of vias (e.g., vias 304A, 305A, etc.) and a first set of interconnects (e.g., BM0 306A, M0 303A, etc.) in a first section of the second area; and a second set of vias (e.g., vias 304B, 305B, etc.) and a second set of interconnects (e.g., BM0 306B, M0 303B, etc.) in a second section of the second area. In some embodiments, the set of vias and the set of interconnects may be arranged as shown in Fig. 3B shown may be arranged along the x-axis and / or the y-axis. In some embodiments, the set of via structures (e.g., via structures 304B, 305B, 304C, 304C, etc.) may be arranged as shown in Fig. Figure 3B shows another set (e.g., the via structures 304A, 305A, etc.) of via structures being offset in both the x-axis and the y-axis. In some embodiments, the set of interconnect structures (e.g., the BM0 306A, M0 303A, etc.) can be as shown in Fig. Figure 3B shows another set (e.g., the BM0 306B, the M0 303B, BM0 306C, the M0 303C, etc.) of interconnect structures offset along both the x-axis and the y-axis. In some embodiments, the circuit may have multiple M1 tracks (e.g., the M1 track 330A, M1 track 330B, etc.) arranged along the y-axis. As shown in Fig. As shown in Figure 3B, the M1 track 330B can be offset from the M1 track 330A in both the x-axis and the y-axis. In some embodiments, the circuit can have multiple BM1 tracks (e.g., BM1 track 340A, BM1 track 340B, etc.) arranged along the y-axis. As shown in Fig. As shown in Figure 3B, the BM1 track 340B can be offset from the BM1 track 340A in both the x-axis and the y-axis.

[0028] In some embodiments, the M1 track 330 can extend along the x-axis (e.g., as the M1 tracks 330A, 330B in Fig. 3B). In some embodiments, the M1 track 330 can cross the first memory cell(s) 325, the second memory cell(s) 326, etc. In some embodiments, the M0 track 303 can extend along the y-axis (e.g., as the M0 tracks 303A, 303B in Fig. (shown in Figure 3B). In some embodiments, the M0 track 303 can cross the M1 track 330, the BM1 track 340, etc. In some embodiments, the MD 301 can extend along the x-axis (e.g., as MD 301A, MD 301B in Figure 3B). Fig. 3B) extend. In some embodiments, the MD 301 can cross the M0 track 303, the BM0 track 306, etc. In some embodiments, the BM0 track 306 can extend along the y-axis (e.g., as the BM0 tracks 306A, 306B in Fig. 3B). In some embodiments, the BM0 track 306 can cross the M1 track 330, the BM1 track 340, etc. In some embodiments, the BM1 track 340 can run along the x-axis (e.g., as the BM1 tracks 340A, 340B in Fig. (3B shown). In some embodiments, the BM1 track 340 can cross the first memory cell(s) 325, the second memory cell(s) 326, etc.

[0029] In some embodiments, the via structures (e.g. the V0 304, VD 302, the via structure 350, BV0 305 etc.) can extend along the z-axis to connect at least one of the M1 330, M0 303, MD 301, BM0 306 and BM1 340 together.

[0030] In some embodiments, one or more of the via structures can extend through the substrate (e.g., through the z-axis). For example, via structure 350 can extend through the substrate to connect a first interconnect structure on the front side to a second interconnect structure on the back side. In some embodiments, one or more of the via structures can be configured to couple the first interconnect structure to the second interconnect structure. For example, the via structures (e.g., via structure 350, VD 302, V0 304, BV0 305, etc.) can be configured as shown in Fig. Figure 3A shows the first interconnect structure (which may be the M1 track 330 or part thereof) and the second interconnect structure (which may be the BM1 track 340 or part thereof). In some embodiments, the via structure may extend through the substrate to connect the first side (e.g., the front) to the second side (e.g., the back) of the substrate.

[0031] In relation to Fig. In some embodiments, the circuit associated with layout 300 (e.g., circuit 200) may have a first interconnect structure formed on a first side (e.g., the front) of the substrate. In some embodiments, the first interconnect structure may be a front-facing interconnect structure or part thereof. For example, the first interconnect structure may be the M1 tracks 330 or part thereof. In some embodiments, the first interconnect structure may be configured to operate as a first section of a word line (e.g., a front-facing word line) for the multiple memory cells (e.g., the first memory cells 325, the second memory cells 326, etc.). In some embodiments, the circuit may have a second interconnect structure formed on a second side opposite the first (e.g., the back) of the substrate.In some embodiments, the second interconnect structure can be a rear-facing interconnect structure or part thereof. For example, the second interconnect structure can be the BM1 tracks 340 or part thereof. In some embodiments, the second interconnect structure can be configured to operate as a second section of a word line (e.g., a rear-facing word line) for the multiple memory cells (e.g., the first memory cells 325, the second memory cells 326, etc.).

[0032] In some embodiments, the circuit associated with layout 300 (e.g., circuit 200) may have several first interconnect structures formed on the first side (e.g., the front) of the substrate. For example, the circuit may have a first interconnect structure that can be the M0 track 303 or a portion thereof. In some embodiments, the circuit may have several back-side interconnect structures formed on the second side of the substrate, perpendicular to the first side (e.g., the back). For example, the circuit may have a second interconnect structure that can be the BM0 track 306 or a portion thereof. In some embodiments, at least one first interconnect structure (e.g., the front-side interconnect structure) may be coupled to gate terminals of access transistors of the plurality of memory cells (e.g., the first memory cells 325, the second memory cells 326, etc.).In some embodiments, at least one second interconnect structure (e.g. the rear interconnect structure) can be coupled to at least one first interconnect structure by one or more of the multiple via structures (e.g. the via structure 350).

[0033] In some embodiments, the circuit associated with layout 300 (e.g., circuit 200) can be configured with respect to Fig. 3B has the first interconnect structure (which may be the M1 track 330 or part of it) and the second interconnect structure (which may be the BM1 track 340 or part of it), each extending along the lateral direction (e.g. the x-axis) to cross both the first and second areas.

[0034] In some embodiments, the circuit associated with layout 300 (e.g., circuit 200) can be configured with respect to Fig. 3A may have multiple first interconnect structures (e.g., front-facing interconnect structures). For example, the circuit may have a second of the first interconnect structures (e.g., a second front-facing interconnect structure) arranged vertically between the substrate and a first of the first front-facing interconnect structures. For example, the first of the first interconnect structures may be the M1 tracks 330 or a portion thereof, and the second of the first interconnect structures may be the MD301 or a portion thereof, such that the second of the first interconnect structures may be arranged vertically between the substrate and the first of the first interconnect structures. In some embodiments, the circuit associated with layout 300 (e.g., circuit 200) may have multiple second interconnect structures (e.g., back-facing interconnect structures).For example, the circuit may have a second of the second interconnect structures arranged vertically between the substrate and a first of the second interconnect structures. For example, the first of the second interconnect structures may be BM1 track 340 or a portion thereof, and the second of the second interconnect structures may be BM0 track 306 or a portion thereof, such that the second of the second interconnect structures may be arranged vertically between the substrate and the first of the second interconnect structures. In some embodiments, the via structure 350 may be as shown in . Fig. 3A is shown in direct contact with the second of the first interconnect structures (e.g. the MD 301) and the second of the second interconnect structures (e.g. the BM0 306).

[0035] Fig. Figure 4 illustrates a schematic diagram of an example circuit 300, which is used in the memory element of Fig. 1 may be shown, in accordance with some embodiments. The circuit 400 may include several memory cells (e.g., memory cells 425, 426), a first word line 410, a second word line 420, first interconnect structures 431, 432, 433, 434, transistors 450, 451, one or more via structures 460, and one or more via structures 461. It is welcome that the schematic diagram of Fig. 4 is simplified for illustrative purposes, and therefore circuit 400 can be implemented as any of several other configurations while remaining within the scope of the present disclosure.

[0036] In some embodiments, the circuit 400 may be substantially similar to the circuit 200 or may adopt structural elements from it. Alternatively, in some embodiments, the circuit 400 may comprise the transistors 450, 451 and the via structures 460, 461, in contrast to the circuit 200, which comprises the via structures 250, 251 and the interconnect structures 230, 240, 235, 241.

[0037] In some embodiments, at least one of the transistors 450, 451 can be formed in the second region of the substrate. For example, the transistors 450, 451 can be formed in the second region adjacent to the first region where the memory cells 425, 426 are formed. In some embodiments, a gate terminal and a first source / drain terminal of the transistors 450, 451 can be configured as shown in Fig. 4 shown with the first interconnect structure (which may be a section of the word line 410), and a second source / drain connection of the transistors 450, 451 may be coupled to the second interconnect structure (which may be a section of the word line 420) by the one or more via structures 460, 461.

[0038] Fig. 5A and Fig. Figure 5B illustrates an example layout 500 associated with an example circuit, in accordance with some embodiments. More details are provided in Fig. 5A a cross-sectional view of layout 500, in particular of section Y in Fig. 5B shown. In Fig. Figure 5B shows a top view of layout 500. In some embodiments, layout 500 may be linked to circuit 400. The in Fig. 5A and Fig. Layout 500 shown in Figure 5B is a non-limiting example and has been simplified for illustrative purposes. It is welcome that Layout 500 can be implemented as any number of different configurations while remaining within the scope of this disclosure.

[0039] In relation to Fig. 5a In some embodiments, the circuit may have, on a front face of the substrate, an active region (e.g., a number of transistors, gate structures, source / drain structures, etc.) in a first region and at least one section of a derivative element 550 (e.g., a dummy element to form a transistor within it) in a second region adjacent to the first region. Across the front face, the circuit may have a number of source / drain interconnect structures (sometimes referred to as MDs 500R), some of which are coupled to gate via structures (sometimes referred to as VDs 502) formed on them and to the derivative element 550. Across the gate structures of the transistors in the active region of the first region, the circuit may have a number of gate via structures (sometimes referred to as VGs) (not shown).

[0040] The VD 502 can couple the MD 501 to a first metal conductor in the first (e.g., bottom) front-side metallization layer (sometimes referred to as an M0 track 503). Above the first metal conductor (e.g., the M0 track 503) (and various other metal conductors in the bottom front-side metallization layer), the circuit can have a number of via structures (sometimes referred to as Vos 504) to couple the first metal conductor (e.g., the M0 track 503) to one or more corresponding metal conductors in the next front-side metallization layer, which is farther from the substrate (sometimes referred to as M1 tracks 530).Furthermore, the circuit can have a number of vias (not shown) across the M1 tracks 530 (and various other metal conductors in the same front-face metallization layer) to couple the M1 tracks 502 to one or more corresponding metal conductors in the next front-face metallization layer located further away from the substrate. Although two front-face metallization layers are shown, it is understood that the circuit can have any number of front-face metallization layers. The metal tracks formed across such front-face metallization layers can be configured to electrically couple different components of the circuit according to various embodiments (to conduct signals and / or supply power).

[0041] In relation to Fig. In 5A, the circuit can have a number of backside vias (sometimes referred to as BVs) on the back side of the substrate, which can couple the source / drain and gate structures of the transistors in the active region of the first area to a number of metal traces in the first (e.g., uppermost) backside metallization layer (sometimes referred to as BM0 tracks 506). In some embodiments, the circuit can have the via 560 on the back side of the substrate, in the second area adjacent to the first area. In some embodiments, the circuit can have a number of vias (sometimes referred to as BVos 505) above the BM0 tracks 506, which can couple the BM0 tracks 506 to a number of metal traces in the next backside metallization layer, which is further away from the substrate (e.g., BM1 tracks 540).Furthermore, the circuit can have a number of via-hole structures (sometimes referred to as BV1s) (not shown) via the BM1 tracks 540, which can couple the BM1 tracks 540 to a number of metal leads in the next backside metallization layer, which is further away from the substrate (sometimes referred to as BM2 tracks) (not shown).

[0042] As shown, the lead element 550 and the via structure 560 can be connected, while they connect the M1 track 540 and the BM1 track 540. In some embodiments, a gate terminal and a first source / drain terminal of the transistor (e.g., the transistors 450) in the lead element 550 can be coupled to the M1 track 540, and a second source / drain terminal of the transistor in the lead element 550 can be coupled to the BM1 track 540 through one or more via structures (e.g., the via structure 560, the BV0, etc.).

[0043] In Fig. Figure 5B shows layout 500 in a top view. In a first region of the substrate, the circuit associated with layout 500 (e.g., circuit 400) can have several memory cells (e.g., the first memory cells 535, second memory cells 526, etc.). The circuit can have several via structures in a second region (e.g., section Y) of the substrate. The second region can be adjacent to the first region along a lateral direction (e.g., the one shown in the diagram). Fig. 5B (shown x-axis) should be.

[0044] In some embodiments, the circuit can have multiple memory cells arranged along a row and across multiple columns of a memory array formed in the first region. In some embodiments, the second memory cells 526 can be aligned with the first memory cells 525 along the x-axis. In some embodiments, although not shown, the second memory cells 526 can be aligned with the first memory cells 525 along the y-axis.

[0045] In some embodiments, the circuit may include transistors, vias, and interconnect structures (e.g., the BM0 506, M0 503, etc.) formed in different sections of the second area. For example, as in Fig. As shown in Figure 5B, the circuit can have a first set of vias (e.g., vias 504A, 505A, 560A, etc.), a derivation element 550A, and a first set of interconnects (e.g., BM0 506A, M0 503A, etc.) in a first section of the second area; and a second set of vias (e.g., vias 504B, 505B, etc.), a derivation element 550B, and a second set of interconnects (e.g., BM0 506B, M0 503B, etc.) in a second section of the second area. In some embodiments, as shown in Fig. As shown in Figure 5B, the set of vias, transistors, and interconnects can be arranged along the x-axis and / or the y-axis. In some embodiments, as in Fig. As shown in Figure 5B, one set of vias (e.g., vias 504B, 505B, 560B, 504C, 505C, 560C, etc.) can be offset from another set (e.g., vias 504A, 505A, 560B, etc.) of vias in both the x-axis and the y-axis. In some embodiments, as shown in Fig. As shown in Figure 5B, one set of interconnect structures (e.g., BM0 506B, M0 503B, BM0 506C, M0 503C, etc.) can be offset from another set (e.g., BM0 506A, M0 503A, etc.) of interconnect structures along both the x-axis and the y-axis. In some embodiments, the circuit can have multiple M1 tracks (e.g., M1 track 530A, M1 track 530B, etc.) arranged along the y-axis. As shown in Fig. As shown in Figure 5B, the M1 track 530B can be offset from the M1 track 530A in both the x-axis and the y-axis. In some embodiments, the circuit can have multiple BM1 tracks (e.g., the BM1 track 540A, BM1 track 540B, etc.) arranged along the y-axis. As shown in Figure 5B, the M1 track 530B can be offset from the M1 track 530A in both the x-axis and the y-axis. Fig. As shown in Figure 5B, the BM1 track 540B can be offset from the BM1 track 540A in both the x-axis and the y-axis.

[0046] In some embodiments, the M1 track 530 can extend along the x-axis (e.g., as the M1 tracks 530A, 530B in Fig. 5B). In some embodiments, the M1 track 530 can cross the first memory cells 525, the second memory cell 526, etc. In some embodiments, the Mo track 503 can extend along the y-axis (e.g., as the M0 tracks 503A, 503B in Fig. 5B). In some embodiments, the Mo track 503 can cross the M1 track 530, the BM1 track 540, etc. In some embodiments, the MD 501 can extend along the x-axis (e.g., as MD 501A, MD 501B in Fig. 5B). In some embodiments, the MD 501 can cross the M0 track 503, the BM0 track 506, etc. In some embodiments, the BM0 track 506 can extend along the y-axis (e.g., as the BM0 tracks 506A, 506B in Fig. 5B shown). In some embodiments, the BM0 track 506 can cross the M1 track 530, the BM1 track 540, etc. In some embodiments, the BM1 track 540 can extend along the x-axis (e.g., as the BM1 tracks 540A, 540B in Fig. 5B shown). In some embodiments, the BM1 track 540 can cross the first memory cells 525, the second memory cell 526, etc.

[0047] In some embodiments, the via structures (e.g., the V0 504, the VD 502, the BV0 505, etc.) can extend along the z-axis to connect at least one of the M1 530, M0 503, MD 501, BM0 506, and BM1 540 to another. In some embodiments, the derivation element 550 can extend along the y-axis (e.g., as derivation elements 550A, 550B in Fig. 5B shown). In some embodiments, the derivative element 550 can cross the M1 track 530, BM1 track 540, etc.

[0048] In some embodiments, one or more of the via structures and / or transistors can extend through the substrate (e.g., through the z-axis). For example, the lead element 550 and the via structure 550 can extend through the substrate to connect a first interconnect structure on the front side to a second interconnect structure on the back side. In some embodiments, one or more of the via structures can be configured to couple the first interconnect structure to the second interconnect structure. For example, as in Fig. As shown in Figure 5A, the transistor formed in the lead element 550 and the via structure 560 can couple the first interconnect structure (which can be the M1 track 530 or part thereof) and the second interconnect structure (which can be the BM1 track 540 or part thereof). In some embodiments, the lead element 550 and the via structure 560 can each extend through the substrate, so that the transistor in the lead element 550 and the via structure 560 can connect the first side (e.g., the front) to the second side (e.g., the back) of the substrate. As shown in Fig. As shown in Figure 5A, the transistor in the derivative element 550 and the via structure 560 can connect the first side (e.g. the front) with the second side (e.g. the back) of the substrate.

[0049] In relation to Fig. In some embodiments, the circuit associated with layout 500 (e.g., circuit 400) may have a first interconnect structure formed on a first side (e.g., the front) of the substrate. In some embodiments, the first interconnect structure may be a front-facing interconnect structure or part thereof. For example, the first interconnect structure may be the M1 tracks 530 or part thereof. In some embodiments, the first interconnect structure may be configured to operate as a first section of a word line (e.g., a front-facing word line) for the multiple memory cells (e.g., the first memory cells 525, second memory cells 526, etc.). In some embodiments, the circuit may have a second interconnect structure formed on a second side of the substrate, perpendicular to the first side (e.g., the back).In some embodiments, the second interconnect structure can be a rear-side interconnect structure or part thereof. For example, the second interconnect structure can be the BM1 tracks 540 or part thereof. In some embodiments, the second interconnect structure can be configured to operate as a second section of a word line (e.g., a rear-side word line) for the multiple memory cells (e.g., the first memory cells 525, second memory cells 526, etc.).

[0050] In some embodiments, the circuit associated with layout 500 (e.g., circuit 400) may have several first interconnect structures formed on the first side (e.g., the front) of the substrate. For example, the circuit may have a first interconnect structure that can be the Mo track 503 or a portion thereof. In some embodiments, the circuit may have several back-side interconnect structures formed on the second side of the substrate, perpendicular to the first side (e.g., the back). For example, the circuit may have a second interconnect structure that can be the BM0 track 506 or a portion thereof. In some embodiments, at least one first interconnect structure (e.g., the front-side interconnect structure) may be coupled to gate terminals of access transistors of the multiple memory cells (e.g., the first memory cells 525, second memory cells 526, etc.).In some embodiments, at least one second interconnect structure (e.g. the rear interconnect structure) can be coupled to at least one first interconnect structure by one or more of the multiple via structures and transistors (e.g. the transistor in the derivation element 550 and the via structure 560).

[0051] In some embodiments, with regard to Fig. 5B the circuit linked to layout 500 (e.g. circuit 400) shall have the first interconnect structure (which may be the M1 track 530 or part thereof) and the second interconnect structure (which may be the BM1 track 540 or part thereof), each extending along the lateral direction (e.g. the x-axis) to cross both the first and second areas.

[0052] In some embodiments, with respect to FIGU R5A, the circuit associated with layout 500 (e.g., circuit 400) can have multiple first interconnect structures (e.g., front-facing interconnect structures). For example, the circuit can have a second of the first interconnect structures (e.g., a second front-facing interconnect structure) arranged vertically between the substrate and a first of the first front-facing interconnect structures. For example, the first of the first interconnect structures can be the M1 tracks 530 or a portion thereof, and the second of the first interconnect structures can be the MD 501 or a portion thereof, such that the second of the first interconnect structures can be arranged vertically between the substrate and the first of the first interconnect structures. In some embodiments, the circuit associated with layout 500 (e.g., circuit 400) can have multiple second interconnect structures (e.g.,(rear-side interconnect structures). For example, the circuit may have a second of the second interconnect structures arranged vertically between the substrate and a first of the second interconnect structures. For example, the first of the second interconnect structures may be the BM1 tracks 540 or a portion thereof, and the second of the second interconnect structures may be the BMo track 506 or a portion thereof, such that the second of the second interconnect structures may be arranged vertically between the substrate and the first of the second interconnect structures. In some embodiments, as in . Fig. Figure 5A shows the derivation element 550 and / or the via structure 560 in direct contact with the second of the first interconnect structures (e.g. the MD 401) and the second of the second interconnect structures (e.g. the BM0 506).

[0053] Fig. Figure 6A illustrates a schematic diagram of an example circuit 600, which is used in the memory element of Fig. 1 may be shown, in accordance with some embodiments. The circuit 600 may have several memory cells (e.g., memory cells 625, 626, 627, 628), a first word line 610, a second word line 620, etc. It is welcome that the schematic diagram of Fig. 6A is simplified for illustrative purposes and therefore the circuit 600 can be implemented as any of several other configurations while remaining within the scope of the present disclosure.

[0054] In some embodiments, the circuit 600 may be substantially similar to or incorporate structural elements of the circuit 200. Alternatively, in some embodiments, the circuit 600 may have the word line 620 connected to a section of columns linked to the multiple memory cells (e.g., memory cells 625, 626, etc.), while it is not connected to any other section of columns linked to the other multiple memory cells (e.g., memory cells 627, 628, etc.), whereas the circuit 200 has the word line 220 connected to the columns linked to the memory cells (e.g., memory cells 225, 226, etc.). For example, as in Fig. Figure 6A shows the circuit having 600 M columns. The word line 620 can be connected to N columns linked to several memory cells (e.g., memory cells 625, 626, etc.), while not being connected to MN columns linked to other several memory cells (e.g., memory cells 627, 628, etc.). In some embodiments, memory cells 627, 628, etc., can be connected to word line 610 without being connected to word line 620.

[0055] Fig. Figure 6B illustrates a schematic diagram of an example circuit 650, which is used in the memory component of Fig. 1 may be shown, in accordance with some embodiments. The circuit 650 may have several memory cells (e.g., memory cells 675, 676, 677, 678), a first word line 660, and a second word line 670. It is welcome that the schematic diagram of Fig. 6B is simplified for illustrative purposes and therefore the circuit 650 can be implemented as any of several other configurations while remaining within the scope of the present disclosure.

[0056] In some embodiments, the circuit 650 may be substantially similar to or incorporate structural elements of the circuit 400. Alternatively, in some embodiments, the circuit 650 may have the word line 670 connected to a section of columns linked to several memory cells (e.g., memory cells 675, 676, etc.), while not connected to another section of columns linked to the other several memory cells (e.g., memory cells 677, 678, etc.), whereas the circuit 400 has the word line 420 connected to all memory cells (e.g., memory cells 425, 426, etc.). For example, as in Fig. Figure 6B shows the circuit having 650 M columns. The word line 670 can be connected to N columns linked to the multiple memory cells (e.g., memory cells 675, 676, etc.), while it is not connected to MN columns linked to the other multiple memory cells (e.g., memory cells 677, 678, etc.). In some embodiments, memory cells 677 and 678 can be connected to the word line 660 without being connected to the word line 670.

[0057] Fig. Figure 7 illustrates a schematic diagram of an example 700 integrated circuit used in the memory component of Fig. 1 may be shown, in accordance with some embodiments. The circuit 700 may have a series 200R of the circuit 200 and a series 700R of a circuit. The series 700R may have a first word line 710, a second word line 720, several memory cells (e.g., memory cells 725, 726), interconnect structures 731, 732, 733, 734, etc. It is welcome that the schematic diagram of Fig. 7 is simplified for illustrative purposes and therefore the circuit 700 can be implemented as any different other configuration while remaining within the scope of the present disclosure.

[0058] In some embodiments, the circuit 700 may be substantially similar to or incorporate structural elements of the circuit 200. In some embodiments, the circuit 700 may alternatively comprise the 700R series, unlike the circuit 200, which may comprise multiple 200R series. In some embodiments, the circuit 700 may comprise multiple series, which may be any arrangement of the 200R series and the 700R series. For example, the 200R series and the 700R series may be arranged alternately.

[0059] The multiple memory cells can be from memory array 120. In some embodiments, the multiple memory cells (e.g., memory cells 725, 726) can be arranged along a row and across multiple columns (e.g., M columns) of a memory array. In some embodiments, the multiple memory cells can be arranged such that each of the multiple memory cells is aligned with a corresponding multiple memory cell in row 200R. For example, memory cells 725, 726 can correspond to memory cells 225, 226, etc.

[0060] In some embodiments, the multiple memory cells (e.g., memory cells 725, 726) may have or be coupled to access transistors (e.g., access transistors 725T, 726T). The access transistors 725T, 726T may connect the memory cells 725, 726 to the corresponding bit lines BL / BLB. In some embodiments, the memory cell(s) 725 may have multiple first memory cells, and the memory cell(s) 726 may have multiple second memory cells. In some embodiments, each of the multiple memory cells (e.g., memory cell(s) 725, memory cell(s) 726, etc.) may have a static random-access memory cell (SRAM cell).

[0061] The first word line 710 and the second word line 720 can be of the memory array 120. In some embodiments, the first word line 710 can be a word line linked to a first metallization layer on a front face. In some embodiments, the second word line 720 can be a word line linked to a second metallization layer on the front face. For example, the first word line 710 can be linked to one or more metallization layers formed on a top section of the front face. The second word line 720 can be linked to one or more metallization layers formed on a bottom section of the front face. In some embodiments, the 700R series can include the interconnect structures 731, 732, 733, 734, etc. The interconnect structures 731, 732, 733, 734 can be coupled to gate terminals of the memory cells 725, 726.For example, the interconnect structures 731, 732 and the interconnect structures 733, 734 can be coupled to the corresponding gate terminals of the access transistors 725T and 726T, respectively.

[0062] In some embodiments, the word line 710 can be connected to a metallization layer (e.g., an M5 track) at a first row (e.g., row[0] or even rows) of the front side, while the word line 720 can be connected to one or more metallization layers (e.g., M1 and M3 tracks) at the first row of the front side. In some embodiments, the word line 210 of row 200R can be connected to one or more metallization layers (e.g., M1 and M3 tracks) at a second row (e.g., row[1] or odd rows) of the front side, while the word line 220 of row 200R can be connected to a metallization layer (e.g., an M5 track) at the second row of the back side.

[0063] Fig. Figure 8 illustrates an example layout 800 associated with an example circuit, in accordance with some embodiments. In particular, in Fig. Figure 8 shows a top view of layout 800. In some embodiments, layout 800 can be linked to circuit 700. The in Fig. Layout 800 shown is a non-limiting example and has been simplified for illustrative purposes. It is welcome that Layout 800 can be implemented as any number of different configurations while remaining within the scope of this disclosure.

[0064] In some embodiments, the layout 800 may be substantially similar to or incorporate structural elements of the layout 500. Alternatively, in some embodiments, the layout 800 may have one row 801, whereas the layout 500 may have multiple rows 500R. In some embodiments, the layout 800 may have multiple rows, which may have any arrangement of the row 801 and the row 500R. For example, the row 801 and the row 500R may be arranged alternately.

[0065] In a first region of the substrate, the circuit associated with layout 800 (e.g., circuit 700) can have several memory cells (e.g., the first memory cells 825, the second memory cells 826, etc.). The circuit can have several via structures in a second region of the substrate. The second region can be located adjacent to the first region along a lateral direction (e.g., the one in Fig. 8 x-axis shown).

[0066] In some embodiments, the circuit can have the multiple memory cells arranged along a row and across multiple columns of a memory array formed in the first region. In some embodiments, the multiple memory cells can be configured such that the 500R row and the 801 row cross the multiple memory cells.

[0067] In some embodiments, the circuit may have via structures (e.g., V1 805, V2 804, V3 803, V4 802, etc.) and interconnect structures (e.g., M5 810, M4 820, M3 830, M2 840, etc.) formed in various sections of the second area. For example, as in Fig. Figure 8 shows the circuit having a first set of vias (e.g., V1 805A, V2 804A, V3 803A, V4 802A, etc.) and a first set of interconnects (e.g., M5 810A, M4 820A, M3 830A, M2 840A, etc.) in a first section of the second area; and a second set of vias (e.g., V1 805B, V2 804B, V3 803B, V4 802B, etc.) and a second set of interconnects (e.g., M5 810B, M4 820B, M3 830B, M2 840B, etc.) in a second section of the second area. In some embodiments, as shown in Fig. Figure 8 shows the set of via structures and the set of interconnect structures arranged along the x-axis (and / or the y-axis (not shown)). In some embodiments, as in Fig. Figure 8 shows the set of via structures (e.g., V1 805A, V2 804A, V3 803A, V4 802A, etc.) being offset from the other set (e.g., via structures 504A, 505A, 560B, etc.) along both the x-axis and the y-axis. In some embodiments, as shown in Fig. Figure 8 shows that one set of interconnect structures (e.g., M5 810A, M4 820A, M3 830A, M2 840A, etc.) is offset from another set (e.g., BM0 506C, M0 503C, etc.) of interconnect structures along both the x-axis and the y-axis. In some embodiments, the circuit may have several rows (e.g., the 801 row, the 500R row, etc.) arranged along the y-axis. As shown in Fig. As shown in Figure 8, the 801 series can be offset from the 500R series in both the x-axis and the y-axis.

[0068] In some embodiments, the M2 track 840 can extend along the y-axis (e.g., as the M2 tracks 840A, 840B in Fig. 8 shown). In some embodiments, the M2 track 840 can cross the M1 track 530, the M3 track 830, etc. In some embodiments, the M3 track 830 can extend along the x-axis (e.g., as the M3 tracks 830A, 830B in Fig. 8 shown). In some embodiments, the M3 track 830 can cross the M2 track 840, the M4 track 820, etc. In some embodiments, the M4 track 820 can extend along the y-axis (e.g., as the M4 tracks 820A, 820B in Fig. 8 shown). In some embodiments, the M4 track 820 can cross the M1 track 530, the M3 track 830, etc. In some embodiments, the M5 track 810 can extend along the x-axis (e.g., as the M5 tracks 810A, 810B in Fig. 8 shown). In some embodiments, the M5 track 810 can cross the M4 track 820, the M2 track 840, the memory cells 825, 826, etc.

[0069] In some embodiments, the via structures (e.g. V1 805A, V2 804A, V3 803A, V4 802A etc.) can extend along the z-axis to connect at least one of the M5 810, M4 820, M3 830, M2 840 etc. to another.

[0070] Fig. Figure 9 illustrates a flowchart of an example method 900 for forming a memory device. In some embodiments, method 900 can be performed to fabricate a memory device based on the properties described in relation to Fig. 3A, Fig. 3B, Fig. 5A, Fig. 5B and Fig. to form the layouts explained in Section 8, and therefore some of the references used previously may be reused in the following explanation of Procedure 900. It is noted that Procedure 900 is merely an example and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations before, during, and after Procedure 900 may be performed by Fig. 9 may be provided and that some other operations are only briefly described here.

[0071] In brief, Method 900 can begin with Operation 910 to create multiple memory cells in a first region and on the first side of a substrate. Method 900 can continue with Operation 920 to create a first interconnect structure on the first side of the substrate and across the multiple memory cells. Method 900 can continue with Operation 930 to flip the substrate. Method 900 can continue with Operation 940 to create a through-hole via structure in a second region and on a second region of the substrate. Method 900 can continue with Operation 950 to create a second interconnect structure on the second side of the substrate.

[0072] In Operation 910, multiple memory cells (e.g., memory cells 225, 226) can be formed in a first region and on a first side (e.g., the front) of a substrate. In some embodiments, the multiple memory cells can be formed such that they are arranged along a row and across multiple columns of a memory array. In some embodiments, the multiple memory cells can include first and second memory cells arranged along a lateral direction. In some embodiments, the multiple memory cells can include a static random-access memory cell (SRAM cell).

[0073] In Operation 920, a first interconnect structure (e.g., the M1 track 530) can be formed on the first side of the substrate and across the multiple memory cells. In some embodiments, the first interconnect structure can be coupled to the respective gate terminals of the multiple memory cells. For example, the first interconnect structure can be coupled to the respective gate terminals of access transistors (e.g., the access transistor 225T) of the multiple memory cells. In Operation 930, the substrate can be flipped.

[0074] In Operation 940, a through-hole plating structure (e.g., through-hole plating structure 350) can be formed in a second region and on a second side (e.g., the back side) of the substrate. In some embodiments, the second region can be located adjacent to the first region along a lateral direction. In Operation 950, a second interconnect structure (e.g., BM1 track 340) can be formed on the second side of the substrate. In some embodiments, the second interconnect structure can be coupled to the first interconnect structure via the through-hole plating structure. In some embodiments, the first interconnect structure and the second interconnect structure can each extend along the lateral direction to traverse both the first and second regions.In some embodiments, the via structure can extend through the substrate to connect the first side to the second side of the substrate. In some embodiments, the via structure can be formed on the second side of the substrate.

[0075] Fig. Figure 10 illustrates a flowchart of an example method 1000 for forming a memory device. In some embodiments, the method 1000 can be carried out to fabricate a memory device based on the properties described in relation to Fig. 3A, Fig. 3B, Fig. 5A, Fig. 5B and Fig. to form the layouts explained in Section 8, and therefore some of the references used previously may be reused in the following explanation of Method 1000. It is noted that Method 1000 is merely an example and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be performed before, during, and after the method of Fig. 10 may be provided, and some other operations are only briefly explained here.

[0076] In brief, Method 1000 can begin with Operation 1010 to create multiple memory cells in a first region and on the first side of a substrate. Method 1000 can continue with Operation 1020 to create a first interconnect structure on the first side of the substrate and across the multiple memory cells. Method 1000 can continue with Operation 1030 to flip the substrate. Method 1000 can continue with Operation 1040 to create a via structure and a transistor connected to the via structure in a second region and on a second region of the substrate. Method 1000 can continue with Operation 1050 to create a second interconnect structure on the second side of the substrate.

[0077] In Operation 1010, multiple memory cells (e.g., memory cells 425, 426) can be formed in a first region and on a first side (e.g., the front) of a substrate. In some embodiments, the multiple memory cells can be arranged along a row and across multiple columns of a memory array. In some embodiments, the multiple memory cells can include first and second memory cells arranged along a lateral direction. In some embodiments, the multiple memory cells can include a static random-access memory cell (SRAM cell).

[0078] In Operation 1020, a first interconnect structure (e.g., the M1 track 530) can be formed on the first side of the substrate and across the multiple memory cells. In some embodiments, the first interconnect structure can be coupled to the respective gate terminals of the multiple memory cells. For example, the first interconnect structure can be coupled to the respective gate terminals of access transistors (e.g., the access transistor 425T) of the multiple memory cells. In Operation 1030, the substrate can be flipped.

[0079] In Operation 1040, a via structure (e.g., via structure 560) and a transistor connected to the via structure (e.g., transistor 450) can be formed in a second region and on a second side (e.g., the back) of the substrate. In some embodiments, a gate terminal and a first source / drain terminal of the transistor can be coupled to the first interconnect structure, and a second source / drain terminal of the transistor can be coupled to the second interconnect structure through the via structure. In some embodiments, the transistor can be formed within a lead element (e.g., lead element 550). For example, the lead element can be a dummy element to form the transistor within it. In some embodiments, the second region can be located adjacent to the first region along a lateral direction.In Operation 1050, a second interconnect structure (e.g., the BM1 track 540) can be formed on the second side of the substrate. In some embodiments, the second interconnect structure can be coupled to the first interconnect structure via the via. In some embodiments, the first and second interconnect structures can each extend laterally to traverse both the first and second regions. In some embodiments, the via can extend through the substrate to connect the first side to the second side of the substrate. In some embodiments, the via can be formed on the second side of the substrate.

[0080] In one aspect of the present disclosure, a memory device is disclosed. The memory device comprises several first memory cells formed in a first region of a substrate, several first via structures formed in a second region of the substrate, the second region being arranged adjacent to the first region along a first lateral direction, a first of several front-side interconnect structures formed on a first side of the substrate, the first front-side interconnect structure being coupled to gate terminals of access transistors of the several first memory cells, and a first of several back-side interconnect structures on a second side of the substrate, vertically opposite to the first side, the first back-side interconnect structure being coupled to the first front-side interconnect structure by one or more of the several first via structures.

[0081] In a further aspect of the present disclosure, a memory device is disclosed. The memory device comprises a memory array having multiple memory cells, wherein the multiple memory cells are formed in a first region of a substrate; a first interconnect structure is formed on a first side of the substrate, wherein the first interconnect structure operatively serves as a first section of a word line for the multiple memory cells; a second interconnect structure is formed on a second side of the substrate opposite the first side, wherein the second interconnect structure operatively serves as a second section of the word line for the multiple memory cells; and one or more via structures are formed in a second region of the substrate adjacent to the first region along a lateral direction, wherein the one or more via structures are configured toto couple the first interconnect structure with the second interconnect structure, wherein the first interconnect structure and the second interconnect structure each extend along the lateral direction to cross both the first and the second area.

[0082] In yet another aspect of the present disclosure, a method for forming a storage device is disclosed.The method comprises forming multiple memory cells in a first region and on a first side of a substrate, forming a first interconnect structure on the first side of the substrate and across the multiple memory cells, wherein the first interconnect structure is coupled to respective gate terminals of the multiple memory cells, turning the substrate over, forming a via structure in a second region and on a second region of the substrate, wherein the second region is adjacent to the first region along a lateral direction, and forming a second interconnect structure on the second side of the substrate, wherein the second interconnect structure is coupled to the first interconnect structure through the via structure, with the first interconnect structure and the second interconnect structure each extending along the lateral direction to cross both the first and the second region.

[0083] As used herein, the terms "about" and "approximately" generally indicate the value of a given quantity, which may vary based on a specific technology node associated with the semiconductor device in question. Based on that specific technology node, the term "about" can indicate a value of a given quantity that varies, for example, within 10-30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0084] The foregoing outlines features of some embodiments so that those skilled in the art will better understand the aspects of this disclosure. Those skilled in the art will appreciate that they can already use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same benefits as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent designs do not deviate from the nature and scope of this disclosure and that they can make various changes, substitutions, and modifications herein without deviating from the nature and scope of this disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 642,080

[0001]

Claims

[1] Storage device comprising: several first storage cells that are formed in a first region of a substrate; several first through-hole structures formed in a second region of the substrate, the second region being arranged next to the first region along a first lateral direction; a first of several front-side interconnect structures is formed on a first side of the substrate, wherein the first front-side interconnect structure is coupled to gate terminals of access transistors of the several first memory cells; and a first of several backside interconnect structures is formed on a second side of the substrate vertically opposite to the first side, wherein the first backside interconnect structure is coupled to the first frontside interconnect structure by one or more of the several first via structures. [2] Storage device according to claim 1, wherein both the first front interconnect structure and the first rear interconnect structure extend along the first lateral direction. [3] Storage device according to claim 1 or 2, further comprising: several second storage cells that are formed in the first region of the substrate; several second through-hole structures formed in the second region of the substrate; a second of the several front-side interconnect structures is coupled with gate terminals of access transistors of the several second memory cells; and a second of the several rear interconnect structures is coupled to the second front interconnect structure by one or more of the several second via structures; where both the second front interconnect structure and the second rear interconnect structure extend along the first lateral direction. [4] Storage device according to claim 3, wherein each of the multiple first memory cells and the multiple second memory cells comprises a static random access memory cell (SRAM cell, Static Random Access Memory cell). [5] Storage device according to claim 3 or 4, wherein the second storage cells are aligned with the first storage cells along a second lateral direction perpendicular to the first lateral direction, while the one or more first via structures are offset from the one or more second via structures in both the first and second lateral directions. [6] Storage device according to any one of claims 1 to 5, wherein the one or more first via structures extend through the substrate. [7] Storage device according to claim 6, further comprising: a second of the several front-side interconnect structures, wherein the second front-side interconnect structure is arranged vertically between the substrate and the first front-side interconnect structure; and a second of the several backside interconnect structures, wherein the second backside interconnect structure is arranged vertically between the substrate and the first backside interconnect structure. [8] Storage device according to claim 7, wherein the one or more first via structures are each in direct contact with the second front interconnect structure and the second rear interconnect structure. [9] Storage device according to claim 7 or 8, wherein the first interconnect structure, the second front interconnect structure and the first rear interconnect structure each extend in the first lateral direction, while the second rear interconnect structure extends in a second lateral direction perpendicular to the first lateral direction. [10] Storage device according to any one of claims 1 to 9, wherein the first front interconnect structure and the first rear interconnect structure operatively serve as a section of a word line of the first memory cells. [11] Storage device according to any one of claims 1 to 10, wherein the first storage cells are arranged to be arranged along a row and over several columns of a storage array, and wherein the storage array is formed in the first region. [12] Storage device comprising: a storage array comprising multiple memory cells, wherein the multiple memory cells are formed in a first region of a substrate; a first interconnect structure formed on a first side of the substrate, wherein the first interconnect structure operatively serves as a first section of a word line for the multiple memory cells; a second interconnect structure formed on a second side of the substrate opposite the first, wherein the second interconnect structure operatively serves as a second section of the word line for the multiple memory cells; and one or more via structures formed in a second area of ​​the substrate adjacent to the first area along a lateral direction, wherein the one or more via structures are configured to couple the first interconnect structure with the second interconnect structure; wherein the first interconnect structure and the second interconnect structure each extend along the lateral direction to cross both the first and the second area. [13] Storage device according to claim 12, wherein the one or more via structures extend through the substrate to connect the first side to the second side of the substrate. [14] Storage device according to claim 12, wherein the one or more via structures are formed on the second side of the substrate. [15] Storage device according to claim 14, further comprising: at least one transistor formed in the second region of the substrate; wherein a gate terminal and a first source / drain terminal of the at least one transistor is coupled to the first interconnect structure and a second source / drain terminal of the at least one transistor is coupled to the second interconnect structure by the one or more via structures. [16] Storage device according to one of claims 12 to 15, wherein each of the multiple memory cells comprises a static direct access memory cell (SRAM cell). [17] Storage device according to one of claims 12 to 16, wherein the first interconnect structure and the second interconnect structure are each coupled to respective gate terminals of the multiple memory cells. [18] Method for forming a storage device, comprising: Forming multiple memory cells in a first area and on a first side of a substrate; Forming a first interconnect structure on the first side of the substrate and across the multiple memory cells, wherein the first interconnect structure is coupled to the respective gate terminals of the multiple memory cells; Turning the substrate; Forming a through-hole structure in a second area and on a second side of the substrate, wherein the second area is located next to the first area along a lateral direction; and Forming a second interconnect structure on the second side of the substrate, wherein the second interconnect structure is coupled to the first interconnect structure through the via structure; wherein the first interconnect structure and the second interconnect structure each extend along the lateral direction to cross both the first and the second area. [19] Method according to claim 18, wherein the through-hole plating structure extends through the substrate to connect the first side to the second side of the substrate. [20] Method according to claim 18, wherein the through-hole structure is formed on the second side of the substrate.

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