Semiconductor devices

Abstract

Semiconductor device comprising: a semiconductor substrate (1) of a first conductivity type in which an active region (11) and an edge termination region (51) that is spaced away from and encloses the active region are defined; a semiconductor element (14) formed in the active region; and several defect layers (38-1, 38-2, 38-3, 38-4) of a second conductivity type, which are formed at least partially overlapping in a region extending from a boundary section of the active region to the boundary termination region in a surface of the semiconductor substrate, where for any pair of an adjacent i-th and i+1-th defect layer among the multiple defect layers, P(i) > P(i+1), D(i) < D(i+1), and B(i) < B(i+1) are satisfied, where P(i) and P(i+1) are surface concentrations, respectively, which are concentrations of second-type defects in the i-th defect layer and in the i+1-th defect layer at the surface of the semiconductor substrate; D(i) and D(i+1) are bottom-end distances, respectively, which are distances from the surface of the semiconductor substrate to the bottom ends of the i-th defect layer and the i+1-th defect layer; and B(i) and B(i+1) are distances from an edge of the edge-termination region on the active-side to edges of the i-th defect layer and the i+1-th defect layer on an edge side of the semiconductor substrate. the surface concentration in an impurity layer (38-4), the distance to the lower end of which is the greatest among the distances to the lower end of the multiple impurity layers, is 10 to 1000 times the concentration of the impurities of the first conductivity type in the semiconductor substrate, and the distance to the lower end of the impurity layer (38-4) is in a range of 15 to 30 µm.

Description

Technical area

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device used at high voltages. State of the art

[0002] Semiconductor devices capable of operating at high voltages are known in which a P-type layer providing a PN junction is formed outside an active region in which a semiconductor element is formed. For such semiconductor devices, various techniques, such as the technique disclosed in Patent Document 1, have been proposed in recent years.

[0003] US 2008 / 0 224 150 A1 proposes a SiC semiconductor device comprising: a substrate of a first conductivity type made of silicon carbide; a drift layer of the first conductivity type made of silicon carbide, the drift layer having a lower doping than the substrate; a cell portion composed of a part of the substrate and a part of the drift layer; a peripheral portion composed of another part of the substrate and another part of the drift layer, the peripheral portion being formed to surround the cell portion; and a RESURF layer of a second conductivity type formed in a surface portion of the drift layer such that it is disposed in the peripheral portion. The RESURF layer consists of first and second RESURF layers having different impurity concentrations.The second RESURF layer is in contact with an outer periphery of the first RESURF layer and extends to a periphery of the cell section.

[0004] An IGBT presented in US Pat. No. 5,489,787 A comprises a semiconductor body with a first region of a first conductivity type, a second region of the opposite second conductivity type, a third region of the first conductivity type separated from the first region by the second region, and at least one injector region for injecting charge carriers of the opposite conductivity type into the first region. The conduction channel region adjacent to the insulated gate has first and second subregions for providing respective first and second subconducting channels.The second sub-region is spaced from the third region and is less doped than the first sub-conducting channel region to cause, when the injected current type of opposite conductivity reaches a given value, the pn junction between the second sub-channel and the second region to be forward biased, causing the bipolar transistor formed by the second sub-channel, the second region and the first region to become conductive to initiate a thyristor action with the at least one injector region, which ends with the disappearance of the conducting channel.

[0005] JP H06-334 188 A aims to further increase the high resistance of an edge termination structure. To this end, a deep, lightly doped p-layer is formed so that it is located below the edge of a diode p-layer. The lateral distance between the edge of the lightly doped p-layer and the edge of the diode p-layer is different from the distance between the edge of an electrode contacting the diode p-layer and the edge of the diode p-layer.

[0006] In US 2012 / 0 097 980 A1, an edge termination configuration of a SiC IGBT includes a semiconductor layer of a first conductivity type with a body region of a second conductivity type, a source region of the first conductivity type, a contact region of the second conductivity type, and a circumferential resurf region of the second conductivity type. A width of a portion of the circumferential resurf region excluding the body region is greater than or equal to half the thickness of the semiconductor layer.

[0007] US 2005 / 035405 A1 discloses a vertical power semiconductor component in which a cathode or emitter is formed on the backside of a substrate with an overlying rear-side metal layer. Injection damping means are provided in the edge region of the component to reduce charge carrier injection from the cathode or emitter into the edge section.

[0008] US 2014 / 0 197 451 A1 discloses an IGBT with an edge termination region. A first N-type buffer layer is provided under an N-type drift layer in the transistor region. A P-type collector layer is provided under the first buffer layer. A second N-type buffer layer is provided under the drift layer in the edge termination region. A collector electrode is directly connected to the collector layer and the second buffer layer. An impurity concentration of the second buffer layer decreases with decreasing distance from the collector electrode. The second buffer layer does not form an ohmic contact with the collector electrode. further prior art documentPatent document

[0009] Patent Document 1: Japanese Laid-Open Patent Application JP 2003-303956 A Summary of the inventionProblems to be solved by the invention

[0010] For a semiconductor device as described above, it has been proposed to arrange a plurality of P-type layers in a region extending from an edge portion of the active region to an edge portion of a substrate along a substrate surface in order to smooth a change in the electric field in the transverse direction of the semiconductor substrate and to increase a withstand voltage of the device. However, such a structure has a problem that the size of the region where the P-type layers are formed increases and that there is a corresponding increase in the area of ​​a single chip. Another problem is that the strong application of high electric fields to local portions of the P-type layers, which have a high curvature in cross section, imposes upper limits on the withstand voltage.

[0011] The semiconductor devices described above are configured to have high carrier concentrations in the active region and surrounding regions in the on-state, and it is proposed to realize an IGBT with a low on-state voltage. However, such a configuration impairs the current interruption capability of the device when performing a turn-off operation because the current densities in the surrounding regions of the active region increase.

[0012] The present invention has been made in view of the problems described above, and an object of the present invention is to provide a technique that can reduce the chip area and that can improve the withstand voltage characteristic and the interruption capability at turn-off without deteriorating the characteristics of a semiconductor element. Means to solve the problems

[0013] A semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type in which an active region and an edge termination region spaced from and enclosing the active region are defined, a semiconductor element formed in the active region, and a plurality of impurity layers of a second conductivity type formed at least partially overlapping in a region extending from an edge portion of the active region to the edge termination region in a surface of the semiconductor substrate. For any pair of adjacent i-th and i+1-th impurity layers among the plurality of impurity layers, P(i)>P(i+1), D(i)<D(i+1), and B(i)<B(i+1) are satisfied, where P(i) and D(i) are respectively.P(i+1) are surface concentrations, which are concentrations of impurities of the second conductivity type in the i-th impurity layer and in the i+1-th impurity layer at the surface of the semiconductor substrate, D(i) and D(i+1) are bottom end distances, which are distances from the surface of the semiconductor substrate to the bottom ends of the i-th impurity layer and the i+1-th impurity layer, respectively, and B(i) and B(i+1) are distances from an edge of the edge termination region on the active region side to edges of the i-th impurity layer and the i+1-th impurity layer on an edge side of the semiconductor substrate.The surface concentration in an impurity layer whose distance to the bottom is the largest among the distances to the bottom of the plurality of impurity layers is 10 to 1000 times a concentration of the impurities of the first conductivity type in the semiconductor substrate, and the distance to the bottom of the impurity layer is in a range of 15 to 30 µm. Advantageous effects of the invention

[0014] According to the present invention, the semiconductor device is configured such that the plurality of second conductivity-type impurity layers have higher impurity concentrations while being closer to the active region, and the surface concentration of the impurity layer that is farthest from the bottom is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the distance to the bottom of this impurity layer is in the range of 15 to 30 μm. Accordingly, it is possible to reduce the chip area and improve the withstand voltage characteristic and the turn-off interruption capability without deteriorating the characteristics of the semiconductor element. Brief description of the drawings Fig. 1 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 1. Fig. 2 is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 1. Fig. Figure 3 is a graph showing the relationship between the edge termination width and the number of P layers. Fig. Figure 4 is a graph showing the relationship between the dielectric strength and the number of P layers. Fig. Figure 5 is a graph showing the relationship between the withstand voltage and the distance to the bottom of a fourth P-layer. Fig. Figure 6 is a graph showing the relationship between the forward voltage and the distance to the bottom of the fourth P-layer. Fig. Figure 7 is a graph showing the relationship between the voltage resistance and the surface concentration of the fourth P layer. Fig. Figure 8 is a diagram showing the relationship between the dielectric strength and the ratio between the distances A1 and A2. Fig. 9 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 1 of Embodiment 1. Fig. 10 is a cross-sectional view showing another configuration of the semiconductor device according to Variation 1 of Embodiment 1. Fig. 11 is a cross-sectional view showing another configuration of the semiconductor device according to Variation 1 of Embodiment 1. Fig. Figure 12 is a diagram showing the relationship between the power-off interrupt capability and the position of the edge of the bottom P layer. Fig. Figure 13 is a diagram showing the relationship between the forward voltage and the position of the edge of the bottom P layer. Fig. 14 is a plan view describing the scales on the horizontal axes in Fig. 12 and Fig. 13. Fig. 15 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 2 of Embodiment 1. Fig. Figure 16 is a diagram showing impurity concentration profiles along lines D-D', E-E', FF', and GG'. Fig. 17 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 3 of Embodiment 1. Fig. 18 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 4 of Embodiment 1. Fig. Figure 19 is a diagram showing impurity concentration profiles along lines HH' and II'. Fig. 20 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 2. Fig. 21 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 1 of Embodiment 2. Fig. 22 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 2 of Embodiment 2. Fig. 23 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 3 of Embodiment 2. Fig. 24 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 4 of Embodiment 2. Fig. 25 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 3. Fig. 26 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 1 of Embodiment 3. Fig. 27 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 2 of Embodiment 3. Fig. 28 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 3 of Embodiment 3. Fig. 29 is a cross-sectional view showing a configuration of a semiconductor device according to a modification 4 of Embodiment 3. Fig. 30 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 4. Fig. 31 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 1 of Embodiment 4. Fig. 32 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 2 of Embodiment 4. Fig. 33 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 3 of Embodiment 4. Fig. 34 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 4 of Embodiment 4. Fig. 35 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 5. Fig. 36 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 1 of Embodiment 5. Fig. 37 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 2 of Embodiment 5. Fig. 38 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 3 of Embodiment 5. Fig. 39 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 4 of Embodiment 5. Fig. 40 is a diagram showing an effect of reducing the edge termination width in the semiconductor device according to Embodiment 1. Fig. Figure 41 is a diagram of an evaluation circuit used in experiments to evaluate the withstand voltage characteristics. Fig. Figure 42 is a diagram showing waveforms for evaluating the withstand voltage and leakage current characteristics of semiconductor devices. Fig. Figure 43 is a diagram showing electric field strengths and electrostatic potentials at positions in the transverse direction of a semiconductor substrate. Fig. Figure 44 is a diagram showing electric field strengths and impurity concentrations at positions in the transverse direction of the semiconductor substrate. Fig. Figure 45 is a diagram showing electric field strengths and impurity concentrations at positions in the longitudinal direction of the semiconductor substrate. Fig. Figure 46 is a diagram showing electric field strengths and electric potentials at positions in the longitudinal direction of the semiconductor substrate. Fig. Figure 47 is a diagram of an evaluation circuit used in experiments to evaluate turn-off characteristics. Fig. 48 shows results of the evaluation of the switch-off characteristic. Fig. Figure 49 is a diagram showing the interruption capability when powering off. Fig. Figure 50 is a graph showing the dependence of turn-off interruption capability on the concentration of the bottom P layer. Fig. Figure 51 is a diagram showing safe operating ranges when switching off. Fig. 52 is a diagram of an evaluation circuit used in experiments for evaluating reverse withstand voltage characteristics. Fig. Figure 53 is a diagram showing waveforms for evaluating reverse withstand voltage and leakage current characteristics. Fig. 54 is a cross-sectional view showing a configuration of a semiconductor device including a diode or an IGBT. Fig. 55 is a plan view showing a configuration of a relevant semiconductor device. Fig. Fig. 56 is an enlarged plan view showing the configuration of the relevant semiconductor device. Fig. Fig. 57 is a cross-sectional view showing the configuration of the relevant semiconductor device. Fig. Fig. 58 is a cross-sectional view showing another configuration of the relevant semiconductor device. Description of embodimentsEmbodiment 1

[0015] Before giving a description of semiconductor devices in accordance with the present invention, a semiconductor device relevant thereto (hereinafter referred to as a "relevant semiconductor device") will first be described.

[0016] Fig. Fig. 55 is a plan view showing a configuration of the relevant semiconductor device, and Fig. 56 is an enlarged view showing a Fig. 55 shows the area indicated by the dashed line. As shown in Fig. 55, the semiconductor device includes an N-type semiconductor substrate (first conductivity type semiconductor substrate) 1 in which an active region 11, an edge termination region 51 spaced from and sandwiching the active region 11, and a primary PN junction region 31 located between the active region 11 and the edge termination region 51 are defined. Here, the active region 11 is sandwiched by the primary PN junction region 31, and the primary PN junction region 31 is sandwiched by the edge termination region 51. Note that the active region 11, the primary PN junction region 31, and the edge termination region 51 will be described in detail later.

[0017] As in Fig. 56, the semiconductor substrate 1 includes a metal film 4 containing aluminum (Al) or the like, which will be described later, P-type (second conductivity type) P-layers 33, an N-type (first conductivity type) N-layer 53, and a gate electrode 13.

[0018] Fig. 57 is a cross-sectional view showing the configuration of the relevant semiconductor device along the line AA' in Fig. 56 shows. As in Fig. 57, the relevant semiconductor device includes an IGBT 14, which is a semiconductor element formed in the active region 11.

[0019] The IGBT 14 includes gate electrodes 18 formed over an insulating film 17 in trenches of the surface of the N-type semiconductor substrate 1, a P-type layer 19 sandwiching the gate electrodes 18 in the surface of the semiconductor substrate 1, an N-type layer 20 formed under the P-type layer 19, a P+ type layer 21 and an N+ type layer 22 formed in the upper part of the P-type layer 19, and emitter electrodes 23 formed from the metal film 4 and connected to the P+ type layer 21 via contact holes of the insulating film 17. Further, the IGBT 14 includes a bottom N-layer 24 formed on the bottom surface of the semiconductor substrate 1 and serving as an N-buffer layer, a bottom P-layer 25 formed on the bottom N-layer 24 and serving as a P-collector layer, and a collector electrode 26 formed on the bottom P-layer 25.

[0020] Note that a portion of the semiconductor substrate 1 where there are no impurity layers such as the N-type layer 20 and the P-type layer 19 serves as an N-type drift layer 16. The gate electrodes 18 of the IGBT 14 are connected by wires, and the emitter electrodes 23 of the IGBT 14 are connected by wires.

[0021] The relevant semiconductor device includes not only the aforementioned IGBT 14, but also a plurality of P-type layers 33 (33-1, 33-2, 33-3, ..., and 33-n) and an N-type layer 53. The P-type layers 33 are arranged in a region extending from an edge portion of the active region 11 to the edge termination region 51 in the surface of the semiconductor substrate 1, and the N-type layer 53 is formed in an edge portion of the semiconductor substrate 1 (an edge portion of the edge termination region 51). Among the P-type layers 33 (33-1, 33-2, 33-3, ..., 33-n), the P-type layer 33-1 (the primary junction P layer), formed on the innermost side of the active region 11, is relatively larger than the other P-type layers. In an upper portion of the P layer 33-1, a P+ layer 34 is formed near the gate electrodes 18 and is connected to the emitter electrodes 23 via the contact holes of the insulating film 17.

[0022] The P-layers 33 and the N-layer 53 are each connected to a plurality of electrodes 35 formed over the contact holes of the insulating film 17 of the metal film 4, and a plurality of protective films 6 are formed on these electrodes 35 and on the insulating film 17. Note that the concentrations, depths, widths, and number of the P-layers 33 and the layout of the electrodes 35 are used as design parameters, which can be changed in accordance with a required withstand voltage (voltage withstand).

[0023] According to the relevant semiconductor device having the above-mentioned configuration, when a voltage equal to or greater than a threshold voltage is applied to the gate electrodes 18, channels are formed in the P-type layer 19 around the gate electrodes 18, and the IGBT 14 is turned on. In other words, a main current is allowed to flow from the emitter electrodes 23 to the collector electrode 26 via the P+ layer 21, the channels (the P-type layer 19), the N-type layer 20, the drift layer 16, the bottom N-type layer 24, and the bottom P-type layer 25. Although a detailed description has been omitted, in order to realize the IGBT 14 with a low forward voltage, the relevant semiconductor device is configured such that the emitter-side portions of the active region 11 and the primary PN junction region 31 have high carrier concentrations (where, for example,the concentration of impurities in the drift layer 16 is increased by three orders of magnitude or more by a modulation operation) when the IGBT 14 is in the on state.

[0024] The above is a description of the configuration of the relevant semiconductor device. Fig. 57, the active region 11, the primary PN junction region 31 and the edge termination region 51 briefly described above, and an edge termination width Le used in the following description.

[0025] The active region 11 is a region where the main current flows when the IGBT 14 is in the on state. The primary PN junction region 31 is a region located between the active region 11 and the edge termination region 51. Here, it is assumed that a boundary B between the active region 11 and the primary PN junction region 31 passes through the edge of the outermost contact hole (in the present example, the contact hole connecting an emitter electrode 23 and the P+ layer 34) on the edge side of the semiconductor substrate 1 in the active region 11.

[0026] The edge termination region 51 is a region located at the outer periphery of the primary PN junction region 31, in which no main current flows when the IGBT 14 is in the on-state. When a bias voltage is applied in the edge termination region 51 in the off-state, a depletion layer expands in the transverse direction of the semiconductor substrate 1 to maintain a withstand voltage. Here, it is assumed that a boundary C between the primary PN junction region 31 and the edge termination region 51 passes through the edge of the P-layer 33-1 on the edge side of the semiconductor substrate 1.

[0027] Here it is assumed that the edge width Le, as in Fig. 57, refers to a width from the boundary C between the primary PN junction region 31 and the edge termination region 51 to the edge of the N-layer 53 on the active region 11 side.

[0028] Fig. Fig. 58 is a cross-sectional view showing another configuration of the relevant semiconductor device. Fig. The relevant semiconductor device shown in Fig. 58 includes, instead of the plurality of P-layers 33, a single P-layer 33a whose impurity concentration steadily increases in a direction from the edge termination region 51 to the active region 11.

[0029] The above-mentioned relevant semiconductor device, in which the plurality of P-type layers 33 (or the single P-type layer 33a) are arranged along the surface of the semiconductor substrate 1, can smooth a change in the electric field in the transverse direction of the semiconductor substrate 1. Consequently, a high-voltage device (semiconductor device) can be realized. However, such a structure has a problem that the sizes of the areas of the primary PN junction region 31 and the edge termination region 51 in which the P-type layers 33 are formed increase, and there is a corresponding increase in the area of ​​a single chip.

[0030] In addition, there is another problem that the strong application of high electric fields to local sections of the P-layer(s) 33 which have a high curvature in the cross-section (e.g., the sections where the circles are on the dashed lines in Fig. 57), imposes upper limits on the dielectric strength.

[0031] As described above, the relevant semiconductor device is also configured such that the emitter-side portions of the active region 11 and the primary PN junction region 31 have high carrier concentrations when the IGBT 14 is in the on-state. However, with such a structure, excess holes are injected from the bottom P layer 25 into the edge termination region 51 when the IGBT 14 performs a turn-off operation, resulting in an increase in the current density at the emitter-side boundary between the primary PN junction region 31 and the edge termination region 51. Furthermore, high carrier concentrations on the emitter side of the primary PN junction region 31 during a turn-off operation of the IGBT 14 make it difficult for the depletion layer on the collector side to expand.A resulting increase in the electric field strength on the emitter side of the primary PN junction region 31 accelerates impact ionization and increases the current density when the IGBT 14 performs a turn-off operation.

[0032] The above-described increase in current density leads to a local temperature increase and induces electrical thermal breakdown, thus impairing the current interruption capability when the IGBT 14 performs a turn-off operation. In particular, unlike those used in large-scale integration (LSI) typified by complementary metal oxide semiconductor (CMOS), IGBTs serving as power semiconductors, in addition to realizing low forward voltage, increased speed, and improved current drive capability, must have a breakdown strength typified by the turn-off capability during a turn-off operation.

[0033] In view of this, the semiconductor device according to Embodiment 1 of the present invention can solve the problems described above. In other words, according to the present embodiment of the invention, it is possible to reduce the chip area and improve the withstand voltage characteristic and the turn-off interruption capability without deteriorating the characteristics of the IGBT 14. The semiconductor device according to the present embodiment, which can achieve the effects described above, will be described below.

[0034] Fig. 1 is a cross-sectional view showing a configuration of a semiconductor device according to the present embodiment. Note that in the semiconductor device according to the present embodiment, the same or similar components as those described for the relevant semiconductor device are denoted by the same reference numerals, and the following description focuses on differences from the relevant semiconductor device.

[0035] As in Fig. 1, the semiconductor device according to the present embodiment includes, instead of the plurality of P layers 33, a plurality of P layers 38 (a plurality of second conductivity type impurity layers) formed at least partially overlapping each other in a region extending from the edge portion of the active region 11 to the edge termination region 51 in the surface of the semiconductor substrate 1.

[0036] In the present embodiment, these P-type layers 38 are formed as a whole to extend over the edge portion of the active region 11, the primary PN junction region 31, and the edge termination region 51, and serve as a P-type field blocking layer (hereinafter referred to as a "PFS layer") that suppresses the occurrence of a high electric field around a gate electrode 18 located on the outermost side of the active region 11 (at the edge of the active region 11).

[0037] Thus, it is assumed that four P-layers 38 (a first P-layer 38-1, a second P-layer 38-2, a third P-layer 38-3, and a fourth P-layer 38-4) are formed by thermal diffusion to enable the semiconductor device to withstand voltages of the 4500V class. Note that the reason why the semiconductor device with the four P-layers 38 can withstand voltages of the 4000V class will be described later.

[0038] The above-mentioned first P-type layer 38-1 among the four P-type layers 38 corresponds to the above-mentioned P-type layer 33-1 (the primary junction P-type layer). The boundary B between the active region 11 and the primary PN junction region 31 passes through the edge of a contact hole connecting the emitter electrode 23 and the P+ layer 34 on the edge side of the semiconductor substrate 1, and the boundary C between the primary PN junction region 31 and the edge termination region 51 passes through the edge of the first P-type layer 38-1 on the edge side of the semiconductor substrate 1.

[0039] For any pair of adjacent i-th and i+1-th P-layers 38 (where i = 1, 2, or 3), P(i) < P(i+1) is satisfied, where P(i) and P(i+1) are P-impurity concentrations (surface concentrations) of the i-th P-layer 38 and the i+1-th P-layer 38 at the surface of the semiconductor substrate 1, respectively. In other words, in the present embodiment, the surface concentrations satisfy the inequality P(1) > P(2) > P(3) > P(4), decreasing stepwise in this order.

[0040] In addition, D(i) < D(i+1) is satisfied, where D(i) and D(i+1) are distances (distances to the bottom end) from the surface of the semiconductor substrate 1 to the bottom ends of the i-th P-layer 38 and the i+1-th P-layer 38, respectively. In other words, in the present embodiment, as shown in Fig. 2, D(1) < D(2) < D(3) < D(4) is satisfied.

[0041] In addition, B(i) < B(i+1) is satisfied, where B(i) and B(i+1) are distances from the edge of the edge termination region 51 on the side of the active region 11 (ie, the boundary C) to the edges of the i-th P-layer 38 and the i+1-th P-layer 38 on the edge side of the semiconductor substrate 1. In other words, in the present embodiment, as shown in Fig. 1 (where B(1) is zero), B(1) < B(2) < B(3) < B(4) is satisfied.

[0042] In the above-described configuration of the present embodiment, the outermost fourth P-type layer 38-4, which has a strain among the plurality of P-type layers 38 (PFS layers), has a relatively low curvature in its cross-sectional shape. Accordingly, strong application of a high electric field to local portions can be suppressed.

[0043] The concentrations of the P-type layers 38 (PFS layers) are designed to satisfy P(1) > P(2) > P(3) > P(4) and gradually increase as the P-type layers 38 are closer to the cell (to the active region 11). This enhances the effect of preventing the depletion layer from expanding in the longitudinal and transverse directions. More specifically, the presence of the second and third P-type layers 38-2 and 38-3 prevents the depletion layer from expanding in the longitudinal and transverse directions and reaching the first P-type layer 38-1. As a result, a difference in electrostatic potential between the inside and outside of a high-curvature portion in the cross-sectional shape of the first P-type layer 38-1 becomes substantially zero. Thus, it is possible to suppress the application of high electric fields to this portion of the first P-type layer 38-1.

[0044] As described above, the semiconductor device according to the present embodiment can suppress the strong application of high electric fields to local portions. In other words, high electric fields are dispersed, and this increases the maximum withstand voltage. Furthermore, as described later, a smooth change in the electric field in the plurality of P-layers 38 can reduce the edge termination width Le ( Fig. 57) if the withstand voltage is constant. Accordingly, the chip area can be reduced.

[0045] Note that the design tolerance range of the fourth P-layer 38-4, as described below, is determined based on the edge termination width Le and the withstand voltage required for the device. Although a detailed description is omitted, the design tolerance ranges of the second and third P-layers 38-2 and 38-3 are determined based on a withstand voltage limit of the device and an optimized electric field distribution in each withstand voltage mode.

[0046] Fig. 3 to 8 are graphic representations mainly for describing the design tolerance range of the fourth P-layer 38-4. The following description focuses on the drawing in order, starting from Fig. 3, mainly on the design tolerance range of the fourth P-layer 38-4.

[0047] Fig. 3 is a graph showing the relationship between the edge termination width Le and the number of P-layers 38 (PFS layers) under a condition that the dielectric strength (BV CES ) is constant. A scale on the vertical axis in Fig. 3 indicates a normalized value for the edge termination width Le of the semiconductor device according to the present embodiment, using the edge termination width Le of the relevant semiconductor device as a reference. As shown in Fig. 3, the edge termination width Le can be reduced to a width that is at least 25% smaller than the edge termination width Le of the relevant semiconductor device when one or more p-layers 38 are formed.

[0048] Under the condition that the dielectric strength (BV CES) is constant, the edge termination width Le can be further reduced by increasing the number of P-layers 38. One conceivable reason for this is that a difference in impurity concentration between each pair of adjacent P-layers 38 decreases as the number of P-layers 38 increases, thereby reducing the concentration of an electric field in a high-curvature portion of each P-layer 38 at the boundary with the diffusion layer on the side of the edge termination region 51. With a suppressed concentration of electric fields at the boundary with the diffusion layer, a change in the electric field shows a steady distribution. This is considered to be the reason why the edge termination width Le can be further reduced by increasing the number of P-layers 38 under the conditions that the withstand voltage (BV CES ) is constant, can be reduced.

[0049] Fig. 3 shows that in the case of forming four P-layers 38, the edge termination width Le can be reduced to a width that is approximately 50% of the edge termination width Le of the relevant semiconductor device, and it is found that forming more than four layers reduces the effect of reducing the edge termination width Le.

[0050] Fig. 4 is a diagram showing the relationship between the dielectric strength (BV CES ) and the number of P-layers 38 (PFS layers) under the condition that the edge termination width Le is constant. A scale on the vertical axis in Fig. 4 indicates a normalized value for the withstand voltage of the semiconductor device according to the present embodiment, using the withstand voltage of the relevant semiconductor device as a reference.

[0051] As in Fig. 4, the voltage withstand voltage can be increased by increasing the number of P-layers 38 in such a way that it approaches a theoretical maximum value (which is shown in Fig. 4) for the withstand voltage of a planar PN junction, with the theoretical maximum value being determined based on the material, concentration, and thickness of the substrate. One conceivable reason for this is that a difference in impurity concentration between each pair of adjacent P-type layers 38 decreases as the number of P-type layers 38 increases, thereby reducing the concentration of an electric field in a high-curvature portion of each P-type layer 38 at the boundary with the diffusion layer on the edge termination region 51 side. Suppression of the concentration of an electric field at the boundary with the diffusion layer is considered to be a reason why a maximum total withstand voltage can approach the theoretical maximum value in the planar PN junction.

[0052] Fig. Figure 5 is a diagram showing the relationship between the dielectric strength (BV CES) and the distance D(4) to the lower end of the fourth P-layer 38-4. It is noted that it is assumed here that the edge termination width Le is set to a width that is 50% of the edge termination width Le of the relevant semiconductor device, since the edge termination width Le in the case of forming four P-layers 38, as described above with reference to Fig. 3, can be reduced to a width approximately 50% of the edge termination width Le of the relevant semiconductor device. Furthermore, it is assumed that the concentration profiles, depths, widths, and positions of the first to third P-layers 38-1 to 38-3 have already been optimized.

[0053] A scale on the vertical axis in Fig. Figure 5 indicates a standardized value for the withstand voltage of the semiconductor device according to the present embodiment, using the withstand voltage of the relevant semiconductor device as a reference. A scale on the horizontal axis in Fig. 5 indicates the distance D(4) to the lower end of the fourth P-layer 38-4. As in Fig. 5, the semiconductor device for high withstand voltage classes (3300 V, 4500 V, 6500 V) can have a higher withstand voltage (higher than 1 on the scale on the vertical axis) than the relevant semiconductor device if the fourth P-layer 38-4 has a distance D(4) to the bottom end of 15 µm or more.

[0054] Fig. Figure 6 is a graph showing the relationship between the forward voltage (V CE (sat) and the distance D(4) to the lower end of the fourth P-layer 38-4 from the surface of the semiconductor substrate 1. Similar to the case of Fig. 5 is in the case of Fig. 6, it is assumed that the edge termination width Le is set to a width that is 50% of the edge termination width Le of the relevant semiconductor device, and that the concentration profiles, depths, widths, and positions of the first to third P-layers 38-1 to 38-3 have already been optimized.

[0055] A scale on the vertical axis in Fig. Figure 6 indicates a normalized value for the forward voltage of the semiconductor device according to the present embodiment, using the forward voltage of the relevant semiconductor device as a reference. A scale on the horizontal axis in Fig. 6 indicates the distance D(4) to the lower end of the fourth P-layer 38-4. As in Fig. 6, for high withstand voltage classes (3300 V, 4500 V, 6500 V), an increase in the forward voltage can be suppressed if the fourth P-layer 38-4 has a distance D(4) to the lower end of 30 µm or less.

[0056] Fig. Figure 7 is a diagram showing the relationship between the dielectric strength (BV CES ) and the surface concentration P(4) of the fourth P layer 38-4. In the case of Fig. 7 is similar to the case of Fig. 5 or the like, it is assumed that the edge termination width Le is set to a width that is 50% of the edge termination width Le of the relevant semiconductor device, and that the concentration profiles, depths, widths, and positions of the first to third P-layers 38-1 have already been optimized.

[0057] A scale on the vertical axis in Fig. 7 gives a standardized value for the dielectric strength (BV CES) of the semiconductor device in accordance with the present embodiment, using a theoretical maximum value for the withstand voltage as a reference. A scale on the horizontal axis in Fig. Figure 7 indicates a normalized peak value for the fourth surface concentration P(4), using the impurity concentration of the semiconductor substrate 1 as a reference. As in Fig. As shown in Figure 7, if the peak value for the fourth surface concentration P(4) is 1 to 2000 times the impurity concentration of the semiconductor substrate 1, the semiconductor device can have a higher withstand voltage (exceeding 0.85 on the scale on the vertical axis) than the relevant semiconductor device. Specifically, if the peak value for the fourth surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate 1, the withstand voltage can be further improved to further approach the above-mentioned theoretical maximum value.

[0058] Fig. Figure 8 is a graph showing the relationship between the dielectric strength (BV CES ) and the ratio (A1 / A2) between the Fig. 2. The distance A1 here is the distance from the edge of an injection window of the i+1-th P-layer 38 to the edge of the injection window of the i-th P-layer 38. The distance A2 is a distance across the injection window of the i+t-th P-layer 38. In the case of Fig. 8 is similar to the case of Fig. 5 or the like, it is assumed that the edge termination width Le is set to a width that is 50% of the edge termination width Le of the relevant device, and that the concentration profiles, depths, widths, and positions of the first to third P-layers 38-1 to 38-3 have already been optimized. In the case of Fig. 8 it is also assumed that the concentration profile, depth, width and position of the fourth P layer 38-4 are also already in view of the Fig. 5 to 7 have been optimized.

[0059] A scale on the vertical axis in Fig. 8 gives a standardized value for the dielectric strength (BV CES ) of the semiconductor device in accordance with the present embodiment, using the optimized withstand voltage value as a reference. A scale on the horizontal axis in Fig. 8 indicates the above-mentioned ratio (A1 / A2). As in Fig. 8, a deterioration of the dielectric strength (BV CES ) can be suppressed if the ratio (A1 / A2) is 0.5 or less.

[0060] From the above, the semiconductor device according to the present embodiment is configured such that the impurity concentrations in the P-type layers 38 increase as the P-type layers 38 are closer to the active region 11, and the surface concentration P(4) of the impurity layer with the greatest distance D(4) to the bottom end (in the present example, the fourth P-type layer 38-4) is 10 to 1000 times the impurity concentration of the semiconductor substrate 1, and the distance D to the bottom end of the impurity layer (here, the fourth P-type layer 38-4) is in the range of 15 to 30 μm. Accordingly, the chip area can be reduced, and the withstand voltage characteristic and the turn-off interruption capability can be improved without deteriorating the characteristics of the IGBT 14.

[0061] While the above description mainly focuses on an example of implementing a semiconductor device including an IGBT with a withstand voltage of approximately 4500 V and serving as a high-voltage power supply module, a semiconductor device including an IGBT with a withstand voltage of 4500 V or more (e.g., 6000 V or more) and serving as a high-voltage power supply module can be similarly implemented. A semiconductor material is not limited to Si, and semiconductor devices using wide bandgap materials such as SiC or GaN can also achieve similar effects to those described above. Amendment 1 of Embodiment 1

[0062] Fig. 9 to 11 are cross-sectional views showing configurations of a semiconductor device according to Modification 1 of Embodiment 1. The semiconductor device according to the present modification differs from the above-mentioned semiconductor device in the structures of the bottom P layer 25 and the collector electrode 26. In the present modification, the bottom N layer 24 (the first bottom impurity layer) is formed on the bottom surface of the semiconductor substrate 1 as in the case of the above-mentioned semiconductor device.

[0063] The bottom P-type layer 25 (the second bottom impurity layer) is formed on the bottom N-type layer 24 in a predetermined region including a region within the active region 11, except for a region of the edge termination region 51 on the edge side of the semiconductor substrate 1. It is noted that the predetermined region in which the bottom P-type layer 25 is formed may also be referred to as a "bottom P-type layer formation region" in the following description. The bottom P-type layer formation region in Fig. 9 is formed in the active region 11 and in the region 31 of the primary PN junction surrounding the active region 11, the formation region of the bottom P layer in Fig. 10 is formed only within the active area 11 and the formation area of ​​the underside P layer in Fig. 11 extends from the active area 11 to the edge termination area 51.

[0064] As in Fig. As shown in FIGS. 9 to 11, the collector electrode 26 (electrode) in the present modification is formed in a region different from the formation region of the bottom P layer on the bottom N layer 24 and is formed in the formation region of the bottom P layer on the bottom P layer 25. In this configuration, in which the collector electrode 26 and the bottom N layer 24 are in direct contact (short-circuited), the bottom N layer 24 in the edge termination region 51 functions to suppress hole injection from the collector side when the IGBT 14 performs a turn-off operation. This improves the interruption capability of the IGBT 14 during turn-off and suppresses an increase in the on-state voltage without having an adverse effect on the on-state of the IGBT 14.

[0065] Fig. 12 is a diagram showing the relationship between the interrupting capability when turning off J C (break) (the maximum current density at which the semiconductor device can be turned off without breakdown) and the position of the edge of the bottom P layer 25 (the boundary between the bottom P layer 25 and the bottom N layer 24 as seen in plan view). Fig. Figure 13 is a diagram showing the relationship between the forward voltage (V CE (sat)) and the position of the edge of the bottom P layer 25 (the boundary between the bottom P layer 25 and the bottom N layer 24 as seen in plan view).

[0066] A scale on the vertical axis in Fig. Figure 12 indicates a standardized value for the turn-off interruption capability of the semiconductor device in accordance with the present amendment, using the turn-off interruption capability of the relevant semiconductor device as a reference. A scale on the vertical axis in Fig. 13 indicates a normalized value for the forward voltage of the semiconductor device in accordance with the present amendment, using the forward voltage of the relevant semiconductor device as a reference.

[0067] The horizontal axes in Fig. 12 and Fig. 13 indicate the position of the edge of the bottom P layer 25 (the position at the boundary between the bottom N layer 24 and the bottom P layer 25), assuming that the boundary between the primary PN junction region 31 and the edge termination region 51 is the origin. Fig. 14 is a plan view describing the scales on the horizontal axes in Fig. 12 and Fig. 13. As in Fig. 14, the scales on the horizontal axes are in Fig. 12 and Fig. 13 is normalized such that, assuming that the boundary between the region 31 of the primary PN junction and the edge termination region 51 is the origin, a position +1 on the scale corresponds to the edge of the semiconductor substrate 1 (chip edge) and a position -1 on the scale corresponds to the center of the semiconductor substrate 1 (chip center).

[0068] Again based on Fig. 12 and Fig. 13, locations A3 and A4 are shown in the graphs. Location A3 indicates a location (-0.05 on the scale) of the edge of the outermost gate electrode 18 in the active region 11 at the edge-side termination region 51. Location A4 indicates a location that is one-quarter of the distance across the edge termination region 51 (a distance from the boundary between the primary PN junction region 31 and the edge termination region 51 to the edge of the semiconductor substrate 1) from the edge of the edge termination region 51 on the active region 11 side, so as to be closer to the edge of the semiconductor substrate 1.

[0069] The semiconductor device according to the present modification is configured such that the edge of the bottom P layer 25 (the boundary between the bottom P layer 25 and the bottom N layer 24 as seen in plan view) is located between the locations A3 and A4. As shown in Fig. 12 and Fig. 13, such a semiconductor device can improve the interruption capability of the IGBT 14 during turn-off and suppress an increase in the forward voltage without having an adverse effect on the on-state of the IGBT 14. As long as the edge of the bottom P-layer 25 (the boundary between the bottom P-layer 25 and the bottom N-layer 24 as seen in plan view) is located between the locations A3 and A4, any of the Fig. The configurations shown in Figures 9 to 11 achieve this effect. Amendment 2 of Embodiment 1

[0070] Fig. 15 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 2 of Embodiment 1. The semiconductor device according to the present modification is configured so that the N-type impurity concentration of the bottom N-type layer 24 has a peak at a deep position from the surface of the semiconductor substrate 1 in the semiconductor device according to Modification 1 of Embodiment 1.

[0071] Fig. Figure 16 is a diagram showing impurity concentration profiles along the lines DD' and EE' in Fig. 9 and impurity concentration profiles along the lines FF' and GG' in Fig. 15 shows a scale on the vertical axis in Fig. 16 indicates an impurity concentration normalized using the impurity concentration of the drift layer 16 (the impurity concentration of the semiconductor substrate 1). A scale on the horizontal axis in Fig. 16 indicates a position along the thickness of the semiconductor substrate 1 and indicates that the position closer to 1 on the scale is closer to the collector electrode 26.

[0072] Of the two peaks of the impurity concentrations for each of the lines DD' and FF', the one that is closer to the collector electrode 26 indicates a peak of the P-type impurity concentration of the bottom P-layer 25, and the other peak that is farther from the collector electrode 26 indicates a peak of the N-type impurity concentration of the bottom N-layer 24. The single peak of the impurity concentration for each of the lines EE' and GG' indicates a peak of the N-type impurity concentration of the bottom N-layer 24. For the lines DD' and GG' in Fig. 16, the impurity concentrations at positions near 0.99 on the scale indicate the impurity concentrations of the drift layer 16 (the impurity concentration of the semiconductor substrate 1).

[0073] In the present modification, the configuration is such that a distance R from the bottom surface of the semiconductor substrate 1 to the peak (first peak) of the impurity concentration of the bottom N-layer 24 satisfies the following inequality. In this inequality, ΔR is a distance between the peak and a position corresponding to one standard deviation of the impurity concentration of the bottom N-layer 24 in the range from the bottom surface of the semiconductor substrate 1 to the peak, N0 is the impurity concentration of the bottom N-layer 24 on the bottom surface of the semiconductor substrate 1, and N bthe impurity concentration at the tip in the bottom N-layer 24. It is assumed that the bottom N-layer 24 in the bottom P-layer formation region and the bottom N-layer 24 in the other region are both formed by the same implantation process (the same implantation amount, the same implantation energy, and the same implantation window). R>2⋅ΔR⋅InNbN0

[0074] As described above, in the present modification, the position of the peak of the impurity concentration of the bottom N-layer 24 (the impurity concentration of the G-G' line) satisfies the above inequality and is deep from the bottom of the semiconductor substrate 1. As a result, the impurity concentration on the collector electrode 26 side for the GG' line is lower than that for the E-E' line, as shown in Fig. 16 is indicated by the dashed line. This reduces the influence of the ohmic contact made by the bottom N-type layer 24 and the collector electrode 26 in the edge termination region 51. Accordingly, the effect of a forward bias diode formed between the P+ layer 21 on the surface side of the semiconductor substrate 1 and the bottom N-type layer 24 is suppressed when the IGBT 14 is in the reverse withstand voltage mode (when the emitter is positive and the collector is negative). Thus, it is possible to improve the blocking voltage capability of the IGBT 14 and reduce the leakage current in the reverse withstand voltage mode. Amendment 3 of Embodiment 1

[0075] Fig. 17 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 3 of Embodiment 1. The semiconductor device according to the present modification is configured such that, in the semiconductor device according to Modification 1 of Embodiment 1, the collector electrode 26 is formed in the bottom P layer formation region on the bottom P layer 25 without being formed on the bottom N layer 24.

[0076] According to the present modification, no ohmic contact is formed by the bottom N-type layer 24 and the collector electrode 26 in the edge termination region 51 in such a configuration. Accordingly, the effect of a forward bias diode formed between the P+ layer 21 on the surface side of the semiconductor substrate 1 and the bottom N-type layer 24 is suppressed when the IGBT 14 is in the reverse withstand voltage mode (when the emitter is positive and the collector is negative). Thus, it is possible to improve the reverse withstand voltage of the IGBT 14 and reduce the leakage current in the reverse withstand voltage mode. Amendment 4 of Embodiment 1

[0077] Fig. 18 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 4 of Embodiment 1. The semiconductor device according to the present modification is configured such that, in the semiconductor device according to Modification 1 of Embodiment 1, a low-concentration P-type layer 27 (third bottom-side impurity layer) having a lower impurity concentration than the bottom-side P-type layer 25 is additionally provided.

[0078] The low-concentration P layer 27 is formed in a region different from the formation region of the bottom P layer on the bottom N layer 24. The collector electrode 26 is formed in the region different from the formation region of the bottom P layer on the low-concentration P layer 27 and is formed in the formation region of the bottom P layer on the bottom P layer 25.

[0079] Fig. Figure 19 is a diagram showing impurity concentration profiles along lines HH' and II' in Fig. 18 in the same form as in Fig. 16 shows. Of the two impurity concentration peaks for the line HH', the one closer to the collector electrode 26 (closer to 1 on the scale on the horizontal axis) indicates a P-type impurity concentration peak of the bottom P layer 25, and the other peak, farther from the collector electrode 26, indicates a N-type impurity concentration peak of the bottom N layer 24.

[0080] Of the two impurity concentration peaks for line II', the one closer to the collector electrode 26 (closer to 1 on the scale on the horizontal axis) indicates a peak of the P-type impurity concentration of the low-concentration P-layer 27, and the other peak, farther from the collector electrode 26, indicates a peak of the N-type impurity concentration of the bottom N-layer 24. The impurity concentrations for lines HH' and I-I', whose areas are constant, indicate the impurity concentration of the drift layer 16 (the impurity concentration of the semiconductor substrate 1).

[0081] As described above, in the semiconductor device having the low-concentration P-type layer 27 according to the present modification, the bottom P-type layer 25, the low-concentration P-type layer 27, the drift layer 16, and the bottom N-type layer 24 form a PN junction. Accordingly, the IGBT 14 has a reverse withstand voltage when the IGBT 14 is in the reverse withstand voltage mode (when the emitter is positive and when the collector is negative), so the blocking voltage capability of the IGBT 14 can be improved and the leakage current in the reverse withstand voltage mode can be reduced.

[0082] As in Fig. 19, in the present modification, moreover, the peak (the second peak) of the impurity concentration of the low concentration P-layer 27 is higher than the impurity concentration of the semiconductor substrate 1 and lower than the peak (the third peak) of the impurity concentration of the bottom N-layer 25.

[0083] When the IGBT 14 in the semiconductor device is in the on-state according to the present modification, the contribution to hole injection from the collector side is reduced, and accordingly, an increase in the carrier concentration of the edge termination region 51 is suppressed. As a result, it is possible to suppress impact ionization due to increased electric field strength on the emitter side caused by an increase in the carrier concentration of the edge termination region 51 or the like, and to suppress excessive increases in current density and temperature. This suppresses a reduction in the current interruption capability when the IGBT 14 performs a turn-off operation. Embodiment 2

[0084] Fig. 20 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 2 of the present invention. Note that in the semiconductor device according to the present embodiment, the same or similar components as those described in Embodiment 1 are denoted by the same reference numerals, and the following description focuses on differences from Embodiment 1.

[0085] As in Fig. 20, the semiconductor device according to the present embodiment includes three P layers 39 (a first P layer 39-1, a second P layer 39-2, and a third P layer 39-3 of the second conductivity type) instead of the plurality of P layers 38.

[0086] The first and second P-type layers 39-1 and 39-2 are formed in a partially overlapping manner in a region extending from the edge portion of the active region 11 to the edge termination region 51 in the surface of the semiconductor substrate 1. The third P-type layer 39-3 adjoins a lower portion of the first P-type layer 39-1 on the edge termination region 51 side and a lower portion of the second P-type layer 39-2 on the active region 11 side.

[0087] In the present embodiment, three P-type layers 39 are formed as a whole extending over the edge portion of the active region 11, the primary PN junction region 31, and the edge termination region 51, and function as a P-type field blocking layer (hereinafter referred to as "PFS layer") that suppresses the occurrence of a high electric field around the gate electrode 18 located on the outermost side of the active region 11 (at the edge of the active region 11).

[0088] The first P-type layer 39-1 among the three P-type layers 39c corresponds to the aforementioned P-type layer 33-1 (primary junction P-type layer). The boundary B between the active region 11 and the primary PN junction region 31 passes through the edge of the contact hole connecting the emitter electrode 23 and the P+ layer 34 on the edge side of the semiconductor substrate 1, and the boundary C between the primary PN junction region 31 and the edge termination region 51 passes through the edge of the first P-type layer 39-1 on the edge side of the semiconductor substrate 1.

[0089] Here, P(1) > P(2) > P(3) is satisfied, where P(1), P(2) and P(3) are, in this order, P-type impurity concentrations (surface concentrations) of the first to third P-type layers 39-1 to 39-3 on the surface of the semiconductor substrate 1.

[0090] In addition, D(1) < D(2) < D(3) is satisfied, where D(1), D(2) and D(3) are, in this order, the distances (distances to the bottom end) from the surface of the semiconductor substrate 1 to the bottom ends of the first to third P layers 39-1 to 39-3.

[0091] As in Fig. 20 (where B(1) = 0), B(1) < B(3) < B(2) is satisfied if B(1), B(2) and B(3) in this order are the distances from the edge of the edge termination region 51 on the active region 11 side (i.e., the boundary C) to the edges of the first to third P layers 39-1 to 39-3 on the edge side of the semiconductor substrate 1.

[0092] In the above-described configuration of the present embodiment, the outer second and third P-type layers 39-2 and 39-3, which have a stress among the P-type layers 39 (PFS layer), have a relatively low curvature in cross section. Accordingly, the strong application of high electric fields to local portions can be suppressed.

[0093] The impurity concentrations in the P-type layers 39 (PFS layer) are designed to satisfy P(1) > P(2) > P(3) and gradually increase as the P-type layers 39 are closer to the cell (to the active region 11). Thus, the presence of the second P-type layer 39-2 prevents the depletion layer from spreading in the transverse direction and reaching the first P-type layer 39-1. As a result, a difference in electrostatic potential between the inside and outside of a high-curvature portion in the cross-sectional shape of the first P-type layer 39-1 becomes substantially zero. Thus, it is possible to suppress the application of a high electric field to this portion of the first P-type layer 39-1.

[0094] As described above, the semiconductor device according to the present embodiment can suppress strong application of high electric fields to local portions. In other words, high electric fields are dispersed, thereby increasing the maximum withstand voltage. Furthermore, a continuous change in the electric field in the plurality of P-layers 39 can reduce the edge termination width Le as in Embodiment 1 when the withstand voltage is constant. Accordingly, the chip area can be reduced.

[0095] It is noted that the design tolerance range of the third P-layer 39-3 is determined based on the edge termination width Le and the withstand voltage required for the device. Here, the distance D(3) to the bottom end of the third P-layer 39-3 is set to a value in the range of 15 to 30 μm ( Fig. 5 and Fig. 6). In addition, the design tolerance range of the second P-layer 39-2 is determined based on a device withstand voltage limit and an optimized electric field distribution in each withstand voltage mode. As in Embodiment 1, the surface concentration P(2) of the second P-layer 39-2 is set to a value that is 10 to 1000 times the impurity concentration of the semiconductor substrate 1 ( Fig. 7).

[0096] As described above, the semiconductor device according to the present embodiment is configured such that the impurity concentrations in the P-type layers 39 increase as the P-type layers 39 are closer to the active region 11, the surface concentration P(2) of the second P-type layer 39-2 is 10 to 1000 times the impurity concentration of the semiconductor substrate 1, and the distance D(3) to the bottom of the third P-type layer 39-3 is in the range of 15 to 30 μm. Accordingly, it is possible to reduce the chip area and improve the withstand voltage characteristics and the turn-off interruption capability without deteriorating the characteristics of the IGBT 14. Amendment 1 of Embodiment 2

[0097] Fig. 21 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 1 of Embodiment 2. Note that the present modification corresponds to Modification 1 of Embodiment 1.

[0098] More specifically, the bottom P-layer 25 is formed on the bottom N-layer 24 in a predetermined region including a region within the active region 11, except for a region of the edge termination region 51 on the edge side of the semiconductor substrate 1. The configuration is such that the edge of the bottom P-layer 25 is between the Fig. 12 and Fig. 13. The collector electrode 26 is formed in a region different from the formation region of the bottom P layer on the bottom N layer 24 (directly short-circuited to the bottom N layer 24) and is formed in the formation region of the bottom P layer on the bottom P layer 25.

[0099] The semiconductor device according to the present modification can, as in Modification 1 of Embodiment 1, improve the interruption capability of the IGBT 14 during turn-off and suppress an increase in the forward voltage without having an adverse effect on the on-state of the IGBT 14. It is noted that the predetermined region in which the bottom P-layer 25 is formed (ie, the formation region of the bottom P-layer) is not limited to the region shown in Fig. 21 shown area is limited and the Fig. 9 to 11. Even in this case, similar effects to those described above can be achieved. Modification 2 of Embodiment 2

[0100] Fig. 22 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 2 of Embodiment 2. Note that the present modification corresponds to Modification 2 of Embodiment 1.

[0101] More specifically, the configuration in the present modification is such that the distance R from the bottom surface of the semiconductor substrate 1 to the peak (first peak) of the impurity concentration of the bottom N-layer 24 satisfies the inequality described in Modification 2 of Embodiment 1, where ΔR is the distance between the peak and a position corresponding to one standard deviation of the impurity concentration of the bottom N-layer 24 in the range from the bottom surface of the semiconductor substrate 1 to the peak, N0 is the impurity concentration of the bottom N-layer 24 on the bottom surface of the semiconductor substrate 1, and N b an impurity concentration at the tip in the bottom N-layer 24.

[0102] Since the position of the peak of the impurity concentration of the bottom N-type layer 24 in the semiconductor device according to the present modification is deep from the bottom of the semiconductor substrate 1, the impurity concentration of the bottom N-type layer 24 on the collector electrode 26 side is reduced, as in Modification 2 of Embodiment 1. This reduces the influence of the ohmic contact formed by the bottom N-type layer 24 and the collector electrode 26 in the edge termination region 51. As a result, as in Modification 2 of Embodiment 1, it is possible to improve the blocking voltage withstand capability of the IGBT 14 and reduce the leakage current in the reverse withstand voltage mode. Amendment 3 of Embodiment 2

[0103] Fig. 23 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 3 of Embodiment 2. Note that the present modification corresponds to Modification 3 of Embodiment 1.

[0104] Specifically, in the present modification, the collector electrode 26 is formed in the bottom P layer formation region on the bottom P layer 25 without being formed on the bottom N layer 24. Accordingly, no ohmic contact is formed through the bottom N layer 24 and the collector electrode 26 in the edge termination region 51, as in Modification 3 of Embodiment 1. Thus, it is possible to improve the reverse withstand voltage of the IGBT 14 and reduce the leakage current in the reverse withstand voltage mode. Amendment 4 of Embodiment 2

[0105] Fig. 24 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 4 of Embodiment 2. Note that the present modification corresponds to Modification 4 of Embodiment 1.

[0106] More specifically, in the present modification, in a region different from the formation region of the bottom P layer on the bottom N layer 24, the low concentration P layer 27 having a lower impurity concentration than the bottom P layer 25 is formed. Note that a peak of the impurity concentration of the low concentration P layer 27 is higher than the impurity concentration of the semiconductor substrate 1 and lower than the peak of the impurity concentration of the bottom N layer 25. The collector electrode 26 is formed on the low concentration P layer 27 in the region different from the formation region of the bottom P layer, and is formed in the formation region of the bottom P layer on the bottom P layer 25.

[0107] The semiconductor device according to the present modification can improve the blocking voltage capability of the IGBT 14, as in Modification 4 of Embodiment 1, thereby suppressing the leakage current in the reverse withstand voltage mode. Furthermore, as in Modification 4 of Embodiment 1, it can suppress deterioration of the current interruption capability when the IGBT 14 performs a turn-off operation. Embodiment 3

[0108] Fig. 25 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 3 of the present invention. Note that in the semiconductor device according to the present embodiment, the same or similar components as those described in Embodiment 1 are denoted by the same reference numerals, and the following description focuses on differences from Embodiment 1.

[0109] As in Fig. 25, the semiconductor device according to the present embodiment includes four P-layers 40 (a first P-layer 40-1, a second P-layer 40-2, a third P-layer 40-3, and a fourth P-layer 40-4 of the second conductivity type) instead of the plurality of P-layers 38.

[0110] The first and second P-type layers 40-1 and 40-2 are formed at least partially overlapping in a region extending from the edge portion of the active region 11 to the edge termination region 51 in the surface of the semiconductor substrate 1. The third P-type layer 40-3 adjoins the edge portion of the first P-type layer 40-1 on the edge termination region 51 side, and the fourth P-type layer 40-4 adjoins the edge portion of the second P-type layer 40-2 on the edge termination region 51 side.

[0111] In the present embodiment, these P-layers 40 are formed as a whole extending over the edge portion of the active region 11, the primary PN junction region 31, and the edge termination region 51, and function as a P-field blocking layer (hereinafter referred to as a "PFS layer") that suppresses the occurrence of a high electric field around the gate electrode 18 located on the outermost side of the active region 11 (at the edge of the active region 11).

[0112] The first P-type layer 40-1 among the four P-type layers 40 corresponds to the aforementioned P-type layer 33-1 (primary junction P-type layer). The boundary B between the active region 11 and the primary PN junction region 31 passes through the edge of the contact hole connecting the emitter electrode 23 and the P+ layer 34 on the edge side of the semiconductor substrate 1, and the boundary C between the primary PN junction region 31 and the edge termination region 51 passes through the edge of the first P-type layer 40-1 on the edge side of the semiconductor substrate 1.

[0113] Here, P(1) > P(3) = P(4) > P(2) is satisfied, where P(1), P(2), P(3) and P(4) are, in this order, the P-type impurity concentrations (surface concentrations) of the first to fourth P-type layers 40-1 to 40-4 on the surface of the semiconductor substrate 1.

[0114] In addition, D(1) < D(3) = D(4) < D(2) is satisfied, where D(1), D(2), D(3) and D(4) are, in this order, the distances (distances to the bottom end) from the surface of the semiconductor substrate 1 to the bottom ends of the first to fourth P layers 40-1 to 40-4.

[0115] As in Fig. 25 (where B(1) = 0), B(1) < B(3) < B(2) < B(4) is satisfied if B(1), B(2), B(3) and B(4) in this order are the distances from the edge of the edge termination region 51 on the active region 11 side (i.e., the boundary C) to the edges of the first to fourth P-layers 40-1 to 40-4 on the edge side of the semiconductor substrate 1.

[0116] In the above-described configuration of the present embodiment, the outer second P-type layer 40-2, which has a stress among the P-type layers 40 (PFS layer), has a relatively low curvature in cross section. Accordingly, strong application of high electric fields to local portions can be suppressed.

[0117] The impurity concentrations in the P-type layers 40 (PFS layer) are designed to satisfy P(1) > P(3) > P(2) and gradually increase as the distance from the second P-type layer 40-2 to the cell (to the active region 11). Thus, the presence of the second and third P-type layers 40-2 and 40-3 prevents the depletion layer from expanding in the transverse direction and reaching the first P-type layer 40-1. As a result, a difference in electrostatic potential between the inside and outside of a high-curvature portion in the cross-sectional shape of the first P-type layer 40-1 becomes substantially zero. Thus, it is possible to suppress the application of a high electric field to this portion of the first P-type layer 40-1.

[0118] As described above, the semiconductor device according to the present embodiment can suppress the strong application of high electric fields to local portions. In other words, high electric fields are dispersed, and this increases the maximum withstand voltage. Furthermore, a continuous change in the electric field in the plurality of P-layers 40, as in Embodiment 1, can reduce the edge termination width Le when the withstand voltage is constant. Accordingly, the chip area can be reduced.

[0119] It is noted that the design tolerance range of the second P-layer 40-2 is determined based on the edge termination width Le and the withstand voltage required for the device. As in Embodiment 1, the distance D(2) to the bottom of the second P-layer 40-2 is set to a value in the range of 15 to 30 μm ( Fig. 5 and Fig. 6). In addition, the design tolerance ranges of the third and fourth P-type layers 40-3 and 40-4 are determined based on a device withstand voltage limit and an optimized electric field distribution in each withstand voltage mode. As in Embodiment 1, the surface concentrations P(3) and P(4) of the third and fourth P-type layers 40-3 and 40-4 are set to values ​​10 to 1000 times the impurity concentration of the semiconductor substrate 1 ( Fig. 7) are.

[0120] As described above, the semiconductor device according to the present embodiment is configured such that the impurity concentrations in the P-type layers 40 increase as the P-type layers 40 are closer to the active region 11, the surface concentration P(4) of the fourth P-type layer 40-4 is 10 to 1000 times the impurity concentration of the semiconductor substrate 1, and the distance D(2) to the bottom of the second P-type layer 40-2 is in the range of 15 to 30 μm. Accordingly, it is possible to reduce the chip area and improve the withstand voltage characteristic and the turn-off interruption capability without deteriorating the characteristics of the IGBT 14. Amendment 1 of Embodiment 3

[0121] Fig. 26 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 1 of Embodiment 3. Note that the present modification corresponds to Modification 1 of Embodiment 1.

[0122] More specifically, the bottom P-layer 25 is formed on the bottom N-layer 24 in a predetermined region including a region within the active region 11, except for a region of the edge termination region 51 on the edge side of the semiconductor substrate 1. In addition, the configuration is such that the edge of the bottom P-layer 25 is between the Fig. 12 and Fig. 13. The collector electrode 26 is formed in a region different from the formation region of the bottom P layer on the bottom N layer 24 (directly short-circuited to the bottom N layer 24) and is formed in the formation region of the bottom P layer on the bottom P layer 25.

[0123] The semiconductor device according to the present modification can, as in Modification 1 of Embodiment 1, improve the interruption capability of the IGBT 14 during turn-off and suppress an increase in the forward voltage without having an adverse effect on the on-state of the IGBT 14. It is noted that the predetermined region in which the bottom P-layer 25 is formed (ie, the formation region of the bottom P-layer) is not limited to the region shown in Fig. 26 is limited and the area shown in Fig. 9 to 11. Even in this case, similar effects to those described above can be achieved. Modification 2 of Embodiment 3

[0124] Fig. 27 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 2 of Embodiment 3. Note that the present modification corresponds to Modification 2 of Embodiment 1.

[0125] More specifically, the configuration in the present modification is such that the distance R from the bottom surface of the semiconductor substrate 1 to the peak (first peak) of the impurity concentration of the bottom N-layer 24 satisfies the inequality described in Modification 2 of Embodiment 1, where ΔR is the distance between the peak and a position corresponding to one standard deviation of the impurity concentration of the bottom N-layer 24 in the range from the bottom surface of the semiconductor substrate 1 to the peak, N0 is the impurity concentration of the bottom N-layer 24 on the bottom surface of the semiconductor substrate 1, and N b an impurity concentration at the tip in the bottom N-layer 24.

[0126] Since the position of the peak of the impurity concentration of the bottom N-type layer 24 in the semiconductor device according to the present modification is deep from the bottom surface of the semiconductor substrate 1, the impurity concentration of the bottom N-type layer 24 on the collector electrode 26 side is reduced as in Modification 2 of Embodiment 1. This reduces the influence of the ohmic contact formed by the bottom N-type layer 24 and the collector electrode 26 in the edge termination region 51. As a result, as in Modification 2 of Embodiment 1, it is possible to improve the blocking voltage withstand capability of the IGBT 14 and reduce the leakage current in the reverse withstand voltage mode. Modification 3 of Embodiment 3

[0127] Fig. 28 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 3 of Embodiment 3. Note that the present modification corresponds to Modification 3 of Embodiment 1.

[0128] Specifically, in the present modification, the collector electrode 26 is formed in the bottom P layer formation region on the bottom P layer 25 without being formed on the bottom N layer 24. Accordingly, as in Modification 3 of Embodiment 1, no ohmic contact is formed by the bottom N layer 24 and the collector electrode 26 in the edge termination region 51. Thus, it is possible to improve the reverse withstand voltage of the IGBT 14 and reduce the leakage current in the reverse withstand voltage mode. Amendment 4 of Embodiment 3

[0129] Fig. 29 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 4 of Embodiment 3. Note that the present modification corresponds to Modification 4 of Embodiment 1.

[0130] More specifically, the low-concentration P layer 27 having a lower impurity concentration than the bottom-side P layer 25 in the present modification is formed in a region different from the formation region of the bottom-side P layer on the bottom-side N layer 24. Note that a peak of the impurity concentration of the low-concentration P layer 27 is higher than the impurity concentration of the semiconductor substrate 1 and lower than the peak of the impurity concentration of the bottom-side N layer 25. The collector electrode 26 is formed in the region different from the formation region of the bottom-side P layer on the low-concentration P layer 27 and is formed in the formation region of the bottom-side P layer on the bottom-side P layer 25.

[0131] The semiconductor device according to the present modification can improve the blocking voltage capability of the IGBT 14, as in Modification 4 of Embodiment 1, thereby suppressing leakage current in the reverse withstand voltage mode. Furthermore, as in Modification 4 of Embodiment 1, it can suppress deterioration of the current interruption capability when the IGBT 14 performs a turn-off operation. Embodiment 4

[0132] Fig. 30 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 4 of the present invention. Note that the same or similar components as those described in Embodiment 1 are denoted by the same reference numerals in the semiconductor device according to the present embodiment, and the following description will focus on differences from Embodiment 1.

[0133] As in Fig. 30, the semiconductor device according to the present embodiment includes two P layers 41 (a first P layer 41-1 and a second P layer 41-2 of the second conductivity type) instead of the plurality of P layers 38.

[0134] The first and second P-type layers 41-1 and 41-2 are formed at least partially overlapping in a region extending from the edge portion of the active region 11 to the edge termination region 51 in the surface of the semiconductor substrate 1. The P-type impurity concentration of the first P-type layer 41-1 in the active region 11 is higher than in the edge termination region 51. The configuration here is such that the impurity concentration of the first P-type layer 41-1 steadily increases in a direction from the edge termination region 51 to the active region 11. To form this first P-type layer 41-1, for example,the following steps are performed: a first step of forming a plurality of impurity concentration regions whose impurity concentrations gradually increase in the direction from the edge termination region 51 to the active region 11; and a second step of thermally diffusing these impurity concentration regions to reduce a difference in impurity concentration between them.

[0135] In the present embodiment, these P-type layers 41 are formed as a whole extending over the edge portion of the active region 11, the primary PN junction region 31, and the edge termination region 51, and function as a P-type field blocking layer (hereinafter referred to as a "PFS layer") that suppresses the occurrence of a high electric field around the gate electrode 18 located on the outermost side of the active region 11 (at the edge of the active region 11).

[0136] The first P-type layer 41-1 of the two P-type layers 41 corresponds to the aforementioned P-type layer 33-1 (primary junction P-type layer). The boundary B between the active region 11 and the primary PN junction region 31 passes through the edge of the contact hole connecting the emitter diode 23 and the P+ layer 34 on the edge side of the semiconductor substrate 1, and the boundary C between the primary PN junction region 31 and the edge termination region 51 passes through the edge of the first P-type layer 41-1 on the edge side of the semiconductor substrate 1.

[0137] Here, Pmin(1) > P(2) is satisfied, where P(2) is the P-type impurity concentration (surface concentration) of the second P-type layer 41-2 at the surface of the semiconductor substrate 1 and Pmin(1) is the minimum surface concentration of the first P-type layer 41-1.

[0138] In addition, D(1) < D(2) is satisfied, where D(1) and D(2) are the distances (lower end distances) from the surface of the semiconductor substrate 1 to the lower ends of the first and second P-layers 41-1 and 41-2, respectively (in the present example, D(1) is a distance to the lower end of the first P-layer).

[0139] As in Fig. 30 (where B(1) = 0), B(1) < B(2) is satisfied when B(1) and B(2) are the distances from the edge of the edge termination region 51 on the active region 11 side (i.e., the boundary C) to the edges of the first and second P-layers 41-1 and 41-2 on the edge side of the semiconductor substrate 1, respectively.

[0140] In the above-described configuration of the present embodiment, the outer second P-type layer 41-2, which has a stress among the P-type layers 41 (PFS layer), has a relatively low curvature in its cross-sectional shape. Accordingly, the strong application of high electric fields to local portions can be suppressed.

[0141] The impurity concentrations in the P-type layers 41 (PFS layer) are designed to satisfy Pmin(1) > P(2) and gradually and steadily increase as the P-type layers 41 are closer to the cell (to the active region 11). Thus, the presence of the second P-type layer 41-2 prevents the depletion layer from expanding in the transverse direction and reaching the first P-type layer 41-1. As a result, the electrostatic potential difference between the inside and outside of a high-curvature portion in the cross-sectional shape of the first P-type layer 41-1 becomes substantially zero.

[0142] Thus, it is possible to suppress the application of a high electric field to this portion of the first P layer 41-1.

[0143] As described above, the semiconductor device according to the present embodiment can suppress the strong application of high electric fields to local portions. In other words, high electric fields are dispersed, and this increases the maximum withstand voltage. Furthermore, a continuous change in the electric field in the plurality of P-layers 41, as in Embodiment 1, can reduce the edge termination width Le when the withstand voltage is constant. Accordingly, the chip area can be reduced.

[0144] It is noted that the design tolerance range of the second P-layer 41-2 is determined based on the edge termination width Le and the voltage withstand voltage required for the device. As in Embodiment 1, the distance D(2) to the bottom of the second P-layer 41-2 is set to a value in the range of 15 to 30 μm ( Fig. 5 and Fig. 6) and the surface concentration P(2) of the second P-layer 41-2 is set to a value which is 10 to 1000 times the impurity concentration of the semiconductor substrate 1 ( Fig. 7). In addition, the design tolerance range of the first P-layer 41-1 is determined based on a device withstand voltage limit and an optimized electric field distribution in each withstand voltage mode.

[0145] As described above, the semiconductor device according to the present embodiment is configured such that the impurity concentrations in the P-type layers 41 increase as the P-type layers 41 are closer to the active region 11, the surface concentration P(2) of the second P-type layer 41-2 is 10 to 1000 times the impurity concentration of the semiconductor substrate 1, and the distance D(2) to the bottom of the second P-type layer 41-2 is in the range of 15 to 30 μm. Accordingly, it is possible to reduce the chip area and improve the withstand voltage characteristic and the turn-off interruption capability without deteriorating the characteristics of the IGBT 14. Amendment 1 of Embodiment 4

[0146] Fig. 31 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 1 of Embodiment 4. Note that the present modification corresponds to Modification 1 of Embodiment 1.

[0147] More specifically, the bottom P-layer 25 is formed on the bottom N-layer 24 in a predetermined region including a region within the active region 11, except for a region of the edge termination region 51 on the edge side of the semiconductor substrate 1. In addition, the configuration is such that the edge of the bottom P-layer 25 is sandwiched between the regions as shown in Fig. 12 and Fig. 13. The collector electrode 26 is formed in a region different from the formation region of the bottom P layer on the bottom N layer 24 (directly short-circuited to the bottom N layer 24) and is formed in the formation region of the bottom P layer on the bottom P layer 25.

[0148] The semiconductor device according to the present modification can, as in Modification 1 of Embodiment 1, improve the interruption capability of the IGBT 14 during turn-off and suppress an increase in the forward voltage without having an adverse effect on the on-state of the IGBT 14. It is noted that the predetermined region in which the bottom P-layer 25 is formed (ie, the formation region of the bottom P-layer) is not limited to the region shown in Fig. 31 shown area is limited and the Fig. 9 and Fig. 11. Even in this case, similar effects to those described above can be achieved. Amendment 2 of Embodiment 4

[0149] Fig. 32 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 2 of Embodiment 4. Note that the present modification corresponds to Modification 2 of Embodiment 1.

[0150] More specifically, the configuration in the present modification is such that the distance R from the bottom of the semiconductor substrate 1 to the peak (first peak) of the impurity concentration of the bottom N-layer 24 satisfies the inequality described in Modification 2 of Embodiment 1, where ΔR is the distance between the peak and a position corresponding to one standard deviation of the impurity concentration of the bottom N-layer 24 in the range from the bottom of the semiconductor substrate 1 to the peak, N0 is the impurity concentration of the bottom N-layer 24 at the bottom of the semiconductor substrate 1, and N b the impurity concentration at the tip in the bottom N-layer 24.

[0151] Since the position of the peak of the impurity concentration of the bottom N-type layer 24 in the semiconductor device according to the present modification is deep from the bottom of the semiconductor substrate 1, the impurity concentration of the bottom N-type layer 24 on the collector electrode 26 side is reduced, as in Modification 2 of Embodiment 1. This reduces the influence of the ohmic contact formed by the bottom N-type layer 24 and the collector electrode 26 in the edge termination region 51. As a result, as in Modification 2 of Embodiment 1, it is possible to improve the blocking voltage withstand capability of the IGBT 14 and reduce the leakage current in the reverse withstand voltage mode. Amendment 3 of Embodiment 4

[0152] Fig. 33 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 3 of Embodiment 4. Note that the present modification corresponds to Modification 3 of Embodiment 1.

[0153] Specifically, in the present modification, the collector electrode 26 is formed in the bottom P layer formation region on the bottom P layer 25 without being formed on the bottom N layer 24. Accordingly, no ohmic contact is formed through the bottom N layer 24 and the collector electrode 26 in the edge termination region 51, as in Modification 3 of Embodiment 1. Thus, it is possible to improve the reverse withstand voltage of the IGBT 14 and reduce the leakage current in the reverse withstand voltage mode. Amendment 4 of Embodiment 4

[0154] Fig. 34 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 4 of Embodiment 4. Note that the present modification corresponds to Modification 4 of Embodiment 1.

[0155] More specifically, the low-concentration P layer 27 having a lower impurity concentration than the bottom-side P layer 25 in the present modification is formed in a region different from the formation region of the bottom-side P layer on the bottom-side N layer 24. Note that a peak of the impurity concentration of the low-concentration P layer 27 is higher than the impurity concentration of the semiconductor substrate 1 and lower than the peak of the impurity concentration of the bottom-side N layer 25. The collector electrode 26 is formed in the region different from the formation region of the bottom-side P layer on the low-concentration P layer 27 and is formed in the formation region of the bottom-side P layer on the bottom-side P layer 25.

[0156] The semiconductor device according to the present modification can improve the blocking voltage capability of the IGBT 14, as in Modification 4 of Embodiment 1, thereby suppressing the leakage current in the reverse withstand voltage mode. Furthermore, as in Modification 4 of Embodiment 1, it can suppress deterioration of the current interruption capability when the IGBT 14 performs a turn-off operation. Embodiment 5

[0157] Fig. 35 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 5 of the present invention. Note that the same or similar components as described in Embodiment 1 are denoted by the same reference numerals in the semiconductor device according to the present embodiment, and the following description will focus on differences from Embodiment 1.

[0158] As in Fig. 35, the semiconductor device according to the present embodiment includes (n+1) P layers 42 (a first P layer 42-1, a second P layer 42-2, ..., and an (n+1)-th P layer 42-(n+1) of the second conductivity type) instead of the plurality of P layers 38.

[0159] The first to n-th P-layers 42-1 to 42-n among these P-layers 42 are arranged in a region extending from the edge portion of the active region 11 to the edge termination region 51 in the surface of the semiconductor substrate 1 in a direction from the active region 11 to the edge termination region 51. Note that the first to n-th P-layers 41-1 to 42-n have the same surface concentration, which is a P-type impurity concentration at the surface of the semiconductor substrate 1, and have the same bottom distance, which is a distance from the surface of the semiconductor substrate 1 to the bottom ends of the first to n-th P-layers 42-1 to 42-n.

[0160] The remaining single (n+1)-th P-layer 42-(n+1) is adjacent to at least a lower portion of the first P-layer 42-1 among the first to n-th P-layers 42-1 to 42-n.

[0161] In the present embodiment, these P-layers 42 are formed as a whole extending over the edge portion of the active region 11, the primary PN junction region 31, and the edge termination region 51, and function as a P-field barrier layer (hereinafter referred to as a "PFS layer") that suppresses the occurrence of a high electric field around the gate electrode 18 located on the outermost side of the active region 11 (at the edge of the active region 11).

[0162] The first P-type layer 42-1 among the (n+1) P-type layers 42 corresponds to the aforementioned P-type layer 33-1 (primary junction P-type layer). The boundary B between the active region 11 and the primary PN junction region 31 passes through the edge of the contact hole connecting the emitter electrode 23 and the P+ type layer 34 on the edge side of the semiconductor substrate 1, and the boundary C between the primary PN junction region 31 and the edge termination region 51 passes through the edge of the first P-type layer 42-1 on the edge side of the semiconductor substrate 1.

[0163] Here, P(1) > P(n+1) is satisfied, where P(1) and P(n+1) are the surface concentrations of the first P layer 42-1 and the (n+1)th P layer 42-(n+1), respectively. Furthermore, D(1) < D(n+1) is satisfied, where D(1) and D(n+1) are distances to the bottom of the first P layer 42-1 and the (n+1)th P layer 42-(n+1), respectively.

[0164] In the above-described configuration of the present embodiment, the outer (n+1)th P-layer 42-(n+1), which has a strain among the P-layers 42 (PFS layer), has a relatively low curvature in its cross-sectional shape. Accordingly, the strong application of high electric fields to local portions can be suppressed.

[0165] The impurity concentrations in the P-layers 42 (PFS layer) are designed to satisfy P(1) > P(n+1), gradually increasing as the P-layers 42 are closer to the cell (to the active region 11). Thus, the presence of the (n+1)th P-layer 42-(n+1) prevents the depletion layer from expanding in the transverse direction and reaching the first P-layer 42-1. As a result, a difference in electrostatic potential between the inside and outside of a high-curvature portion in the cross-sectional shape of the first P-layer 42-1 becomes substantially zero. Thus, it is possible to suppress the application of a high electric field to this portion of the (n+1)th P-layer 42-(n+1).

[0166] As described above, the semiconductor device according to the present embodiment can suppress the strong application of high electric fields to local portions. In other words, high electric fields are dispersed, and this increases the maximum withstand voltage. Furthermore, a continuous change in the electric field in the plurality of P-layers 42, as in Embodiment 1, can reduce the edge termination width Le when the withstand voltage is constant. Accordingly, the chip area can be reduced.

[0167] It is noted that the design tolerance range of the (n+1)th P-layer 42-(n+1) is determined based on the edge termination width Le and the withstand voltage required for the device. Thus, as in Embodiment 1, the distance D(n+1) to the bottom of the (n+1)th P-layer 42-(n+1) is set to a value in the range of 15 to 30 μm ( Fig. 5 and Fig. 6) and the surface concentration P(n+1) of the (n+1)-th P-layer 42-(n+1) is set to a value which is 10 to 1000 times the impurity concentration of the semiconductor substrate 1 ( Fig. 7). The number, widths, and pitches of the first to n-th P-layers 42-1 to 42-n are determined based on a device withstand voltage limit and an optimized electric field distribution in each withstand voltage mode.

[0168] As described above, the semiconductor device according to the present embodiment is configured such that the impurity concentrations in the P-type layers 42 increase as the P-type layers 42 are closer to the active region 11, the surface concentration P(n+1) of the (n+1)th P-type layer 42-(n+1) is 10 to 1000 times the impurity concentration of the semiconductor substrate 1, and the distance D(n+1) to the bottom of the (n+1)th P-type layer 42-(n+1) is in the range of 15 to 30 μm. Accordingly, it is possible to reduce the chip area and improve the withstand voltage characteristic and the turn-off interruption capability without deteriorating the characteristics of the IGBT 14. Amendment 1 of Embodiment 5

[0169] Fig. 36 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 1 of Embodiment 5. Note that the present modification corresponds to Modification 1 of Embodiment 1.

[0170] More specifically, the bottom P-layer 25 is formed on the bottom N-layer 24 in a predetermined region including a region within the active region 11, except for a region of the edge termination region 51 on the edge side of the semiconductor substrate 1. In addition, the configuration is such that the edge of the bottom P-layer 25 is between the Fig. 12 and Fig. 13. The collector electrode 26 is formed in a region different from the formation region of the bottom P layer on the bottom N layer 24 (directly short-circuited to the bottom N layer 24) and is formed in the formation region of the bottom P layer on the bottom P layer 25.

[0171] The semiconductor device according to the present modification can, as in Modification 1 of Embodiment 1, improve the interruption capability of the IGBT 14 during turn-off and suppress an increase in the forward voltage without having an adverse effect on the on-state of the IGBT 14. It is noted that the predetermined region in which the bottom P-layer 25 is formed (ie, the formation region of the bottom P-layer) is not limited to the region shown in Fig. 36 is limited and the area shown in Fig. 9 to 11. Even in this case, similar effects to those described above can be achieved. Amendment 2 of Embodiment 5

[0172] Fig. 37 is a cross-sectional view of a semiconductor device according to Modification 2 of Embodiment 5. Note that the present modification corresponds to Modification 2 of Embodiment 1.

[0173] More specifically, the configuration in the present modification is such that the distance R from the bottom of the semiconductor substrate 1 to the peak (first peak) of the impurity concentration of the bottom N-layer 24 satisfies the inequality described in Modification 2 of Embodiment 1, where ΔR is the distance between the peak and a position corresponding to one standard deviation of the impurity concentration of the bottom N-layer 24 in the range from the bottom of the semiconductor substrate 1 to the peak, N0 is the impurity concentration of the bottom N-layer 24 at the bottom of the semiconductor substrate 1, and N b an impurity concentration at the tip in the bottom N-layer 24.

[0174] Since the position of the peak of the impurity concentration of the bottom N-type layer 24 in the semiconductor device according to the present modification is deep from the bottom of the semiconductor substrate 1, the impurity concentration of the bottom N-type layer 24 on the collector electrode 26 side is reduced, as in Modification 2 of Embodiment 1. This reduces the influence of the ohmic contact formed by the bottom N-type layer 24 and the collector electrode 26 in the edge termination region 51. As a result, as in Modification 2 of Embodiment 1, it is possible to improve the blocking voltage withstand capability of the IGBT 14 and reduce the leakage current in the reverse withstand voltage mode. Amendment 3 of Embodiment 5

[0175] Fig. 38 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 3 of Embodiment 5. Note that the present modification corresponds to Modification 3 of Embodiment 1.

[0176] Specifically, in the present modification, the collector electrode 26 is formed in the bottom P layer formation region on the bottom P layer 25 without being formed on the bottom N layer 24. Accordingly, as in Modification 3 of Embodiment 1, no ohmic contact is formed by the bottom N layer 24 and the collector electrode 26 in the edge termination region 51. Thus, it is possible to improve the reverse withstand voltage of the IGBT 14 and reduce the leakage current in the reverse withstand voltage mode. Amendment 4 of Embodiment 5

[0177] Fig. 39 is a cross-sectional view showing a configuration of a semiconductor device according to Modification 4 of Embodiment 5. Note that the present modification corresponds to Modification 4 of Embodiment 1.

[0178] More specifically, the low-concentration P layer 27 having a lower impurity concentration than the bottom-side P layer 25 in the present modification is formed in a region different from the formation region of the bottom-side P layer on the bottom-side N layer 24. Note that a peak of the impurity concentration of the low-concentration P layer 27 is higher than the impurity concentration of the semiconductor substrate 1 and lower than the peak of the impurity concentration of the bottom-side N layer 25. The collector electrode 26 is formed in the region different from the formation region of the bottom-side P layer on the low-concentration P layer 27 and is formed in the formation region of the bottom-side P layer on the bottom-side P layer 25.

[0179] The semiconductor device according to the present modification can improve the blocking voltage capability of the IGBT 14, as in Modification 4 of Embodiment 1, thereby suppressing the leakage current in the reverse withstand voltage mode. Furthermore, as in Modification 4 of Embodiment 1, it can further suppress deterioration of the current interruption capability when the IGBT 14 performs a turn-off operation. Evaluation of semiconductor devices in accordance with embodiments 1 to 5Edge termination width

[0180] Fig. Fig. 40 is a diagram showing the effect of reducing the area of ​​the edge termination region 51, that is, the effect of reducing the edge termination width Le, in the semiconductor device according to Embodiment 1 ( Fig. 1). Here, for all withstand voltage classes (600, ..., 6500 W), it is assumed that the dielectric strength BV CESwhich is 1.3 times the withstand voltage class. A scale on the vertical axis in Fig. 40 indicates a normalized value for the edge termination width Le of the semiconductor device according to Embodiment 1, using the edge termination width Le of the relevant semiconductor device as a reference.

[0181] As from Fig. As can be seen from Figure 40, the semiconductor device according to Embodiment 1 can reduce the edge termination width Le for each withstand voltage class to a value approximately 50% of that of the relevant semiconductor device. In other words, the semiconductor device according to Embodiment 1 can have the same withstand voltage with a smaller edge termination width Le. One conceivable reason for this is that, among the plurality of P-type layers 38 (PFS layers), the outer P-type layers 38 have a relatively low curvature of the cross-sectional shape, which suppresses strong application of high electric fields to local portions.Although there are slight differences in degree, it is noted that the semiconductor devices according to Embodiments 2 to 5 in which the P layers are arranged in the longitudinal direction can also reduce the edge termination widths Le to a smaller value than that of the relevant semiconductor device. Leakage current and dielectric strength in withstand voltage mode

[0182] Fig. 41 is a diagram of an evaluation circuit used in experiments for evaluating the withstand voltage characteristics of the relevant semiconductor device and the semiconductor device in accordance with Embodiment 1 ( Fig. 1). Here, an IGBT device with a withstand voltage of 4500 V was used and the various evaluation conditions included a gate-emitter voltage V GEof 0 V, a transition temperature Tj of 398 K, a DC operating mode and a variable voltage V CC (ie collector-emitter voltage V CE ). In addition, as in the semiconductor device according to Embodiment 1, a semiconductor device having an edge termination width Le approximately 50% of that of the relevant semiconductor device was used.

[0183] Fig. 42 is a diagram showing waveforms for evaluating the withstand voltage and leakage current characteristics of the relevant semiconductor device and the semiconductor device according to Embodiment 1 under the conditions described above. As shown in Fig. 42, the semiconductor device according to Embodiment 1 can reduce the leakage current J CES (which in Fig. 42 is indicated by the solid line) for the voltage V CCfrom 4500 V to a value that is approximately 90 % of the leakage current J CES (in Fig. 42 (indicated by the dashed line) of the relevant semiconductor device for the same voltage. In other words, a reduced surface electric field in the edge termination region 51 can reduce the drift current caused by a high electric field. Furthermore, suppressed local impact ionization can reduce the possibility of device breakdown caused as a result of exceeding a critical electric field.

[0184] Fig. Figure 43 is a diagram showing electric field strengths (lower graphs) and electrostatic potentials (upper graphs) at a constant withstand voltage (V CE= 4500 V) at horizontal positions along the surface of the semiconductor substrate 1 in the relevant semiconductor device and in the semiconductor device according to Embodiment 1. It is noted that the Fig. 43 and the Fig. 44 to 46, which will be described later, were obtained by simulation.

[0185] A scale on the left vertical axis in Fig. 43 indicates the electric field strength at the surface of the semiconductor substrate 1 and a scale on the right vertical axis in Fig. 43 indicates the electrostatic potential at the surface of the semiconductor substrate 1. The horizontal axis in Fig. 43 corresponds to line xx' in Fig. 57 and line XX' in Fig. 1, Fig. 0 on the scale indicates the position of the edge of the gate electrode 18 on the edge side of the semiconductor substrate 1 and 1 on the scale indicates the position of the edge of the semiconductor substrate 1.

[0186] As in Fig. 43, the semiconductor device according to Embodiment 1 can have substantially the same electrostatic potential (in Fig. 43 indicated by the upper solid line) as the relevant semiconductor device (in Fig. 43 by the upper dashed line) and can also have its maximum electric field strength (a peak of the lower solid line in Fig. 43) to a value that is at least 40% smaller than that of the relevant semiconductor device (one peak of the lower dashed line in Fig. 43).

[0187] Fig. Figure 44 is a diagram showing electric field strengths (lower graphs) and impurity concentrations (upper graphs) at a constant voltage (V CE = 4500 V) at horizontal positions along the surface of the semiconductor substrate 1 in the relevant semiconductor device and in the semiconductor device according to Embodiment 1. A scale on the left vertical axis in Fig. 44 indicates the electric field strength and a scale on the right vertical axis in Fig. 44 indicates a normalized value for the impurity concentration, using the impurity concentration of the semiconductor substrate 1 as a reference. The horizontal axis in Fig. 44 is the same as the one in Fig. 43.

[0188] As indicated by the dotted line in Fig. 44, the relevant semiconductor device has a depletion layer extending to the P-layer 33 closest to the gate electrode 18. As indicated by the solid line and the dashed line in Fig. In contrast, as shown in FIG. 44, the depletion layer of the semiconductor device according to Embodiment 1 does not extend to the first P-type layer 38-1. Accordingly, the semiconductor device according to Embodiment 1 can suppress strong application of high electric fields to local portions.

[0189] Fig. Figure 45 is a diagram showing electric field strengths (the lower graphs) and impurity concentrations (the upper graphs) at a constant voltage (V CE= 4500 V) at longitudinal positions in the semiconductor substrates 1 of the relevant semiconductor device and the semiconductor device in accordance with Embodiment 1. A scale on the left vertical axis in Fig. 45 indicates the electric field strength and a scale on the right vertical axis in Fig. 45 indicates a normalized value for the impurity concentration, using the impurity concentration of the semiconductor substrate 1 as a reference. The horizontal axis in Fig. 45 corresponds to the line yy' in Fig. 57 and line YY' in Fig. 1, Fig. 0 indicates the position of the surface of the semiconductor substrate 1 on the axis.

[0190] Fig. Figure 46 is a diagram showing electric field strengths (the lower graphs) and electrostatic potentials (the upper graphs) at a constant voltage (V CE= 4500 V) at longitudinal positions of the semiconductor substrates 1 of the relevant semiconductor device and the semiconductor device in accordance with Embodiment 1. A scale on the left vertical axis in Fig. 46 indicates the electric field strength and a scale on the right vertical axis in Fig. 46 indicates the electrostatic potential. The horizontal axis in Fig. 46 is the same as in Fig. 45. As in Fig. 46, the semiconductor device according to Embodiment 1 can have substantially the same electrostatic potential (in Fig. 46 indicated by the upper solid line) as the relevant semiconductor device (in Fig. 46 by the upper dashed line) and can also have its maximum electric field strength (a peak of the lower solid line in Fig. 46) to a value that is at least 40% smaller than that of the relevant semiconductor device (one peak of the lower dashed line in Fig. 46). Switch-off behavior

[0191] Fig. 47 is a diagram of an evaluation circuit used in experiments for evaluating the turn-off characteristics of the relevant semiconductor device and the semiconductor device in accordance with Embodiment 1 ( Fig. 1). Here, an IGBT with a withstand voltage of 4500 V was used, and various evaluation conditions were as follows: Vcc = 2800 V, leakage inductance Ls = 2.47 µH, Tj = 398 K and J C = 56 A / cm 2 . Furthermore, as the semiconductor device according to Embodiment 1, a semiconductor device having an edge termination width Le approximately 50% of that of the relevant semiconductor device was used.

[0192] Fig. Figure 48 is a graph showing results of evaluation of the turn-off characteristic of the relevant semiconductor device (in Fig. 48 indicated by the dashed line) and the turn-off characteristic of the semiconductor device in accordance with Embodiment 1 (in Fig. 48 by the solid line) under the conditions described above. As shown in Fig. 48, the turn-off loss of the semiconductor device according to Embodiment 1 and that of the relevant semiconductor device are substantially constant.

[0193] As shown by the Fig. 48, the semiconductor device according to Embodiment 1 can further suppress the peak voltage at the time of reducing the current to a greater extent than the relevant semiconductor device, and as shown by a portion enclosed in Fig. 48 is indicated by a section enclosed by the dash-dot-dot line, it can suppress oscillations of the voltage and current after turn-off more than the relevant semiconductor device. The reason for this is considered to be that, as a result, it becomes possible to suppress the peak voltage and oscillations caused by the leakage inductance Ls, that holes in the P-type layer 38 with a large distance D from the bottom end accumulate in the edge termination region 51, and that a hole current is supplied at the time of current reduction, so that the rate of change of the current is reduced. Switch-off capability

[0194] Using the evaluation circuit diagram described above, which is shown in Fig. 47, the turn-off characteristics of the relevant semiconductor device ( Fig. 57), the semiconductor device in accordance with Embodiment 1 ( Fig. 1), the semiconductor device in accordance with Amendment 1 of Embodiment 1 ( Fig. 9), the semiconductor device in accordance with Embodiment 5 ( Fig. 35) and the semiconductor device in accordance with Amendment 1 of Embodiment 5 ( Fig. 36). Here, an IGBT device with a withstand voltage of 4500 V was used and various evaluation conditions were used as follows: Vcc = 3400 V, Ls = 2.47 µH and Tj = 423 K. The current density J C was starting from 56 A / cm 3 by 0.5 A / cm 2 incremented and the evaluation is carried out until the breakdown of the semiconductor devices. It is noted that the maximum current density J C (break), at which any semiconductor device can be turned off without breakdown, was used as an index indicating the interruption capability when turned off.

[0195] Fig. 49 is a diagram showing the interrupt capability J C (break) of the relevant semiconductor device and the semiconductor devices according to Embodiment 1, etc., when turned off under the conditions described above. The break capabilities of the semiconductor devices according to Embodiment 1, with Modification 1 of Embodiment 1, with Embodiment 5, and with Modification 1 of Embodiment 5 when turned off are normalized here using the break capability of the relevant semiconductor device when turned off as a reference.

[0196] Since the impact ionization is suppressed by the effect of mitigating the surface electric field, the structure of the semiconductor device in accordance with Embodiment 1 ( Fig. 1) have improved turn-off interruption capability compared to the relevant semiconductor device. Since impact ionization is suppressed not only by the effect of mitigating the surface electric field but also by the effect of suppressing carrier accumulation in the edge termination region 51 during turn-off, and since the application of a high electric field caused by high-concentration carriers in the primary PN junction region 31 is suppressed, the structure of the semiconductor device in accordance with Modification 1 of Embodiment 1 ( Fig. 9) have an even more improved interruption capability when switching off.

[0197] Fig. 50 is a diagram showing the dependence of the interruption capabilities of the relevant semiconductor device ( Fig. 57) and the semiconductor device in accordance with Embodiment 1 ( Fig. 1) when switching off the concentration of impurities in the bottom P-layer 25. A scale on the horizontal axis in Fig. 50 indicates a normalized impurity concentration of the bottom P layer 25, the dashed line indicates a graph for the relevant semiconductor device, and the solid line indicates a graph for the semiconductor device according to Embodiment 1.

[0198] As in Fig. As shown in Figure 50, the impurity concentration in the bottom P-layer 25 is one of the device parameters used to control the forward voltage of the IGBT 14, and the turn-off interruption capability of the IGBT 14 also depends on the impurity concentration in the bottom P-layer 25. Even if there are some changes in the impurity concentration in the bottom P-layer 25, the semiconductor device according to Embodiment 1 can maintain a higher turn-off interruption capability than the relevant semiconductor device. Although this is Fig. 50 is not shown, it is noted that the semiconductor devices according to Embodiments 2 to 5 can also maintain a higher interruption capability at power-off than the relevant semiconductor device.

[0199] Fig. 51 is a diagram showing safe operating ranges of the relevant semiconductor device and the semiconductor device in accordance with Embodiment 1 ( Fig. 1) when turned off. The dashed line indicates a graph for the relevant semiconductor device, and the solid line indicates a graph for the semiconductor device according to Embodiment 1.

[0200] As in Fig. 51, the semiconductor device according to Embodiment 1 can have a larger safe operating range when turning off the IGBT 14 than the relevant semiconductor device. Although this is Fig. 51 is not shown, it is noted that the semiconductor devices according to Embodiments 2 to 5 may similarly have a larger safe operating range when turning off the IGBT 14 than the relevant semiconductor device.

[0201] Accordingly, the semiconductor devices according to Embodiments 1 to 5 can improve the interruption capability of the IGBT 14 when turning off and increase the safe operating range, thus increasing the withstand voltage of the IGBT 14. Leakage current in reverse withstand voltage mode

[0202] Fig. Fig. 52 is a circuit diagram of an evaluation circuit used in experiments for evaluating the reverse withstand voltage characteristics of modifications 1 to 4 of embodiment 1 ( Fig. 9, Fig. 10, Fig. 11 and Fig. 15). An IGBT device with a withstand voltage of 4500 V was used.

[0203] Fig. 53 is a diagram showing waveforms for evaluating the reverse withstand voltage and leakage current characteristics of the semiconductor devices in accordance with modifications 1 to 4 of embodiment 1. As shown in Fig. As shown in Fig. 53, the reverse withstand voltage and leakage current of the semiconductor devices in accordance with Amendments 2 to 4 (indicated by the solid line) can be reduced to a value that is 10% or less than the reverse withstand voltage of the semiconductor device in accordance with Amendment 1 (indicated by the dashed line) when the voltage V CE -60 V. One possible reason for this is that in the semiconductor device in accordance with Amendment 4 ( Fig. 15) no ohmic contact is formed by the bottom N-type layer 24 and the collector electrode 26, and a low-concentration withstand voltage (reverse withstand voltage) is maintained in the junction between the bottom N-type layer 24 and the P-type layer 27 when the IGBT 14 is in the reverse withstand voltage mode. Another conceivable reason is that since the action of a forward bias diode formed between the P+ layer 21 on the surface side of the semiconductor substrate 1 and the bottom N-type layer 24 is suppressed when the IGBT 14 is in the reverse withstand voltage mode, it is possible to increase the blocking voltage capability of the IGBT 14 and suppress the leakage current in the reverse withstand voltage mode. Other changes

[0204] Above, a case is described in which the semiconductor element formed in the active region 11 includes the IGBT 14. However, it is noted that the semiconductor element is not limited to including the IGBT 14, and that the semiconductor element as described in part (a) of Fig. 54, a diode 28 or, as shown in part (b) of Fig. 54, may include an IGBT 29 having a flat gate structure as an emitter structure of the active region 11. These configurations are expected to achieve similar effects to those described above. Description of reference symbols 1 semiconductor substrate 11 active area 14, 29 IGBT 18 Gate electrode 24 sub-side N layer 25 Underside P layer 26 Collector electrode 27 Low concentration P layer 28 diodes 38, 39, 40, 41, 22 P-layer 51 Border closure area

Claims

[1] Semiconductor device comprising: a semiconductor substrate (1) of a first conductivity type in which an active region (11) and an edge termination region (51) spaced from and enclosing the active region are defined; a semiconductor element (14) formed in the active region; and a plurality of impurity layers (38-1, 38-2, 38-3, 38-4) of a second conductivity type, which are formed at least partially overlapping in a region extending from an edge portion of the active region to the edge termination region in a surface of the semiconductor substrate, wherein for any pair of adjacent i-th and i+1-th impurity layers among the plurality of impurity layers, P(i) > P(i+1), D(i) < D(i+1), and B(i) < B(i+1) are satisfied, where P(i) and P(i+1) are surface concentrations, respectively, the concentrations of impurities of the second conductivity type in the i-th impurity layer and in the i+1-th impurity layer at the surface of the semiconductor substrate, D(i) and D(i+1) are bottom-end distances, respectively, the distances from the surface of the semiconductor substrate to the bottom ends of the i-th impurity layer and the i+1-th impurity layer, and B(i) and B(i+1) are distances from an edge of the edge termination region on the active region side to edges of the i-th impurity layer and the i+1-th impurity layer on an edge side of the semiconductor substrate, and the surface concentration in an impurity layer (38-4) whose distance to the lower end is the greatest among the distances to the lower end of the plurality of impurity layers is 10 to 1000 times a concentration of the impurities of the first conductivity type in the semiconductor substrate, and the distance to the lower end of the impurity layer (38-4) is in a range of 15 to 30 µm. [2] Semiconductor device comprising: a semiconductor substrate (1) of a first conductivity type in which an active region (11) and an edge termination region (51) spaced from and enclosing the active region are defined; a semiconductor element (14) formed in the active region; first and second impurity layers (39-1, 39-2) of a second conductivity type, which are formed in a partially overlapping manner in a region extending from an edge region of the active region to the edge termination region in a surface of the semiconductor substrate; and a third impurity layer (39-3) of the second conductivity type adjacent to a lower portion of the first impurity layer on the edge termination region side and to a lower portion of the second impurity layer on the active region side, where P(1) > P(2) > P(3), D(1) < D(2) < D(3) and B(1) < B(3) < B(2) are satisfied, where P(1), P(2) and P(3) in this order are surface concentrations, the concentrations of impurities of the second conductivity type in the first, second and third impurity layers on a surface of the semiconductor substrate, D(1), D(2) and D(3) in this order are bottom end distances, the distances from the surface of the semiconductor substrate to the bottom ends of the first to third impurity layers, and B(1), B(2) and B(3) in this order are distances from an edge of the edge termination region on the active region side to the edges of the first to third impurity layers on an edge side of the semiconductor substrate, and the surface concentration P(2) of the second impurity layer (39-2) is 10 to 1000 times a concentration of the impurities of the first conductivity type in the semiconductor substrate and the distance D(3) to the lower end of the third impurity layer (39-3) is in a range of 15 to 30 µm. [3] Semiconductor device comprising: a semiconductor substrate (1) of a first conductivity type in which an active region (11) and an edge termination region (51) spaced from and enclosing the active region are defined; a semiconductor element (14) formed in the active region; a first and a second impurity layer (40-1, 40-2) of a second conductivity type, which are formed at least partially overlapping in a region extending from an edge portion of the active region to the edge termination region in a surface of the semiconductor substrate; a third impurity layer (40-3) of the second conductivity type adjacent to an edge portion of the first impurity layer on the edge termination region side; and a fourth impurity layer (40-4) of the second conductivity type adjacent to an edge portion of the second impurity layer on the edge termination region side, where P(1) > P(3) = P(4) > P(2), D(1) < D(3) = D(4) < D(2) and B(1) < B(3) < B(2) < B(4) are satisfied, where P(1), P(2), P(3), and P(4) in this order are surface concentrations, the concentrations of impurities of the second conductivity type in the first to fourth impurity layers on the surface of the semiconductor substrate, D(1), D(2), D(3), and D(4) in this order are bottom-end distances, the distances from the surface of the semiconductor substrate to the bottom ends of the first to fourth impurity layers, and B(1), B(2), B(3), and B(4) in this order are distances from an edge of the edge termination region on the active region side to the edges of the first to fourth impurity layers on an edge side of the semiconductor substrate, and the surface concentration P(4) of the fourth impurity layer (40-4) is 10 to 1000 times a concentration of impurities of the first conductivity type in the semiconductor substrate, and the distance D(2) to the lower end of the second impurity layer (40-2) is in a range of 15 to 30 µm. [4] Semiconductor device comprising: a semiconductor substrate (1) of a first conductivity type in which an active region (11) and an edge termination region (51) spaced from and enclosing the active region are defined; a semiconductor element (14) formed in the active region; and a first and a second impurity layer (41-1, 41-2) of a second conductivity type, which are formed overlapping at least in a region extending from an edge portion of the active region to the edge termination region in a surface of the semiconductor substrate, wherein a concentration of the impurities of the second conductivity type in the first impurity layer (41-1) in the active region is higher than a concentration of the impurities of the second conductivity type in the first impurity layer in the edge termination region, Pmin(1) > P(2), D(1) < D(2) and B(1) < B(2) are satisfied, where P(2) is a surface concentration, which is a concentration of impurities of the second type in the second impurity layer at the surface of the semiconductor substrate, Pmin(1) is a minimum value for the surface concentration of the first impurity layer, D(1) and D(2) are bottom end distances, which are distances from the surface of the semiconductor substrate to the bottom ends of the first and second impurity layers, and B(1) and B(2) are distances from an edge of the edge termination region on the active region side to the edges of the first and second impurity layers on an edge side of the semiconductor substrate, and the surface concentration P(2) of the second impurity layer (41-2) is 10 to 1000 times a concentration of the impurities of the first conductivity type in the semiconductor substrate and the distance D(2) to the lower end of the second impurity layer (41-2) is in a range of 15 to 30 µm. [5] Semiconductor device comprising: a semiconductor substrate (1) of a first conductivity type in which an active region (11) and an edge termination region (51) spaced from and enclosing the active region are defined; a semiconductor element (14) formed in the active region; a first to n-th impurity layer (42-1 to 42-n) of a second conductivity type arranged in a region extending from an edge portion of the active region to the edge termination region in a direction from the active region to the edge termination region in a surface of the semiconductor substrate, and an n+1-th impurity layer (42-(n+1)) of the second conductivity type adjacent to a lower portion of at least the first impurity layer among the first to n-th impurity layers, wherein the first to n-th impurity layers have the same surface concentration and the same distance to the bottom, wherein the surface concentration is a concentration of impurities of the second conductivity type at the surface of the semiconductor substrate, and the distance to the bottom is a distance from the surface of the semiconductor substrate to the bottom ends of the first to n-th impurity layers, P(1) > P(n+1) and D(1) < D(n+1) are satisfied, where P(1) and P(n+1) are the surface concentrations of the first and n+1-th impurity layers, respectively, and D(1) and D(n+1) are the distances to the bottom of the first and n+1-th impurity layers, respectively, and the surface concentration P(n+1) of the n+1-th impurity layer (42-(n+1)) is 10 to 1000 times a concentration of the impurities of the first conductivity type in the semiconductor substrate, and the distance D(n+1) to the lower end of the n+1-th impurity layer is in a range of 15 to 30 µm. [6] A semiconductor device according to claim 1, further comprising: a first bottom impurity layer of the first conductivity type formed on a bottom surface of the semiconductor substrate; a second bottom impurity layer of the second conductivity type formed on the first bottom impurity layer in a predetermined region including a region of the active region, except in a region of the edge termination region on the edge side of the semiconductor substrate; and an electrode formed in a region different from the predetermined region on the first bottom impurity layer and formed in the predetermined region on the second bottom impurity layer. [7] A semiconductor device according to claim 1, further comprising: a first bottom impurity layer of the first conductivity type formed on a bottom surface of the semiconductor substrate; a second bottom impurity layer of the second conductivity type formed on the first bottom impurity layer in a predetermined region including a region of the active region, except in a region of the edge termination region on the edge side of the semiconductor substrate; and an electrode formed in the predetermined region on the second bottom impurity layer without being formed on the first bottom impurity layer. [8] A semiconductor device according to claim 1, further comprising: a first bottom impurity layer of the first conductivity type formed on a bottom surface of the semiconductor substrate; a second bottom impurity layer of the second conductivity type formed on the first bottom impurity layer in a predetermined region including a region of the active region except in a region of the edge termination region on the edge side of the semiconductor substrate; a third bottom impurity layer of the second conductivity type formed in a region different from the predetermined region on the first bottom impurity layer and having a lower impurity concentration than the second bottom impurity layer; and an electrode formed in a region different from the predetermined region on the third bottom impurity layer and formed in the predetermined region on the second bottom impurity layer. [9] A semiconductor device according to claim 2, further comprising: a first bottom impurity layer of the first conductivity type formed on a bottom surface of the semiconductor substrate; a second bottom impurity layer of the second conductivity type formed on the first bottom impurity layer in a predetermined region including a region of the active region, except in a region of the edge termination region on the edge side of the semiconductor substrate; and an electrode formed in a region different from the predetermined region on the first bottom impurity layer and formed in the predetermined region on the second bottom impurity layer. [10] A semiconductor device according to claim 2, further comprising: a first bottom impurity layer of the first conductivity type formed on a bottom surface of the semiconductor substrate; a second bottom impurity layer of the second conductivity type formed on the first bottom impurity layer in a predetermined region including a region of the active region, except in a region of the edge termination region on the edge side of the semiconductor substrate; and an electrode formed in the predetermined region on the second bottom impurity layer without being formed on the first bottom impurity layer. [11] A semiconductor device according to claim 2, further comprising: a first bottom impurity layer of the first conductivity type formed on a bottom surface of the semiconductor substrate; a second bottom impurity layer of the second conductivity type formed on the first bottom impurity layer in a predetermined region including a region of the active region except in a region of the edge termination region on the edge side of the semiconductor substrate; a third bottom impurity layer of the second conductivity type formed in a region different from the predetermined region on the first bottom impurity layer and having a lower impurity concentration than the second bottom impurity layer; and an electrode formed in a region different from the predetermined region on the third bottom impurity layer and formed in the predetermined region on the second bottom impurity layer. [12] A semiconductor device according to claim 3, further comprising: a first bottom impurity layer of the first conductivity type formed on a bottom surface of the semiconductor substrate; a second bottom impurity layer of the second conductivity type formed on the first bottom impurity layer in a predetermined region including a region of the active region, except in a region of the edge termination region on the edge side of the semiconductor substrate; and an electrode formed in a region different from the predetermined region on the first bottom impurity layer and formed in the predetermined region on the second bottom impurity layer. [13] A semiconductor device according to claim 3, further comprising: a first bottom impurity layer of the first conductivity type formed on a bottom surface of the semiconductor substrate; a second bottom impurity layer of the second conductivity type formed on the first bottom impurity layer in a predetermined region including a region of the active region, except in a region of the edge termination region on the edge side of the semiconductor substrate; and an electrode formed in the predetermined region on the second bottom impurity layer without being formed on the first bottom impurity layer. [14] A semiconductor device according to claim 3, further comprising: a first bottom impurity layer of the first conductivity type formed on a bottom surface of the semiconductor substrate; a second bottom impurity layer of the second conductivity type formed on the first bottom impurity layer in a predetermined region including a region of the active region except in a region of the edge termination region on the edge side of the semiconductor substrate; a third bottom impurity layer of the second conductivity type formed in a region different from the predetermined region on the first bottom impurity layer and having a lower impurity concentration than the second bottom impurity layer; and an electrode formed in a region different from the predetermined region on the third bottom impurity layer and formed in the predetermined region on the second bottom impurity layer. [15] A semiconductor device according to claim 4, further comprising: a first bottom impurity layer of the first conductivity type formed on a bottom surface of the semiconductor substrate; a second bottom impurity layer of the second conductivity type formed on the first bottom impurity layer in a predetermined region including a region of the active region, except in a region of the edge termination region on the edge side of the semiconductor substrate; and an electrode formed in a region different from the predetermined region on the first bottom impurity layer and formed in the predetermined region on the second bottom impurity layer. [16] A semiconductor device according to claim 4, further comprising: a first bottom impurity layer of the first conductivity type formed on a bottom surface of the semiconductor substrate; a second bottom impurity layer of the second conductivity type formed on the first bottom impurity layer in a predetermined region including a region of the active region, except in a region of the edge termination region on the edge side of the semiconductor substrate; and an electrode formed in the predetermined region on the second bottom impurity layer without being formed on the first bottom impurity layer. [17] A semiconductor device according to claim 4, further comprising: a first bottom impurity layer of the first conductivity type formed on a bottom surface of the semiconductor substrate; a second bottom impurity layer of the second conductivity type formed on the first bottom impurity layer in a predetermined region including a region of the active region except in a region of the edge termination region on the edge side of the semiconductor substrate; a third bottom impurity layer of the second conductivity type formed in a region different from the predetermined region on the first bottom impurity layer and having a lower impurity concentration than the second bottom impurity layer; and an electrode formed in a region different from the predetermined region on the third bottom impurity layer and formed in the predetermined region on the second impurity layer. [18] A semiconductor device according to claim 5, further comprising: a first bottom impurity layer of the first conductivity type formed on a bottom surface of the semiconductor substrate; a second bottom impurity layer of the second conductivity type formed on the first bottom impurity layer in a predetermined region including a region of the active region, except in a region of the edge termination region on the edge side of the semiconductor substrate; and an electrode formed in a region different from the predetermined region on the first bottom impurity layer and formed on the second bottom impurity layer in the predetermined region. [19] A semiconductor device according to claim 5, further comprising: a first bottom impurity layer of the first conductivity type formed on a bottom surface of the semiconductor substrate; a second bottom impurity layer of the second conductivity type formed on the first bottom impurity layer in a predetermined region including a region of the active region, except in a region of the edge termination region on the edge side of the semiconductor substrate; and an electrode formed in the predetermined region on the second bottom impurity layer without being formed on the first bottom impurity layer. [20] A semiconductor device according to claim 5, further comprising: a first bottom impurity layer of the first conductivity type formed on a bottom surface of the semiconductor substrate; a second bottom impurity layer of the second conductivity type formed on the first bottom impurity layer in a predetermined region including a region of the active region except in a region of the edge termination region on the edge side of the semiconductor substrate; a third bottom impurity layer of the second conductivity type formed in a region different from the predetermined region on the first bottom impurity layer and having a lower impurity concentration than the second bottom impurity layer; and an electrode formed in a region different from the predetermined region on the third bottom impurity layer and formed on the second bottom impurity layer in the predetermined region. [21] A semiconductor device according to any one of claims 6, 9, 12, 15 and 18, wherein the semiconductor element includes a gate electrode formed in a trench of the semiconductor substrate, and an edge of the second bottom impurity layer is positioned between a location of an edge of the gate electrode on the edge termination region side and a location remote from an edge of the edge termination region on the active region side in such a way as to be closer to the edge of the semiconductor substrate by a quarter of a distance across the edge termination region. [22] A semiconductor device according to any one of claims 8, 11, 14, 17 and 20, wherein a second peak of an impurity concentration of the third bottom impurity layer is higher than the impurity concentration of the semiconductor substrate and is lower than a third peak of an impurity concentration of the first bottom impurity layer. [23] A semiconductor device according to claim 6 to 20, wherein a distance R from the bottom side of the semiconductor substrate to a first peak of an impurity concentration of the first bottom side impurity layer satisfies the following: R>2⋅ΔR⋅InNbN0 where ΔR is a distance between the first peak and a position corresponding to a standard deviation of the impurity concentration of the first bottom impurity layer in a region from the back surface of the semiconductor substrate to the first peak, N0 is an impurity concentration of the first bottom impurity layer at the bottom of the semiconductor substrate, and N ban impurity concentration at the first peak in the first bottom impurity layer.

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