Stacks of magnetic inductors with multilayer insulating layers

Abstract

Inductor structure (100) which features: a laminated thin-film stack comprising alternating layers of a magnetic material (112) and a multilayer insulating material, wherein the multilayer insulating material is located between adjacent layers (112) of the magnetic material and has a first insulating layer (114A) that abuts at least one additional insulating layer (14B), and wherein the first insulating layer (114A) and the at least one additional insulating layer (114B) have different dielectric materials, wherein the first insulating layer (114A) comprises silicon dioxide and the insulating layer adjacent to at least one additional layer comprises an insulating silicon nitride layer.

Description

BACKGROUND

[0001] The present invention relates to magnetic units on a chip and in particular to magnetic structures on a chip and to methods for minimizing magnetic losses in magnetic inductors.

[0002] Stacks of magnetic inductors on a chip are significant passive elements with applications in areas such as on-chip power converters and integrated RF (radio frequency) circuits. To achieve the high energy storage required for power management, on-chip inductors typically require relatively thick magnetic yoke materials (e.g., several micrometers or more).

[0003] Stacks of magnetic inductors generally consist of alternating layers of a magnetic material and a dielectric material. The dielectric material helps to prevent eddy current losses. The dielectric material used in magnetic inductor stacks is generally deposited at low temperatures to avoid compromising the magnetic properties of the magnetic material. In the past, low-temperature oxides and nitrides have been used; however, these are prone to pores that can allow electrical contact between adjacent layers of the magnetic material and unwanted eddy currents, leading to magnetic loss. These pores are particularly problematic for high-throughput, low-temperature dielectric processes.

[0004] Several concepts have already been presented in this technical context. Document US 2015 / 0048918A1 describes a coil unit for a thin-film inductor with an insulator consisting of two layers.

[0005] Document JP H-09 63 844 A describes a laminated magnetic thin film used for a thin-film inductor. The document by Wand et al., "Integrated on-chip inductors with electroplated magnetic yokes," from J. of Appl. Phys., 111.07e732 (2012), describes ferromagnetic thin-film inductors for integrated power management in semiconductor chips. Finally, document US 2001 / 0050607 A1 describes an integrated transformer in which a first conductor and a second conductor have grooves within an integrated unit. SUMMARY

[0006] Exemplary embodiments of the concept presented here are described by the independent claims. Further embodiments are described by the respective dependent claims.

[0007] Additional features and advantages are implemented through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered part of the claimed invention. For a better understanding of the invention, its advantages and features, reference is made to the further description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The subject matter, which is considered to be the invention, is precisely set out and expressly claimed in the claims at the end of the description.

[0009] The above and other features and advantages of the invention will become apparent from the following detailed description in conjunction with the accompanying drawings, in which: Fig. Figure 1 (“FIG”) of the prior art illustrates a cross-section of an inductor structure; Fig. 2 illustrates a cross-section of an inductor structure with multilayer insulating layers according to the present invention; and Fig. 3 a process flow for forming an inductor structure according to one or more embodiments of the present invention. DETAILED DESCRIPTION

[0010] The present invention addresses prior art problems by providing a method and a magnetic inductor structure in one or more embodiments that eliminate problems resulting from porosity in the dielectric layer, while simultaneously exhibiting low temperature and high throughput. The method and structure eliminate the effects of porosity by means of a multilayer insulation scheme. In one or more embodiments, the multilayer insulation scheme is implemented by depositing two or more layers of different dielectric materials between adjacent magnetic layers in the laminate structure of the magnetic inductors. Although each deposited dielectric layer may contain pores, it has been found that the pores between layers are not continuous.For example, the multilayer insulation scheme can involve depositing a first layer of silicon dioxide, followed by a layer of silicon nitride, followed by another layer of silicon dioxide. In other examples, a stack of silicon nitride / silicon dioxide / silicon nitride can be deposited. Furthermore, the stack can be fabricated using more than two different types of dielectric materials. By employing the multilayer insulation scheme, the multilayer dielectric can exhibit an overall reduced thin-film thickness compared to a single-layer dielectric, while simultaneously addressing porosity-related issues. Additionally, the thinner thin film provides a lower aspect ratio for easier subsequent processing.

[0011] Fig. Figure 1 of the prior art illustrates a known magnetic inductor structure 10, which demonstrates one of the problems associated with the low-temperature deposition of dielectric materials. Low-temperature deposition means that the temperatures used to deposit the dielectric material within the magnetic inductor structure are generally temperatures that do not impair the magnetic properties associated with the magnetic layers, which generally means less than 300 °C, although the specific temperature generally depends on the deposition process. The exemplary magnetic inductor structure 10 includes a substrate 16 on which the inductor structure is formed. The substrate 16 can be a machined wafer.A “processed wafer” is defined herein as a wafer that has undergone front-end-of-line (FEOL) processing, middle-of-the-line (MOL) processing and back-end-of-the-line (BEOL) processing of the semiconductor, forming various desired units and circuits.

[0012] Typical FEOL processes include wafer preparation, insulation, well formation, gate structuring, spacer placement, expansion and source / drain implantation, silicide formation, and the formation of a double strain layer. MOL primarily involves the formation of gate and source-drain contacts, which is an increasingly challenging part of the overall manufacturing process, particularly in lithographic structuring. State-of-the-art semiconductor chips, the so-called 14 nm node of complementary metal-oxide-semiconductor (CMOS) chips, feature a second-generation three-dimensional (3D) FinFET, a metal-to-one pitch of approximately 55 nm, and copper (Cu) / low-k and air-gap interconnects in mass production.At BEOL, the Cu / Low-k compounds are primarily manufactured using a dual Damascus process with the aid of interlayer dielectrics (ILDs) deposited by plasma-enhanced CVD (PECVD), PVD-Cu barriers and electrochemically clad Cu wire materials.

[0013] On the substrate 16, alternating layers of a dielectric material 14 and a magnetic material 12 are arranged, with the total thickness of the magnetic material ranging from more than 1 micrometer to several micrometers. As discussed above, one of the problems with current low-temperature deposition processes of dielectric materials used in the formation of stacks of magnetic inductor thin films involves the formation of pores, which are randomly formed during the deposition of the dielectric material layers. The pores can extend from a bottom surface to an top surface of the dielectric layer or partially through it, adversely leading to undesired electrical connections between adjacent magnetic layers and to eddy currents that cause magnetic loss.

[0014] Low-temperature deposition processes vary and generally include physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), thermal oxidation, or any combination thereof. The temperatures of these various deposition processes also vary depending on the specific process. In one or more embodiments, the dielectric deposition process involves PECVD at temperatures below 300 °C.

[0015] In one or more other embodiments, the second dielectric layer (and / or any additional dielectric layer) is formed from a different material (e.g. silicon nitride) compared to the first dielectric layer (e.g. silicon dioxide), while the deposition technique 114 n=1The same. In one or more other unclaimed embodiments, the second layer (and / or each additional dielectric layer) can be the same material as the first material (e.g., silicon dioxide), but different deposition techniques can be used, e.g., PECVD, PVD, spin deposition, and atomic layer deposition. In the claimed embodiments, the materials for the first and second dielectric layers are different, and the deposition technique for forming each layer can be different.

[0016] With reference to Fig. Figure 2 shows a cross-section of an exemplary inductor structure according to one or more embodiments of the present invention. The inductor structure 100 generally comprises a plurality of alternating magnetic layers 112 and insulating layers 114 arranged on a substrate 116, such as a machined wafer.

[0017] Each of the insulating layers 114 has several dielectric layers 114A, 114B deposited by means of a low-temperature deposition process specific to the dielectric material and which processes the deposited dielectric material. At least two or more of the dielectric layers 114A and 114B within a multilayer insulation scheme are formed from different materials or, in an unclaimed manner, by different deposition techniques. As used herein, the term multilayer insulation scheme generally refers to two or more dielectric layers, where at least two of the dielectric materials are different. Although each deposited layer may contain pores, it has been found that the pores between layers are not continuous.This prevents eddy current losses between adjacent magnetic layers, which were previously caused by pore formation in the dielectric layer. The maximum number of dielectric layers between adjacent magnetic layers is not intended to be limited and is generally restricted by the desired thickness of the insulating layer, although a minimum thickness is generally desirable to electrically insulate the magnetic layers while simultaneously preventing eddy current losses. In general, the use of multiple dielectric layers 114A to 114B instead of a single insulating layer allows for smaller layer thicknesses and an overall lower aspect ratio for the magnetic stack, which is desirable for increasingly smaller components.

[0018] The multiple dielectric layers 114A to 114B are not limited to a specific material and can include dielectric materials such as oxides, nitrides, and the like, with silicon dioxide and silicon nitride always being present as claimed. Examples of such oxides include silicon dioxide (SiO₂), thermal silicon oxide, and silicon oxynitride (SiO₂). x N y Magnesium oxide (MgO), aluminum oxide (AlO2) and / or (Al2O3), boron oxide (B2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), or the like, without being limited thereto. Silicon nitride is an example of a nitride.

[0019] The bulk resistance and eddy current loss of the magnetic structure can be controlled by the multilayer dielectric layer 114. As previously noted, the overall thickness of the insulating layer 114 (i.e., the thickness of the multiple dielectric layers 114A to 114B that define the respective insulating layer 114A, 114B) should be minimal and is generally of a thickness effective for electrically insulating the magnetic layer on which it is deposited from other magnetic layers in the thin-film stack. In general, the insulating layer 114A, 114B has a thickness of about 1 nanometer to about 500 nanometers and can be at least about half or more the thickness of the magnetic layer. In one or more embodiments, the thickness of the insulating layer is about 2 to about 100 nanometers.

[0020] Each of the magnetic layers 112 in the laminate stack 100 can have a thickness of approximately 100 nanometers or more and can be deposited by vacuum deposition technologies (i.e., sputtering) or electroplating using an aqueous solution. Vacuum processes are capable of depositing a wide variety of magnetic materials and readily fabricating laminated structures. However, they typically exhibit low deposition rates, poor conformal coverage, and the resulting magnetic thin films are difficult to structure. Electroplating is a standard technique for depositing thick metal thin films due to its high deposition rate, conformal coverage, and low cost.

[0021] The magnetic layers are not limited to a specific material and can include CoFe, CoFeB, CoZrTi, CoZrTa, CoZr, CoZrNb, CoZrMo, CoTi, CoNb, CoHf, CoW, FeCoN, FeCoAIN, CoP, FeCoP, CoPW, CoBW, CoPBW, FeTaN, FeCoBSi, FeNi, CoFeHfO, CoFeSiO, CoZrO, CoFeAlO, combinations of these, or similar materials. Inductor core structures made from these materials have generally been shown to exhibit low eddy current losses, high magnetic permeability, and high saturation flux density.

[0022] The magnetic inductor, which incorporates the laminate structure as described, can be integrated into a variety of units. Two basic configurations are closed-yoke and solenoid inductors. The closed-yoke inductor has a copper wire around which a magnetic material is wound, and the solenoid inductor has a magnetic material around which a copper wire is wound. Both inductor types benefit from very thick magnetic materials, with the required total thickness of the magnetic thin film typically exceeding 1 micrometer (µm).

[0023] A non-restrictive example of inductor integration is a transformer, which can incorporate metal conductors that can be formed parallel to each other using standard silicon machining techniques designed to create metal structural elements. The inductor structures can be formed around these parallel metal conductors to create a closed magnetic circuit, providing high inductance and magnetic coupling among the metal conductors. Incorporating the magnetic material and substantially or completely enclosing the metal conductors can enhance the magnetic coupling between the metal conductors and the inductor for a given inductor size. Magnetic inductor materials are also applicable to RF and wireless circuits, as well as power converters and EMI reduction.

[0024] With reference to Fig. Figure 3 shows a process 300 for forming the magnetic inductor on a chip, and it generally begins with a first step 110 for depositing a first dielectric layer 114A on the processed wafer 116, which has a planar top surface after FEOL, MOL and BEOL processing.

[0025] In step 120, a second dielectric layer 114B is deposited on the first dielectric layer 114A. The second dielectric layer 114B is made of a different material. Optionally, one or more additional dielectric layers can be deposited on the second dielectric layer 114B, which are made of a different material than the second dielectric layer 114B. In one or more unclaimed embodiments, the additional dielectric layer is made of the same material as the first dielectric layer 114A.In one or more embodiments, the second dielectric layer 114B (and / or any additional dielectric layer) is formed from a different material than the first dielectric layer 114A, while the deposition technique used to form the second dielectric layer 114B is the same as the deposition method used to form the first dielectric layer 114A. In one or more other unclaimed embodiments, the second layer (and / or any additional dielectric layer) may consist of the same material but use a different deposition technique. In one or more other embodiments, the materials for the first and second dielectric layers 114A, 114B are different, and the deposition technique for forming each layer is different.

[0026] As described in step 130, after the desired thickness of the dielectric layer 114A, 114B has been formed, a magnetic layer 112 is deposited on the uppermost dielectric layer. The preceding process steps are repeated to provide alternating magnetic layers and multilayer insulation schemes until the desired magnetic inductor structure is formed, which includes a magnetic thin film with a total thickness of more than 1 micrometer. By utilizing a laminate structure that includes the multilayer insulation scheme, as described, eddy current losses between adjacent magnetic layers are prevented.

[0027] Once the desired laminate structure has been formed, the process can further involve depositing a hard mask onto the laminate structure, followed by lithography to complete the unit, after which lithography can be performed.

[0028] The terminology used herein serves only to describe certain embodiments and is not intended to limit the invention. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. Furthermore, it is understood that the terms "has" and / or "having" when used in this description denote the presence of specified features, integers, steps, processes, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, processes, element components, and / or groups thereof.

[0029] The corresponding structures, materials, processes, and correspondences of all means or elements consisting of a step plus function in the following claims are intended to include any structure, material, or action for performing the function in combination with other claimed elements than those expressly claimed. The description of the present invention is provided for illustrative and descriptive purposes but is not intended to be exhaustive or limited to the invention as described. Numerous modifications and variants are apparent to those skilled in the art without deviating from the scope of the invention. The embodiment was selected and described to best explain the basic concepts of the invention and its practical application, and to enable other skilled in the art to understand the invention in relation to various embodiments with different modifications suitable for the intended use.

[0030] It should be evident that numerous variations of this diagram or the steps (or processes) described herein are possible without deviating from the scope of the invention. For example, the steps can be performed in a different order, or steps can be added, omitted, or modified. All such variations are considered part of the claimed invention.

Claims

[1] Inductor structure (100) comprising: a laminated thin-film stack comprising alternating layers of a magnetic material (112) and a multi-layer insulating material, the multi-layer insulating material being located between adjacent layers (112) of the magnetic material and comprising a first insulating layer (114A) adjacent to at least one additional insulating layer (14B), and wherein the first insulating layer (114A) and the at least one additional insulating layer (114B) comprise different dielectric materials, wherein the first insulating layer (114A) comprises silicon dioxide and the insulating layer adjacent to at least one additional insulating layer comprises a silicon nitride insulating layer. [2] The inductor structure (100) of claim 1, further comprising a plurality of metal lines; and wherein the laminated thin film stack comprising alternating layers (112) of a magnetic material and a multi-layer insulating material (114A, 114B) encloses the metal lines. [3] Inductor structure (100) according to claim 1, wherein the first insulating layer and / or the at least one additional insulating layer has one or more pores and is not continuous between the first insulating layer and the at least one additional insulating layer. [4] The inductor structure (100) of claim 1, wherein the magnetic material is selected from the group consisting of CoFe, CoFeB, CoZrTi, CoZrTa, CoZr, CoZrNb, CoZrMo, CoTi, CoNb, CoHf, CoW, FeCoN, FeCoAIN, CoP, FeCoP, CoPW, CoBW, CoPBW, FeTaN, FeCoBSi, FeNi, CoFeHfO, CoFeSiO, CoZrO, CoFeAlO, and combinations thereof. [5] The inductor structure (100) of claim 1, wherein the dielectric materials (114A, 114B) are selected from the group consisting of silicon dioxide, thermal Si oxide, silicon oxynitride, magnesium oxide, aluminum oxide, boron oxide, tantalum oxide, titanium oxide, silicon nitride, and combinations thereof. [6] The inductor structure (100) of claim 1, wherein the layer (114A) of multilayer insulating material has a thickness of approximately one-half a thickness of the layer (112) of magnetic material. [7] The inductor structure (100) of claim 1, wherein the layer (114A, 114B) of multi-layer insulating material has a thickness effective to electrically isolate each layer of magnetic material from other layers (112) of magnetic material in the inductor structure (100). [8] The inductor structure (100) of claim 1, wherein the layer (114a, 114B) of multilayer insulating material comprises a first silicon dioxide layer overlying a silicon nitride layer, the silicon nitride layer overlying a second silicon dioxide layer. [9] The inductor structure (100) of claim 1, wherein the layer (114A, 114B) of multilayer insulating material comprises a first silicon nitride layer overlying a silicon dioxide layer, the silicon dioxide layer overlying a second silicon nitride layer. [10] The inductor structure (100) of claim 1, wherein the inductor structure (100) is a closed yoke inductor and is wound around a metal wire. [11] The inductor structure (100) of claim 10, wherein the inductor structure (100) is a solenoid inductor, wherein a metal wire is wound around the inductor structure (100). [12] A method (300) for forming an inductor structure (100), comprising: Depositing (110, 120, 130, 140) a laminated thin-film stack comprising alternating layers of a magnetic material and a multilayer insulating material, wherein the multilayer insulating material is located between adjacent layers of the magnetic material and comprises a first insulating layer adjacent to at least one additional insulating layer, and wherein the first insulating layer and the at least one additional insulating layer comprise different dielectric materials, wherein the first insulating layer (114a) comprises silicon dioxide and the insulating layer (114B) adjacent to at least one additional insulating layer comprises an insulating silicon nitride layer. [13] The method (300) of claim 12, wherein depositing the first insulating layer (114A) and adjoining the at least one additional insulating layer (114B) comprises CVD, PECVD, or combinations thereof. [14] The method (300) of claim 12, wherein the deposition of the first insulating layer (114A) and the application to the at least one additional insulating layer (114B) occurs at a temperature of less than 300°C. [15] The method (300) of claim 12, wherein depositing the magnetic material comprises an electroplating process. [16] The method (300) of claim 12, wherein the magnetic layers comprise CoFe, CoFeB, CoZrTi, CoZrTa, CoZr, CoZrNb, CoZrMo, CoTi, CoNb, CoHf, CoW, FeCoN, FeCoAIN, CoP, FeCoP, CoPW, CoBW, CoPBW, FeTaN, FeCoBSi, FeNi, CoFeHfO, CoFeSiO, CoZrO, CoFeAlO or combinations thereof. [17] The method (300) of claim 12, wherein the first insulating layer (114A) and / or the at least one additional insulating layer (114B) has one or more pores and is not continuous between the first insulating layer (114A) and the at least one additional insulating layer (114B). [18] The method (300) of claim 12, wherein the insulating layers (114A, 114B) are selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and combinations thereof.

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