3D IC in embedded chip substrate

Abstract

Three-dimensional (3D) integrated circuit (IC) structures that are less constrained by the 2D footprint of a conventional IC chip. The novel 3D IC structures combine 3D ICs fabricated using various die and / or wafer bonding technologies with embedded die packaging technology. Embodiments include a 3D IC structure including one or more 3D IC chips embedded in a stack of one or more planar lamination layers. The combination of one or more 3D ICs with an embedded die packaging technology results in a high degree of integration and miniaturization by utilizing the placement of electrical connection pads on both the top and bottom surfaces of the 3D ICs.This enables better integration of active components as well as passive components, enables flexible partitioning of circuits and systems for 3D integration, and enables low-profile 3D IC structures that utilize scaling effects.

Description

CROSS-REFERENCE TO SIMILAR APPLICATIONS

[0001] This application claims priority to U.S. Patent Application No. 18 / 085,003, filed December 20, 2022, the contents of which are incorporated herein by reference in their entirety. BACKGROUND(1) Technical field

[0002] The present invention relates to three-dimensional integrated circuit structures and circuits. (2) Background

[0003] The electronics industry continues to strive for ever-increasing electronic functionality and performance in a variety of products, including (by way of example only) personal electronics (e.g., "smart" watches and fitness wearables), PCs, tablet computers, wireless networking components, televisions, cable set-top boxes, radar systems, and mobile phones. Increased functionality and / or performance typically results in more transistors and other electronic components on an integrated circuit (IC) die.While the number of transistors per unit area of ​​an IC chip has increased over time as IC manufacturing process nodes have shrunk device dimensions, the two-dimensional (2D) planar footprint of some IC chips has not decreased at the same rate, primarily due to the use of more (albeit smaller) transistors to implement increased functionality and / or performance. The 2D footprint of an IC chip is a constraint on reducing the size of modules and circuit boards within products.

[0004] Accordingly, there is a need for integrated circuit structures with higher functionality that are less constrained by the 2D footprint of an IC chip. SUMMARY

[0005] The present invention encompasses three-dimensional (3D) integrated circuit (IC) structures that are less constrained by the 2D footprint of a conventional IC chip. The novel 3D IC structures combine 3D ICs fabricated using die and / or wafer bonding technologies with embedded die packaging technology or embedded chip packaging technology, an advanced form of laminate technology. The combination of one or more 3D ICs with embedded die packaging technology results in a high degree of integration and miniaturization by utilizing the placement of electrical connection pads on both the top and bottom surfaces of the 3D ICs.This enables better integration of active and passive components in a single IC structure, enables flexible partitioning of circuits and systems for 3D integration, and enables low-profile 3D IC structures that take advantage of scaling effects.

[0006] Embodiments include a 3D IC structure including one or more 3D IC chips embedded in a stack of one or more planar lamination layers. Other embodiments include a 3D IC structure having a top surface and a bottom surface opposite the top surface, the 3D IC structure including: one or more 3D IC chips embedded in a stack of one or more planar lamination layers, wherein at least one of the one or more 3D IC chips includes a plurality of contact chip pads on a first surface and on a second surface opposite the first surface; and one or more interconnect pads formed on at least one of the top surface and a bottom surface of the 3D IC structure.

[0007] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the following description. Further features, objects, and advantages of the invention will become apparent from the description and drawings, as well as from the claims. DESCRIPTION OF THE DRAWINGS It shows / It shows: Fig. 1A is a side cross-sectional view along a YZ dimensional plane of an embodiment of a 3D IC structure according to the present invention. Fig. 1B is an expanded cross-sectional side view along a YZ dimensional plane of the one or more planar lamination layers of the 3D IC structure of Fig. 1A. Fig. 1C a side cross-sectional view along a YZ dimensional plane of the 3D IC structure of Fig. 1A, which shows a first method of attaching an MLCC. Fig. 1D a cross-sectional side view along a YZ dimension plane of the 3D IC structure of Fig. 1A, which shows a second method of attaching an MLCC. Fig. 2A is a cross-sectional side view of a first exemplary 3D IC chip formed from two 2D ICs, Die 1 and Die 2. Fig. 2B is a cross-sectional side view of a second exemplary 3-D IC chip formed from two 2-D ICs, Chip 1 and Chip 2. Fig. 2C is a cross-sectional side view of a third exemplary 3-D IC chip formed from two 2-D ICs, Die 1 and Die 2. Fig. 2D is a cross-sectional side view of a fourth exemplary 3-D IC chip formed from two 2-D ICs, CHIP 1 and CHIP 2. Fig. 2E is a side cross-sectional view of a fifth exemplary 3D IC chip with substructure / topstructures formed on both sides of a single substrate. Fig. 3 a cross-sectional side view of a 3D IC structure including two adjacent (horizontally spaced with respect to the side) 3D IC chips. Fig. 4 is a cross-sectional side view of a 3D IC structure including a first pair of side-by-side (horizontally spaced with respect to the side) 3D IC chips that are vertically spaced from a second pair of side-by-side 3D IC chips. Fig. 5 is a schematic diagram of an integrated circuit radio frequency antenna switch that may be implemented using the present invention. Fig. 6 a plan view of a substrate, which may be, for example, a printed circuit board or a chip module substrate (e.g., a thin-film tile). Fig. 7 is a process flow diagram showing a method for manufacturing a 3D IC structure.

[0008] The same reference symbols and designations in the various drawings indicate the same elements. DETAILED DESCRIPTION

[0009] The present invention encompasses three-dimensional (3D) integrated circuit (IC) structures that are less constrained by the 2D footprint of a conventional IC chip. The novel 3D IC structures combine 3D ICs fabricated using die and / or wafer bonding technologies with embedded die packaging technology, an advanced form of laminate technology. Combining one or more 3D ICs with embedded die packaging technology results in a high degree of integration and miniaturization by utilizing the placement of electrical connection pads on both the top and bottom surfaces of the 3D ICs. This enables better integration of active and passive components, enables flexible partitioning of circuits and systems for 3D integration, and enables low-profile 3D IC structures that take advantage of scaling effects. MOSFET IC manufacturing

[0010] It may be useful to review how 2D metal-oxide-semiconductor field-effect transistor (MOSFET) circuits are fabricated using a conventional silicon-on-insulator (SOI) process. Starting from a wafer substrate, such as silicon, an insulating buried oxide (BOX) layer is formed, upon which an active layer, typically of doped silicon, is formed. On and / or within the active layer, one or more MOSFET structures are formed within the confines of a single IC chip (unsingulated at this point). Each wafer substrate typically contains hundreds to thousands of unsingulated dies.

[0011] A MOSFET structure generally includes a mask-shaped channel, a gate, a source, a drain, and isolation regions. The current IC manufacturing process is generally considered front-end-of-line (FEOL), where individual components (transistors, capacitors, resistors, inductors, etc.) are patterned in or on the active layer. FEOL generally covers everything up to the deposition of metal interconnect layers and can be considered the fabrication of tool substructures.

[0012] After the final FEOL step, a wafer contains multiple die regions, each containing isolated transistors without interconnect conductors. The back-end-of-line (BEOL) is the second stage of IC manufacturing, where the individual devices (transistors, capacitors, resistors, inductors, etc.) within a die region are connected with conductors formed as part of or spanning one or more metal interconnect layers. BEOL includes the formation of electrical contacts (pads), vias, insulating layers (dielectrics), metal levels, and die-to-package interconnect points. In some applications, through-silicon vias (TSVs) can be fabricated, with each TSV passing through the wafer substrate between the active layer and an interconnect point, such as a bond pad.

[0013] Some BEOL manufacturing processes or post-BEOL manufacturing processes (e.g., as part of an outsourced semiconductor assembly and outsourced test) allow for the deposition of a redistribution layer (RDL), which is generally an additional patterned conductive layer (usually aluminum) on an IC die that provides the input / output (I / O) pads of an IC die for coupling to other locations on the die and / or to another IC die and / or to special packaging structures. The RDL can be formed on the "top" BEOL buildup of an IC die. In some cases (e.g., for single-layer transfer or SLT die structures), the RDL can be formed adjacent to a primary circuit layer containing FET active regions after removing the wafer substrate and reattaching the primary circuit layer and top structure to a handle wafer.

[0014] Thus, a 2D MOSFET IC chip is essentially formed in two parts: a "lower" FEOL substructure and an "upper" BEOL superstructure, formed within a die area of ​​a wafer. After FEOL and BEOL processing, the wafer undergoes a series of additional known process steps, including dicing, testing, and packaging, to form multiple IC chips. While a MOSFET IC chip is actually manufactured by building up multiple layers and is thus technically a three-dimensional structure, the layers are extremely thin, and such MOSFETs are conventionally considered two-dimensional structures. 3D stacking technology

[0015] To reduce the 2D footprint of an IC chip, a number of 3D technologies have been developed, focusing on stacking and bonding aligned IC chips originally fabricated on different wafers (also known as wafer-to-wafer bonding), stacking and bonding individual IC chips onto non-isolated IC chips on a wafer (also known as die-to-wafer bonding), and stacking and bonding a single IC chip onto another IC chip (also known as die-to-die bonding). One such technology can be referred to as a "hybrid bonding interconnect" (HBI), in which a circuit is fabricated on different wafers or dies and then stacked vertically and interconnected in a 3D structure. When bonding the two wafers / chips, both dielectric materials (e.g. silicon dioxide, SiCN, SiCOH and / or analogous alloys) and conductive interconnect materials (e.g.Copper, aluminum, and / or their alloys) are used. In general, a high density of interconnects between the upper and lower wafers / dies is desirable to achieve good communication between them. The interconnect pitch can be between approximately 0.2 to 10 µm and preferably in the range of approximately 2-5 µm. HBI technology has a proven high interconnect density, is a planar technology that does not require underfill or carrier wafer integration, and allows the formation of interconnects between two IC wafers / dies during the bonding phase of processing at relatively low temperatures (e.g., < 400 °C).

[0016] Another stacking and bonding technology for shrinking the 2D footprint of an IC chip uses thermocompression bonding of pillar bumps on paired ICs. Thermocompression bonding is also known as diffusion bonding, compression bonding, thermocompression welding, or solid-state welding. Pillar bumps can be made of copper, with one contact end coated with nickel and then silver or tin (e.g., solder). Two IC chips containing correspondingly aligned pillar bumps are joined together using a simultaneous application of force and heat, creating an electrical coupling between mated conductors. Atoms migrate between the metallic crystal lattices of the two components based on crystal lattice vibration, which adheres the interfaces together. This process enables a direct electrical connection between two structures without additional steps.

[0017] Another technology for shrinking the 2D footprint of an IC chip uses 3D embedded chip packaging. For example, a single IC chip can be embedded in a substrate layer (typically an organic material such as a laminate) with conductive (e.g., copper) connections or "vias" electrically coupled to connection points (e.g., die pads, bond pads, bumps, or pins) for internal and / or external connections. The embedded die substrate layer, or embedded chip substrate layer, on which an IC chip is embedded essentially functions as a printed circuit board. One method for constructing interconnections is to use conventional BEOL processes (e.g., sequential formation of one or more dielectric or conductive layers around an embedded IC chip, including the formation of interlayer interconnects or vias, respectively).Another method for constructing interconnects is to laminate multiple layers designed to accommodate an embedded IC chip and containing horizontal and vertical conductors. After the initial lamination, additional laminated layers can be added and / or conventional BEOL processes can be applied post-lamination to form additional structures, layers, and / or connection pads. Example 3D IC structure

[0018] Fig. Figure 1A is a side cross-sectional view along a YZ-dimensional plane of one embodiment of a 3D IC structure 100 according to the present invention. A 3D IC chip 102 is embedded in a substrate layer comprising a stack of one or more planar lamination layers 104 (each lamination layer AM is indicated by a bracketed dashed line) including horizontal (in-plane) conductors 106 and vertical (perpendicular to the plane) conductors or vias 108. Fig. 1B is an expanded cross-sectional side view along a YZ dimensional plane of the one or more planar lamination layers 104 of the 3D IC structure 100 of Fig. 1A. It should be noted that the vertical dimensions of the lamination layers 104 are not to scale, especially the lamination layer 104 in which the 3D IC chip 102 is embedded.

[0019] In the illustrated example, some of the horizontal conductors 106 contact chip pads 110 that form part of the 3D IC chip 102. Connection pads 112 are shown formed on the top and bottom surfaces of the lamination layers 104, enabling connections to the 3D IC chip 102 and other components (e.g., resistors, capacitors, including supply capacitors, inductors) that may be included in the lamination layers 104. In some embodiments, one or more connection pads 112 may be formed on only one of the top and bottom surfaces of the lamination layers 104. In some embodiments, the connection pads 112 may be omitted from a surface that is to undergo hybrid bonding or the like.

[0020] In some embodiments, external components may be attached to the outside of the 3D IC structure 100. For example, in Fig. 1A shows a multi-layer ceramic capacitor (MLCC) 114 attached to two of the top-side terminal pads 112. Details of one type of MLCC are listed below. However, embodiments of the present invention are not limited to the use of MLCC capacitors, but may incorporate other known capacitor structures, including (but not limited to) ceramic capacitors, tantalum capacitors, aluminum electrolytic capacitors, capacitors incorporated into a silicon substrate, and conductive polymer capacitors. Furthermore, other types of electronic, electromechanical, and / or electro-optical components, such as inductors, resistors, sensors, microelectromechanical system (MEMS) devices, photodetectors or emitters, etc., may be attached to the terminal pads 112 of the 3D IC structure 100 in a similar manner.

[0021] The finished 3D IC structure 100 with attached external components can be overmolded to form a robust chip-scale package (CSP) that can be used in subsequent processes such as a 2D integrated circuit, such as by attaching to other structures (e.g., spacers, die modules, or circuit boards).

[0022] Fig. 1C is a cross-sectional side view along a YZ dimensional plane of the 3D IC structure 100 of Fig. 1A, which shows a first method for attaching an MLCC 114. The body of the MLCC 114 includes interdigitated electrically insulated conductive plates (also known as internal electrodes) 120, 122 separated by a ceramic dielectric 124. Internal via-type main electrodes 126, 128 (instead of external end-cap main electrodes) are connected to corresponding sets of the internal electrodes 120, 122. An advantage of the internal main electrodes 126, 128 is that they are protected from possible inadvertent electrical contact with the sides of the capacitor MLCC 114. Each of the internal VIA main electrodes 126, 128 is coupled to a corresponding bonding pad 130 or pad 132 on at least one surface (a "bond pad") of the MLCC 114, which is suitable for forming hybrid bonds. Details regarding the fabrication of an MLCC 114 are set forth below.

[0023] Fig. 1C shows the MLCC 114 positioned immediately prior to bonding, with the MLCC 114 being moved into contact with the 3D IC structure 100 as indicated by arrows 134. The MLCC 114 is placed on and electrically coupled to corresponding terminal pads 112 and associated dielectric of the 3D IC structure 100. If HBI is the selected bonding technique, the spaces between the terminal pads 112 may be filled with a dielectric 113, as hybrid bonding creates bonds between corresponding dielectric materials and corresponding conductive interconnect materials and generally results in no void space between the bond pads. The MLCC 114 may be placed using die-to-die, die-to-wafer, or wafer-to-wafer (e.g., using a reconstituted wafer supporting multiple MLCCs 114).

[0024] Fig. 1D is a cross-sectional side view along a YZ dimensional plane of the 3D IC structure 100 of Fig. 1A, which shows a second method for attaching an MLCC 114. The 3D IC structure 100 and the MLCC 114, in this example, also include pillar bumps 140 formed on corresponding connection pads 112, 130, 132. Pillar bumps enable a finer pitch compared to solder bumps (typically at least twice as fine), enabling more connections between components within a specified 2D flat footprint. The MLCC 114 is deposited and electrically coupled using thermocompression bonding of aligned pillar bumps 140. Fig. 1D shows the MLCC 114 positioned immediately prior to bonding, with the MLCC 114 being moved into contact with the 3D IC structure 100 as indicated by arrows 138. The MLCC 114 may be placed using die-to-die, die-to-wafer, or wafer-to-wafer (e.g., using a reconstituted wafer supporting multiple MLCCs 114). 3D IC examples

[0025] The 3D IC chip 102, which is integrated into the 3D IC structure 100 of Fig. 1A may contain active IC devices (e.g., MOSFETs) and / or integrated passive components (e.g., resistors, capacitors, inductors), depending on the application requirements. How Fig. 1A illustrates the case of an MLCC 114, components (e.g., passive components such as resistors, capacitors, inductors, resonators, other IC chips, discrete devices, etc.) may also be attached through the connection pads 112 of the 3D IC structure 100 and electrically connected to the 3D IC structure 100. Such components may be connected to the embedded 3D IC chip 102 and / or other connection pads or package pins using routing layers available within and between the lamination layers 104 of the 3D IC structure 100.

[0026] The 3D IC chip 102 from Fig. 1A can be produced in a number of different ways, examples of which are related to the Fig. 2A-2E are described.

[0027] Fig. 2A shows a cross-sectional side view of a first exemplary 3D IC chip 200 formed from two 2D ICs, Die 1 and Die 2. Each of Die 1 and Die 2 includes an isolated region of a die or substrate 202 on which a substructure (e.g., active areas of the die formed by FEOL processes) and a superstructure (e.g., interconnects formed by BEOL processes) 204 (shown in combined form) are formed, supporting contact dies 110. After fabrication as 2D dies, the insulating substrates 202 of Die 1 and Die 2 are bonded back-to-back along the boundary 206. The 2D matrices can be brought into contact with each other using die-to-die, die-to-wafer, or wafer-to-wafer (for example, using a reconstituted wafer carrying multiple 2D matrices).The thickness of the combined dies depends on the thickness of the individual DIE 1 and DIE 2.

[0028] After bonding CHIP 1 and CHIP 2, the contact chip pads 110 are exposed on both the top and bottom surfaces of the combined chips, thus enabling a greater number of connections to the 3D IC chip 102 within the 3D IC structure 100 compared to a conventional 2D IC chip. Other advantages of the 3D IC chip configuration of Fig. 2A include: each 2D die keeps its contact chip pads 110 intact; power-related circuits / devices (e.g., high-frequency switches) can be split between Die 1 and Die 2 according to a specific application; and other support circuits can be split between the two dies and routed using internal routing layers available in the embedded substrate technology.

[0029] Fig. 2B is a cross-sectional side view of a second exemplary 3-D IC die 210 formed from two 2-D ICs, Cube 1 and Cube 2. Each of Cube 1 and Cube 2 includes an insulating substrate 202 having formed thereon a substructure and a topstructure 204 (shown in combined form). Die 2 supports contact dies 110 on its combined substructure / topstructure 204. However, IC die 1 has undergone a single layer transfer (SLT) process that essentially reverses or "flips" Nozzle 1 and bonds the substructure / topstructure 204 of Nozzle 1 to the substrate 202 of Nozzle 2 (which may be thinned prior to bonding). The substrate 202 of Die 1 may then be removed or thinned, and if necessary, vias 212 may be formed to connect the circuitry within the substructure / topstructure 204 of Die 1 to “top” side contact chip pads 110.The advantages of the 3D IC chip 210 configuration from . Fig. 2B includes the ability to achieve lower profiles for the final 3D IC structure 100 by removing part or all of the substrate 202 of Die 1 and optionally thinning the substrate 202 of Die 2.

[0030] Fig. 2C is a cross-sectional side view of a third exemplary 3-D IC chip 220 formed from two 2-D ICs, Die 1 and Die 2. Each of Die 1 and Die 2 includes an insulating substrate 202 having formed thereon a substructure and a topstructure 204 (shown in combined form) supporting contact die pads 110. After being fabricated as 2-D dies, one or both of Die 1 and Die 2 undergo a double layer transfer (DLT) process that essentially inverts or "flips" the die(s) and bonds the substructure / topstructure 204 of that die to a handle wafer (not shown), after which the insulating substrate 202 of the flipped die is thinned. Thereafter, the insulating substrates 202 of the folded chip(s) (CHIPS 1 and / or CHIPS 2) are bonded back-to-back along the boundary 206 and the handle wafer(s) is / are removed.The result is a 3D IC chip 220 that has a lower profile compared to the example from . Fig. 2A due to thinning of the substrate 202 of the CUBE 1 and optionally thinning of the substrate 202 of the CUBE 2.

[0031] Fig. 2D is a cross-sectional side view of a fourth exemplary 3D IC chip 230 formed from two 2D ICs, Cube 1 and Cube 2. The manufacturing process is similar to the DLT process used Fig. 2C, except that after bonding the substructure / top structure 204 of Die 1 to a handle wafer (not shown), the insulating substrate 202 of the flipped Die 1 is removed. Thereafter, the exposed backside of the substructure / top structure 204 of the flipped Die 1 is bonded back-to-back along the boundary 206 to the insulating substrate 202 of Die 2 (note that the insulating substrate 202 of Die 2 may optionally be thinned prior to the bonding process). Subsequently, the handle wafer of Stamp 1 is removed. The result is a 3D IC chip 230 which, compared to the example of Fig. 2A has a lower profile due to the removal of the substrate 202 of CUBE 1 and optionally the thinning of the substrate 202 of CUBE 2.

[0032] Fig. 2E is a side cross-sectional view of a fifth exemplary 3D IC chip 240 having substructure(s) formed on both sides of a single substrate 242. Using double-sided wafer processing techniques, the substrate 242 is processed sequentially (one side at a time) or in parallel to form a combined substructure / superstructure 204 on each side of the substrate 242. For example, a first side of the substrate 242 may be subjected to conventional FEOL and BEOL processes to form a combined substructure / superstructure 204a on the "top" side of the substrate 242, and then a second side of the substrate 242 may be subjected to conventional FEOL and BEOL processes to form a combined substructure / superstructure 204b on the "bottom" side of the substrate 242.Although two separate 2D ICs are not involved, the result is a 3D IC structure 100 that includes contact chip pads 110 on both the top and bottom of the 3D IC structure 100, as well as a low profile structure. Multiple embedded 3D ICs

[0033] The exemplary 3D IC structure 100 shown in Fig. 1A, includes a single 3D IC chip 102. However, the combination of the 3D IC chip with embedded die packaging technology enables scaling advantages. For example, Fig. 3 is a cross-sectional side view of a 3D IC structure 300 including two adjacent (horizontally embedded and side-spaced) 3D IC chips 302, 304. In the illustrated example, an MLCC 306 is coupled to both 3D IC chips 302, 304, and the finished 3D IC structure 300 is shown including an overmold material 308 to form a robust CSP 310.

[0034] As another example, Fig. 4 is a cross-sectional side view of a 3D IC structure 400 including a first pair of stacked (vertically spaced with respect to the side) 3D IC dies 402, 404 horizontally spaced from a second pair of stacked 3D IC dies 406, 408. In the depicted example, an MLCC 410 is coupled to IC die 1 of the 3D IC die 402 and to IC die 4 of the 3D IC die 404. The finished 3D IC structure 400 with attached external components may be embedded in overmold material (not shown) to form a robust CSP.

[0035] As should be clear, the Fig. 3 and Fig. The examples shown in Figure 4 are illustrative and not limiting. Thus, other numbers and layouts of 3D IC chips 102 may be integrated into a 3D IC structure to meet the requirements of a particular application. The realized chip-scale package may be embedded in or attached to another substrate (e.g., a main board substrate of a larger system). Example of a circuit application

[0036] The applications of the present invention are numerous. For example, Fig. 5 is a schematic diagram of an integrated circuit radio-frequency antenna switch 500 that can be implemented using the present invention. The antenna switch 500 includes a first switch S1 that can couple signals at port A1 to port B1, and a second switch S2 that can couple signals at port A2 to port B2. The open or closed states of both switches S1, S2 can be controlled by a conventional serial wire interface. Both switches S1, S2 can be implemented using MOSFETs. A circuit ground terminal GND provides a reference potential to the antenna switch 500.

[0037] It is common for an antenna switch to require at least a relatively large capacitor (e.g., 1.5 µF) for proper operation. In conventional antenna switches, such an external supply capacitor is coupled between a contact pad of the antenna switch IC and circuit ground. However, using the present invention, the illustrated antenna switch 500 may be implemented as a single 3D IC structure including an embedded capacitor C, as in the example shown in Fig. 1A, all of which have a compact 2D footprint. Such an embodiment meets customer requirements for a higher level of integration and miniaturization, while maintaining or reducing the resulting 2D footprint compared to conventional IC implementations. MLCC manufacturing process

[0038] With respect to MLCCs of the type shown in the examples of this disclosure, a method for manufacturing such MLCCs may be based on a combination of multilayer ceramic capacitor (MLCC) and low-temperature co-firing ceramic (LTCC) technology. The pre-ground ceramic dielectric powder may, for example, be mixed with a suitable amount of a binder (typically an organic polymer) to form a dielectric "green" sheet. The ceramic powder may, for example, be barium titanate (BaTiO3). Internal electrodes may be formed by printing (e.g., screen printing) a conductive paste (e.g., nickel) onto the green sheet to form multiple sets of parallel capacitor plates. At a later time, the sets of parallel capacitor plates may be separated (diced) to form individual discrete capacitors.

[0039] Multiple printed green sheets can then be stacked and pressed (laminated). The number of stacking layers and the total layer thickness are predetermined to achieve a target capacitance value. Vias can be formed and then filled with a suitable conductor, such as copper or aluminum. Vias can be formed using a variety of techniques, including laser drilling through the laminated stack. In alternative processes, vias can be formed prior to printing and stacking the capacitor plate by punching holes through the green sheet and filling the holes with a conductor. A single discrete capacitor structure can be internally divided into an array of two or more capacitor cells or dividers, with the dividers being electrically isolated from each other.

[0040] Surface termination electrodes or pads can be printed to connect to the vias, and then the multilayer laminated green sheet can be loaded into a furnace for burnout and sintering of the binder. The sintering temperature of BaTiO3 produced by a conventional mixed oxide process is generally well above 1200 °C to obtain dense ceramic bodies. Sintering temperatures of approximately 1100 °C are possible with nanosized BaTiO3 and a two-step sintering process. However, such temperatures are well above typical IC manufacturing temperatures, especially for CMOS ICs (generally below approximately 300 °C).

[0041] In some processes, additional conductor printing may be performed. The individual capacitors can then be separated and electrically tested for capacitance, dissipation factor, and intrinsic resistance values, and shielded. In some processes, testing may be performed prior to singulation.

[0042] As can be seen, MLCC manufacturing using stacking and lamination layers differs from semiconductor device manufacturing, where layers are generally processed serially, with each new layer being fabricated on top of previous layers.

[0043] As noted above, embodiments of the present invention are not limited to the use of MLCC capacitors, but include other known capacitor structures, including (but not limited to) ceramic capacitors, tantalum capacitors, aluminum electrolytic capacitors, and conductive polymer capacitors. Circuit designs

[0044] Circuits and devices according to the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be enclosed in IC packages and / or modules for ease of handling, manufacturing, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into a package.The ICs and / or modules are then typically combined with other components, often on a printed circuit board (PCB), to form part of a final product, such as a mobile phone, laptop, or electronic tablet, or to form a higher-level module that can be used in a variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless.

[0045] As an example of further integration of embodiments of the present invention with other components, Fig. 6 is a top view of a substrate 600, which may be, for example, a printed circuit board or a chip module substrate (e.g., a thin-film tile). In the depicted example, the substrate 600 includes a plurality of ICs 602a-602d having connection pads 604 that would be interconnected by conductive vias and / or traces on and / or within the substrate 600 or on the opposite (back) surface of the substrate 600 (to avoid clutter, the conductive surface traces are not shown and not all connection pads are labeled). The ICs 602a-602d may embody, for example, signal switches, active filters, amplifiers (including one or more LNAs), and other circuits, and may comprise 3D IC structures in accordance with the present invention.

[0046] The substrate 600 may also include one or more passive devices 606 embedded in, formed on, and / or attached to the substrate 600. Although shown as generic rectangles, the passive devices 606 may be, for example, filters, capacitors, inductors, transmission lines, resistors, planar antenna elements, transducers (including, for example, MEMS-based transducers such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., connected by conductive traces on or in the substrate 600 to other passive devices 606 and / or the individual ICs 602a-602d. The front or back surface of the substrate 600 may be used as a site for forming other structures. System aspects

[0047] Embodiments of the present invention are useful in a variety of larger radio frequency (RF) circuits and systems for performing a variety of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, RF low-noise amplifiers (LNAs), phase shifters, attenuators, antenna beam steering systems, charge pump devices, RF switches, etc. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.

[0048] Radio system use includes wireless RF systems (including base stations, relay stations, and handheld transceivers) that use various technologies and protocols, including various types of Orthogonal Frequency Division Multiple Access (“OFDM”), Quadrature Amplitude Modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, 6G, and WiFi (e.g., 802.11a, b, g, ac, ax, be) protocols, as well as other radio communications standards and protocols.

[0049] The present invention enables 3D IC structures with increased functionality that are less constrained by the 2D footprint of a conventional IC chip. Embodiments of the present invention enable smaller end-use products and shorter signal paths between IC chips, which can, for example, improve range, reception quality, power consumption, and bandwidth in radio frequency applications. Methods

[0050] Another aspect of the invention includes methods for manufacturing 3D IC structures. For example, Fig.7 is a process flow diagram 700 illustrating a method for fabricating a 3D IC structure. The method includes: embedding one or more 3D IC chips in a stack of one or more planar lamination layers, wherein the stack of one or more planar lamination layers has a top surface and a bottom surface opposite the top surface, and wherein at least one of the one or more 3D IC chips includes a plurality of contact chip pads on a first surface and on a second surface opposite the first surface (block 702); and forming one or more interconnect pads on at least one of the top surface and a bottom surface of the one or more planar lamination layers.

[0051] Additional aspects of the above method may include one or more of the following: forming at least one conductive trace within the one or more planar lamination layers connecting at least one of the plurality of contact chip pads to at least one of the one or more interconnect pads; attaching at least one electronic, electromechanical, and / or electro-optical component to at least one of the one or more interconnect pads; wherein the at least one component is a capacitor; wherein the at least one component is a multilayer ceramic capacitor comprising interdigitated electrically insulated internal electrodes, internal VIA main electrodes connected to respective sets of the internal electrodes, and terminal pads located on a connection surface of the multilayer ceramic capacitor and connected to respective ones of the internal VIA main electrodes;wherein the at least one of the one or more 3-D IC chips comprises first and second 2-D IC chips, each having a substrate, the first and second 2-D IC chips being bonded to each other such that the substrate of the first 2-D IC chip faces the substrate of the second 2-D IC chip; wherein the substrate of at least one of the first and second 2-D IC chips is thinned prior to bonding; wherein the at least one of the one or more 3-D IC chips comprises first and second two-dimensional IC chips, each having a substrate and a substructure / top structure formed on the substrate, the first and second 2-D IC chips being bonded to each other such that the substructure / top structure of the first 2-D IC chip faces the substrate of the second 2-D IC chip;wherein the at least one of the one or more 3-D IC chips comprises first and second two-dimensional IC chips, each having a substrate, a substructure formed on the substrate, and a superstructure formed on the substructure, wherein the first and second 2-D IC chips are bonded together such that the substructure of the first 2-D IC chip faces the substrate; the second 2-D IC chip and the substrate of the first 2-D IC chip are removed; wherein the at least one of the one or more 3-D IC chips comprises a substrate having a first surface and a second surface opposite the first surface, wherein the first surface is processed to form a combined substructure / superstructure on the first surface, and the second surface is processed to form a combined substructure / superstructure on the second surface;Arranging at least two 3D IC chips horizontally spaced from each other within the 3D IC structure; and / or arranging at least two 3D IC chips vertically spaced from each other within the 3D IC structure.; Manufacturing technologies & options

[0052] The term "MOSFET" as used in this disclosure includes any field-effect transistor (FET) with an insulated gate whose voltage determines the conductivity of the transistor, and includes insulated gates with a metal or metal-like, insulator, and / or semiconductor structure. The terms "metal" or "metal-like" include at least one electrically conductive material (such as aluminum, copper, or another metal, or highly doped polysilicon, graphene, or another electrical conductor), "insulator" includes at least one insulating material (such as silicon oxide or another dielectric material), and "semiconductor" includes at least one semiconductor material.

[0053] As used in this disclosure, the term "radio frequency" (RF) refers to an oscillation rate in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency can be the frequency of an electromagnetic wave or an alternating voltage or current in a circuit.

[0054] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions may be greatly exaggerated vertically and / or horizontally for clarity or emphasis. Furthermore, references to orientations and directions (e.g., "top," "bottom," "above," "below," "side," "vertical," "horizontal," etc.) refer to the example drawings and do not necessarily represent absolute orientations or directions.

[0055] Various embodiments of the invention may be implemented to meet a variety of specifications. Unless otherwise noted above, the selection of appropriate component values ​​is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including, but not limited to, MOSFET structures) or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including, but not limited to, standard bulk silicon, high-resistance bulk silicon CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS).Unless otherwise stated above, embodiments of the invention may be implemented in other transistor technologies such as bipolar junction transistors (BJTs), BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, MESFET, InP HBT, InP HEMT, FinFET, GAAFET, and SiC-based power device technologies using 2D, 2.5D, and 3D structures. However, embodiments of the invention are particularly useful when fabricated using an SOI- or SOS-based process, or when fabricated using processes that have similar characteristics. Fabrication in CMOS using SOI or SOS processes enables low-power circuits, the ability to withstand high-power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., radio frequencies up to and above 300 GHz).Monolithic IC implementation is particularly useful because parasitic capacitances can generally be kept low through careful design (or at least kept uniform across all units so that they can be compensated).

[0056] Voltage levels may be adjusted and / or voltage and / or logic signal polarities reversed depending on a particular specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS and enhancement-mode or depletion-mode transistor devices). Component voltage, current, and power handling capabilities may be adjusted as needed, for example, by adjusting device sizes, serially "stacking" components (particularly FETs) to withstand larger voltages, and / or using multiple components in parallel to handle larger currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or provide additional functionality without substantially altering the functionality of the disclosed circuits. Conclusion

[0057] A number of embodiments of the invention have been described. It should be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order-independent and thus may be performed in an order different from that described. Furthermore, some of the steps described above may be optional. Various activities described with respect to the methods identified above may be performed repetitively, serially, and / or in parallel.

[0058] It should be understood that the foregoing description is intended to illustrate, not limit, the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufacturers, or compositions of matter set forth in the following claims. (It should be noted that parenthesized designations of claim elements are provided for convenience in referring to such elements and do not, in and of themselves, indicate any particular required order or enumeration of elements; further, such designations may be reused in dependent claims as references to additional elements without being considered to initiate a conflicting characterization sequence.) QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 085,003

[0001]

Claims

[1] Three-dimensional, 3-D, integrated circuit, IC, structure that includes one or more 3-D IC chips embedded in a stack of one or more planar lamination layers. [2] The device of claim 1, wherein the 3D IC structure includes a top surface and a bottom surface opposite the top surface, the 3D IC structure further including: (a) one or more connection pads formed on at least one of the top surface and a bottom surface of the 3D IC structure; and (b) at least one electronic, electromechanical and / or electro-optical component attached and electrically coupled to at least one of the one or more connection pads. [3] The apparatus of claim 2, wherein at least one of the one or more 3D IC chips includes a plurality of contact chip pads on a first surface and on a second surface opposite the first surface. [4] The device of claim 3, wherein the 3-D IC structure further includes at least one conductive path connecting at least one of the plurality of contact chip pads to at least one of the one or more connection pads. [5] The device of claim 2, wherein the at least one component is a capacitor. [6] The device of claim 2, wherein the at least one component is a multilayer ceramic capacitor including interdigitated electrically insulated internal electrodes, internal through main electrodes connected to respective sets of the internal electrodes, and terminal pads located on a bonding surface of the multilayer ceramic capacitor and connected to respective ones of the internal through main electrodes. [7] The device of claim 1, wherein at least one of the one or more 3D IC chips includes a plurality of contact chip pads on a first surface and on a second surface opposite the first surface. [8] The apparatus of claim 7, wherein the at least one of the one or more 3-D IC chips comprises first and second two-dimensional, 2-D, IC chips each having a substrate, the first and second 2-D IC chips being connected to each other such that the substrate of the first 2-D IC chip faces the substrate of the second 2-D IC chip. [9] The device of claim 8, wherein the substrate of at least one of the first and second 2-D IC chips is thinned prior to bonding. [10] The device of claim 7, wherein the at least one of the one or more 3D IC chips comprises a first and a second two-dimensional, 2D, IC chip, each having a substrate and a substructure / superstructure formed on the substrate, wherein the first and the second 2D IC chip are connected to each other such that the substructure / superstructure of the first 2D IC chip faces the substrate of the second 2D IC chip. [11] The device of claim 7, wherein the at least one of the one or more 3-D IC chips comprises first and second two-dimensional, 2-D, dies, each having a substrate, a substructure formed on the substrate, and a superstructure formed on the substructure, wherein the first and second 2-D IC chips are connected to each other such that the substructure of the first 2-D IC chip faces the substrate of the second 2-D IC chip and the substrate of the first 2-D IC chip is removed. [12] The apparatus of claim 7, wherein the at least one of the one or more 3D IC chips comprises a substrate having a first surface and a second surface opposite the first surface, the first surface being processed to form a combined substructure / superstructure on the first surface and the second surface being processed to form a combined substructure / superstructure on the second surface. [13] The device of claim 1, wherein the 3D IC structure includes at least two 3D IC chips spaced horizontally with respect to each other within the 3D IC structure. [14] The device of claim 1, wherein the 3D IC structure includes at least two 3D IC chips that are vertically spaced with respect to each other within the 3D IC structure. [15] A three-dimensional, 3-D, integrated circuit, IC, structure having a top surface and a bottom surface opposite the top surface, the 3-D IC structure including: (a) one or more 3-D IC chips embedded within a stack of one or more planar lamination layers, wherein at least one of the one or more 3-D IC chips includes a plurality of contact chip pads on a first surface and on a second surface opposite the first surface; and (b) one or more connection pads formed on at least one of the top surface and a bottom surface of the 3D IC structure. [16] The apparatus of claim 15, wherein the 3-D IC structure further includes at least one conductive path connecting at least one of the plurality of contact chip pads to at least one of the one or more interconnect pads. [17] The device of claim 15, further comprising at least one electronic, electromechanical and / or electro-optical component mounted and electrically coupled to at least one of the one or more terminal pads. [18] The apparatus of claim 17, wherein the at least one component is a capacitor. [19] The device of claim 17, wherein the at least one component is a multilayer ceramic capacitor including interdigitated electrically insulated internal electrodes, internal through main electrodes connected to respective sets of the internal electrodes, and terminal pads located on a bonding surface of the multilayer ceramic capacitor and connected to respective ones of the internal through main electrodes. [20] The apparatus of claim 15, wherein the at least one of the one or more 3-D IC chips comprises first and second two-dimensional, 2-D, IC chips each having a substrate, the first and second 2-D IC chips being connected to each other such that the substrate of the first 2-D IC chip faces the substrate of the second 2-D IC chip. [21] The device of claim 20, wherein the substrate of at least one of the first and second 2-D IC chips is thinned prior to bonding. [22] The device of claim 15, wherein the at least one of the one or more 3D IC chips comprises first and second two-dimensional, 2D, IC chips, each having a substrate and a substructure / superstructure formed on the substrate, the first and second 2D IC chips being connected to each other such that the substructure / superstructure of the first 2D IC chip faces the substrate of the second 2D IC chip. [23] The apparatus of claim 15, wherein the at least one of the one or more 3-D IC chips comprises first and second two-dimensional, 2-D, IC chips, each comprising a substrate, a substructure formed on the substrate, and a superstructure formed on the substructure, wherein the first and second 2-D IC chips are connected to each other such that the substructure of the first 2-D IC chip faces the substrate of the second 2-D IC chip and the substrate of the first 2-D IC chip is removed. [24] The apparatus of claim 15, wherein the at least one of the one or more 3D IC chips comprises a substrate having a first surface and a second surface opposite the first surface, the first surface being processed to form a combined substructure / superstructure on the first surface and the second surface being processed to form a combined substructure / superstructure on the second surface. [25] The device of claim 15, wherein the 3D IC structure includes at least two 3D IC chips spaced horizontally with respect to each other within the 3D IC structure. [26] The device of claim 15, wherein the 3D IC structure includes at least two 3D IC chips that are vertically spaced with respect to each other within the 3D IC structure. [27] A method for manufacturing a three-dimensional, 3-D, integrated circuit structure, IC structure, comprising: (a) embedding one or more 3D IC chips in a stack of one or more planar lamination layers, wherein the stack of one or more planar lamination layers has a top surface and a bottom surface opposite the top surface, and wherein at least one of the one or more 3D IC chips includes a plurality of contact chip pads on a first surface and on a second surface opposite the first surface; and (b) forming one or more bonding pads on at least one of the top surface and a bottom surface of the one or more planar lamination layers. [28] The method of claim 27, further comprising forming at least one conductive trace within the one or more planar lamination layers connecting at least one of the plurality of contact chip pads to at least one of the one or more terminal pads. [29] The method of claim 27, further comprising attaching at least one electronic, electromechanical and / or electro-optical component to at least one of the one or more connection pads. [30] The method of claim 29, wherein the at least one component is a capacitor. [31] The method of claim 29, wherein the at least one component is a multilayer ceramic capacitor including interdigitated electrically insulated internal electrodes, internal through main electrodes connected to respective sets of the internal electrodes, and terminal pads located on a bonding surface of the multilayer ceramic capacitor and connected to respective ones of the internal through main electrodes. [32] The method of claim 27, wherein the at least one of the one or more 3-D IC chips comprises first and second two-dimensional (2-D) IC chips, each having a substrate, the first and second 2-D IC chips being connected to each other such that the substrate of the first 2-D IC chip faces the substrate of the second 2-D IC chip. [33] The method of claim 32, wherein the substrate of at least one of the first and second 2-D IC chips is thinned prior to bonding. [34] The method of claim 27, wherein the at least one of the one or more 3-D IC chips comprises a first and a second two-dimensional, 2-D, IC chip, each having a substrate and a substructure / superstructure formed on the substrate, the first and second 2-D IC chips being connected to each other such that the substructure / superstructure of the first 2-D IC chip faces the substrate of the second 2-D IC chip. [35] The method of claim 27, wherein the at least one of the one or more 3-D IC chips comprises first and second two-dimensional, 2-D, IC chips, each having a substrate, a substructure formed on the substrate, and a superstructure formed on the substructure, wherein the first and second 2-D IC chips are connected to each other such that the substructure of the first 2-D IC chip faces the substrate of the second 2-D IC chip and the substrate of the first 2-D IC chip is removed. [36] The method of claim 27, wherein the at least one of the one or more 3D IC chips comprises a substrate having a first surface and a second surface opposite the first surface, the first surface being processed to form a combined substructure / superstructure on the first surface and the second surface being processed to form a combined substructure / superstructure on the second surface. [37] The method of claim 27, further comprising arranging at least two 3D IC chips horizontally spaced with respect to each other within the 3D IC structure. [38] The method of claim 15, further comprising arranging at least two 3D IC chips vertically spaced with respect to each other within the 3D IC structure.

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