Electronic device, p-contact structure and process for preparing the same

Abstract

A MQW LED active layer configured to emit deep UV light is contacted on its p-side by a Mg doped p-AlGaN electron blocking layer, a Mg doped p-AlN hole injection layer of 1-10nm thickness, a Mg doped p-GaN contact layer of 1-20nm thickness, and a p-side electrode contact. The contact layer can also be a one-dimensional nanowire or nanotube layer, a graphene layer, a two-dimensional selenide layer, a conductive oxide, amorphous carbon, or an aluminium free nitride semiconductor layer which is a contact barrier regulator.

Description

Field of the Invention This invention concerns an electronic device comprising a p-i-n or p-n junction, a hole injector, an intermediate layer and a p-contact; and a process for preparing the same. The invention also concerns a multilayer p-contact structure for an electronic device comprising a hole injector, intermediate layer and p-contact. Background There is a constant need to improve the efficiencies of semiconductor electronic devices based on p-n or p-i-n junctions, such as in LEDs or photodetectors. Certain semiconductor electronic devices, such as UV optoelectronic devices, e.g. deep UV light-emitting diodes (DUV LEDs) with light emission in the 200-300 nm wavelength range are in high demand, not only to replace traditional large and toxic mercury lamps, but to serve the fast-growing market of applications in the biomedical sector, such as sterilisation and water disinfection. Besides the obvious benefit of being non-toxic, nitride-based semiconductor LEDs also have the advantages of being much smaller, cost-efficient requiring only low voltages and therefore are highly integrable. Electronic devices such as DUV LEDs are commonly based on group-Ill nitride p-n- or p-i-n-junctions, mostly in thin film heterostructures. Their overall efficiency (wall-plug efficiency, WPE) describes the ability of the device to convert electrical input power to optical output power. Among the factors playing into the WPE are the internal quantum efficiency (IQE), light extraction efficiency (LEE) and electric efficiency (EE). The IQE is dependent on the quality and properties of the p-i-n-junction itself, whereas the LEE and EE are more connected to contacting and packaging of the LED. As of today, p-i-n-junctions are well developed, achieving recombination efficiencies (RE) of 80% or above (Guo-Dong Hao et al, 2020, J. Phys. D: Appl. Phys., 53, 505107), resulting in high IQEs. However, improvements can be made. In particular, achieving high electric efficiency (EE) and high light extraction efficiency (LEE) remain challenging for DUV LEDs in particular. One of the most limiting factors for the EE and LEE is the p-side contact material: in order to provide sufficient hole injection, it has to form a good ohmic contact to the p-type (typically wide-gap Ill-nitride semiconductor) underneath, but at the same time, the material of choice has to be transparent, e.g. for the emitting DUV light. Often, p-doped GaN is used on the p-side, since it can provide a good basis for ohmic contact and sufficient hole-injection; however, due to its low bandgap, the absorption coefficient, e.g. in the DUV range, is high, blocking almost all of the emitted light. New approaches such as superlattices or Al-content grading in the p-contact have been proposed; however, any improvement in transparency seems to have a negative effect on the electrical efficiency. The present inventors have fabricated a device which aims to increase the EE and LEE by using a very thin AIN hole-injector on top of the p-side of the p-n or p-i-n junction, as well as a very thin intermediate layer disposed on the hole injector before the metallic p-contact is fabricated. The present inventors have surprisingly shown that the use of the intermediate layer, disposed between the hole injector and the metallic p-contact, can enhance the emission intensity (e.g. by lowering contact resistance or improving hole injection) of the electronic device, which is attributed to a low barrier between the p-doped layers, thus maintaining an efficient vertical tunnelling current and injection of the activated holes into the valence band of the p-doped part of the p-n or p-i-n junction. Summary of Invention Thus, viewed from one aspect, the present invention concerns an electronic device comprising: (i) a p-i-n or p-n junction; (ii) a hole injector disposed on the p-side of the p-i-n or p-n junction comprising an AIN layer having a thickness of 10 nm or less; (iii) an intermediate layer having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide, amorphous carbon or an aluminium-free lll-N semiconductor; and (iv) a metallic p-contact disposed on said intermediate layer. Altematively, viewed from another aspect, the present invention concerns an electronic device comprising: (i) a p-i-n or p-n junction; (ii) a hole injector disposed on the p-side of the p-i-n or p-n junction comprising an AIN layer having a thickness of 10 nm or less; (iii) an intermediate layer having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer is a contact barrier regulator; and (iv) a metallic p-contact disposed on said intermediate layer. Viewed from another aspect, the present invention concerns a multilayer p-contact structure for an electronic device comprising: (ii) a hole injector disposed on the p-side of the p-i-n or p-n junction comprising an AIN layer having a thickness of 10 nm or less; (iii) an intermediate layer having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide, amorphous carbon or an aluminium-free lll-N semiconductor; and (iv) a metallic p-contact disposed on said intermediate layer. Alternatively, viewed from another aspect, the present invention concerns a multilayer p-contact structure for an electronic device comprising: (ii) a hole injector comprising an AIN layer having a thickness of 10 nm or less; (iii) an intermediate layer having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide, amorphous carbon or an aluminium-free lll-N semiconductor; and (iv) a metallic p-contact disposed on said intermediate layer. Viewed from yet a further aspect, the present invention concerns a process for preparing an electronic device as described herein, comprising: (a) forming a p-i-n or p-n junction; (b) forming a hole injector on the p-side of the p-i-n or p-n junction, wherein the hole injector comprises an AIN layer having a thickness of 10 nm or less; (c) forming an intermediate layer on the hole injector having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide, amorphous carbon or an aluminium-free lll-N semiconductor; and (d) forming a metallic p-contact on said intermediate layer. Viewed from another aspect, the invention provides a process for preparing the electronic device as defined herein, comprising the steps of: (a) forming a p-i-n or p-n junction; (b) forming a hole injector on the p-side of the p-i-n or p-n junction, wherein the hole injector comprises an AIN layer having a thickness of 10 nm or less; (c) forming an intermediate layer on the hole injector having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer is an aluminium-free contact barrier regulator; and (d) forming a metallic p-contact on said intermediate layer. Viewed from another aspect, the invention provides a process for preparing the multilayer p-contact structure as defined herein, comprising the steps of: (b) forming a hole injector, optionally on the p-side of the p-i-n or p-n junction, wherein the hole injector comprises an AIN layer having a thickness of 10 nm or less; (c) forming an intermediate layer on the hole injector having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide, amorphous carbon or an aluminium-free lll-N semiconductor; and (d) forming a metallic p-contact on said intermediate layer. The features of the aspects and / or embodiments indicated herein are useable individually and in combination in all aspects and embodiments of the invention where technically viable, unless otherwise indicated. Brief Description of Figures Figure 1 illustrates the structure of a particular embodiment of the present invention, wherein the electronic device comprises, from bottom to top, an AIN / Sapphire(0001) template (i.e. substrate); a n-current spreader comprising Si-doped Alo 53Gao 4?N (1500 nm); a n-contact layer comprising Si-doped Alo 4aGao 52N (400 nm); a multiple quantum well active region comprising a plurality of multiple quantum wells (Alo.4Gao.6N (2 nm)) and multiple quantum barriers (Alo6sGao32N (10 nm)); a p-type electron blocking layer comprising Mg-doped Alo.68Gao.32N (20-100 nm); a Mg-doped AIN hole injector (1-10 nm); a Mg-doped intermediate GaN layer (1 to 10 nm) and a metallic p-contact. Figure 2 illustrates the structure of a particular embodiment of the present invention, wherein the electronic device has a similar structure to that depicted in Figure 1, but wherein the Mg-doped intermediate GaN layer is substituted for a intermediate graphene layer comprising either a single or multiple sheets of graphene. Figure 3 illustrates a graphical comparison of the emission spectra fora UV LED with and without a p-GaN intermediate layer. Detailed Description of the Invention Viewed from one aspect, the present invention refers to an electronic device comprising: (i) a p-i-n or p-n junction; (ii) a hole injector disposed on the p-side of the p-i-n or p-n junction comprising an AIN layer having a thickness of 10 nm or less; (iii) an intermediate layer having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide, amorphous carbon or an aluminium-free lll-N semiconductor; and (iv) a metallic p-contact disposed on said intermediate layer. The electronic device may comprise (i) to (iv) in this order. Viewed from another aspect, the present invention refers to a multilayer p-contact structure for an electronic device comprising (ii) to (iv). The multilayer p-contact structure for an electronic device may comprise (ii) to (iv) in that order. The multilayer p-contact structure may further comprise a p-type group 11 l-V structure disposed on the hole injector e.g. the opposite side of the hole injector to the intermediate layer. As used herein, a multilayer p-contact structure refers to a plurality of layers which are disposed on the p-side of a p-n or p-i-n junction, wherein at least one layer has p-type doping. The wording “free from” preferably means the material comprises less than 5 % by weight, preferably less than 2 % by weight, especially less than 1 % by weight, such as less than 0.5 % or 0.1 % by weight of aluminium. The wording “free from” may refer to being substantially free from aluminium, as defined herein. Preferably, the lll-N semiconductor in the intermediate layer does not contain any Aluminium. The term “electronic device” includes, but is not limited to, any of the following a light emitting diode (LED), a laser, a photodetector or a transistor. When used herein the wording “device” should be interpreted as “electronic device”. An electronic device as referred to herein is a semiconductor device. It is typically preferred if the electronic device is an optoelectronic device, preferably a UV optoelectronic device. The term “UV optoelectronic device” refers to devices and systems which emit, find, detect and control light in the ultraviolet (UV) range of the electromagnetic spectrum. The UV range of the electromagnetic spectrum refers to light with a wavelength of 10 to 400 nm. The UV optoelectronic device may be selected from an ultraviolet A (UVA), an ultraviolet B (UVB) or an ultraviolet C (UVC) optoelectronic device, preferably a UVC optoelectronic device. As described herein, UVA refers to UV light with a wavelength of 315 to 400 nm, UVB refers to UV light with a wavelength of 280 to 315 nm and UVC refers to light with a wavelength of 100 to 280 nm. A preferable embodiment for the UV optoelectronic device is as a LED, preferably UVB or UVC LED, especially a UVC LED. The device may act as or be a flip chip device. For an optoelectronic device that can act as a flip chip device, the metallic p-contact layer will typically comprise or be a reflective layer which directs light, e.g. all light, back towards (and through) the layers / regions underneath, or the device may comprise an additional reflective layer disposed on the p-contact layer. For photodetectors, the light goes in the other direction, i.e. the reflective layer reflects light back onto the p-n or p-i-n junction. Therefore, the optoelectronic device may be or act as a flip chip and the metallic p-contact may comprise a reflective layer. Unless otherwise indicated, the term ‘on’ (as in a layer ‘on’ another region or layer) typically means ‘directly on’, i.e. without any intermediate layers or regions. The term also typically means ‘in electrical contact with’. Similarly, ‘in contact with’ typically means in ‘direct contact with’ or ‘in electrical contact with’. Unless otherwise stated, the term ‘bottom’ refers to the substrate side of the device, and the term ‘top’ refers to the p-contact side of the device. The terms are meant as relative terms only and may not reflect final positioning in the device. p-n or p-i-n Junction The electronic device of the present invention comprises a p-n or a p-i-n junction. The p-n or p-i-n junction is typically composed of a number of regions or layers disposed on a substrate. Whilst the term ‘layer’ is used herebelow, the device is not so limited and any discussion of layers may also apply to regions without any particular dimensional limitation, unless otherwise stated. The layers may be in the form of heterostructured thin films (i.e. continuous layers) disposed on a substrate with different types of doping. In an alternative embodiment, the p-n or p-i-n junction may be in the form of or comprise heterostructured nanostructures (e.g. nanowires or nanopyramids) disposed on a substrate. The wording “disposed on” refers to the formation of an electrical contact. It is preferred if the n-side of the p-i-n or p-n junction is disposed on the substrate. The substrate is typically disposed on the underside of the n-side of the p-i-n or p-n junction. The substrate as defined herein is not particularly limited. It is preferred if the substrate is a crystalline substrate. The substrate may comprise a single layer or multiple layers. At least one of the substrate layers is typically semiconducting and is preferably undoped. However, the substrate may be doped. In certain cases, the substrate is doped. The wording “substrate”, “support” and “template” may be used interchangeably herein. The substrate may have a crystal orientation of

[111] ,

[110] ,

[0001] or

[100] perpendicular to the surface.

[0001] is preferred. The substrate may be selected from: sapphire, silica (SiO2), quartz, alumina (AI2O3), Si, SiC, Ga2O3, graphene, or group lll-V semiconducting compounds. As referred herein, “group lll-V semiconducting compounds”, “group lll-V compounds” and “lll-V compounds” can all be used interchangeably. For substrate group lll-V semiconducting compounds, group III options are B, Al, Ga, In, and Tl. Preferred options here are Ga, Al, B and In, preferably Ga, Al, and In. Group V options are N, P, As, Sb. N is preferred. The lll-V compounds may be binary, ternary, quaternary, quintinary etc. The substrate may comprise ternary compounds and may be represented by formula XYZ wherein X is a group III element, Y is a group III different from X, and Z is a group V element. The X to Y molar ratio in XYZ is preferably 0.01-0.99, e.g. 0.1 to 0.9, i.e. the formula is preferably XxYi.xZ where subscript x is 0.01-0.99, e.g. 0.1 to 0.9. The substrate may comprise quaternary compounds and may e.g. be represented by the formula AxBi.xCyDi-y where A and B are group III elements and C and D are group V elements or AxByCi-x-yD where A, B and C are group III elements and D is a group V element. Again, subscripts x and y are typically 0.01-0.99, e.g. 0.1 to 0.9. Other options will be clear to the skilled person. It is preferred if the substrate is selected from AIN or sapphire, or a combination of AIN and sapphire, preferably AIN on sapphire. The thickness of the substrate is not particularly limited, but preferably is in the range of 0.1 to 2000 pm, such as 10 to 1000 pm, especially 100 to 1000 pm. In the preferred case of AIN on sapphire, comprising two layers, the individual thickness of the AIN layer is in the range of 1 to 10000 nm, such as 10 to 1000 nm, especially 20 to 500 nm, and the individual thickness of the sapphire is 100 to 2000 pm, especially 100 to 1000 pm. The substrate may be transparent or substantially transparent. Transparent as defined herein typically covers transparency across all UV wavelengths (i.e. for UV optoelectronic devices). Preferably the substrate is transparent or substantially transparent to UVC wavelengths. The p-n or p-i-n junction of the present invention comprises (or consists of) a p-type region, and n-type region and optionally an intrinsic (i) region. In the case of the p-i-n junction, when charge carriers (e.g. holes and electrons) are injected into the respective p-type and n-type regions, they recombine in the i-region, wherein the recombination generates light. For the p-n junction, recombination will occur in the space charge region (as there is no intrinsic region). It is therefore preferred if the electronic device herein comprises a number of layers comprising group lll-V semiconducting compounds which are doped. Doping described below refers to doping with respect to any feature across all aspects of the invention herein, whether the regions of the p-n / p-i-n junction, hole injector, intermediate layer etc. Doping typically involves the introduction of impurity ions into the layer, e.g. during epitaxial growth. The doping level can be controlled from ~ 1015 / cm3to 1022 / cm3, preferably 1016 / cm3to 1021 / cm3, preferably 1017 / cm3to 1020 / cm3, preferably 1018 / cm3to 1019 / cm3. The n-type region has a larger electron concentration than hole concentration by doping with donor impurities. Suitable donor impurities for the n-type region include Te, Sn, Si, Ge and C. The n-type region may be in the form of a single layer or multiple layers. It is especially preferred if the n-type region comprises at least one layer which is Si-doped. The p-type region has a larger hole concentration than electron concentration by doping with acceptor impurities. Suitable acceptor impurities for the p-type region include Be, Mg and Zn. The p-type region may be in the form of a single layer or multiple layers. It is especially preferred if the p-type region comprises at least one layer which is Mg-doped. Si can be amphoteric and can act as a donor or acceptor, depending on the site where Si goes to, the orientation of the growing surface and the growth conditions. The intrinsic region may consist of a single layer of material or a heterostructure consisting of multiple quantum wells and barriers. Typically, the intrinsic layer is a multiple quantum well. The intrinsic region typically acts as the light emitting layer, in the case of light emitters (such as LEDs), or as the light absorbing layer, in the case of absorbers (e.g. photodetectors). The intrinsic region is preferably a multiple quantum well (MQW) comprising a number of quantum well layers and a number of barrier layers alternatively stacked, preferably wherein the multiple quantum well comprises 3-10 repetitions of well and barrier layers. Typically, the intrinsic layer / region is positioned directly between the p-type and n-type regions. The p-n or p-i-n junction may comprise at least one electron blocking layer, preferably disposed directly on the intrinsic region, preferably wherein the electron blocking layer is p-doped. “Directly” as used herein across all aspects of this invention typically refers to direct contact between two regions or layers. The electron blocking layer is selected from a group 11 l-V semiconducting compound as defined herein. The electron blocking layer typically forms part of the p-type region of the p-n or p-i-n junction. The p-side of the p-i-n junction may also comprise an additional lll-V layer (e.g. a thin p-GaN layer) in its uppermost region (see discussion below) The p-n or p-i-n junction may comprise at least one current spreader or a current spreader layer. Preferably the current spreader will be n-doped, and thus forms part of the n-type region of the p-n or p-i-n junction. The current spreader will also preferably be selected from a group lll-V semiconducting compound as defined herein. The n-region may comprise two or more different n-doped lll-V regions, differing in their atomic ratios or carrier concentration. The n-region may comprise, for example, two different n-AIGaN regions or layers. One may be an n-contacting region, which is in contact with the light emitting or light absorbing (i.e. intrinsic) region. This n-contacting layer may be disposed on the n-current spreader region. The n-current spreader is typically in contact with the substrate (i.e. located between the substrate and the n-contacting layer). The n-current spreader may have, for example a larger Al concentration than the n-contacting layer. The p-n or p-i-n junction will typically comprise at least one n-type group III-V (preferably 11 l-N) semiconducting compound and at least one p-type group lll-V (preferably Ill-N) semiconducting compound. In addition to the at least one p-type and n-type group lll-V semiconducting compounds, the p-n or p-i-n junction may comprise an undoped group lll-V (preferably lll-N) semiconducting compound. The group lll-V semiconducting compounds refer to any as described herein across all aspects of the invention. For the group lll-V semiconducting compounds, group III options are B, Al, Ga, In, and Tl. Preferred options here are Ga, Al, B and In, preferably Ga, Al, and In. Group V options are N, P, As, Sb, but N is preferred. The lll-V compounds may be binary, ternary, quaternary, quintinary etc. Ternary is preferred, in particular ternary lll-N. Compounds based on Al, Ga and In in combination with N are preferred. Compounds based on Al and Ga in combination with N are particularly preferred. Preferably the lll-V compounds comprise at least Al. For ternary group lll-V compounds of formula XYZ (wherein X is a group III element, Y is a group III different from X, and Z is a group V element) the X to Y molar ratio in XYZ is preferably 0.01 to 0.99, e.g. 0.1 to 0.9, i.e. the formula is preferably XxY-i.xZ where subscript x is 0.01 to 0.99, e.g. 0.1 to 0.9. In a preferred embodiment, subscript X is 0.4 to 0.7. AlxGa^xN, wherein x is in the range of 0.4 to 0.7 is particularly preferred, therefore. It is further preferred if the value of x differs between the different regions of the p-i-n or p-n junction. In a preferably embodiment, each region (e.g. p-, n- and optionally i-region) may comprise (or consist of) one or more layers of group lll-V semiconducting compounds of formula XYZ which differ in their value of x. The regions may alternatively or additionally differ in the nature of the dopant or the doping concentration. Quaternary compounds for the p-n or p-i-n junction may be represented by the formula AxBi.xCyDi.y where A and B are group III elements and C and D are group V elements or AxByC-i.x.yD where A, B and C are group III elements and D is a group V element. Again, subscripts x and y are typically 0.01-0.99, e.g. 0.1 to 0.9. Other options will be clear to the skilled person. AIGaN, InAIN, InAIGaN, and InGaN are most preferred, especially AIGaN. Preferably, for UV applications in particular, the p-n or p-i-n junction does not comprise InGaN, since InGaN is not suitable for UV / UVC applications. In a preferred embodiment, the p-n or p-i-n junction will comprise (or consist of) at least one layer of p-AIGaN, at least one layer of n-AIGaN and at least one layer of i-AIGaN. Preferably, the p-n junction or p-i-n junction does not comprise GaN, other than an optional thin p-GaN layer (0-1 nm) in the uppermost region of the p-region (see discussion below), e.g. located on top of a p-AIGaN layer in the p-side of the p-n or p-i-n junction. Preferably the device does not comprise a GaN region or layer other than the intermediate layer defined herein and the thin optional p-GaN layer (0-1 nm) located on the uppermost region of the p-region. Preferably any GaN present in the device is limited to a thickness of 20 nm or less, preferably 10 nm or less. The thickness of each region or layer in the p-n or p-i-n junction is not particularly limited, but preferably is in the range of 10 to 2500 nm, such as 1000 to 2000 nm or 50 to 500 nm. In certain embodiments, the p-n junction will comprise at least one layer which is 10 nm or less, such as 0.1 to 5 nm. The thickness of the p-region of the p-n or p-i-n junction may be 20-100 nm. The thickness of the intrinsic region may be 10-100 nm, for example. The thickness of the n-region of the p-n or p-i-n junction may be 500 nm to 2500 nm. The thickness of the n-contacting layer may be 100 nm to 1000 nm. The thickness of the n-current spreader may be 500-2000 nm. The electronic device may comprise an additional lll-V layer as an uppermost layer of the p-side of the p-i-n junction. In such an instance, the hole injector is disposed on the additional lll-V layer. The additional lll-V layer may be considered to form part of the p-side of the p-i-n or p-n junction. The additional group lll-V layer may therefore be disposed on the underside of the hole injector. The additional lll-V layer preferably comprises or consists of p-GaN. The thickness of the p-GaN additional layer is preferably 10 nm or less, such as 0.2 to 2.0 nm. Without being bound by theory, the presence of a p-GaN additional layer between the hole injector and the p-side of the p-n or p-i-n junction facilitates vertical hole injection by further increasing the charge density in the hole injector and / or through the formation of two-dimensional hole gas which can lower the activation energy for acceptors, creating holes in the hole injector. In certain cases, the p-n or p-i-n junction may be part of, in the form of, or comprise a heterostructured nanostructure or microstructure. ‘Nanostructure’ may herein mean a nanowire (also termed a nanorod, nanopillar, nanocolumn or nanowhisker), a nanopyramid, or a nanoribbon. Any discussion of nanostructures herein equally applies to microstructures, where technically viable. The term nanowire is used herein to describe a solid, wire-like structure of nanometer dimensions. Nanowires preferably have an even diameter throughout the majority of the nanowire, e.g. at least 75% of its length. Nanowires may have tapered end structures. The nanowires can be said to be in essentially in onedimensional form with nanometer dimensions in their width or diameter and their length typically in the range of 100 nm to a few (e.g. 5) pm. Preferably the nanowires are at least 1 micrometer in length. Where a plurality of nanowires are grown, it is preferred if at least 90%, preferably all, meet these dimension requirements. Ideally, at least 90% of the nanowires grown on a substrate will be at least 1 micrometer in length. Preferably substantially all the nanowires will be at least 1 micrometer in length. Ideally the nanowire diameter / width is not greater than 1000 nm. Ideally the nanowire diameter / width is between 10 and 1000 nm, e.g. 50 and 500 nm. Ideally, the diameter at the base of the nanowire and at the top of the nanowire should remain about the same (e.g. within 20% of each other). The term nanopyramid refers to a solid pyramidal type structure. The term pyramidal is used herein to define a structure with a base whose sides taper to a single point generally above the centre of the base. It will be appreciated that the single vertex point may appear chamfered, e.g. such that the pyramid has a flat top. Typically, the chamfered portion is equivalent to less than 50%, e.g. less than 40%, e.g. less than 30%, e.g. less than 20%, e.g. less than 10%, e.g. less than 5% of the total length of the nanopyramid edge. The nanopyramids may have multiple faces, such as 3 to 8 faces, or 4 to 7 faces. Thus, the base of the nanopyramids might be a triangle, square, pentagonal, hexagonal, heptagonal, octagonal and so on. The pyramid is formed as the faces taper from the base to a central point (forming therefore triangular faces). The triangular faces are normally terminated with {1 -101} or {1-102} planes. The triangular side surfaces with {1-101}facets could either converge to a single point at the tip or could form new facets ({1-102} planes) before converging at the tip. These 4-digit indices are typically most appropriate for hexagonal crystals. In some cases, the nanopyramids are truncated with its top terminated with {0001} planes. The base itself may comprise a portion of even cross-section before tapering to form a pyramidal structure begins. The thickness of the base may therefore be up to 500 nm, e.g. up to 200 nm, such as 50 nm. The base of the nanopyramids can be between 50 and 500 nm in diameter across its widest point. In another embodiment, the base of the nanopyramids can be 200 nm to one micrometer in diameter across its widest point. The height of the nanopyramids may be 200 nm to a few (e.g. 5) micrometers, such as 400 nm to 1 micrometer in length. In certain cases, the nanostructure may be etched to form a corrugated / ridged design. For example, the nanostructure may be etched to form a nanopyramid. Etching the nanostructure may, in certain cases, improve the light extraction or absorption efficiency of the device. It is preferred for nanostructures to have an epitaxial relationship with the substrate. The term epitaxy comes from the Greek roots epi, meaning "above", and taxis, meaning "in ordered manner". The atomic arrangement of the nanostructure is typically based on the crystallographic structure of the substrate. Epitaxial growth means herein the growth on the substrate of a nanostructure or microstructures that mimics the orientation of the substrate. Heterostructured nanostructures may be axially heterostructured or radially heterostructured. It is generally preferred for any nanostructure to be axially heterostructured. In cases where at least some of the nanostructures are radially heterostructured, the nanostructures may coalesce, thus having an appearance of a continuous or partially continuous film opposed to individual nanostructures. For any case where the p-n or p-i-n junction is in the form of a plurality of heterostructured nanostructures, the n-type region may be in the form of the nanostructure core and the p-type region, and optionally intrinsic region, may be in the form of additional layers on the core or vice versa. The nanostructure core is herein defined as the (innermost) part of the nanostructure which grows first on the substrate, and / or which is in physical contact with the substrate. For any case where the p-i-n or p-n junction is in the form of a heterostructured film, the film may be planar or non-planar. Any thin film present in the p-i-n or p-n junction preferably has an epitaxial relationship with the substrate. Typically, the regions within the p-n or p-i-n junction are epitaxial with each other. The region of the p-i-n or p-n junction (e.g. n-region) which is in contact with the substrate is typically epitaxial with the substrate. In the case of a thin film which is non-planar, it may have a corrugated structure or parts which are semipolar (e.g. pyramidal). Semipolar as referred herein refers to planes which are not vertical (i.e. non-polar) or horizontal (polar). A non-planar structure may be beneficial in certain cases as it can enable good light extraction for transverse-magnetic (TM) polarisation, a larger emitting area, higher doping levels, better tunnelling, or improved strain management by elastic deformation. In alternative cases, a planar thin film is alternatively preferred, as it may reduce the carrier activation energy in the hole injector by polarization-assisted acceptor ionization or it may improve simplicity and cost structure of device fabrication. The layers or regions of the p-n or p-i-n junction are preferably conformal with each other (i.e. the structure or shape of an upper region / layer matches that of the underlying layer / region) The p-n or p-i-n junction is preferably conformally formed on the substrate. Hole Injector The hole injector of the present invention is disposed on the p-side (i.e. on the p-region or p-layer) of the p-n or p-i-n junction. For example, the hole injector is directly in contact with the p-side of the p-n or p-i-n junction. The hole injector, which may be referred interchangeably as the hole injector layer, comprises or consists of an AIN layer with a thickness of 10 nm or less. Preferably the hole injector comprises or consists of p-AIN. Preferably the p-AIN is doped with Mg. Moreover, in the case of a hole injector comprising undoped AIN, some intrinsic holes are considered to be present thus enabling this material to act as a hole injector. A main source of holes is the externally applied current at the p-contact metal, providing and pushing the holes from the p-contact metal towards the MQW. While the intermediate layer might be seen as a moderating metal-like hole reservoir, a key function of the hole injector is to take and transfer holes to the p-side of the p-n or p-i-n junction (EBL in particular). P-doping of the hole injector increases efficiency of the device as additional hole carriers are generated. The hole injector typically consists of an AIN layer (e.g. a p-AIN layer) with a thickness of 10 nm or less. It is especially preferred if the thickness of the AIN layer (e.g. p-AIN layer) is in the range of 1 to 9 nm, such as 4 to 8 nm. Such a thin hole injector layer is beneficial for enabling efficient hole injection from the p-contact metal into the p-side of the p-n or p-i-n junction via polarization-enhanced conduction and / or tunnelling. Efficient hole injection means no extra voltage required for the hole injection mechanism itself, leading to reduced heating, reduced thermal stress or other detrimental effects for device performance, e.g. lifetime. Especially, such a thin hole injector layer is not insulating, which would be considered for thicker AIN layers (e.g. p-AIN layers) . The AIN layer (e.g. p-AIN layer) can act as (or is) a tunnel barrier, e.g. for carrier tunnel injection from the intermediate layer to the p-side (e.g. p-AIGaN layer) of the p-n or p-i-n junction. Having a thin AIN layer (e.g. p-AIN layer) is important for the electronic properties. The thinner the AIN layer (e.g. p-AIN layer), the better the tunnelling between the intermediate layer and the p-side (e.g. p-AIGaN layer) of the p-n or p-i-n junction. AIN layers (e.g. p-AIN layers) that are much thicker than the above thicknesses may typically not exhibit the beneficial tunnelling required, and hence will have poor tunnelling efficiency. The hole injector of the present invention is under a tensile strain which induces polarisation / intrinsic electrical fields that aid vertical injection of carriers and tunnelling. Without being bound by theory, tilting of the bandstructure may lower the acceptor (Mg) activation energy and a hole gas may form at the interface. Furthermore, intraband tunnelling of the activated holes into the valence band is promoted with the increase of the intrinsic electric field. Thus, more efficient hole current injection can be achieved than with the traditional p-AIGaN cladding layer approach, where the activated dopant concentrations are typically very low. An additional benefit is the improved contact to the metallic p-contact layer with the increase of dopant concentration. The strain state of the hole injector is affected by the underlaying layers, especially the n-side of the p-i-n orp-n junction (e.g. n-AIGaN) which is typically thick. The lattice mismatch between the hole injector and the underlaying layers, and the resulting strain, depends on the strain state of the underlying layers and with that on their thickness and the Al-composition. For example, the n-side of the p-i-n or p-n junction (e.g. n-AIGaN) is typically slightly relaxed with respect to the template (i.e. substrate) when the template comprises AIN on sapphire as discussed earlier. This causes a lattice mismatch between the n-AIGaN and the hole injector (e.g.p-AIN), resulting in tensile strain. This gives rise to the piezoelectric polarization field, which can be tuned by the thickness of the hole injector (e.g. p-AIN) or the strain state of the n-side layers. The geometry of the hole injector is not particular limited, and can be aligned to the layer(s) underneath (e.g. the layer(s) or nanostructures which form the p-i-n or p-n junction). Typically, the hole injector is planar. Alternatively, the hole injector may be semipolar. A semipolar hole injector may be preferred as it may benefit the light extraction or absorption efficiency. The hole injector may be in the form of a thin film. Alternatively, the hole injector may be part of, or disposed on, nanostructures, as defined herein for any aspect of the invention. The hole injector may completely cover or substantially cover the p-side of the p-i-n or p-n junction. The hole injector may continuously cover at least a portion of the p-side of the p-i-n or p-n junction, e.g. at least 50% of the p-side of the p-i-n or p-n junction, such as at least 75%, at least 90% or at least 99% of the p-side of the p-i-n or p-n junction. The hole injector is preferably conformally formed on the p-side of the p-n or p-i-n junction. Intermediate Layer The intermediate layer of the present invention comprises a onedimensional material or is selected from a two-dimensional material, a conductive oxide, amorphous carbon or an aluminium-free lll-N semiconductor. Typically, the intermediate layer is free from aluminium. The intermediate layer herein is disposed on the hole injector. For example, there is a direct contact between the hole injector and the intermediate layer. The intermediate layer may be referred to as a contact barrier regulator or contact barrier reducer, for example. These terms mean intermediate layers that regulate or lower the electrical contact barrier between the p-doped part of the p-n or p-i-n junction and the metal contact (thus maintaining an efficient vertical current and injection of holes into the valence band of the p-doped part of the p-n or p-i-n junction). Any discussion herein relating to the intermediate layer may apply to ‘the contact barrier regulator1. The intermediate layer of the present invention has a thickness of 20 nm or less. Typically, it is difficult to achieve an ohmic contact directly to the (e.g. p-AIN) hole injector, and exotic metals such as Rh or the more common Pd are commonly used. However, there is usually a penalty of Schottky barrier, higher forward voltage (Vf) or reduced reliability. The use of the intermediate layer as defined herein has proven to result in a low contact barrier, lower than the contact barrier when only a hole injector (e.g. p-AIN) is used, as demonstrated in the Examples. The use of the intermediate layer as defined here further enables the use of more common and proven metals to be used as an ohmic contact, including reflective materials. The use of an intermediate layer comprising or consisting of a lll-N semiconductor which is aluminium-free may be beneficial because it would prevent unintended AIGaN alloy clustering and / or AIGaN phase separation in the intermediate layer, improving lateral uniformity. Moreover, Al-free intermediate layers typically have a lower band gap, resulting in a lower resistance and / or avoiding voltage penalty. When used herein, the term two-dimensional material refers to a material with a layered structure e.g. one formed with a structure formed of sheets stacked on top of each other, preferably wherein the sheets are held together by van der Waals forces. When used herein, the term one-dimensional material refers to an amorphous, polycrystalline, or crystalline material where any charge carriers are confined to one dimension and cannot move freely in other dimensions, typically due to having a physical size in the nanometer scale in the confined dimensions, with a greater length on the micrometer scale or larger in the free dimension. The two-dimensional material may be graphene, silicene, hexagonal-BN (h-BN), M0S2, WS2, MoSe2, NbSe2, TaSe2, Bi2Te3, Bi2Se3 orNiTe2. The one-dimensional material may comprise or be nanotubes or fullerene-type materials. When the intermediate layer comprises a one-dimensional material, it typically means the intermediate layer comprises a plurality of nanotubes (or fullerenes) forming a mesh, e.g. a randomly oriented interpenetrating network structure. In other words, the intermediate layer may be a film of nanotubes and / or fullerenes. Nanotubes may include, but are not limited to, any of the following: carbon nanotubes (CNT), boron nitride nanotubes (BNNT), silicon carbide nanotubes (SiCNT), aluminium nitride nanotubes (AINNT) or combinations thereof, or any fullerene-type structures based on these materials. For amorphous carbon, it is preferable for a thin sheet to be used of thickness 10 nm or less, especially 5 nm or less. The conductive oxide is preferably a transparent conductive oxide. Indium tin oxide (ITO) is preferred as the conductive oxide. Whilst graphene is preferred, other ‘graphene-like’ materials with onedimensional or two-dimensional structures are therefore suitable herein, e.g. silicene, hexagonal-BN, carbon nanotubes (CNT), boron nitride nanotubes (BNNT), M0S2, WS2, MoSe2, NbSe2, TaSe2, Bi2Te3, Bi2Se3, orNiTe2. The intermediate layer may therefore comprise or consist of graphene, silicene, hexagonal-BN, carbon nanotubes (CNT), boron nitride nanotubes (BNNT), M0S2, WS2, MoSe2, NbSe2, TaSe2, Bi2Te3, Bi2Se3, or NiTe2. The term graphene refers to a planar sheet of sp2-bonded carbon atoms in a honeycomb (hexagonal) crystal structure. It is especially preferred if the intermediate layer consists of graphene. Whilst it is preferred to use graphene, it is also possible to use derivatives of graphene, such as those with surface modification. Therefore, the graphene intermediate layer may comprise or consist of a derivative of graphene. For example, hydrogen atoms can be attached to the graphene surface to form graphane. Graphene with oxygen atoms attached to the surface along with carbon and hydrogen atoms is called as graphene oxide. Graphitic herein typically means graphene, graphane or graphene oxide. The surface modification can be also possible by chemical doping or oxygen / hydrogen or nitrogen plasma treatment. The intermediate layer may comprise or consist of single- or multilayer graphene. Single or multilayer as used herein refers to the number of sheets of graphene. The interplanar spacing in graphene is around 0.3 nm, e.g. 0.335 nm. The intermediate layer should ideally contain 10 sheets or less of two-dimensional material (e.g. graphene or graphene-like material), preferably 5 sheets or less, preferably 4 sheets or less, preferably 3 sheets or less, preferably 2 sheets or less of two-dimensional material. Preferably the intermediate layer should contain 1-5 sheets, preferably 1-4 sheets, preferably 1-3 sheets, preferably 1-2 sheets of two-dimensional material, most preferably 1 sheet of two-dimensional material (i.e. a monolayer of graphene or graphene-like material). Especially preferred, the intermediate layer is a one-atom-thick planar sheet of graphene. In the case of graphene or graphene derivatives for the intermediate layer, particularly efficient tunnelling (see discussion below) through the intermediate layer is obtained when the intermediate layer is thin, e.g. one or two atomic layers thick, preferably when the intermediate layer is a one-atom thick sheet of graphene. Any graphene used in the intermediate layer is preferably used without surface modification. The intermediate layer may be doped, as described in relation to any aspect of the invention reported herein. Doping may help to improve the electrical conductivity of the intermediate layer. For intermediate layers which are doped, it is preferable for p-type doping to be used. If the intermediate layer comprises or consists of graphene, said graphene is preferably undoped. Using undoped graphene for the intermediate layer is beneficial because it preserves the atomical thinness of graphene, avoids contamination or damage typically associated with doping and facilitates ease of processing. Alternatively, it may be preferable if the graphene is doped as it may allow the contact barrier to be lowered. Graphene is well known for its superior optical, electrical, thermal and mechanical properties. Graphene is very thin but very strong, light, flexible, and impermeable. An intermediate layer comprising graphene is typically not under biaxial compressive strain, but it may lower the Schottky barrier between the hole injector and the metallic p-contact, reducing the resistance and facilitating tunnelling. Carbon nanotubes are another polymorph of sp2-bonded carbon closely related to graphene. They can be understood as one or more graphene strips which are rolled and closed into covalently bonded cylinders. The tubes may be single walled nanotubes (SWCNT), or multi-walled nanotubes (MWCNT) which comprise two or more concentrically nested SWCNTs. CNTs may be open at the end faces of the cylinder, or include fullerene-like geodesic structured end caps. CNTs share many chemical properties with graphene, particularly regarding bonding, passivation, doping, and functionalization of the sidewalls. Additionally, if carbon end caps are not present, open edges of CNT cylinders may be readily functionalized chemically for many purposes including tuning of chemical and electrical properties. SWCNTs have diameters between approximately 0.4 nm - 2.0 nm. MWCNTs may have larger diameters up to approximately 40 nm. The length of CNTs can vary widely from <1 nm to >10 cm, though typical lengths are in the micrometer scale. (0.5 pm - 10 pm). In MWCNTs, the spacing between walls is typically about 0.3 - 0.4 nm, similar to the spacing between layers in multi-layer graphene or bulk graphite. SWCNTs have an extremely high tensile strength in the longitudinal direction of approximately 100 GPa, with MWCNTs and CNT bundles showing lower strength due to shear between non-covalently bonded shells and tubes. However, CNTs are extremely compliant to bending, as the sidewalls can readily form kinks with little strain of their covalent bonds. As a result, CNTs can easily form cable-like bundles, unstructured mats, or more ordered arrangements depending on their processing, and can be conformally applied to non-flat or rough surfaces, e.g. nano-faceted crystals. The electronic and thermal properties of CNTs are distinct from graphene in that they vary widely based on the structure of the tube. While single-layer graphene (SLG) can be understood as a zero-bandgap semiconductor or semimetal which is functionally conductive, SWCNTs may have a bandgap varying from 0 eV to about 2.5 eV, depending on the diameter and orientation of the tube cylinder axis with respect to the symmetry of the graphene lattice comprising the sidewall. CNTs with a zero bandgap are referred to as metallic tubes, while CNTs with a bandgap larger than zero are referred to as semiconducting tubes. MWCNTs may contain shells with differing symmetries, and their electronic properties are a hybrid of all sub-shells, typically close to metallic in nature. CNTs generally exhibit significant optical absorption, particularly at UV wavelengths. However, a well-dispersed and thin mat of CNTs can have a high transparency due to the relatively high void percentage. Thus, CNT coatings can be used to realize optically transparent conductive layers, with a trade-off between inplane conductivity and transparency. In addition to carbon, nanotubes with comparable structures may be formed from other materials with similar bonding, notably boron nitride (BNNTs), silicon carbide (SiCNTs), and aluminium nitride (AINNTs). BNNTs are functionally insulators, with a wide bandgap around 5.5 eV, while AINNTs are semiconductors and SiCNTs are semimetals or semiconductors. Composite nanotubes have also been formed, notably boron nitride I carbon composites (BNCNTs) with intermediate properties between the two species. In certain cases, an encapsulation layer may be present which is disposed on the two-dimensional or one-dimensional material. The encapsulation layer would typically be disposed on the intermediate (e.g. graphene) layer on an area of the intermediate layer which is not covered by a metallic p-contact, e.g. adjacent to the metallic p-contact. Therefore, the encapsulation layer may cover at least a portion of the intermediate layer, e.g. at least 5% of the intermediate layer, such as at least 20% of the intermediate layer, such as at least 50% of the intermediate layer, at least 75% or at least 90% of the intermediate layer. The encapsulation layer, where present, typically comprises an oxide, e.g. alumina, silica. The encapsulation layer may prevent degradation of the intermediate layer (e.g. graphene), and could also be used for indirect p-doping to enhance contact properties. The intermediate layer, in particular graphene, may be patterned. Patterning may be used to enhance adhesion and / or anchor the metallic p-contact and / or any encapsulation layer. Patterning is a known technique in the art, and includes the formation of voids or defects, e.g. using conventional lithography techniques such as photo / e-beam lithography, nanoimprinting, focussed ion beam technology etc. The skilled person would be familiar with this term. The voids here refer to physical holes with a diameter of 5 pm or less, such as 1 to 5 pm. Ideally the voids will have a diameter of 500 nm or less, such as 20 to 200 nm. Without being bound by theory, when the intermediate layer is graphene, patterning may enhance carrier transfer in / out of graphene via the altered bonding states at the unterminated edges. The intermediate layer may comprise a group lll-N semiconductor which is free from aluminium. In an especially preferred embodiment, the intermediate layer consists of a group lll-N semiconductor which is free from aluminium. The intermediate layer in this instance comprises or consists of an Al-free lll-N semiconductor layer or film, e.g. a continuous Al-free lll-N semiconductor layer or film. The Al-free aspect does not necessarily cover the one-dimensional materials, which may comprise aluminium nitride nanotubes (AINNT), for example. For the intermediate layer, group III options for the group lll-N semiconductor include B, Ga, In, and Tl. Group III does not include Al for the lll-N semiconductor intermediate layer. It is especially preferred if the group III element is Ga. Therefore, it is preferred if the intermediate layer comprises or consists of GaN. Preferably the intermediate layer will comprise a group lll-N semiconductor which is free from aluminium, such as GaN, which is p-doped. The nature of doping for the intermediate layer corresponds to any form of doping described herein across all aspects of the invention. For intermediate layers which are doped, it is preferable for p-type doping to be used. Preferably, the intermediate layer will comprise or consist of GaN which has been doped with a p-type dopant (i.e. acceptor) such as Mg. When the intermediate layer comprises a group lll-N semiconductor which is free from aluminium, the intermediate layer may be in the form of a film or part of nanostructures, as previously defined for any aspect of the invention defined herein. The present inventors have surprisingly shown that the use of an intermediate layer disposed between the hole injector and the metallic p-contact can enhance the emission intensity (e.g. by lowering contact resistance or improving hole injection), which is attributed to a low barrier between the p-doped layers, thus maintaining an efficient vertical tunnelling current and injection of the activated holes into the valence band of the p-doped part of the p-n or p-i-n junction. This is particularly surprising for devices wherein the intermediate layer comprises GaN semiconductor, which is known to absorb UV light. Traditionally, p-GaN is a strong absorber of UV light and thus precise control of the thickness of the intermediate layer comprising this material must be taken to enable efficient emission of light. Moreover, the intermediate layer will have a thickness of 20 nm or less, preferably 10 nm or less, in order to reduce absorption of emitted light (e.g. UV light for UV optoelectronic applications) as far as possible. The intermediate layer may be transparent or substantially transparent. Transparent as defined herein covers transparency across the wavelengths of interest, e.g. UV wavelengths, in particular UVC wavelengths. However, it is not a requirement for the intermediate layer to be transparent, and it is surprising that emission properties are increased even when non-transparent materials are used, e.g. p-GaN. Typically, electronic devices as defined herein where the intermediate layer is transparent or substantially transparent could be used as top emitting structures, flip chip devices with reflecting p-contacts or vertically integrated devices, but the invention is not so limited. In terms of metric thicknesses, it is preferred if the intermediate layer is 20 nm in thickness or less, preferably 10 nm in thickness or less, preferably 5 nm or less, such as 2 nm or less. The intermediate layer is ideally less than 1.5 nm in thickness. Even more preferably, the intermediate layer may be 1 nm or less in thickness, more preferably 0.9 nm or less in thickness, more preferably 0.8 nm or less in thickness, more preferably 0.7 nm or less in thickness, more preferably 0.6 nm or less in thickness, more preferably 0.5 nm or less in thickness. Preferred thickness ranges include 0.1 to 20 nm, such as 0.2 to 10 nm, preferably 0.3-2 nm, preferably 0.3-1.5 nm, e.g. 0.3-1 nm, 0.3-0.9 nm, 0.3-0.8 nm, 0.3-0.7 nm e.g. 0.3-0.5 nm. Monolayer GaN has a thickness of 0.25 nm and thus this also represents an appropriate minimum for the thickness. In case of hole injection into the p-AIGaN layer by a tunnelling mechanism the intermediate layer acts as a hole reservoir and starting point enabling more effective hole tunnelling from the intermediate layer through the hole injector (e.g. p-AIN layer) into the p-side (e.g. p-AIGaN layer) of the p-n or p-i-n junction. The intermediate layer may further moderate the energy step to the hole injector (e.g. p-AIN layer), thus improving the tunnelling by reducing the barrier height. In the case of polarization-enhanced hole injection into the p-side (e.g. p-AIGaN layer) of the junction the intermediate layer may induce additional strain to the (e.g. p-AIN) hole injector, thus enhance polarization fields, hole density and conductivity. Preferably, the intermediate layer will not act as the metallic p-contact as a current spreader or as an electrode. In certain cases, the intermediate layer will completely cover or substantially cover the hole injector. The intermediate layer may continuously cover at least a portion of the hole injector, e.g. at least 50% of the hole injector, such as at least 75%, at least 90% or at least 99% of the hole injector. The intermediate layer is preferably conformally formed on the hole injector. P-contact The electronic device and multilayer p-contact structure defined herein comprises a metallic p-contact or a metallic p-contact layer disposed on the intermediate layer. For example, there is a direct contact between the metallic p-contact and the intermediate layer. “Metallic” defined herein refers to comprising a metal or an alloy. “Metallic” defined herein does not include semiconductor materials, such as group 11 l-V compounds. Preferred metals include: Al, In, Rh, Ni, Au, Pd and / or Pt. Particularly preferred metals include: Al, In, Ni, Au, and / or Pt, especially a Ni / Au stack and / or Pt The metallic p-contact defined herein may have a structure in the form of a single layer or a multi-layered film. The metallic p-contact may be in the form of a strip-like sheet of metal. In some cases, it is preferred if light is emitted (or absorbed) in a direction substantially opposite to the substrate. Alternatively, the metallic p-contact may be reflective or comprise a reflective layer. The metallic p-contact may thus comprise at least one light reflective layer and thus the device may act as a flip chip device. For an electronic device which acts as a flip chip device, light will be reflected back in the direction towards the substrate, thus emitting light from the bottom of the device. The flip chip configuration may be preferable when at least one of the hole injector and / or the intermediate layer is transparent or substantially transparent. The metallic p-contact is preferably 5 nm or more in thickness. It may have a thickness of 5-1000 nm for example. If the reflective layer is separate from the p-contact, then its thickness may also be between 5-1000 nm, though the thickness is preferably thicker than 25% of the optical wavelength emitted by the device. Preferably, the metallic p-contact completely covers or substantially cover the intermediate layer. Alternatively, the p-contact may continuously cover at least a portion of the intermediate layer, e.g. at least 50% of the intermediate layer, such as at least 75%, at least 90% or at least 99% of the intermediate layer. The electronic device of the invention will also comprise a n-contact which is disposed on any layer in the n-type region of the p-i-n or p-n junction. The n-contact generally will also be metallic. The n-contact may completely cover or substantially cover at least one layer of the n-type region of the p-i-n or p-n junction. Alternatively, the n-contact may continuously cover at least a portion of the n-type region of the p-i-n or p-n junction, e.g. at least 50% of the n-type region of the p-i-n or p-n junction, such as at least 75%, at least 90% or at least 99% of the n-type region of the p-i-n or p-n junction. In certain cases, the n-contact may cover only a small portion of the n-type region of the p-i-n or p-n junction, such as 20% or less, 10% or less or 5% or less. The metallic p-contact, in addition to the n-contact, will be appropriately connected to a power supply to enable the electronic device to function. The present invention preferably is directed to an electronic device comprising: - An n-type AIGaN region; - A p-type AIGaN region; - A light-emitting region or light-absorbing region positioned between the n-type AIGaN region and the p-AIGaN region; - An optional p-GaN layer, preferably having a thickness of 10 nm or less, disposed on the p-type AIGaN region; - A hole injector disposed on the p-type AIGaN region or on the optional p-GaN layer, comprising a p-AIN layer having a thickness of 10 nm or less; An intermediate layer having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer is selected from graphene ora lll-N semiconductor which is free from aluminium; - a metallic p-contact disposed on said intermediate layer; - a metallic n-contact disposed on the n-type AIGaN region. The p-contact is preferably conformally formed on the intermediate layer. Process Viewed from a yet alternative aspect, the present invention provides a process for preparing an electronic device as defined herein, comprising the steps of: (a) forming a p-i-n or p-n junction; (b) forming a hole injector on the p-side of the p-i-n or p-n junction wherein the hole injector comprising an AIN layer has a thickness of 10 nm or less; (c) forming an intermediate layer on the hole injector having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide, amorphous carbon or an aluminium-free lll-N semiconductor; and (d) forming a metallic p-contact on said intermediate layer. For step (a), typically the regions of the p-i-n or p-n junction (e.g. AIGaN regions) are formed using metalorganic vapour phase epitaxy (MOVPE) (also referred to as metalorganic chemical vapour deposition (MOCVD)), or molecular beam epitaxy (MBE). In case of MOCVD / MOVPE, the deposition material is supplied in the form of metalorganic precursors, which on reaching the high temperature substrate decomposes leaving atoms on the substrate surface. In addition, this method requires a carrier gas (typically H2 and / or N2) to transport deposition materials (atoms / molecules) across the substrate surface. These atoms reacting with other atoms form an epitaxial layer on the substrate surface. Choosing the deposition parameters carefully results in the formation of a nanowire or thin film. A higher degree of control of the nucleation and growth might be achieved with the MOCVD technique by using pulsed layer growth technique, where e.g. the group III and V elements can be supplied alternatively. Molecular beam epitaxy (MBE) is a method of forming depositions on crystalline substrates. The MBE process is performed by heating a crystalline substrate in a vacuum so as to energize the substrate's lattice structure. Then, an atomic or molecular mass beam(s) is directed onto the substrate's surface. When the directed atoms or molecules arrive at the substrate's surface, the directed atoms or molecules encounter the substrate's energized lattice structure or a catalyst droplet as described in detail below. Overtime, the oncoming atoms form a nanowire or thin film. A higher degree of control of the nucleation and growth of the nanowires or thin films on the substrate might be achieved with the MBE technique by using migration-enhanced epitaxy (MEE) or atomic-layer MBE (ALMBE) where e.g. the group III and V elements can be supplied alternatively instead of simultaneously. MBE takes place in ultra-high vacuum, with a background pressure of typically around 10-10 to 10-9 Torr. Nanostructures or films are typically grown slowly, such as at a speed of up to a few, such as about 10, pm per hour. This allows nanostructures or films to grow epitaxially and maximises structural performance. Typically, for step (b) the hole injector is also formed using MOCVD or MBE. For step (c), when the intermediate layer is a lll-N semiconductor which is free from aluminium, it will be typically formed using MOCVD or MBE. Alternatively, when the intermediate layer is a two-dimensional material, it may be formed using other known material-specific deposition methods. For example, if the intermediate layer is graphene, it may be formed using direct growth or it may be formed using growth and transfer. There are many variations of direct growth which may be used, such as variations with a plasma or low temperature. Alternatively, an intermediate layer comprising or consisting of graphene may be grown in an external environment and transferred (using a variety of methods) and placed on the hole injector. For example, the graphene intermediate layer may be grown on metal catalysts, such as metallic films or foils made of e.g. Cu, Ni or Pt. Graphene may also be grown on a SiC substrate using a thermal sublimation process and then transferred onto the hole injector. Alternatively, an intermediate layer comprising or consisting of a mat or film of carbon nanotubes (CNTs) or other similar nanotubes may be transferred and placed on the hole injector. CNTs may be synthesized using a variety of processes, including chemical vapor deposition (CVD) mediated by metal catalyst nanoparticles (e.g. Fe, Co, Ni); high-pressure carbon monoxide disproportionation (HiPCO); and arc discharge, laser, or thermal ablation of graphite or amorphous carbon. CNTs may be suspended in a variety of liquid solvents or processed in solid or dry particulate state. As a raw material, CNTs may be filtered, purified, and selected for desirable properties such as length, chirality, diameter, and number of walls; furthermore they may be chemically processed to alter chemical, physical, and electrical properties before use. CNTs may be transferred to a substrate using a variety of methods; in the case of CNTs suspended in liquid solvent, they may be coated using e.g. spin coating, spray coating, dip coating, drop casting, or inkjet printing. As used herein, the term “about”, “around” “substantially” or “approximately” in relation to a number or a range of numbers will generally indicate that the number or range specified is preferred but that such a number may be varied to a certain extent without materially affecting the properties of the relevant material, composition, method or product. The skilled worker will typically be able to readily establish the extent by which such numbers may be varied without prejudicing the key advantages of the present invention. As a general guide, such numbers or the ends of such ranges referred to with such terms may be varied by ± 20% or ± 10%, preferably ± 5% and more preferably ±1%. A corresponding meaning may be attributed to compositions “consisting essentially of’ certain components, which may include up to 20% or up to 10%, preferably up to 5% and most preferably up to 1% of other components in addition to those specified. Compositions described as comprising or consisting essentially of certain components include the compositions consisting solely of those components. However, “consisting of’ does not typically exclude the presence of doping compounds. An intermediate layer “consisting of’ graphene, for example, would not exclude an intermediate layer consisting of doped graphene. Examples The following Example demonstrates the present invention, particularly highlighting the effect of the intermediate layer as defined herein. Electronic Device 1 is an optoelectronic device, namely a UV LED, that has been fabricated using MOCVD comprising: a p-i-n junction; a hole injector disposed on the p-side of the p-i-n junction comprising a p-AIN layer having a thickness of 6.2 nm; a p-doped GaN intermediate layer having a thickness of 0.3 nm disposed on the hole injector; and a metallic p-contact disposed on said intermediate layer. The p-i-n junction of Electronic Device 1 is in line with that illustrated in Figure 1, and thus comprises a n-current spreader comprising Si-doped Alo ssGao^N (1500 nm); a n-contact layer comprising Si-doped Alo.4sGao.52N (400 nm); a multiple quantum well active region comprising a plurality of multiple quantum wells (Alo 4Ga0 6N (2 nm)) and multiple quantum barriers (Alo.68Gao.32N (10 nm)); and a p-type electron blocking layer comprising Mg-doped Alo.68Gao.32N (20-100 nm) all grown epitaxially on an AIN / Sapphire(0001) template (i.e. substrate) in an Aixtron close-coupled showerhead (CCS) reactor. Growth parameters for the respective layers included a setpoint temperature of 1520 degree Celsius for the AIN and undoped AIGaN layers, 1370 degree Celsius for the Si-doped AIGaN layers, gradings, MQW, EBL and p-GaN layers, as well as reactor pressure of 50 Torr for all mentioned layers. The p-contacting structure of Electronic Device 1 includes a p-AIN hole injection layer with 6.2 nm thickness, a p-GaN intermediate layer with 0.3 nm thickness and p-contact metal disposed on the intermediate layer. Here, the p-AIN and the p-GaN were epitaxially grown by MOCVD within 345 seconds (p-AIN) and 20 seconds (p-GaN) using 1050 degree Celsius and 150 Torr as growth parameters. The precursor flux values were 22 seem TMAI, 520 seem Cp2Mg and 24 slm NH3 for p-AIN, as well as 270 seem TEG, 880 seem Cp2Mg, and 36 slm NH3 for p-GaN. After the p-GaN intermediate layer was grown, an in-situ annealing step was performed for 10 min at 1015 degree Celsius (setpoint temperature) to activate Mg acceptors. After removing the wafer from the MOCVD reactor, the chip process was performed by mesa etching and metal deposition, which includes Ti for the n-contact and Ni / Au for the p-contact. The mentioned thickness values, especially for the p-AIN hole injector and the p-GaN intermediate layer, were obtained by cross-section transmission electron microscopy (TEM) analysis on a second wafer which was grown similar to the wafer which was processed into Electronic Device 1. For comparison, Electronic Device 2 was also prepared which is an optoelectronic device with the same structure as Electronic Device 1 but wherein the p-GaN intermediate layer is absent. Therefore, for Electronic Device 2 the metallic p-contact is disposed on the hole injector. Both Electronic Device 1 and Electronic Device 2 were tested in a quick test setup with indium dots as well as in a second setup after chip process with full metallization on both n-side and p-side. The results from the quick test setup with indium dots are shown in Figure 3. Emission spectra comparing the UV LEDs with and without the p-GaN intermediate layer show an increase in intensity for the device with the p-GaN intermediate layer at the emission wavelength near 280 nm. Both devices emit near 280 nm with a full width of half maximum (FWHM) of 11 nm, measured at 100 mA. The emitted intensity increases from 31100 counts without the p-GaN intermediate layer to 44400 counts with the p-GaN intermediate layer, showing a 42% increase in light intensity when measured using the test. The analysis after the chip process with the full metallization gives more solid statistical values as well as calibrated output power. For this test, the UV LED without the p-GaN intermediate layer show emission power of up to 46 mW versus the UV LED with the p-GaN intermediate layer which shows emission power of up to 57 mW. This highlights an increase in emission power of around 24% using this chip test type, when the p-GaN intermediate layer is included in the device. The drive voltage at 350 mA is not sacrificed when the intermediate layer is included. The drive voltage at 350 mA is near 6 V for both structures. Multiple devices with a p-GaN intermediate layer have been fabricated and analysed, showing LED emission centred in a spectral range between 273 nm and 5 283 nm. This demonstrates that this design for optoelectronic devices is potentially applicable to broader optoelectronic devices beyond LEDs emitting in the UVB or UVC spectral range. 10

Claims

1. An electronic device comprising:(i) a p-i-n or p-n junction;(ii) a hole injector disposed on the p-side of the p-i-n or p-n junction comprising an AIN layer having a thickness of 10 nm or less;(iii) an intermediate layer having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide, amorphous carbon or an aluminium-free lll-N semiconductor; and(iv) a metallic p-contact disposed on said intermediate layer.

2. An electronic device as claimed in claim 1, wherein the hole injector comprises a p-AIN layer.

3. An electronic device as claimed in claim 1 or 2, wherein the electronic device is an optoelectronic device4. An electronic device as claimed in any preceding claim, wherein the device is a UV optoelectronic device, especially a UVC optoelectronic device (e.g. a UVC LED).

5. An electronic device as claimed in any preceding claim, wherein the two-dimensional material is graphene or a graphene derivative, preferably single layer graphene.

6. An electronic device as claimed in claim 5, wherein the graphene is undoped.

7. An electronic device as claimed in any preceding claim, wherein the lll-Nsemiconductor in the intermediate layer is p-doped.

8. An electronic device as claimed in any preceding claim, wherein said intermediate layer is p-GaN.

9. An electronic device as claimed in any preceding claim, wherein the intermediate layer has a thickness of 0.1 to 20 nm, preferably 0.3 to 2 nm.

10. An electronic device as claimed in any preceding claim, wherein the two-dimensional material is selected from a graphitic material (e.g. graphene), silicene, hexagonal-BN (h-BN), M0S2, WS2, MoSe2, NbSe2, TaSe2, Bi2Te3, Bi2Se3 or NiTe2.

11. An electronic device as claimed in any preceding claim, wherein when said intermediate layer comprises a one-dimensional material, said intermediate layer is a film of nanotubes and / or fullerenes.

12. An electronic device as claimed in any preceding claim, wherein the intermediate layer consists of the one-dimensional material (e.g. carbon nanotubes), the two-dimensional material (e.g. graphene), the conductive oxide, the amorphous carbon or the Al-free lll-N semiconductor (e.g. p-GaN).

13. An electronic device as claimed in any preceding claim, wherein the p-n or p-i-n is a group lll-N p-n or p-i-n junction.

14. An electronic device as claimed in any preceding claim, wherein the p-side of the p-i-n junction comprises a p-GaN layer, preferably in its uppermost region (i.e. furthest away from the n-side of the p-n or p-i-n junction, preferably wherein the p-GaN layer has a thickness of 10 nm or less.

15. An electronic device as claimed in any preceding claim, wherein the p-i-n or p-n junction comprises at least one region or layer of AIGaN, preferably wherein the p-n or p-i-n junction comprises: an n-type AIGaN region, a p-type AIGaN region, and a light-emitting region or light-absorbing region (typically comprising i-AIGaN) positioned between the n-type AIGaN region and p-type AIGaN region.

16. An electronic device as claimed in any preceding claim, wherein the hole injector consists of p-AIN.

17. An electronic device as claimed in any preceding claim, wherein at least one of (i) to (iv) is in the form of, or part of, a nanostructure, such as a nanowire or nanopyramid.

18. An electronic device as claimed in any preceding claim, wherein at least one of (i) to (iv) is planar, preferably all are planar.

19. An electronic device as claimed in any preceding claim, comprising a metallic n-contact in electrical contact with the n-type side of the p-n or p-i-n junction.

20. An electronic device as claimed in any preceding claim, wherein:(iv) is conformally formed on (iii)(iii) is conformally formed on (ii), and- (ii) is conformally formed on (i).

21. An electronic device as claimed in any preceding claim, comprising:- an n-type AIGaN region;- a p-type AIGaN region;- a light-emitting region or light-absorbing region positioned between the n-type AIGaN region and p-type AIGaN region;- an optional p-GaN layer, preferably having a thickness of 10 nm or less, disposed on the p-type AIGaN region;- a hole injector disposed on the p-type AIGaN region or on the optional p-GaN layer, comprising a p-AIN layer having a thickness of 10 nm or less;- an intermediate layer having a thickness of 10 nm or less disposed on the hole injector, wherein said intermediate layer is selected from graphene ora lll-N semiconductor which is free from aluminium; and- a metallic p-contact disposed on said intermediate layer;- a metallic n-contact in electrical contact with the n-type AIGaN region.

22. An electronic device comprising:(i) a p-i-n or p-n junction;(ii) a hole injector disposed on the p-side of the p-i-n or p-n junction comprising an AIN layer having a thickness of 10 nm or less;(iii) an intermediate layer having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer is an aluminium-free contact barrier regulator; and(iv) a metallic p-contact disposed on said intermediate layer.

23. A multilayer p-contact structure for an electronic device comprising:(ii) a hole injector disposed on the p-side of the p-i-n or p-n junction comprising an AIN layer having a thickness of 10 nm or less;(iii) an intermediate layer having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide, amorphous carbon or an aluminium-free lll-N semiconductor; and(iv) a metallic p-contact disposed on said intermediate layer.

24. A multilayer p-contact structure for an electronic device comprising:(ii) a hole injector comprising an AIN layer having a thickness of 10 nm or less;(iii) an intermediate layer having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide, amorphous carbon or an aluminium-free lll-N semiconductor; and(iv) a metallic p-contact disposed on said intermediate layer.

25. A process for preparing the electronic device as claimed in any of claims 1-21, comprising the steps of:(a) forming a p-i-n or p-n junction;(b) forming a hole injector on the p-side of the p-i-n or p-n junction, wherein the hole injector comprises an AIN layer having a thickness of 10 nm or less;(c) forming an intermediate layer on the hole injector having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide, amorphous carbon or an aluminium-free lll-N semiconductor; and(d) forming a metallic p-contact on said intermediate layer.

26. A process for preparing the electronic device as claimed in claim 22, comprising the steps of:(a) forming a p-i-n or p-n junction;(b) forming a hole injector on the p-side of the p-i-n or p-n junction, wherein the hole injector comprises an AIN layer having a thickness of 10 nm or less;(c) forming an intermediate layer on the hole injector having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer is an aluminium-free contact barrier regulator; and(d) forming a metallic p-contact on said intermediate layer.

27. A process for preparing the multilayer p-contact structure as claimed in claim23 or 24, comprising the steps of:(b) forming a hole injector, optionally on the p-side of the p-i-n or p-n junction, wherein the hole injector comprises an AIN layer having a thickness of 10 nm or less;(c) forming an intermediate layer on the hole injector having a thickness of 20 nm or less disposed on the hole injector, wherein said intermediate layer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide, amorphous carbon or an aluminium-free lll-N semiconductor; and(d) forming a metallic p-contact on said intermediate layer.36

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