Semiconductor device, manufacturing method of semiconductor device, and electronic device

Abstract

To realize a high-performance semiconductor device which has excellent reliability.SOLUTION: A semiconductor device 1 includes a semiconductor layer 70b which is provided in a semiconductor laminate structure 20 that includes an electron transit layer 22 and an electron supply layer 24 on a drain electrode 40 side and is connected to the drain electrode 40. The semiconductor layer 70b extends from a surface 20a on the electron supply layer 24 side of the semiconductor laminate structure 20 to the electron transit layer 22 and contains n-type impurities. The drain electrode 40 covers the semiconductor layer 70b and a portion 20ab of the surface 20a adjacent to the semiconductor layer 70b. With this, the formation of an interface where the semiconductor layer 70b contacts an insulating film 60 provided on the surface 20a is avoided, and electron traps of the interface and the performance reduction caused by the electron traps can be suppressed. In addition, the increase in the current density between the drain electrode 40 and the electron transit layer 22 and the reliability reduction due to electromigration caused by the increase can be suppressed.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device. [Background technology]

[0002] 2. Description of the Related Art As an example of a semiconductor device, a high electron mobility transistor (HEMT) using a gallium nitride-based nitride semiconductor is known. For example, a gallium nitride transistor is known in which an N+ doped source / drain structure is regrown in a recess formed in a gallium nitride layer and part of the charge induction layer thereon, and source / drain contacts are provided on the source / drain structure (Patent Document 1).

[0003] In addition, an n-type Al layer is provided between the compound semiconductor layer including the carrier supply layer above the carrier transport layer and a portion of the ohmic electrode provided thereon, the portion being spaced from the end of the ohmic electrode on the gate electrode side. x Ga 1-x A compound semiconductor device having N (0≦x<1) is known (Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2016 / 068935 Brochure [Patent Document 2] JP 2017-22214 A Summary of the Invention [Problem to be solved by the invention]

[0005] Regarding HEMTs, a technique is known in which a recess is provided in a semiconductor laminate structure including an electron transit layer and an electron supply layer, the recess is formed to reach the electron transit layer, a semiconductor layer containing n-type impurities is regrown in the recess, and an electrode that is ohmically connected to the electron transit layer is connected to the semiconductor layer. By providing a semiconductor layer containing n-type impurities between the electron transit layer and the electrode, the contact resistance between the electrode and the electron transit layer, where a two-dimensional electron gas (2DEG) region is generated, is reduced.

[0006] However, in a HEMT that provides an n-type semiconductor layer to reduce contact resistance, depending on the arrangement of the semiconductor layer and the electrodes connected to it, a decrease in performance and reliability of the semiconductor device may occur.

[0007] In one aspect, the present invention aims to realize a high-performance semiconductor device having excellent reliability. [Means for solving the problem]

[0008] In one aspect, a semiconductor device is provided, including a semiconductor laminate structure including an electron transit layer and an electron supply layer; a first semiconductor layer provided in the semiconductor laminate structure, extending from a first surface of the semiconductor laminate structure on the electron supply layer side to the electron transit layer and containing an n-type impurity; and a first electrode connected to the first semiconductor layer, covering the first semiconductor layer, and in contact with a first portion of the first surface of the semiconductor laminate structure adjacent to the first semiconductor layer.

[0009] In another aspect, there is provided a method for manufacturing the semiconductor device as described above, and an electronic device including the semiconductor device as described above. Effect of the Invention

[0010] In one aspect, it is possible to realize a high-performance semiconductor device having excellent reliability. [Brief description of the drawings]

[0011] [Figure 1] 1A and 1B are diagrams illustrating a first example of a semiconductor device. [Diagram 2] 11A and 11B are diagrams illustrating a second example of a semiconductor device. [Diagram 3] 10A to 10C are diagrams further illustrating the configuration of the second example of the semiconductor device. [Figure 4] 1A and 1B are diagrams illustrating an example of a semiconductor device according to a first embodiment. [Diagram 5] 4A to 4C are diagrams illustrating an example of characteristics of the semiconductor device according to the first embodiment. [Figure 6] 1A and 1B are diagrams illustrating a first configuration example of a semiconductor device according to a first embodiment. [Figure 7] 11A and 11B are diagrams illustrating current density in a semiconductor device according to a comparative example. [Figure 8] FIG. 4 is a diagram illustrating a current density of a semiconductor device according to a first configuration example of the first embodiment. [Figure 9] 5A to 5C are diagrams illustrating a second configuration example of the semiconductor device according to the first embodiment. [Figure 10] 6 is a diagram illustrating a current density of a semiconductor device according to a second configuration example of the first embodiment. FIG. [Figure 11] 1A to 1C are diagrams illustrating an example of a method for manufacturing a semiconductor device according to a first embodiment; [Figure 12] FIG. 2 is a second diagram for explaining an example of the method for manufacturing the semiconductor device according to the first embodiment; [Figure 13] FIG. 4 is a view (part 3) illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 10A to 10C are diagrams illustrating an example of a semiconductor device according to a second embodiment. [Figure 15] 13A to 13C are diagrams illustrating an example of a semiconductor device according to a third embodiment. [Figure 16] 13A to 13C are diagrams illustrating an example of a semiconductor package according to a fourth embodiment. [Figure 17] FIG. 13 is a diagram illustrating an example of a power factor correction circuit according to a fifth embodiment. [Figure 18]FIG. 13 is a diagram illustrating an example of a power supply device according to a sixth embodiment. [Figure 19] FIG. 13 is a diagram illustrating an example of an amplifier according to a seventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] First, an example of a semiconductor device will be described. As an example of a semiconductor device, one using a nitride semiconductor is known. For example, a HEMT using gallium nitride (GaN) or the like for an electron transit layer and aluminum gallium nitride (AlGaN) or the like for an electron supply layer, so-called GaN-based HEMT, is known. The electron transit layer is also called transit layer, carrier transit layer, channel layer, etc. The electron supply layer is also called supply layer, carrier supply layer, barrier layer, etc. The HEMT has a structure in which a 2DEG region is generated in the electron transit layer where the electron supply layer is laminated, and a large current flows through the 2DEG region. The HEMT is expected to be applied as a high-frequency and high-output transistor for defense systems, long-distance communication systems, etc. In recent years, in order to further increase the current, a HEMT using a nitride semiconductor containing indium (In) for the electron supply layer, such as indium aluminum gallium nitride (InAlGaN) or indium aluminum nitride (InAlN), has also been proposed.

[0013] Fig. 1 is a diagram for explaining a first example of a semiconductor device. Fig. 1(A) is a schematic cross-sectional view of a main part of the example of the semiconductor device. Fig. 1(B) is a schematic diagram showing the current-voltage characteristics of the example of the semiconductor device. Fig. 1(C) is a schematic diagram showing the input / output characteristics of the example of the semiconductor device.

[0014] 1A is an example of a HEMT. The semiconductor device 100A includes a substrate 110, a semiconductor stacked structure 120, a source electrode 130, a drain electrode 140, a gate electrode 150, and an insulating film 160.

[0015] Various substrates such as a silicon carbide (SiC) substrate, a GaN substrate, a silicon (Si) substrate, a sapphire substrate, etc. are used as the substrate 110. A semiconductor laminate structure 120 is provided on a given substrate 110 by using a metal organic vapor phase epitaxy (MOVPE) method or the like.

[0016] The semiconductor laminated structure 120 includes, for example, a buffer layer 121, an electron transit layer 122, a spacer layer 123, and an electron supply layer 124. The buffer layer 121, the electron transit layer 122, the spacer layer 123, and the electron supply layer 124 are each made of a nitride semiconductor. The buffer layer 121 is made of, for example, aluminum nitride (AlN). The electron transit layer 122 is made of, for example, GaN. The spacer layer 123 is made of, for example, AlN or AlGaN. The electron supply layer 124 is made of, for example, AlGaN, InAlGaN, or InAlN. The buffer layer 121, the electron transit layer 122, the spacer layer 123, and the electron supply layer 124 are sequentially laminated on the substrate 110 by MOVPE or the like. A 2DEG region 180 is generated in the electron transit layer 122 of the semiconductor laminated structure 120 on which the electron supply layer 124 is laminated.

[0017] The source electrode 130 and the drain electrode 140 are provided on a surface 120a of the semiconductor laminated structure 120 on the electron supply layer 124 side. The source electrode 130 and the drain electrode 140 are provided at opposing positions and separated from each other. The source electrode 130 and the drain electrode 140 are made of a metal material such as tantalum (Ta) or aluminum (Al). The source electrode 130 and the drain electrode 140 are provided to function as ohmic electrodes.

[0018] The gate electrode 150 is provided on the surface 120a of the semiconductor laminated structure 120, between the source electrode 130 and the drain electrode 140. The gate electrode 150 is provided separately from the source electrode 130 and the drain electrode 140. The gate electrode 150 is made of a metal material such as nickel (Ni) or gold (Au). The gate electrode 150 is provided to function as, for example, a Schottky electrode. Alternatively, the gate electrode 150 may be provided on the surface 120a of the semiconductor laminated structure 120 via a gate insulating film (not shown), forming a MIS (Metal Insulator Semiconductor) type gate structure.

[0019] The insulating film 160 is provided on a surface 120a of the semiconductor stacked structure 120 on which the source electrode 130, the drain electrode 140, and the gate electrode 150 are provided. The insulating film 160 is made of an insulating material such as silicon nitride (SiN). The insulating film 160 protects the semiconductor stacked structure 120. The insulating film 160 is also called a protective film, a passivation film, or the like.

[0020] During operation of the semiconductor device 100A, for example, a voltage is applied so that the drain electrode 140 has a higher potential than the source electrode 130, and a predetermined voltage is applied to the gate electrode 150. The amount of charge passing through the 2DEG region 180 immediately below the gate electrode 150 between the source electrode 130 and the drain electrode 140 is controlled by the electric field effect caused by the voltage applied to the gate electrode 150, thereby controlling the magnitude of the output drain current.

[0021] In the semiconductor device 100A, layers such as the electron supply layer 124 are interposed between the source electrode 130 and the drain electrode 140 and the electron transit layer 122. Therefore, in the semiconductor device 100A, the contact resistance Rc between the source electrode 130 and the drain electrode 140 and the electron transit layer 122 in which the 2DEG region 180 is generated becomes relatively high.

[0022] Here, FIG. 1B is a schematic diagram showing an example of the relationship between the drain voltage Vd and the drain current Id of the semiconductor device 100A. "w / o pulse" in Figure 1(B) shows the transition of drain current Id when measured under conditions of a given gate voltage, drain voltage Vd = 0V as the initial bias point, and applying a given drain voltage Vd in a pulsed manner from the initial bias point. Note that "w / o" stands for "without." The measurement condition for "w / o pulse" is a DC (Direct Current) pseudo-reproduction of the operation when drain voltage Vd is applied to semiconductor device 100A while being swept (also called "sweep operation").

[0023] "w / pulse" in FIG. 1(B) shows the transition of the drain current Id when measured under conditions where a predetermined gate voltage is applied and a predetermined positive drain voltage Vd greater than 0V is set as the initial bias point, and the predetermined drain voltage Vd is applied in a pulsed manner from the initial bias point. Note that "w / " means "with." The measurement condition of "w / pulse" is a DC imitation of the operation when a drain voltage Vd is applied to the semiconductor device 100A by a radio frequency (RF) pulse (also called "RF pulse operation").

[0024] In the semiconductor device 100A in which the contact resistance Rc is relatively high, the drain current Id and its maximum drain current Imax are lower than the "ideal characteristics" under the measurement conditions of the sweep operation as shown in "w / o pulse" in FIG. 1B. The drain current Id and its maximum drain current Imax of the semiconductor device 100A are lower than the "w / o pulse" under the measurement conditions of the RF pulse operation as shown in "w / o pulse" in FIG. 1B. As shown in FIG. 1B, in the semiconductor device 100A, the contact resistance Rc is relatively high, and therefore the on-resistance Ron between the source electrode 130 and the drain electrode 140, which has the contact resistance Rc as a resistance component, is also higher than the "ideal characteristics".

[0025] 1C is a schematic diagram showing an example of the relationship between the input power Pin and the output power Pout of the semiconductor device 100A. In the semiconductor device 100A, as a result of the decrease in the drain current Id and its maximum drain current Imax and the increase in the on-resistance Ron, the output power Pout and its saturated output power Psat decrease compared to the "ideal characteristics" as shown in the "actual characteristics" of FIG. 1C.

[0026] As described above, the semiconductor device 100A may not be able to achieve sufficient performance by taking advantage of the characteristics of the HEMT. In contrast to the above-described semiconductor device 100A, a semiconductor device as shown in FIG. 2 has been proposed.

[0027] Fig. 2 is a diagram for explaining a second example of a semiconductor device. Fig. 2(A) is a schematic cross-sectional view of a main part of an example of a semiconductor device. Fig. 2(B) is a schematic diagram showing the current-voltage characteristics of the example of the semiconductor device. Fig. 2(C) is a schematic diagram showing the input / output characteristics of the example of the semiconductor device.

[0028] The semiconductor device 100B shown in Fig. 2(A) is an example of a HEMT. The semiconductor device 100B has a configuration in which a semiconductor layer 170a and a semiconductor layer 170b are provided between the source electrode 130 and the electron transit layer 122, and between the drain electrode 140 and the electron transit layer 122, respectively. The source electrode 130 is connected to the semiconductor layer 170a. The drain electrode 140 is connected to the semiconductor layer 170b. The semiconductor device 100B differs from the semiconductor device 100A (Fig. 1) in having such a configuration.

[0029] The semiconductor layer 170a and the semiconductor layer 170b are provided so as to extend from the surface 120a of the semiconductor laminated structure 120 to the electron transit layer 122. The semiconductor layer 170a and the semiconductor layer 170b are made of a nitride semiconductor. The semiconductor layer 170a and the semiconductor layer 170b contain n-type impurities. The semiconductor layer 170a and the semiconductor layer 170b are made of, for example, n-type GaN containing Si as an n-type impurity. The semiconductor layer 170a and the semiconductor layer 170b are grown (regrown) by MOVPE or the like in the recesses 125a and the recesses 125b provided so as to extend from the surface 120a of the semiconductor laminated structure 120 to the electron transit layer 122. The semiconductor layer 170a and the semiconductor layer 170b are also referred to as regrown layers or the like.

[0030] In the semiconductor device 100B, the n-type semiconductor layers 170a and 170b are provided, so that the contact resistance between the source electrode 130 and the drain electrode 140 and the electron transit layer 122 in which the 2DEG region 180 is generated is reduced compared to the semiconductor device 100A.

[0031] Here, Fig. 2(B) is a schematic diagram showing an example of the relationship between the drain voltage Vd and the drain current Id of the semiconductor device 100B. The measurement conditions for "w / o pulse" and "w / pulse" shown in Fig. 2(B) are the same as those described above for Fig. 1(B).

[0032] In the semiconductor device 100B in which the n-type semiconductor layer 170a and the semiconductor layer 170b are provided, the contact resistance between the source electrode 130 and the drain electrode 140 and the electron transit layer 122 is reduced. With the contact resistance reduced in this manner, the semiconductor device 100B has a drain current Id that is equivalent to or close to the ideal characteristic under the measurement condition of the sweep operation, as shown in "w / o pulse" in FIG. 2B. However, the drain current Id of the semiconductor device 100B is lower than the ideal characteristic and the w / o pulse under the measurement condition of the RF pulse operation, as shown in "w / o pulse" in FIG. 2B. That is, in the semiconductor device 100B, under the operation condition in which the drain voltage Vd is applied by the RF pulse, the drain current Id decreases as the drain voltage Vd increases, and the current collapse increases.

[0033] 2C is a schematic diagram showing an example of the relationship between the input power Pin and the output power Pout of the semiconductor device 100B. As a result of an increase in current collapse, the output power Pout and its saturated output power Psat of the semiconductor device 100B decrease relative to the "ideal characteristics" as shown in the "actual characteristics" of FIG. 2C.

[0034] The semiconductor device 100B will be further described. Fig. 3 is a diagram further explaining the configuration of the second example of the semiconductor device. Fig. 3 is a schematic enlarged cross-sectional view of the drain electrode side Q0 part of Fig. 2(A). Fig. 3 shows the flow of current with arrows.

[0035] As described above, the semiconductor device 100B includes the semiconductor laminated structure 120 including the electron transit layer 122, the electron supply layer 124, etc., and includes the semiconductor layer 170b, which contains n-type impurities and extends from the surface 120a of the semiconductor laminated structure 120 to the electron transit layer 122, on the drain electrode 140 side. The drain electrode 140 is provided on the semiconductor layer 170b. The drain electrode 140 is provided on a part of the semiconductor layer 170b, as shown in FIG. 3, for example. That is, in this example, the end 171 of the semiconductor layer 170b on the gate electrode 150 (FIG. 2(A)) side is not covered by the drain electrode 140. An insulating film 160 such as SiN is provided as a passivation film so as to cover the end 171 of the semiconductor layer 170b that is not covered by the drain electrode 140 and the surface 120a of the semiconductor laminated structure 120.

[0036] During operation of the semiconductor device 100B, as shown by the arrow in Fig. 3, a current 190 flows from the drain electrode 140 through the semiconductor layer 170b to the electron transit layer 122. The current 190 that has flowed into the electron transit layer 122 flows through the electron transit layer 122, along the 2DEG region 180, toward the source electrode 130 (Fig. 2(A)).

[0037] Here, in the semiconductor device 100B including the semiconductor layer 170b and the drain electrode 140 arranged as shown in FIG. 3, the insulating film 160 of the passivation film is provided so as to cover the end portion 171 of the semiconductor layer 170b, which may cause the following:

[0038] That is, in the semiconductor device 100B, an electron trap level may be formed at the interface between the end 171 of the semiconductor layer 170b and the insulating film 160 covering it. For example, such an electron trap level may be formed due to instability in the process of regrowing the semiconductor layer 170b. Therefore, as shown in FIG. 3, electrons 191 may be trapped at the interface between the end 171 of the semiconductor layer 170b and the insulating film 160. For example, electrons that jump out of the level of the 2DEG region 180 of the electron transit layer 122 during high voltage operation may be trapped as electrons 191 at the interface between the end 171 of the semiconductor layer 170b and the insulating film 160. Alternatively, electrons due to a gate leakage current may be trapped as electrons 191 at the interface between the end 171 of the semiconductor layer 170b and the insulating film 160.

[0039] When electrons 191 are trapped at the interface between the end 171 of the semiconductor layer 170b and the insulating film 160, the trapped electrons 191 affect the electron transit layer 122 in a region AR0 (shown by a dotted line frame in FIG. 3) directly below the electron transit layer 122, causing a decrease in the electron concentration in the region AR0. In the semiconductor device 100B, a decrease in the electron concentration in the electron transit layer 122 caused by the trapping of the electrons 191 may increase current collapse, reduce output power, and degrade high-frequency characteristics, as shown in FIGS. 2B and 2C above.

[0040] Furthermore, as shown in FIG. 3, in the semiconductor device 100B, the current 190 flowing from the drain electrode 140 tends to flow through the semiconductor layer 170b toward the 2DEG region 180, which has a relatively high electron concentration. Therefore, in the semiconductor device 100B, the current density tends to increase when the current 190 flows from the drain electrode 140 through the semiconductor layer 170b to the electron transit layer 122. The increase in current density may cause electromigration, which causes element migration between the drain electrode 140, the semiconductor layer 170b, and the electron transit layer 122 on the current path through which the current 190 flows. Note that FIG. 3 shows the drain electrode 140 side as an example, but the current density of the current flowing from the electron transit layer 122 to the semiconductor layer 170a may also increase on the source electrode 130 side, which may cause electromigration. Electromigration may degrade the performance and reliability of the semiconductor device 100B.

[0041] As described above, in the semiconductor device 100B, it may not be possible to realize sufficient performance that takes advantage of the characteristics of the HEMT, and furthermore, to realize sufficient performance with high reliability. In view of the above, a configuration as shown in the following embodiment is adopted to realize a high-performance semiconductor device having excellent reliability.

[0042] [First embodiment] Fig. 4 is a diagram for explaining an example of the semiconductor device according to the first embodiment, which diagrammatically shows a cross-sectional view of a main part of the example of the semiconductor device.

[0043] 4 is an example of a HEMT. The semiconductor device 1 includes a substrate 10, a semiconductor stacked structure 20, a semiconductor layer 70a, a semiconductor layer 70b, a source electrode 30, a drain electrode 40, a gate electrode 50, and an insulating film 60.

[0044] As the substrate 10, various substrates such as a SiC substrate, a GaN substrate, a Si substrate, a sapphire substrate, etc. The substrate 10 may be conductive, insulating, or semi-insulating. A semiconductor laminate structure 20 is provided on a given substrate 10 by using a MOVPE method or the like.

[0045] The semiconductor laminated structure 20 includes, for example, a buffer layer 21, an electron transit layer 22, a spacer layer 23, and an electron supply layer 24. The buffer layer 21, the electron transit layer 22, the spacer layer 23, and the electron supply layer 24 are each made of a nitride semiconductor. The buffer layer 21 is made of, for example, AlN. The electron transit layer 22 is made of, for example, GaN. The spacer layer 23 is made of, for example, AlN or AlGaN. The electron supply layer 24 is made of, for example, AlGaN, InAlGaN, or InAlN. The buffer layer 21, the electron transit layer 22, the spacer layer 23, and the electron supply layer 24 are sequentially laminated on the substrate 10 by MOVPE or the like. The thickness of the buffer layer 21 is set to, for example, a predetermined thickness that allows each layer including the electron transit layer 22 to be sequentially formed thereon. The thickness of the electron transit layer 22 is set to, for example, 3 μm. The thickness of the spacer layer 23 is set to, for example, 1 nm. The thickness of the electron supply layer 24 is set to, for example, 10 nm. A 2DEG region 80 is generated in the electron transit layer 22 on which the electron supply layer 24 is stacked in the semiconductor stacked structure 20, in this example, in the electron transit layer 22 on which the electron supply layer 24 is stacked via the spacer layer 23.

[0046] In the semiconductor laminated structure 20, the electron supply layer 24 is made of a nitride semiconductor having a larger band gap than that of the nitride semiconductor used in the electron transit layer 22. In the semiconductor laminated structure 20, the spontaneous polarization of the nitride semiconductor used in the electron supply layer 24 and the piezoelectric polarization generated in the electron supply layer 24 due to the strain caused by the lattice constant difference between the electron supply layer 24 and the nitride semiconductor used in the electron transit layer 22 generate a 2DEG region 80 in the electron transit layer 22. Here, a nitride semiconductor containing In, such as InAlGaN or InAlN, is a type of nitride semiconductor that can realize a relatively high Al composition. InAlGaN, InAlN, etc., which have a high Al composition, have a very strong spontaneous polarization. Therefore, when such In-containing InAlGaN, InAlN, etc. are used in the electron supply layer 24, a 2DEG region 80 with a higher concentration can be generated compared to the case of using AlGaN, etc., which does not contain In.

[0047] In the semiconductor laminated structure 20, the spacer layer 23 may be omitted, and the electron supply layer 24 may be formed directly on the electron transit layer 22. The buffer layer 21 may also be regarded as a part of the substrate 10 (its surface layer).

[0048] The nitride semiconductor contained in the electron transit layer 22 is also referred to as a "first nitride semiconductor." The nitride semiconductor contained in the electron supply layer 24 is also referred to as a "second nitride semiconductor." The semiconductor layer 70a and the semiconductor layer 70b are provided in the semiconductor laminated structure 20. The semiconductor layer 70a and the semiconductor layer 70b are provided so as to reach the electron transit layer 22 from the surface 20a of the semiconductor laminated structure 20 on the electron supply layer 24 side. The semiconductor layer 70a and the semiconductor layer 70b are provided in the regions in which the source electrode 30 and the drain electrode 40 are formed, respectively. The semiconductor layer 70a and the semiconductor layer 70b are provided at positions facing each other and separated from each other. The semiconductor layer 70a and the semiconductor layer 70b are made of a nitride semiconductor. The semiconductor layer 70a and the semiconductor layer 70b contain an n-type impurity. The semiconductor layer 70a and the semiconductor layer 70b are made of, for example, n-type GaN containing Si as an n-type impurity. The semiconductor layer 70a and the semiconductor layer 70b are grown (regrown) by MOVPE or the like in the recesses 25a and the recesses 25b provided so as to reach the electron transit layer 22 from the surface 20a of the semiconductor laminated structure 20, respectively. The semiconductor layer 70a and the semiconductor layer 70b have a tapered shape in which, for example, the width in a direction parallel to the surface 20a of the semiconductor laminate structure 20 narrows from the surface 20a toward the electron transit layer 22. The semiconductor layer 70a and the semiconductor layer 70b are also referred to as a re-grown layer, a contact layer, a low-resistance layer, or the like.

[0049] The surface 20a of the semiconductor laminate structure 20 on the electron supply layer 24 side is also referred to as a "first surface." The nitride semiconductor included in the semiconductor layer 70a and the semiconductor layer 70b, or one of them (for example, the semiconductor layer 70b), is also referred to as a "third nitride semiconductor."

[0050] The source electrode 30 and the drain electrode 40 are provided on the semiconductor layer 70a and the semiconductor layer 70b provided in the semiconductor laminated structure 20 and on a part of the surface 20a, respectively. The source electrode 30 and the drain electrode 40 are provided at opposing positions and separated from each other. The source electrode 30 is connected to the semiconductor layer 70a. The drain electrode 40 is connected to the semiconductor layer 70b. The source electrode 30 is provided so as to cover the semiconductor layer 70a and a portion 20aa of the surface 20a of the semiconductor laminated structure 20 adjacent to the semiconductor layer 70a. This portion 20aa is a portion adjacent to the semiconductor layer 70b side of the semiconductor layer 70a that faces the semiconductor layer 70a. The drain electrode 40 is provided so as to cover the semiconductor layer 70b and a portion 20ab of the surface 20a of the semiconductor laminated structure 20 adjacent to the semiconductor layer 70b. This portion 20ab is a portion adjacent to the semiconductor layer 70b side of the semiconductor layer 70b that faces the semiconductor layer 70a. A metal material such as Ta or Al is used for the source electrode 30 and the drain electrode 40. The source electrode 30 and the drain electrode 40 are provided so as to function as ohmic electrodes.

[0051] The semiconductor layer 70b provided in the semiconductor laminated structure 20, connected to the drain electrode 40, and covered by the drain electrode 40 is also referred to as the "first semiconductor layer." The portion 20ab of the surface 20a of the semiconductor laminated structure 20, adjacent to the semiconductor layer 70b and covered by the drain electrode 40, is also referred to as the "first portion." The semiconductor layer 70a provided in the semiconductor laminated structure 20, connected to the source electrode 30, and covered by the source electrode 30 is also referred to as the "second semiconductor layer." The portion 20aa of the surface 20a of the semiconductor laminated structure 20, adjacent to the semiconductor layer 70a and covered by the source electrode 30, is also referred to as the "third portion."

[0052] The gate electrode 50 is provided on the surface 20a of the semiconductor laminated structure 20 between the source electrode 30 and the drain electrode 40. The gate electrode 50 is provided separately from the source electrode 30 and the drain electrode 40. The gate electrode 50 is made of a metal material such as Ni or Au. The gate electrode 50 is provided to function as a Schottky electrode, for example. Alternatively, the gate electrode 50 may be provided on the surface 20a of the semiconductor laminated structure 20 via a gate insulating film (not shown) to form an MIS type gate structure. The gate electrode 50 may be disposed asymmetrically, closer to the source electrode 30 than to the drain electrode 40, in order to achieve a high breakdown voltage.

[0053] The drain electrode 40 is also referred to as a "first electrode." The source electrode 30 is also referred to as a "second electrode." The gate electrode 50 is also referred to as a "third electrode." The insulating film 60 is provided on the surface 20a of the semiconductor laminated structure 20 on which the source electrode 30, the drain electrode 40, and the gate electrode 50 are provided. The insulating film 60 is provided so as to cover at least a portion 20ad of the surface 20a of the semiconductor laminated structure 20 that is exposed from the source electrode 30, the drain electrode 40, and the gate electrode 50. That is, the insulating film 60 is provided so as to cover a portion 20ad of the surface 20a of the semiconductor laminated structure 20, excluding a portion 20aa covered by the source electrode 30, a portion 20ab covered by the drain electrode 40, and a portion 20ac covered by the gate electrode 50. The insulating film 60 contacts the portion 20ad of the surface 20a of the semiconductor laminated structure 20 and the source electrode 30 covering the portion 20aa, and is separated from the semiconductor layer 70a covered by the source electrode 30. The insulating film 60 contacts the portion 20ad of the surface 20a of the semiconductor laminated structure 20 and the drain electrode 40 covering the portion 20ab, and is separated from the semiconductor layer 70b covered by the drain electrode 40. The insulating film 60 is made of an insulating material such as SiN. The insulating film 60 protects the semiconductor laminated structure 20 from moisture, outside air, external forces, and the like. The insulating film 60 functions as a passivation film. The insulating film 60 may be provided to cover the portion 20ad of the surface 20a of the semiconductor laminated structure 20, as well as the source electrode 30 and the drain electrode 40.

[0054] The portion 20ad of the surface 20a of the semiconductor laminated structure 20 that is covered with the insulating film 60 is also referred to as a "second portion." During operation of the semiconductor device 1, for example, a voltage is applied so that the drain electrode 40 has a higher potential than the source electrode 30, and a predetermined voltage is applied to the gate electrode 50. The amount of charge passing through the 2DEG region 80 immediately below the gate electrode 50 between the source electrode 30 and the drain electrode 40 is controlled by the electric field effect caused by the voltage applied to the gate electrode 50, thereby controlling the magnitude of the output drain current.

[0055] In the semiconductor device 1 having the above configuration, a semiconductor layer 70a containing n-type impurities is provided between the source electrode 30 and the electron transit layer 22. This reduces the contact resistance between the source electrode 30 and the electron transit layer 22 in which the 2DEG region 80 is generated. In the semiconductor device 1, a semiconductor layer 70b containing n-type impurities is provided between the drain electrode 40 and the electron transit layer 22. This reduces the contact resistance between the drain electrode 40 and the electron transit layer 22 in which the 2DEG region 80 is generated.

[0056] Furthermore, in the semiconductor device 1, the semiconductor layer 70a and the adjacent portion 20aa of the face 20a of the semiconductor laminated structure 20 are covered with the source electrode 30. The semiconductor layer 70b and the adjacent portion 20ab of the face 20a of the semiconductor laminated structure 20 are covered with the drain electrode 40. The insulating film 60 is provided so as to cover a portion 20ad of the face 20a of the semiconductor laminated structure 20 that is different from the portions 20aa and 20ab that are covered with the source electrode 30 and the drain electrode 40, respectively. Therefore, the insulating film 60 is separated from the semiconductor layer 70a and the semiconductor layer 70b. Therefore, in the semiconductor device 1, the formation of an interface where the insulating film 60 contacts the semiconductor layer 70a and the semiconductor layer 70b is avoided.

[0057] By avoiding the formation of such an interface, the generation of electron traps on the semiconductor layer 70b is suppressed on the drain electrode 40 side to which a relatively high voltage is applied during operation of the semiconductor device 1, and the decrease in electron concentration in the electron transit layer 22 caused by the electron traps is suppressed. As a result, an increase in current collapse and a decrease in output power are suppressed in the semiconductor device 1. This point will be described further.

[0058] 5A and 5B are diagrams illustrating an example of the characteristics of the semiconductor device according to the first embodiment. Fig. 5A shows a schematic diagram of the current-voltage characteristics of the example of the semiconductor device. Fig. 5B shows a schematic diagram of the input / output characteristics of the example of the semiconductor device.

[0059] Fig. 5(A) is a schematic diagram showing an example of the relationship between the drain voltage Vd and the drain current Id of the semiconductor device 1. The measurement conditions for "w / o pulse" and "w / pulse" shown in Fig. 5(A) are the same as those described above for Fig. 1(B) and Fig. 2(B), respectively.

[0060] In the semiconductor device 1, n-type semiconductor layers 70a and 70b are provided, and the contact resistance between the source electrode 30 and the drain electrode 40 and the electron transit layer 22 is reduced. In the semiconductor device 1, the contact resistance is reduced in this manner, so that, in the case of the measurement condition of the sweep operation, the transition of the drain current Id becomes equivalent to or close to the "ideal characteristic", as shown in "w / o pulse" in FIG.

[0061] Furthermore, in the semiconductor device 1, on the drain electrode 40 side, the semiconductor layer 70b and the portion 20ab of the surface 20a adjacent thereto are covered with the drain electrode 40. When the insulating film 60 of the passivation film is provided, the semiconductor layer 70b is separated from the insulating film 60. This prevents the formation of an interface where the insulating film 60 and the semiconductor layer 70b come into contact with each other. Therefore, even when a relatively high voltage is applied to the drain electrode 40 side during operation of the semiconductor device 1, the generation of electron traps on the semiconductor layer 70b is suppressed, and the decrease in the electron concentration of the electron transit layer 22 and the increase in current collapse caused by the electron traps are suppressed. Therefore, in the semiconductor device 1, the contact resistance is reduced and the increase in current collapse is suppressed, so that the transition of the drain current Id approaches the cases of the "ideal characteristics" and "w / o pulse" even under the measurement conditions of RF pulse operation, as shown in "w / pulse" in FIG. 5(A).

[0062] Fig. 5(B) is a schematic diagram showing an example of the relationship between the input power Pin and the output power Pout of the semiconductor device 1. In the semiconductor device 1, the contact resistance is reduced and an increase in current collapse is suppressed, so that the output power Pout and its saturated output power Psat become equal to or close to the "ideal characteristics", as shown in the "actual characteristics" of Fig. 5(B).

[0063] As described above, in the semiconductor device 1, the semiconductor layer 70b is provided in the semiconductor stacked structure 20, and the drain electrode 40 is provided so as to cover the semiconductor layer 70b and the portion 20ab of the surface 20a adjacent thereto. By adopting such a configuration, the formation of an interface where the semiconductor layer 70b and the insulating film 60 come into contact is avoided, and electron traps at the interface, a decrease in the electron concentration in the electron transit layer 22 due to the electron traps, and an increase in current collapse are suppressed. This realizes a high-performance semiconductor device 1.

[0064] Furthermore, in the semiconductor device 1, for example, on the drain electrode 40 side, the semiconductor layer 70b and the portion 20ab adjacent thereto are covered with the drain electrode 40. Therefore, a current not only flows from the drain electrode 40 to the semiconductor layer 70b, but also flows from the portion 20ab to the electron supply layer 24 and then to the electron transit layer 22. This reduces the current density of the current flowing from the drain electrode 40 to the electron transit layer 22. By reducing the current density, electromigration of elements present on the current path is suppressed, and deterioration in the performance and reliability of the semiconductor device 1 is suppressed.

[0065] Here, a configuration example of the semiconductor device 1 and the reduction in current density will be further described. First, the first configuration example will be described. 6 is a diagram for explaining a first configuration example of the semiconductor device according to the first embodiment, which diagrammatically shows an enlarged cross-sectional view of the first configuration example of the drain electrode side Q1 portion of FIG.

[0066] As described above, the semiconductor device 1 includes the semiconductor laminate structure 20 including the electron transit layer 22, the electron supply layer 24, etc., and includes, on the drain electrode 40 side, a semiconductor layer 70b that contains n-type impurities and extends from the face 20a of the semiconductor laminate structure 20 to the electron transit layer 22. The drain electrode 40 is provided so as to cover the semiconductor layer 70b and a portion 20ab of the face 20a adjacent thereto. A portion 20ad of the face 20a, which is different from the portion 20ab covered by the drain electrode 40, is covered with an insulating film 60 of a passivation film.

[0067] In the semiconductor device 1, the semiconductor layer 70b may be provided such that an end 71 on the gate electrode 50 (FIG. 4) side partially covers a portion 20ab of the surface 20a of the semiconductor laminate structure 20, as shown in FIG. 6. For example, the semiconductor layer 70b is provided so as to cover a portion of the portion 20ab covered with the drain electrode 40 that is located on the inner side than the end 41 of the drain electrode 40. It can also be said that the semiconductor layer 70b has a shape in which the end 71 rides up onto the portion 20ab so as to cover a portion of the portion 20ab covered with the drain electrode 40 that is located on the inner side than the end 41 of the drain electrode 40.

[0068] Here, the drain electrode 40 side is taken as an example, but in the semiconductor device 1, the end of the semiconductor layer 70a may be shaped to run up onto the portion 20aa of the surface 20a in the same manner on the source electrode 30 side. When the semiconductor layer 70a and the semiconductor layer 70b are formed (regrown), if they are shaped to run up onto the surface 20a in this way, the recesses 25a and the recesses 25b are sufficiently filled with the semiconductor layer 70a and the semiconductor layer 70b, respectively. This suppresses insufficient filling of the recesses 25a with the semiconductor layer 70a and insufficient filling of the recesses 25b with the semiconductor layer 70b, and the distribution of the depressions formed by these in the substrate (wafer) surface. As a result, for example, the deterioration of the patterning accuracy and the non-uniformity of the shapes of various layers further formed on the wafer are suppressed.

[0069] The reduction in current density in the semiconductor device 1 employing the configuration shown in FIG. 6 will be described with reference to the following FIGS. FIG. 7 is a diagram for explaining the current density of a semiconductor device according to a comparative example. FIG. 8 is a diagram for explaining the current density of a semiconductor device according to a first configuration example of the first embodiment. FIG. 7(A) is a schematic cross-sectional view of a main part on the drain electrode side of the semiconductor device 100B shown in FIG. 2 and FIG. 3, together with a current flow. FIG. 7(B) is a diagram for explaining the current density [A / cm2] on the drain electrode side of the semiconductor device 100B shown in FIG. 2 and FIG. 3. 2 8(A) is a schematic diagram showing a cross-sectional view of a main part on the drain electrode side of the semiconductor device 1 shown in FIGS. 4 and 6, together with a current flow. FIG. 8(B) is a schematic diagram showing a current density [A / cm2] on the drain electrode side of the semiconductor device 1 shown in FIGS. 4 and 6. 2 ] is shown diagrammatically.

[0070] As shown in FIG. 7A, in the semiconductor device 100B of the comparative example, a drain electrode 140 is provided on a semiconductor layer 170b provided on a semiconductor laminated structure 120. The drain electrode 140 is provided on the semiconductor layer 170b extending in the range from position a1 to position b1 so as not to protrude from position b1 to the gate electrode 150 (FIG. 2) side. That is, the drain electrode 140 is provided so as not to cover an end 171 of the semiconductor layer 170b. An insulating film 160 of a passivation film is provided on the surface 120a of the semiconductor laminated structure 120 so as to cover an end 171 of the semiconductor layer 170b that is not covered by the drain electrode 140. The position a1 is, for example, an end of the drain electrode 140, an end of an active region (element region) in which a field effect transistor structure of the semiconductor device 1 is formed, or a boundary between the active region and an element isolation region formed outside the active region.

[0071] In the semiconductor device 100B employing the configuration as shown in FIG. 7A, the current density of the current 190 flowing from the drain electrode 140 to the electron transit layer 122 has a distribution as shown in FIG. 7B, for example. In FIG. 7B, the current density distribution of the semiconductor device 100B is indicated by "Tr0". In the semiconductor device 100B in which the end 171 of the semiconductor layer 170b is not covered with the drain electrode 140, the electron concentration of the electron transit layer 122 directly below the end 171 may decrease due to electron traps at the interface between the end 171 and the insulating film 160 in contact with it. In the semiconductor device 100B in which the drain electrode 140 does not protrude from the position b1 of the semiconductor layer 170b, the current 190 flowing from the drain electrode 140 tends to flow through the semiconductor layer 170b toward the 2DEG region 180 in the electron transit layer 122, which has a relatively high electron concentration. Therefore, in the semiconductor device 100B, the current 190 tends to concentrate in a region of a certain width W1 from the position b1 to the position a1 side, and the current density becomes high. For example, a current density peak appears in a region of width W1 of about 5 μm from the position b1 to the position a1 side, and the current density J0 of the peak is 5×10 6 A / cm 2 It can show extremely high values ​​such as

[0072] In contrast, in the semiconductor device 1 shown in FIG. 8(A), a semiconductor layer 70b is provided in the semiconductor laminated structure 20, and a drain electrode 40 is provided on the semiconductor layer 70b and on a portion 20ab of the surface 20a of the semiconductor laminated structure 20 adjacent thereto. The semiconductor layer 70b extends from a position a1 to a position d1. The semiconductor layer 70b is a portion whose width changes in a tapered manner from a position b1 to a position c1, and a portion that runs onto the surface 20a of the semiconductor laminated structure 20 from a position c1 to a position d1. The surface 20a is a portion 20ab adjacent to the semiconductor layer 70b from a position c1 to a position e1. The drain electrode 40 is provided so as to cover the semiconductor layer 70b and the portion 20ab adjacent thereto. An insulating film 60 of a passivation film is provided in a portion 20ad of the surface 20a of the semiconductor laminated structure 20 that is different from the portion 20ab. The position a1 is, for example, the edge of the drain electrode 40, or the edge of an active region (device region) in which a field effect transistor structure is formed, or the position of the boundary between the active region and the device isolation region on the outside thereof.

[0073] In the semiconductor device 1 employing the configuration as shown in FIG. 8(A), the current density of the current 90 flowing from the drain electrode 40 to the electron transit layer 22 is distributed as shown in FIG. 8(B), for example. In FIG. 8(B), the current density distribution of the semiconductor device 1 employing the configuration of FIG. 8(A) is shown by "Tr1" (solid line). For comparison, FIG. 8(B) also shows the current density distribution of the semiconductor device 100B employing the configuration of FIG. 7(A) by "Tr0" (chain line). In the semiconductor device 1 (Tr1) in which the semiconductor layer 70b and the adjacent portion 20ab are covered by the drain electrode 40, the formation of an interface where the semiconductor layer 70b and the insulating film 60 come into contact with each other is avoided. Therefore, the generation of electron traps at the interface and the resulting decrease in the electron concentration of the electron transit layer 22 are suppressed. In the semiconductor device 1 (Tr1) in which the semiconductor layer 70b and the portion 20ab adjacent thereto are covered with the drain electrode 40, the current 90 flowing from the drain electrode 40 not only flows into the semiconductor layer 70b, but also flows from the portion 20ab to the electron supply layer 24 and then into the electron transit layer 22. This reduces the current density of the current 90 flowing from the drain electrode 40 to the electron transit layer 22.

[0074] For example, as shown in FIG. 8B, the current density of the semiconductor device 1 (Tr1) peaks in a constant-width region from position b1 to position a1, where the semiconductor layer 70b is present. The peak current density J1 of the semiconductor device 1 (Tr1) is significantly reduced compared to the peak current density J0 of the semiconductor device 100B (Tr0). The current density of the semiconductor device 1 (Tr1) gradually decreases from the peak current density J1 in the region from position b1 to position c1, where the width of the semiconductor layer 70b changes in a tapered shape. In the semiconductor device 1 (Tr1), a current 90 flows at a constant current density also in the region from position c1 to position e1 of the portion 20ab adjacent to the semiconductor layer 70b.

[0075] 8(A), the peak current density is reduced, and a wider region including the semiconductor layer 70b and the portion 20ab adjacent thereto becomes the current path, thereby mitigating the current density of the current 90 flowing from the drain electrode 40 to the electron transit layer 22. The mitigation of the current density suppresses electromigration of elements present on the current path, and thus suppresses deterioration in the performance and reliability of the semiconductor device 1.

[0076] Although the drain electrode 40 side is taken as an example here, the source electrode 30 is also provided on the source electrode 30 side in the same manner, covering the semiconductor layer 70a and the adjacent portion 20aa. This provides the same effect as that described above for the drain electrode 40 side with respect to current density. That is, a wider region including the semiconductor layer 70a and the adjacent portion 20aa serves as a current path, thereby reducing the current density of the current flowing from the electron transit layer 22 to the source electrode 30. The reduction in current density suppresses electromigration of elements present on the current path, thereby suppressing deterioration in the performance and reliability of the semiconductor device 1.

[0077] Next, a second configuration example will be described. 9 is a diagram for explaining a second configuration example of the semiconductor device according to the first embodiment, which diagrammatically shows an enlarged cross-sectional view of the second configuration example of the drain electrode side Q1 portion of FIG.

[0078] In the semiconductor device 1, the semiconductor layer 70b may have a shape in which its end does not partially cover the surface 20a of the semiconductor laminated structure 20, that is, does not run over the adjacent portion 20ab, as shown in FIG. It can also be said that the semiconductor layer 70b has a shape in which its upper surface is located in the same plane as the surface 20a of the semiconductor laminated structure 20. In the example of FIG. 9, the semiconductor layer 70b is provided in the recess 25b of the semiconductor laminated structure 20, and the drain electrode 40 is provided so as to cover the semiconductor layer 70b and the portion 20ab of the surface 20a adjacent thereto. The portion 20ad of the surface 20a, which is different from the portion 20ab covered by the drain electrode 40, is covered with the insulating film 60 of the passivation film.

[0079] Here, the drain electrode 40 side is taken as an example, but in the semiconductor device 1, the source electrode 30 side may also be shaped such that the end of the semiconductor layer 70a does not run onto the portion 20aa of the surface 20a, or the upper surface of the semiconductor layer 70b is located in the same plane as the surface 20a. When the semiconductor layers 70a and 70b are formed (regrown), if the semiconductor layers 70a and 70b are shaped so as not to run onto the surface 20a, the flatness of the substrate (wafer) is improved. As a result, for example, the deterioration of the patterning accuracy and the non-uniformity of the shapes of various layers further formed on the wafer are suppressed.

[0080] The reduction in current density in the semiconductor device 1 employing the configuration shown in FIG. 9 will be described with reference to FIG. 10 is a diagram for explaining the current density of the semiconductor device according to the second configuration example of the first embodiment. Fig. 10(A) is a schematic cross-sectional view of the main part on the drain electrode side of the semiconductor device 1 shown in Figs. 4 and 9, together with the current flow. Fig. 10(B) is a diagram for explaining the current density [A / cm2] on the drain electrode side of the semiconductor device 1 shown in Figs. 4 and 9. 2 ] is shown diagrammatically.

[0081] In the semiconductor device 1 shown in FIG. 10A, the semiconductor layer 70b extends from position a1 to position c1. The semiconductor layer 70b has a tapered width from position b1 to position c1. The surface 20a has a portion 20ab adjacent to the semiconductor layer 70b from position c1 to position e1. The drain electrode 40 is provided so as to cover the semiconductor layer 70b and the portion 20ab adjacent thereto. An insulating film 60 of a passivation film is provided in a portion 20ad of the surface 20a of the semiconductor laminated structure 20 that is different from the portion 20ab. The position a1 is, for example, an end of the drain electrode 40, or an end of an active region (element region) in which a field effect transistor structure of the semiconductor device 1 is formed, or a boundary between the active region and an element isolation region formed outside the active region.

[0082] In the semiconductor device 1 employing the configuration as shown in FIG. 10(A), the current density of the current 90 flowing from the drain electrode 40 to the electron transit layer 22 is distributed as shown in FIG. 10(B), for example. In FIG. 10(B), the current density distribution of the semiconductor device 1 employing the configuration of FIG. 10(A) is shown by "Tr2" (solid line). For comparison, FIG. 10(B) also shows the current density distribution of the semiconductor device 100B employing the configuration of FIG. 7(A) by "Tr0" (chain line) and the current density distribution of the semiconductor device 1 employing the configuration of FIG. 8(A) by "Tr1" (dotted line). In the semiconductor device 1 (Tr2) in which the semiconductor layer 70b and the portion 20ab adjacent thereto are covered by the drain electrode 40, the formation of an interface where the semiconductor layer 70b and the insulating film 60 come into contact with each other is avoided. Therefore, the generation of electron traps at the interface and the resulting decrease in the electron concentration of the electron transit layer 22 are suppressed. In the semiconductor device 1 (Tr2) in which the semiconductor layer 70b and the portion 20ab adjacent thereto are covered with the drain electrode 40, the current 90 flowing from the drain electrode 40 not only flows into the semiconductor layer 70b, but also flows from the portion 20ab to the electron supply layer 24 and then into the electron transit layer 22. This reduces the current density of the current 90 flowing from the drain electrode 40 to the electron transit layer 22.

[0083] For example, as shown in FIG. 10B, the current density of the semiconductor device 1 (Tr2) peaks in a constant-width region from position b1 to position a1, where the semiconductor layer 70b is present. The peak current density J2 of the semiconductor device 1 (Tr2) is significantly reduced compared to the peak current density J0 of the semiconductor device 100B (Tr0). The current density of the semiconductor device 1 (Tr2) gradually decreases from the peak current density J2 in the region from position b1 to position c1, where the width of the semiconductor layer 70b changes in a tapered shape. In the semiconductor device 1 (Tr2), a current 90 flows at a constant current density also in the region from position c1 to position e1 of the portion 20ab adjacent to the semiconductor layer 70b.

[0084] In the semiconductor device 1 (Tr2) having the configuration of FIG. 10(A), the peak current density J2 in a certain width region from position b1 to position a1 side where the semiconductor layer 70b is present is lower than in the semiconductor device 1 (Tr1) having the configuration of FIG. 8(A). In the region from position b1 to position c1 where the width of the semiconductor layer 70b changes in a tapered shape, the decrease from the peak current density J2 is gentle, and the current density is high in the region from position c1 to position e1 of the portion 20ab adjacent to the semiconductor layer 70b. In the semiconductor device 1 (Tr2) not having the end 71 riding on the portion 20ab, the current 90 flowing through the semiconductor layer 70b to the electron transit layer 22 is reduced compared to the semiconductor device 1 (Tr1) having such an end 71. On the other hand, in the semiconductor device 1 (Tr2), the current 90 flowing from the portion 20ab to the electron transit layer 22 through the electron supply layer 24 is increased compared to the semiconductor device 1 (Tr1).

[0085] 10(A) also reduces the peak current density, and a wider region including the semiconductor layer 70b and the portion 20ab adjacent thereto becomes the current path, thereby mitigating the current density of the current 90 flowing from the drain electrode 40 to the electron transit layer 22. The mitigation of the current density suppresses electromigration of elements present on the current path, and thus suppresses deterioration in the performance and reliability of the semiconductor device 1.

[0086] Although the drain electrode 40 side is taken as an example here, in the semiconductor device 1, the source electrode 30 is also provided on the source electrode 30 side so as to cover the semiconductor layer 70a and the adjacent portion 20aa. This provides the same effect as that described for the drain electrode 40 side with respect to current density. That is, a wider region including the semiconductor layer 70a and the adjacent portion 20aa serves as a current path, thereby reducing the current density of the current flowing from the electron transit layer 22 to the source electrode 30. By reducing the current density, electromigration of elements present on the current path is suppressed, and deterioration in the performance and reliability of the semiconductor device 1 is suppressed.

[0087] As described above, the semiconductor device 1 has a configuration in which the semiconductor layer 70b is provided in the semiconductor laminated structure 20, and the drain electrode 40 is provided so as to cover the semiconductor layer 70b and the adjacent portion 20ab of the surface 20a. This avoids the formation of an interface where the semiconductor layer 70b and the insulating film 60 come into contact, and suppresses electron traps at the interface and the resulting decrease in the electron concentration of the electron transit layer 22. Furthermore, the current density of the current flowing from the drain electrode 40 to the electron transit layer 22 is reduced, and electromigration is suppressed. Furthermore, the semiconductor device 1 has a configuration in which the semiconductor layer 70a is provided in the semiconductor laminated structure 20, and the source electrode 30 is provided so as to cover the semiconductor layer 70a and the adjacent portion 20aa of the surface 20a. This reduces the current density of the current flowing from the electron transit layer 22 to the source electrode 30, and suppresses electromigration. The above configuration is adopted to realize a high-performance semiconductor device 1 with excellent reliability.

[0088] In the semiconductor device 1, the semiconductor layers 70a and 70b have a tapered shape such that the width in a direction parallel to the surface 20a of the semiconductor laminate structure 20 narrows from the surface 20a toward the electron transit layer 22. For example, when the semiconductor layer 70b has a tapered shape, a steep change between the current density of the current 90 flowing through the semiconductor layer 70b to the electron transit layer 22 and the current density of the current 90 flowing through the electron supply layer 24 at the portion 20ab to the electron transit layer 22 is suppressed. That is, as seen in the range from position b1 to position c1 in Figures 8(A) and 8(B) or the range from position b1 to position c1 in Figures 10(A) and 10(B), the change (gradient) of the current density decreasing from a peak current density to a constant current density becomes gentler. Similarly, when the semiconductor layer 70a is tapered, the change (gradient) between the current density of the current flowing from the electron transit layer 22 to the semiconductor layer 70a and the current density of the current flowing from the electron transit layer 22 to the electron supply layer 24 in portion 20aa is prevented from becoming too steep.

[0089] However, the semiconductor layer 70a and the semiconductor layer 70b do not necessarily have to have a tapered shape. The semiconductor layer 70a and the semiconductor layer 70b may have a shape in which the width in the direction parallel to the surface 20a of the semiconductor laminate structure 20 is constant from the surface 20a to the electron transit layer 22. In the semiconductor device 1, for example, even when the semiconductor layer 70b has a constant width, the drain electrode 40 is provided so as to cover the semiconductor layer 70b and the adjacent portion 20ab of the surface 20a, thereby realizing high performance and reliability. That is, a decrease in the electron concentration of the electron transit layer 22 caused by electron traps at the interface between the semiconductor layer 70b and the insulating film 60 is suppressed, and further, an increase in the current density of the current flowing from the drain electrode 40 to the electron transit layer 22 is suppressed, thereby realizing high performance and reliability of the semiconductor device 1. Furthermore, in the semiconductor device 1, even when the semiconductor layer 70a has a constant width, the source electrode 30 is provided so as to cover the semiconductor layer 70a and the adjacent portion 20aa of the surface 20a, thereby realizing high performance and reliability. That is, an increase in the current density of the current flowing from the electron transit layer 22 to the source electrode 30 is suppressed, and the semiconductor device 1 has high performance and reliability.

[0090] In the semiconductor device 1, the portion 20ab adjacent to the semiconductor layer 70b and covered by the drain electrode 40 is adjacent to the semiconductor layer 70a side (or the source electrode 30 side) facing the semiconductor layer 70b. In the semiconductor device 1, the portion 20aa adjacent to the semiconductor layer 70a and covered by the source electrode 30 is adjacent to the semiconductor layer 70b side (or the drain electrode 40 side) facing the semiconductor layer 70a. In the semiconductor device 1, the current 90 flows from the drain electrode 40 to the source electrode 30. Therefore, by covering the portion 20ab on the side where the current 90 flows from the drain electrode 40 to the source electrode 30 with the drain electrode 40, the decrease in electron concentration and the increase in current density due to electron traps are effectively suppressed. By covering the portion 20aa on the side where the current 90 flows from the drain electrode 40 to the source electrode 30 with the source electrode 30, the increase in current density is effectively suppressed. This realizes high performance and reliability of the semiconductor device 1.

[0091] Furthermore, if the drain electrode 40 is configured to cover the semiconductor layer 70b and be in contact with the portion 20ab of the surface 20a of the semiconductor laminate structure 20 adjacent to the semiconductor layer 70b, a certain effect can be obtained in suppressing electron traps and the resulting decrease in electron concentration, as well as the increase in current density.

[0092] Next, a method for manufacturing the above-described semiconductor device 1 will be described. Figures 11 to 13 are diagrams for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. Figures 11(A), 11(B), 12(A), 12(B), 13(A), and 13(B) each show a schematic cross-sectional view of a main part of an example of a semiconductor device manufacturing process.

[0093] First, a substrate 10 and a semiconductor laminated structure 20 as shown in FIG. 11(A) are prepared. First, a predetermined substrate 10 is prepared, and a buffer layer 21, an electron transit layer 22, a spacer layer 23, and an electron supply layer 24 of the semiconductor laminated structure 20 are sequentially formed on the substrate 10 by, for example, MOVPE. For example, a SiC substrate is used as the substrate 10, and an AlN buffer layer 21, a GaN electron transit layer 22, an AlN spacer layer 23, and an InAlGaN electron supply layer 24 are sequentially formed thereon. The thickness of the buffer layer 21 is set to, for example, a predetermined thickness that allows each layer including the electron transit layer 22 to be sequentially grown thereon. The thickness of the electron transit layer 22 is set to, for example, 3 μm. The thickness of the spacer layer 23 is set to, for example, 1 nm. The thickness of the electron supply layer 24 is set to, for example, 10 nm. A 2DEG region 80 is generated in the electron transit layer 22 on which the electron supply layer 24 is laminated, in this example, in the electron transit layer 22 on which the electron supply layer 24 is laminated with the spacer layer 23 interposed therebetween.

[0094] After the semiconductor laminated structure 20 is formed, as shown in FIG. 11B, the recesses 25a and 25b are formed in the regions in which the semiconductor layers 70a and 70b are to be formed. For example, lithography and etching techniques are used to form the recesses 25a and 25b in predetermined regions of the semiconductor laminated structure 20. The recesses 25a and 25b are formed so as to reach the electron transit layer 22 from the surface 20a of the semiconductor laminated structure 20 on the electron supply layer 24 side through the spacer layer 23. For example, dry etching is used to form the recesses 25a and 25b. The recesses 25a and 25b can be formed by dry etching in a tapered shape such that the width in the direction parallel to the surface 20a narrows toward the electron transit layer 22. The recesses 25a and 25b may be formed in a tapered shape by adjusting the etching conditions during dry etching. The inclination angle of the recesses 25a and 25b when they are formed into a tapered shape may be adjusted by adjusting the etching conditions during dry etching. The recesses 25a and 25b may be formed by wet etching instead of or in addition to dry etching.

[0095] After the recesses 25a and 25b are formed, as shown in FIG. 12(A), the semiconductor layers 70a and 70b are formed in the recesses 25a and 25b, respectively. For example, SiN or the like (not shown) is formed in the region other than the region where the semiconductor layers 70a and 70b are to be formed, and the semiconductor layers 70a and 70b are formed (regrown) using the SiN or the like as a mask, for example, by MOVPE. For example, n-type GaN doped with Si, which is an n-type impurity, is formed as the semiconductor layers 70a and 70b. As a result, the semiconductor layer 70a containing the n-type impurity is formed in the recesses 25a of the semiconductor laminated structure 20. The semiconductor layer 70b containing the n-type impurity is formed in the recesses 25b of the semiconductor laminated structure 20. For example, after the semiconductor layers 70a and 70b are formed, the SiN or the like used as the mask is removed.

[0096] The semiconductor layer 70a formed in the recess 25a may be formed so that its end portion is on a part of the surface 20a of the semiconductor laminate structure 20. The semiconductor layer 70b formed in the recess 25b may be formed so that its end portion is on a part of the surface 20a of the semiconductor laminate structure 20. By forming the semiconductor layer 70a and the semiconductor layer 70b in this manner, the semiconductor layer 70a and the semiconductor layer 70b having the shape described in FIG. 6 and the like are obtained. By forming the semiconductor layer 70a and the semiconductor layer 70b in this manner, the recess 25a and the recess 25b are sufficiently filled with the semiconductor layer 70a and the semiconductor layer 70b, respectively, and the distribution of depressions in the substrate surface formed due to insufficient filling of the recess 25a and the recess 25b is suppressed.

[0097] The semiconductor layer 70a formed in the recess 25a may be formed so that its upper surface is located in the same plane as the surface 20a of the semiconductor laminated structure 20 (i.e., a shape that does not run onto the surface 20a). The semiconductor layer 70b formed in the recess 25b may be formed so that its upper surface is located in the same plane as the surface 20a of the semiconductor laminated structure 20 (i.e., a shape that does not run onto the surface 20a). By forming the semiconductor layer 70a and the semiconductor layer 70b in this manner, the semiconductor layer 70a and the semiconductor layer 70b having the shapes described in FIG. 9 and the like can be obtained. Furthermore, by forming the semiconductor layer 70a and the semiconductor layer 70b in this manner, the flatness of the substrate is improved.

[0098] After the semiconductor layer 70a and the semiconductor layer 70b are formed, the source electrode 30 and the drain electrode 40 are formed as shown in FIG. 12(B). For example, lithography, deposition, and lift-off techniques are used to form a metal electrode material in the region where the source electrode 30 and the drain electrode 40 are to be formed. For example, a laminate of Ta and Al or an Al-containing metal is formed as the metal electrode material. The metal electrode material is formed so as to cover the semiconductor layer 70a and the portion 20aa of the surface 20a of the semiconductor laminated structure 20 adjacent thereto. The metal electrode material is formed so as to cover the semiconductor layer 70b and the portion 20ab of the surface 20a of the semiconductor laminated structure 20 adjacent thereto. After the metal electrode material is formed, a heat treatment is performed in a nitrogen atmosphere at a temperature in the range of 400° C. to 1000° C., for example, at 600° C., to establish an ohmic connection of the metal electrode material. 12(B), the source electrode 30 covering the semiconductor layer 70a and the adjacent portion 20aa, and the drain electrode 40 covering the semiconductor layer 70b and the adjacent portion 20ab are formed. The source electrode 30 and the drain electrode 40 function as ohmic electrodes.

[0099] After the source electrode 30 and the drain electrode 40 are formed, as shown in FIG. 13(A), an insulating film 60 is formed as a passivation film. For example, first, an insulating material such as SiN used for the insulating film 60 is formed so as to cover at least the portion 20ad exposed from the source electrode 30 and the drain electrode 40 on the surface 20a of the semiconductor laminated structure 20. The insulating material may be formed so as to cover the source electrode 30 and the drain electrode 40 in addition to the portion 20ad. After the insulating material is formed, lithography and etching techniques are used to form an opening 61 in the region where the gate electrode 50 is to be formed (the portion 20ac of the surface 20a). As a result, the insulating film 60 as shown in FIG. 13(A), that is, the insulating film 60 that covers the portion 20ad of the surface 20a of the semiconductor laminated structure 20 and exposes the portion 20ac of the surface 20a from the opening 61, is formed. The insulating film 60 is in contact with the portion 20ad of the surface 20a and the source electrode 30 and the drain electrode 40, and is separated from the semiconductor layer 70a and the semiconductor layer 70b.

[0100] After the insulating film 60 having the opening 61 is formed, the gate electrode 50 is formed as shown in FIG. 13(B). For example, lithography, deposition, and lift-off techniques are used to form a metal electrode material in the region where the gate electrode 50 is to be formed, that is, in the portion 20ac of the surface 20a of the semiconductor laminated structure 20. For example, a laminate of Ni and Au is formed as the metal electrode material. Such a metal electrode material is formed to form the gate electrode 50. The gate electrode 50 functions as a Schottky electrode. The gate electrode 50 may be formed on a part of the upper surface of the insulating film 60 (the edge of the opening 61) as well as on the portion 20ac of the surface 20a of the semiconductor laminated structure 20, and may have a T-shaped cross section. In addition, before the metal electrode material is formed, a gate insulating film using an oxide, nitride, oxynitride, or the like may be formed on the portion 20ac of the surface 20a to form the MIS-type gate electrode 50. The gate electrode 50 may be asymmetrically disposed closer to the source electrode 30 than to the drain electrode 40.

[0101] For example, the semiconductor device 1 shown in Fig. 13(B) (and Figs. 4, 6, 9, etc.) is manufactured by the above-mentioned steps. The semiconductor device 1 adopts a configuration in which a semiconductor layer 70b is provided in the semiconductor laminated structure 20, and a drain electrode 40 is provided to cover the semiconductor layer 70b and a portion 20ab of the surface 20a adjacent thereto. The semiconductor device 1 further adopts a configuration in which a semiconductor layer 70a is provided in the semiconductor laminated structure 20, and a source electrode 30 is provided to cover the semiconductor layer 70a and a portion 20aa of the surface 20a adjacent thereto. This realizes a high-performance semiconductor device 1 with excellent reliability.

[0102] The types and layer structures of the metal materials used for the source electrode 30, drain electrode 40, and gate electrode 50 of the semiconductor device 1 are not limited to the above examples, and the method of forming them is not limited to the above examples. The source electrode 30, drain electrode 40, and gate electrode 50 may each have a single layer structure or a laminated structure. When forming the source electrode 30 and drain electrode 40, it is not necessary to perform the above-mentioned heat treatment as long as ohmic connection is realized by forming the metal material for the electrodes. When forming the gate electrode 50, a heat treatment may be further performed after forming the metal material for the electrodes.

[0103] Here, an example is shown in which a SiC substrate is used as the substrate 10, but other substrate materials may be used as long as a nitride semiconductor is used in the structure having the function of a field effect transistor. A conductive substrate, an insulating substrate, or a semi-insulating substrate may be used as the substrate 10. A SiC substrate, a GaN substrate, a Si substrate, a sapphire substrate, a diamond substrate, or the like may be used for the whole or part of the substrate 10.

[0104] Furthermore, the nitride semiconductors used in the buffer layer 21, the electron transit layer 22, the spacer layer 23, and the electron supply layer 24 included in the semiconductor laminate structure 20 are not limited to the above examples. As long as the semiconductor device 1 functions as a HEMT, various nitride semiconductors may be used in the layers of the semiconductor laminate structure 20. Furthermore, in the semiconductor laminate structure 20, the spacer layer 23 may be omitted, and the electron supply layer 24 may be formed directly on the electron transit layer 22.

[0105] [Second embodiment] Fig. 14 is a diagram illustrating an example of a semiconductor device according to the second embodiment. Fig. 14 is a schematic cross-sectional view of a main part of the example of the semiconductor device.

[0106] The semiconductor device 1A shown in Fig. 14 is an example of a HEMT. The semiconductor device 1A has a configuration in which a source electrode 30 is provided on a part of a semiconductor layer 70a, and an end 72 of the semiconductor layer 70a is not covered by the source electrode 30. The semiconductor device 1A differs from the semiconductor device 1 described in the first embodiment in that it has such a configuration. In the semiconductor device 1A, the end 72 of the semiconductor layer 70a that is not covered by the source electrode 30 is in contact with the insulating film 60 of the passivation film.

[0107] During operation of the semiconductor device 1A, a voltage is applied to the source electrode 30 so that the source electrode 30 has a lower potential than the drain electrode 40. On the source electrode 30 side, which has a relatively low potential, electron traps are less likely to occur at the interface between the semiconductor layer 70a and the insulating film 60. This suppresses depletion of the electron transit layer 22 directly below the end 72 and the resulting decrease in electron concentration. On the other hand, the drain electrode 40, which has a relatively high potential, is provided so as to cover the semiconductor layer 70b and the portion 20ab of the surface 20a adjacent thereto. The insulating film 60 is provided at a portion 20ad different from the portion 20ab. This prevents the formation of an interface where the semiconductor layer 70b and the insulating film 60 come into contact with each other, suppressing electron traps at the interface and the resulting decrease in electron concentration in the electron transit layer 22. Furthermore, on the drain electrode 40 side, the current density of the current flowing from the drain electrode 40 to the electron transit layer 22 is mitigated, suppressing electromigration.

[0108] The configuration shown in FIG. 14 also realizes a high-performance semiconductor device 1A having excellent reliability. In the semiconductor device 1A, the spacer layer 23 of the semiconductor stack 20 may be omitted. In the semiconductor device 1A, the semiconductor layer 70a and the semiconductor layer 70b may have a tapered shape in which the width narrows from the surface 20a of the semiconductor stack 20 toward the electron transit layer 22, or may have a constant width from the surface 20a to the electron transit layer 22.

[0109] [Third embodiment] Fig. 15 is a diagram illustrating an example of a semiconductor device according to the third embodiment. Fig. 15 is a schematic cross-sectional view of a main part of the example of the semiconductor device.

[0110] The semiconductor device 1B shown in Fig. 15 is an example of a HEMT. The semiconductor device 1B has a configuration in which a semiconductor laminated structure 20 includes a cap layer 26 provided on a surface 20a side of the semiconductor laminated structure 20. The upper surface of the cap layer 26 becomes the surface 20a of the semiconductor laminated structure 20. The semiconductor device 1B differs from the semiconductor device 1 described in the first embodiment in that it has such a configuration.

[0111] The cap layer 26 is made of a nitride semiconductor. The cap layer 26 is made of, for example, GaN, AlN, or the like. In the semiconductor device 1B, a semiconductor layer 70a and a semiconductor layer 70b are provided in the recesses 25a and 25b that penetrate the cap layer 26, the electron supply layer 24, and the spacer layer 23 and reach the electron transit layer 22. In the semiconductor device 1B, a source electrode 30 is provided so as to cover the semiconductor layer 70a and a portion 20aa of the surface 20a (the upper surface of the cap layer 26) adjacent thereto. In the semiconductor device 1B, a drain electrode 40 is provided so as to cover the semiconductor layer 70b and a portion 20ab of the surface 20a (the upper surface of the cap layer 26) adjacent thereto. An insulating film 60 of a passivation film is provided in a portion 20ad different from the portions 20aa and 20ab.

[0112] Even when the semiconductor laminated structure 20 includes such a cap layer 26, the semiconductor layer 70a and the source electrode 30, and the semiconductor layer 70b and the drain electrode 40 can be provided according to the example of the semiconductor device 1 described in the first embodiment. This makes it possible to obtain the same effects as those described for the semiconductor device 1.

[0113] The configuration shown in FIG. 15 also realizes a high-performance semiconductor device 1B having excellent reliability. In the semiconductor device 1B, the spacer layer 23 of the semiconductor laminated structure 20 may be omitted. In the semiconductor device 1B, the semiconductor layer 70a and the semiconductor layer 70b may have a tapered shape narrowing from the surface 20a of the semiconductor laminated structure 20 toward the electron transit layer 22, or may have a constant width from the surface 20a to the electron transit layer 22. In the semiconductor device 1B, a configuration may be adopted on the source electrode 30 side such that the end of the semiconductor layer 70a is not covered by the source electrode 30, following the example of the semiconductor device 1A described in the second embodiment.

[0114] The first to third embodiments have been described above. The above-described semiconductor devices 1, 1A, 1B, etc. can be applied to various electronic devices. As an example, the following describes the case where the semiconductor device having the above-described configuration is applied to a semiconductor package, a power factor correction circuit, a power supply device, and an amplifier.

[0115] [Fourth embodiment] Here, an example of application of the semiconductor device having the above-mentioned configuration to a semiconductor package will be described as the fourth embodiment.

[0116] Fig. 16 is a diagram illustrating an example of a semiconductor package according to the fourth embodiment. Fig. 16 is a schematic plan view of a main part of the example of the semiconductor package. The semiconductor package 200 shown in Fig. 16 is an example of a discrete package. The semiconductor package 200 includes, for example, the semiconductor device 1 (Fig. 4, etc.) as described in the first embodiment, a lead frame 210 on which the semiconductor device 1 is mounted, and a resin 220 that seals them.

[0117] The semiconductor device 1 is mounted on a die pad 210a of a lead frame 210 using, for example, a die attach material or the like (not shown). The semiconductor device 1 is provided with a pad 50a connected to the gate electrode 50, a pad 30a connected to the source electrode 30, and a pad 40a connected to the drain electrode 40. The pads 50a, 30a, and 40a are connected to the gate lead 211, the source lead 212, and the drain lead 213 of the lead frame 210 using wires 230 made of Au, Al, or the like, respectively. The lead frame 210, the semiconductor device 1 mounted thereon, and the wires 230 connecting them are sealed with resin 220 so that parts of the gate lead 211, the source lead 212, and the drain lead 213 are exposed.

[0118] An external connection electrode connected to the source electrode 30 may be provided on the surface of the semiconductor device 1 opposite to the surface on which the pad 50a connected to the gate electrode 50 and the pad 40a connected to the drain electrode 40 are provided. The external connection electrode may be connected to the die pad 210a connected to the source lead 212 by using a conductive bonding material such as solder.

[0119] For example, the semiconductor device 1 as described in the first embodiment is used, and a semiconductor package 200 having such a configuration is obtained. As described above, the semiconductor device 1 has a configuration in which the semiconductor layer 70b is provided in the semiconductor laminated structure 20, and the drain electrode 40 is provided so as to cover the semiconductor layer 70b and the portion 20ab of the surface 20a adjacent thereto. This avoids the formation of an interface where the semiconductor layer 70b and the insulating film 60 come into contact with each other, and suppresses the electron trap at the interface and the resulting decrease in the electron concentration of the electron transit layer 22. Furthermore, the current density of the current flowing from the drain electrode 40 to the electron transit layer 22 is reduced, and electromigration is suppressed. Furthermore, the semiconductor device 1 has a configuration in which the semiconductor layer 70a is provided in the semiconductor laminated structure 20, and the source electrode 30 is provided so as to cover the semiconductor layer 70a and the portion 20aa of the surface 20a adjacent thereto. This reduces the current density of the current flowing from the electron transit layer 22 to the source electrode 30, and suppresses electromigration. By adopting the above-mentioned configuration, a high-performance semiconductor device 1 having excellent reliability is realized. By using such a semiconductor device 1, a high-performance semiconductor package 200 is realized.

[0120] Although the semiconductor device 1 is taken as an example here, it is possible to obtain a semiconductor package in a similar manner using other semiconductor devices 1A, 1B, etc. [Fifth embodiment] Here, an example of application of the semiconductor device having the above-mentioned configuration to a power factor correction circuit will be described as the fifth embodiment.

[0121] Fig. 17 is a diagram for explaining an example of a power factor correction circuit according to the fifth embodiment. Fig. 17 shows an equivalent circuit diagram of the example of the power factor correction circuit. A power factor correction (PFC) circuit 300 shown in FIG. 17 includes a switch element 310, a diode 320, a choke coil 330, a capacitor 340, a capacitor 350, a diode bridge 360, and an AC power supply 370 (AC).

[0122] In the PFC circuit 300, a drain electrode of a switch element 310 is connected to an anode terminal of a diode 320 and one terminal of a choke coil 330. A source electrode of the switch element 310 is connected to one terminal of a capacitor 340 and one terminal of a capacitor 350. The other terminal of the capacitor 340 is connected to the other terminal of the choke coil 330. The other terminal of the capacitor 350 is connected to a cathode terminal of the diode 320. A gate driver is connected to the gate electrode of the switch element 310. An AC power supply 370 is connected between both terminals of the capacitor 340 via a diode bridge 360, and a DC power supply (DC) is taken out from between both terminals of the capacitor 350.

[0123] For example, the semiconductor device 1, 1A, 1B, etc. is used for the switch element 310 of the PFC circuit 300 having such a configuration. As described above, in the semiconductor devices 1, 1A, 1B, etc., a configuration is adopted in which the semiconductor layer 70b is provided in the semiconductor laminated structure 20, and the drain electrode 40 is provided so as to cover the semiconductor layer 70b and the portion 20ab of the surface 20a adjacent thereto. This avoids the formation of an interface where the semiconductor layer 70b and the insulating film 60 come into contact with each other, and suppresses the electron trap at the interface and the resulting decrease in the electron concentration of the electron transit layer 22. Furthermore, the current density of the current flowing from the drain electrode 40 to the electron transit layer 22 is reduced, and electromigration is suppressed. Also, for example, as in the semiconductor device 1, a configuration may be adopted in which the semiconductor layer 70a is provided in the semiconductor laminated structure 20, and the source electrode 30 is provided so as to cover the semiconductor layer 70a and the portion 20aa of the surface 20a adjacent thereto. This reduces the current density of the current flowing from the electron transit layer 22 to the source electrode 30, and suppresses electromigration. By adopting the above-mentioned configuration, the semiconductor devices 1, 1A, 1B, etc., with excellent reliability and high performance are realized. A high-performance PFC circuit 300 is realized by using such semiconductor devices 1, 1A, 1B, etc.

[0124] [Sixth embodiment] Here, an example in which the semiconductor device having the above-mentioned configuration is applied to a power supply device will be described as the sixth embodiment.

[0125] Fig. 18 is a diagram illustrating an example of a power supply device according to the sixth embodiment. Fig. 18 shows an equivalent circuit diagram of the example of the power supply device. The power supply device 400 shown in FIG. 18 includes a primary side circuit 410, a secondary side circuit 420, and a transformer 430 provided between the primary side circuit 410 and the secondary side circuit 420.

[0126] The primary side circuit 410 includes the PFC circuit 300 as described in the fifth embodiment above, and an inverter circuit, for example, a full-bridge inverter circuit 440, connected between both terminals of the capacitor 350 of the PFC circuit 300. The full-bridge inverter circuit 440 includes a plurality of switch elements, for example, four switch elements 441, 442, 443, and 444.

[0127] The secondary side circuit 420 includes a plurality of switch elements, three of which, as an example here, are a switch element 421, a switch element 422, and a switch element 423. For example, the semiconductor devices 1, 1A, 1B, etc. are used for the switch element 310 of the PFC circuit 300 included in the primary side circuit 410 of the power supply device 400 having such a configuration, and for the switch elements 441-444 of the full bridge inverter circuit 440. For example, normal MIS type field effect transistors using Si are used for the switch elements 421, 422, 423 of the secondary side circuit 420 of the power supply device 400.

[0128] As described above, in the semiconductor devices 1, 1A, 1B, etc., a configuration is adopted in which the semiconductor layer 70b is provided in the semiconductor laminated structure 20, and the drain electrode 40 is provided so as to cover the semiconductor layer 70b and the portion 20ab of the surface 20a adjacent thereto. This avoids the formation of an interface where the semiconductor layer 70b and the insulating film 60 come into contact with each other, and suppresses the electron trap at the interface and the resulting decrease in the electron concentration of the electron transit layer 22. Furthermore, the current density of the current flowing from the drain electrode 40 to the electron transit layer 22 is reduced, and electromigration is suppressed. Also, for example, as in the semiconductor device 1, a configuration may be adopted in which the semiconductor layer 70a is provided in the semiconductor laminated structure 20, and the source electrode 30 is provided so as to cover the semiconductor layer 70a and the portion 20aa of the surface 20a adjacent thereto. This reduces the current density of the current flowing from the electron transit layer 22 to the source electrode 30, and suppresses electromigration. By adopting the above-mentioned configuration, the semiconductor devices 1, 1A, 1B, etc., with excellent reliability and high performance are realized. A high-performance power supply device 400 is realized by using such semiconductor devices 1, 1A, 1B, etc.

[0129] [Seventh embodiment] Here, an example of application of the semiconductor device having the above-mentioned configuration to an amplifier will be described as the seventh embodiment.

[0130] Fig. 19 is a diagram for explaining an example of an amplifier according to the seventh embodiment, showing an equivalent circuit diagram of the example of the amplifier. The amplifier 500 shown in FIG. 19 includes a digital predistortion circuit 510, a mixer 520, a mixer 530, and a power amplifier 540.

[0131] The digital predistortion circuit 510 compensates for nonlinear distortion of the input signal. The mixer 520 mixes the input signal SI, for which the nonlinear distortion has been compensated, with an AC signal. The power amplifier 540 amplifies the signal obtained by mixing the input signal SI with the AC signal. In the amplifier 500, for example, by switching a switch, the output signal SO can be mixed with the AC signal in the mixer 530 and sent to the digital predistortion circuit 510. The amplifier 500 can be used as a high-frequency amplifier or a high-power amplifier.

[0132] The above-mentioned semiconductor device 1, 1A, 1B, etc. is used in the power amplifier 540 of the amplifier 500 having such a configuration. As described above, in the semiconductor devices 1, 1A, 1B, etc., a configuration is adopted in which the semiconductor layer 70b is provided in the semiconductor laminated structure 20, and the drain electrode 40 is provided so as to cover the semiconductor layer 70b and the portion 20ab of the surface 20a adjacent thereto. This avoids the formation of an interface where the semiconductor layer 70b and the insulating film 60 come into contact with each other, and suppresses the electron trap at the interface and the resulting decrease in the electron concentration of the electron transit layer 22. Furthermore, the current density of the current flowing from the drain electrode 40 to the electron transit layer 22 is reduced, and electromigration is suppressed. Also, for example, as in the semiconductor device 1, a configuration may be adopted in which the semiconductor layer 70a is provided in the semiconductor laminated structure 20, and the source electrode 30 is provided so as to cover the semiconductor layer 70a and the portion 20aa of the surface 20a adjacent thereto. This reduces the current density of the current flowing from the electron transit layer 22 to the source electrode 30, and suppresses electromigration. By adopting the above-mentioned configuration, the semiconductor devices 1, 1A, 1B, etc., with excellent reliability and high performance are realized. A high-performance amplifier 500 is realized by using such semiconductor devices 1, 1A, 1B, etc.

[0133] Various electronic devices to which the semiconductor devices 1, 1A, 1B and the like are applied (such as the semiconductor package 200, the PFC circuit 300, the power supply device 400 and the amplifier 500 described in the fourth to seventh embodiments) can be mounted in various electronic devices or electronic devices. For example, they can be mounted in various electronic devices or electronic devices such as computers (personal computers, supercomputers, servers, etc.), smartphones, mobile phones, tablet terminals, sensors, cameras, audio equipment, measuring devices, inspection devices, manufacturing devices, transmitters, receivers, and radar devices.

[0134] The following supplementary notes are further provided with respect to the embodiment described above. (Note 1) A semiconductor laminate structure including an electron transport layer and an electron supply layer; a first semiconductor layer provided in the semiconductor laminate structure, extending from a first surface of the semiconductor laminate structure on the electron supply layer side to the electron transit layer, and containing an n-type impurity; a first electrode connected to the first semiconductor layer, covering the first semiconductor layer, and in contact with a first portion of the first surface of the semiconductor laminated structure that is adjacent to the first semiconductor layer; 13. A semiconductor device comprising:

[0135] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the first electrode covers the first portion. (Appendix 3) The semiconductor device described in appendix 1 or 2, further including an insulating film provided on the first surface of the semiconductor laminated structure and covering a second portion of the first surface that is different from the first portion covered by the first electrode.

[0136] (Supplementary Note 4) The semiconductor device according to Supplementary Note 3, wherein the insulating film is in contact with the second portion on the first surface of the semiconductor laminate structure and the first electrode covering the first portion. (Supplementary Note 5) The semiconductor device according to Supplementary Note 1 or 2, wherein the first semiconductor layer has a tapered shape in which a width in a direction parallel to the first surface narrows from the first surface toward the electron transit layer.

[0137] (Additional Note 6) The semiconductor device described in Additional Note 2, wherein the first semiconductor layer covers a portion of the first portion of the first surface of the semiconductor laminated structure that is covered by the first electrode and is located inside an edge of the first electrode.

[0138] (Additional Note 7) The electron transport layer includes a first nitride semiconductor containing gallium, the electron supply layer includes a second nitride semiconductor containing indium and at least one of aluminum and gallium; 3. The semiconductor device according to claim 1, wherein the first semiconductor layer includes a third nitride semiconductor containing gallium.

[0139] (Supplementary Note 8) The semiconductor device according to Supplementary Note 1 or 2, wherein the semiconductor laminate structure further includes a cap layer on the first surface side. (Note 9) A second semiconductor layer is provided in the semiconductor laminate structure, separated from the first semiconductor layer, extends from the first surface to the electron transit layer, and contains an n-type impurity; a second electrode provided separately from the first electrode and connected to the second semiconductor layer; 3. The semiconductor device according to claim 1 or 2, further comprising:

[0140] (Supplementary Note 10) The semiconductor device according to Supplementary Note 9, wherein the first portion on the first surface of the semiconductor laminate structure is adjacent to the first semiconductor layer on a side of the second semiconductor layer. (Supplementary Note 11) The semiconductor device according to Supplementary Note 9, wherein the second electrode covers the second semiconductor layer and a third portion of the first surface of the semiconductor laminated structure adjacent to the second semiconductor layer.

[0141] (Supplementary Note 12) The semiconductor device according to Supplementary Note 11, wherein the third portion on the first surface of the semiconductor laminate structure is adjacent to the second semiconductor layer on a side of the first semiconductor layer. (Supplementary Note 13) The semiconductor device according to Supplementary Note 9, further comprising a third electrode provided between the first electrode and the second electrode and separated from the first electrode and the second electrode.

[0142] (Appendix 14) A step of forming a semiconductor laminate structure including an electron transport layer and an electron supply layer; forming a first semiconductor layer in the semiconductor laminate structure, the first semiconductor layer including an n-type impurity and extending from a first surface of the semiconductor laminate structure on the electron supply layer side to the electron transit layer; forming a first electrode connected to the first semiconductor layer, covering the first semiconductor layer, and in contact with a first portion of the first surface of the semiconductor laminate structure adjacent to the first semiconductor layer; A method for manufacturing a semiconductor device comprising the steps of:

[0143] (Appendix 15) A semiconductor laminate structure including an electron transport layer and an electron supply layer; a first semiconductor layer provided in the semiconductor laminate structure, extending from a first surface of the semiconductor laminate structure on the electron supply layer side to the electron transit layer, and containing an n-type impurity; a first electrode connected to the first semiconductor layer, covering the first semiconductor layer, and in contact with a first portion of the first surface of the semiconductor laminated structure that is adjacent to the first semiconductor layer; An electronic device comprising a semiconductor device including: [Explanation of symbols]

[0144] 1, 1A, 1B, 100A, 100B Semiconductor device 10, 110 Board 20, 120 Semiconductor laminate structure 20a, 120a side 20aa, 20ab, 20ac, 20ad parts 21, 121 Buffer layer 22, 122 Electron transport layer 23, 123 Spacer layer 24, 124 electron supply layer 25a, 25b, 125a, 125b Recess 26 Cap Layer 30, 130 Source electrode 30a, 40a, 50a pads 40, 140 Drain electrode 41 edge 50, 150 Gate electrode 60, 160 Insulating film 61 Opening 70a, 70b, 170a, 170b Semiconductor layers 71, 72, 171 End 80, 180 2DEG area 90, 190 current 191 Electronic 200 Semiconductor Packages 210 Lead Frame 210a Die pad 211 Gate Lead 212 Source Read 213 Drain Lead 220 Resin 230 Wire 300 PFC circuit 310, 421, 422, 423, 441, 442, 443, 444 Switch elements 320 Diode 330 Choke Coil 340, 350 Capacitor 360 Diode Bridge 370 AC power supply 400 power supply 410 Primary circuit 420 Secondary circuit 430 Trans 440 Full-bridge inverter circuit 500 Amplifier 510 Digital Pre-Distortion Circuit 520, 530 Mixer 540 Power Amplifier a1, b1, c1, d1, e1 position AR0 area W1 width

Claims

1. a semiconductor laminate structure including an electron transport layer and an electron supply layer; a first semiconductor layer provided in the semiconductor laminate structure, the first semiconductor layer extending from a first surface of the semiconductor laminate structure on the electron supply layer side to the electron transit layer, and containing an n-type impurity; a first electrode connected to the first semiconductor layer, covering the first semiconductor layer, and in contact with a first portion of the first surface of the semiconductor laminated structure adjacent to the first semiconductor layer; 13. A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the first electrode covers the first portion.

3. 3 . The semiconductor device according to claim 1 , further comprising an insulating film provided on the first surface of the semiconductor laminated structure, the insulating film covering a second portion of the first surface that is different from the first portion covered by the first electrode.

4. The semiconductor device according to claim 3 , wherein the insulating film is in contact with the second portion on the first surface of the semiconductor laminate structure and the first electrode covering the first portion.

5. 3 . The semiconductor device according to claim 1 , wherein the first semiconductor layer has a tapered shape in which a width in a direction parallel to the first surface narrows from the first surface toward the electron transit layer.

6. The semiconductor device according to claim 2 , wherein the first semiconductor layer covers a part of the first portion covered by the first electrode on the first surface of the semiconductor laminate structure, the part being located inside an edge of the first electrode.

7. a second semiconductor layer that is provided in the semiconductor laminate structure and is separated from the first semiconductor layer, that extends from the first surface to the electron transit layer, and that contains an n-type impurity; a second electrode provided separately from the first electrode and connected to the second semiconductor layer; The semiconductor device according to claim 1 , further comprising:

8. The semiconductor device according to claim 7 , wherein the second electrode covers the second semiconductor layer and a third portion of the first surface of the semiconductor laminate structure adjacent to the second semiconductor layer.

9. forming a semiconductor laminate structure including an electron transit layer and an electron supply layer; forming a first semiconductor layer in the semiconductor laminate structure, the first semiconductor layer including an n-type impurity and extending from a first surface of the semiconductor laminate structure on the electron supply layer side to the electron transit layer; forming a first electrode connected to the first semiconductor layer, covering the first semiconductor layer, and in contact with a first portion of the first surface of the semiconductor laminate structure adjacent to the first semiconductor layer; A method for manufacturing a semiconductor device comprising the steps of:

10. a semiconductor laminate structure including an electron transport layer and an electron supply layer; a first semiconductor layer provided in the semiconductor laminate structure, the first semiconductor layer extending from a first surface of the semiconductor laminate structure on the electron supply layer side to the electron transit layer, and containing an n-type impurity; a first electrode connected to the first semiconductor layer, covering the first semiconductor layer, and in contact with a first portion of the first surface of the semiconductor laminated structure adjacent to the first semiconductor layer; An electronic device comprising a semiconductor device including:

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