Surrounding pattern and process aware metrology

Abstract

A method and system are described for designing a mark for use in imaging a pattern on a substrate using a lithographic process in a lithographic apparatus, the method comprising obtaining a mark construct, obtaining spatial variations of geometric parameters associated with the mark construct, and determining a geometry design for an individual pattern of the mark based on the spatial variations and spatial positions of the mark.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to European Application No. 21213572.7, filed December 9, 2021, which is incorporated by reference in its entirety into this specification. [Background technology]

[0002] FIELD OF THE DISCLOSURE

[0002] The description herein relates to metrology of products in lithography processes, and in particular to designing metrology targets.

[0003]

[0003] A lithographic apparatus is a machine constructed to apply a desired pattern onto a substrate. Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). A lithographic apparatus can project, for example, a pattern (often called a "design layout" or "design") from a patterning device (e.g., a mask) onto a layer of radiation-sensitive material (resist) provided on a substrate (e.g., a wafer). This manufacturing process can be called a patterning process or a lithography process. For example, in a smartphone, an IC chip can be as small as a human thumbnail and can contain over 2 billion transistors. Manufacturing ICs is a complex and time-consuming process involving hundreds of separate steps, with circuit components on various layers. Even an error in one step can cause problems in the final IC and may result in device failure. High process yields and high wafer throughput can be affected by the presence of defects, especially if operator intervention is required to investigate the defects.

[0004]

[0004] Metrology processes are used to monitor and / or control the process at various steps during a patterning process. For example, a metrology process can be used to measure one or more characteristics of a substrate, such as the relative location (e.g., registration, overlay, alignment, etc.) or dimensions (e.g., line width, critical dimension (CD), thickness, etc.) of features formed on a substrate during a patterning process, so that, for example, the performance of the patterning process can be determined from the one or more characteristics. If one or more characteristics are unacceptable (e.g., outside a predetermined range for the characteristics), one or more variables of the patterning process can be designed or altered, for example, based on the measurement of the one or more characteristics, so that a substrate produced by the patterning process has acceptable characteristics. Summary of the Invention

[0005] In some embodiments, a non-transitory computer readable medium is provided having instructions that, when executed by a computer, cause the computer to perform a method for mark design for use in imaging a pattern on a substrate using a lithographic process in a lithographic apparatus, the method including obtaining a mark construct, obtaining a spatial variation of a geometric parameter associated with the mark construct, the spatial variation being associated with the lithographic process, and determining a geometric design of an individual pattern of the mark based on the spatial variation of the mark.

[0006] In some embodiments, a method is provided for designing a mark for use in imaging a pattern on a substrate using a lithographic process in a lithographic apparatus, the method including obtaining a mark construct, obtaining a spatial variation of a geometric parameter associated with the mark construct, the spatial variation being associated with the lithographic process, and determining a geometry design of an individual pattern of the mark based on the spatial variation of the mark.

[0007]

[0007] In some embodiments, an apparatus is provided for designing a mark for use in imaging a pattern on a substrate using a lithographic process in a lithographic apparatus, the apparatus including a memory storing a set of instructions and a processor configured to execute the set of instructions to cause the apparatus to perform a method, the method comprising: obtaining a mark construct, obtaining a spatial variation of a geometric parameter associated with the mark construct, the spatial variation being associated with the lithographic process, and determining a geometric design of an individual pattern of the mark based on the spatial variation of the mark. [Brief description of the drawings]

[0008] [Figure 1]

[0008] FIG. 1 is a schematic diagram of a lithographic projection apparatus according to an embodiment. [Diagram 2]

[0009] 1 illustrates an embodiment of a lithographic cell or cluster. [Figure 3A]

[0010] 1 is a schematic diagram of a measurement apparatus (eg, a metrology apparatus) used to measure a target using a first pair of illumination apertures that provide a particular illumination mode, according to one embodiment. [Figure 3B]

[0011] FIG. 2 is a schematic detailed diagram of the diffraction spectrum of a target for a given direction of illumination, according to one embodiment; [Figure 3C]

[0012] FIG. 13 is a schematic diagram of a second pair of illumination apertures that provide an additional illumination mode when using a diffraction metrology apparatus based on overlay measurements, according to one embodiment. [Figure 3D]

[0013] FIG. 13 is a schematic diagram of a third pair of illumination apertures that combines the first and second pairs of apertures to provide an additional illumination mode when using a diffraction metrology apparatus based on overlay measurements, according to one embodiment. [Figure 3E]

[0014] 1 shows a schematic of one configuration of a multiple periodic structure (eg, multiple grating) target and measurement spots on a substrate, according to one embodiment. [Figure 3F]

[0015] 3E shows an image of the target of FIG. 3E acquired in the apparatus of FIG. 3A. [Figure 4A-4C]

[0016] 1 includes a flowchart of various aspects of an exemplary target design method that can be used in designing targets disclosed herein, according to one embodiment. [Diagram 5]

[0017] FIG. 1 is a block diagram of a system for designing a mark based on the local geometry of the mark, according to one embodiment. [Figure 6A-6B]

[0018] FIG. 2 is a flow diagram of a method for designing a mark based on the local geometry of the mark, according to one embodiment. [Figure 7]

[0019] 1 illustrates an exemplary dummification process of a mark according to one embodiment. [Figure 8]

[0020] FIG. 1 is a block diagram illustrating a computer system that can assist in implementing the systems and methods disclosed herein. [Figure 9]

[0021] 1 shows a flow of a lithography process or patterning simulation method according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]

[0022] Metrology is a process used to measure one or more characteristics of a substrate, such as the relative location (e.g., registration, overlay, alignment, etc.) or dimensions (e.g., line width, critical dimension (CD), thickness, etc.) of features formed on the substrate during a patterning process, so that, for example, the performance of the patterning process can be determined from the one or more characteristics. Metrology targets (also called "metrology marks" or "marks"), such as overlay (OVL) marks, alignment marks, or other marks (fiducials), may be used in obtaining the measurements. Metrology marks are constructed or designed based on one or more lithography process parameters. Metrology marks may include several individual patterns therein (e.g., periodic structures such as gratings). Simulation models may be used in designing or optimizing metrology marks, or in determining the metrology performance of metrology marks (e.g., the accuracy of measurements obtained using metrology marks). However, conventional methods of designing metrology marks are inefficient. For example, when optimizing a metrology mark, conventional methods use nominal geometric parameters (e.g., for the entire metrology mark or for only a portion of the metrology mark) without considering geometric variations within the mark or surrounding patterns (e.g., patterns within a specified adjacent region of the metrology mark). For example, in a metrology mark simulated by a conventional method, it is assumed that each individual pattern may have the same geometric parameters, such as sidewall angle, etch depth, CD, pitch, etc. However, in reality, there are variations in the geometric parameters of individual patterns within the mark. The variations may result from one or more manufacturing processes in manufacturing the metrology mark, such as deposition, etching, CMP, photolithography, etc. The variations in the geometric parameters of individual patterns, or the presence or absence of surrounding patterns, may significantly affect the measurement performance of the mark.Therefore, metrology marks designed without such considerations may have a non-optimal design, which may result in inaccurate measurements being taken, which may in turn affect the yield of the manufacturing process.

[0010]

[0023] According to the present disclosure, a mark (e.g., a metrology mark) is designed (or optimized) by considering the local geometry of the mark (e.g., spatial variation of the geometric parameters of each of the individual patterns of the mark). The design method may also consider the spatial location of the mark in a target design layout (e.g., a full-chip design layout) or the presence or absence of surrounding patterns of the mark. In some embodiments, a simulation model is used to design the mark, simulate the measurement performance of the mark, and optimize the mark based on the measurement performance. For example, a simulation model is used to simulate the target design layout (e.g., for an entire integrated circuit, also called a "full-chip design layout") based on an input target design layout and processing parameters of a lithography process to generate the target design layout. However, metrology marks in the simulated full-chip design layout are not considered by the simulation model for optimization of the full-chip design layout, and therefore may not be optimized based on the variations in the mark (e.g., spatial variation of the geometric parameters of the individual patterns that make up the mark). Thus, a coarse grid having metrology marks to be optimized is identified in the target design layout, and the coarse grid is interpolated to extract spatial variations of geometric parameters of each of the individual patterns of the metrology marks. The metrology marks are reconstructed based on at least one of the extracted geometric parameters, the spatial locations of the metrology marks in the target design layout, or the surrounding patterns of the metrology marks. A measurement simulation model can simulate measurement parameters (e.g., optical measurement parameters) that would be obtained using the reconstructed metrology marks (e.g., that would have been obtained using a metrology tool). In some embodiments, Key Performance Indicators (KPIs) representative of measurement performance are calculated based on the simulated measurement parameters, and the metrology marks are iteratively optimized until the KPIs are optimized.In some embodiments, adjusting the metrology marks includes adjusting the geometric design (eg, critical dimension, pitch, or sub-segmentation) of individual patterns of the marks.

[0011]

[0024] Figure 1 illustrates a schematic diagram of a lithographic apparatus according to one or more embodiments. - an illumination system (illuminator) IL configured to condition a radiation beam B (e.g. UV radiation or DUV radiation); - a first object holder or support structure (e.g. mask table) MT constructed to hold a patterning device (e.g. mask) MA and connected to a first positioner PM configured to accurately position the patterning device according to certain parameters; - a second object holder, such as a substrate holder or substrate table (e.g. a wafer table) WT constructed to hold a substrate (e.g. a resist-coated wafer) W and connected to a second positioner PW configured to accurately position the substrate according to certain parameters; a projection system (eg a refractive projection lens system) PS configured to project a pattern imparted to a radiation beam B by a patterning device MA onto a target portion C (eg comprising one or more dies) of a substrate W.

[0012]

[0025] Illumination systems may include various types of optical components, such as refractive, reflective, magnetic, electromagnetic, electrostatic, or other types of optical components, or any combination thereof, for directing, shaping, or controlling radiation.

[0013]

[0026] The support structure holds the patterning device in a manner that depends on the orientation of the patterning device, the design of the lithographic apparatus, and other conditions, such as for example whether the patterning device is held in a vacuum environment. The support structure can use mechanical, vacuum, electrostatic or other clamping techniques to hold the patterning device. The support structure may be, for example, a frame or a table, which can be fixed or movable as required. The support structure may ensure that the patterning device is at a desired position, for example with respect to the projection system. Any use of the terms "reticle" or "mask" herein may be considered as synonymous with the more general term "patterning device".

[0014]

[0027] The term "patterning device", as used herein, should be interpreted broadly as referring to any device that can be used to impart a radiation beam with a pattern in its cross-section to create a pattern in a target portion of a substrate. It should be noted that the pattern imparted to the radiation beam may not exactly correspond to the desired pattern in the target portion of the substrate if, for example, the pattern includes phase-shifting features or so-called assist features. Generally, the pattern imparted to the radiation beam corresponds to a particular functional layer in a device being created in the target portion, such as an integrated circuit.

[0015]

[0028] A patterning device may be of a transmissive or reflective type. Examples of patterning devices include masks, programmable mirror arrays, and programmable LCD panels. Masks are well known in lithography, and include mask types such as binary, alternating phase-shift, and attenuated phase-shift, as well as various hybrid mask types. An example of a programmable mirror array employs a matrix arrangement of small mirrors, each of which is individually tilted so as to reflect an incoming radiation beam in different directions. The tilted mirrors impart a pattern to the radiation beam that is reflected by the mirror matrix.

[0016]

[0029] The term "projection system" as used herein should be interpreted broadly as encompassing any type of projection system including, for example, refractive, reflective, catadioptric, magnetic, electromagnetic and electrostatic optical systems, or any combination thereof, as appropriate to the exposure radiation used or other factors such as the use of an immersion liquid or the use of a vacuum. Where the term "projection lens" is used herein, this term can be considered as synonymous with the more general term "projection system".

[0017]

[0030] As here depicted, the apparatus may be of a transmissive type (e.g. employing a transmissive mask) Alternatively, the apparatus may be of a reflective type (e.g. employing a programmable mirror array of a type as referred to above, or employing a reflective mask).

[0018]

[0031] The lithographic apparatus may be of a type having two (dual stage) or more substrate tables (and / or two or more support structures). In such a "multi-stage" machine, the additional tables / support structures can be used in parallel, or preparatory steps can be carried out on one or more tables / support structures while one or more other tables / support structures are being used for exposure.

[0019]

[0032] With reference to Figure 1, the illuminator IL receives a radiation beam from a radiation source SO. The source and the lithographic apparatus may be separate entities, for example when the source is an excimer laser. In such cases, the source is not considered to form part of the lithographic apparatus and the radiation beam is passed from the source SO to the illuminator IL with the aid of a beam delivery system BD, which may include, for example, suitable directing mirrors and / or beam expanders. In other cases the source may be an integral part of the lithographic apparatus, for example when the source is a mercury lamp. The source SO and the illuminator IL, together with the beam delivery system BD if required, may be referred to as a radiation system.

[0020]

[0033] The illuminator IL may comprise an adjuster AD configured to adjust the angular intensity distribution of the radiation beam. Generally, the outer and / or inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution in a pupil plane of the illuminator IL may be adjusted. The illuminator IL may also comprise various other components, such as an integrator IN and a condenser CO. The illuminator IL may be used to condition the radiation beam to have a desired uniformity and intensity distribution across its cross-section.

[0021]

[0034] The radiation beam B is incident on a patterning device (e.g. mask) MA, which is held on a support structure (e.g. mask table) MT, and is patterned by the patterning device. Having traversed the patterning device MA, the radiation beam B passes through a projection system PS, which focuses the beam onto a target portion C of a substrate W. With the aid of a second positioner PW and a position sensor IF (e.g. an interferometric device, a linear encoder or a capacitive sensor), the substrate table WT can be accurately moved, e.g. so that different target portions C can be positioned in the path of the radiation beam B. Similarly, the first positioner PM and another (not explicitly shown in FIG. 1 ) position sensor can be used to accurately position the patterning device MA with respect to the path of the radiation beam B, e.g. after mechanical retrieval from a mask library or during a scan. In general, movement of the support structure MT can be realized with the aid of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning), which form part of the first positioner PM. Similarly, movement of the substrate table WT may be realized using a long-stroke module and a short-stroke module, which form part of the second positioner PW. In the case of a stepper (as opposed to a scanner) the support structure MT may be connected to a short-stroke actuator only, or may be fixed. The patterning device MA and substrate W may be aligned using patterning device alignment marks M1, M2 and substrate alignment marks P1, P2. The substrate alignment marks as illustrated occupy dedicated target portions, but may also be located in spaces between the target portions (these are known as scribe-lane alignment marks). Similarly, in situations in which more than one die is provided on the patterning device MA, the patterning device alignment marks may be located between the dies.

[0022]

[0035] The depicted apparatus can be used in at least one of the following modes: 1. In step mode, the support structure MT and substrate table WT are kept essentially stationary, while an entire pattern imparted to the radiation beam is projected onto the target portion C in one go (i.e. a single static exposure). The substrate table WT is then shifted in the X and / or Y direction so that a different target portion C can be exposed. In step mode, the maximum size of the exposure field limits the size of the target portion C that can be imaged in a single static exposure. 2. In scan mode, the support structure MT and the substrate table WT are scanned synchronously while a pattern imparted to the radiation beam is projected onto a target portion C (i.e. a single dynamic exposure). The velocity and direction of the substrate table WT relative to the support structure MT may be determined by the (de-)magnification and image reversal characteristics of the projection system PS. In scan mode, the maximum size of the exposure field limits the width (in the non-scanning direction) of the target portion in a single dynamic exposure, and the length of the scanning movement determines the height (in the scan direction) of the target portion. 3. In another mode, the support structure MT is kept essentially stationary holding a programmable patterning device and the substrate table WT is moved or scanned while a pattern imparted to the radiation beam is projected onto a target portion C. In this mode, a pulsed radiation source is typically used and the programmable patterning device is updated as required with each movement of the substrate table WT, or between successive pulses of radiation during a scan. This mode of operation is readily applicable to maskless lithography employing a programmable patterning device such as a programmable mirror array of the type referred to above.

[0023]

[0036] Combinations and / or variations on the above described modes of use or entirely different modes of use may also be used.

[0024]

[0037] As shown in FIG. 2, the lithographic apparatus LA may form part of a lithographic cell LC, sometimes also called a lithocell or lithocluster, which also includes apparatus for performing one or more pre-exposure and post-exposure processes on a substrate. Conventionally, these include one or more spin coaters SC for depositing a resist layer, one or more developers DE for developing the exposed resist, one or more chill plates CH, and / or one or more bake plates BK. A substrate handler or robot RO picks up one or more substrates from input / output ports I / O1, I / O2, moves them between the different processing devices, and delivers them to a loading bay LB of the lithographic apparatus. These apparatuses are often collectively called a track and are under the control of a track control unit TCU, which is itself controlled by a supervisory control system SCS, which also controls the lithographic apparatus via a lithography control unit LACU. In this way, the different apparatuses can be operated to maximize throughput and processing efficiency.

[0025]

[0038] To ensure that a substrate exposed by a lithographic apparatus is correctly and consistently exposed and / or to monitor a portion of a patterning process (e.g., a device manufacturing process) that includes at least one pattern transfer step (e.g., an optical lithography step), it is desirable to inspect a substrate or other object to measure or determine one or more properties such as alignment, overlay (e.g., between structures on an upper layer, or between structures of the same layer that have been provided separately on the layer, e.g., by a double patterning process), line thickness, critical dimension (CD), focus offset, material properties, etc. Accordingly, a manufacturing facility in which the lithocell LC is located typically also includes a metrology system MET that measures some or all of the substrates W processed in the lithocell or other objects in the lithocell. The metrology system MET may be part of the lithocell LC, or may be part of the lithographic apparatus LA (e.g., alignment sensor AS, etc.).

[0026]

[0039] The one or more measured parameters may include, for example, overlay between successive layers formed in or on the patterned substrate, critical dimension (CD) (e.g., critical linewidth) of features formed in or on the patterned substrate, focus or focus error of an optical lithography step, dose or dose error of an optical lithography step, optical aberrations of an optical lithography step, etc. The measurements may be made on targets on the product substrate itself and / or on dedicated metrology targets provided on the substrate. Measurements may be performed after resist development, before etching, or after etching.

[0027]

[0040] There are various techniques for making measurements of structures formed in a patterning process, including the use of scanning electron microscopes, image-based metrology tools, and / or various dedicated tools. As mentioned above, a fast, non-invasive form of specialized metrology tool is one in which a beam of radiation is directed at a target on the surface of a substrate and properties of the scattered (diffracted / reflected) beam are measured. By evaluating one or more properties of the radiation scattered by the substrate, one or more properties of the substrate can be determined. This is sometimes referred to as diffraction-based metrology. One such application of this diffraction-based metrology is the measurement of the asymmetry of features in a target. This can be used, for example, as a measure of overlay, although other applications are known. For example, the asymmetry can be measured by comparing opposite parts of the diffraction spectrum (e.g., comparing the -1st and +1st orders of the diffraction spectrum of a periodic grating). This can be done as described above, for example, in U.S. Patent Application Publication US2006-0066855, which is incorporated herein by reference in its entirety. Another application of diffraction-based metrology is the measurement of feature widths (CDs) in a target. Such techniques may use the apparatus and methods described below.

[0028]

[0041] Thus, in a device manufacturing process (e.g., a patterning process or a lithography process), a substrate or other object may be subjected to various types of measurements during or after the process. The measurements may determine whether a particular substrate is defective, establish adjustments to the process and apparatus used in the process (e.g., to align two layers on a substrate or to align a patterning device to a substrate), measure the performance of the process and apparatus, or may serve other purposes. Examples of measurements include optical imaging (e.g., optical microscopy), non-imaging optical measurements (e.g., diffraction-based measurements), mechanical measurements (e.g., profiling using a stylus, atomic force microscopy (AFM)), and / or non-optical imaging (e.g., scanning electron microscopy (SEM)). The alignment system of U.S. Pat. No. 6,961,116, the entirety of which is incorporated herein by reference, uses a self-referencing interferometer that generates two overlapping, relatively rotated images of an alignment marker, detects the intensity at the pupil plane where the Fourier transform of the images gives rise to interference, and extracts position information from the phase difference between the diffraction orders of the two images, which appears as an intensity variation in the interference order.

[0029]

[0042] The metrology results may be provided directly or indirectly to the supervisory control system SCS. If an error is detected, adjustments may be made to the exposure of subsequent substrates (especially if inspection can be performed early enough that one or more other substrates of the batch are still exposed) and / or to subsequent exposures of the exposed substrate. Also, already exposed substrates may be stripped and reworked to improve yield, or discarded, thereby avoiding performing further processing of substrates known to be defective. If only some target portions of a substrate are defective, further exposures may be performed only on good target portions.

[0030]

[0043] Within the metrology system MET, a metrology apparatus is used to determine one or more properties of a substrate, in particular how the one or more properties vary for different substrates or how different layers of the same substrate vary from layer to layer. As mentioned above, the metrology apparatus may be integrated into the lithographic apparatus LA or lithocell LC, or may be a stand-alone device.

[0031]

[0044] To enable metrology, one or more metrology targets (also referred to as "targets", "metrology marks" or "marks") can be provided on the substrate. In one embodiment, the target is specially designed and can include a periodic structure. In one embodiment, the target is a part of a device pattern, for example, a periodic structure of a device pattern. In one embodiment, the device pattern is a periodic structure of a memory device, for example, a bipolar transistor (BPT), bit line contact (BLC) or other structure.

[0032]

[0045] In one embodiment, the target on the substrate can include one or more 1-D periodic structures (e.g., gratings) that are printed such that after development, the periodic structural features are formed of solid resist lines. In one embodiment, the target can include one or more 2-D periodic structures (e.g., gratings) that are printed such that after development, the periodic structural features are formed of solid resist pillars or vias in the resist. Alternatively, the bars, pillars, or vias can be etched into the substrate (e.g., in one or more layers on the substrate).

[0033]

[0046] In one embodiment, one of the parameters of interest in the patterning process is overlay. Overlay can be measured using dark-field scatterometry, where the zeroth diffraction order (corresponding to specular reflection) is blocked and only higher orders are processed. Examples of dark-field metrology can be found in PCT Patent Application Publication Nos. WO2009 / 078708 and WO2009 / 106279, which are incorporated herein by reference in their entirety. Further developments of this technology are described in U.S. Patent Application Publications US2011-0027704, US2011-0043791, and US2012-0242970, which are incorporated herein by reference in their entirety. Diffraction-based overlay using dark-field detection of diffraction orders allows overlay measurements on smaller targets. These targets can be smaller than the illumination spot and may be surrounded by device product structures on the substrate. In one embodiment, multiple targets can be measured in one radiation capture.

[0034]

[0047] In Fig. 3A a metrology apparatus suitable for use in an embodiment for example to measure overlay is shown in schematic form. In Fig. 3B a target T (with a periodic structure such as a grating) and diffracted light beams are shown in more detail. The metrology apparatus may be a stand-alone apparatus or may be integrated in a lithographic apparatus LA, for example in a measurement station or in a lithographic cell LC. An optical axis with several branches throughout the apparatus is represented by a dotted line O. In this apparatus, radiation emitted by an output 11 (for example a radiation source such as a laser or a xenon lamp, or an aperture connected to a radiation source) is directed onto a substrate W through a prism 15 by an optical system comprising lenses 12, 14 and an objective lens 16. These lenses are arranged in a double arrangement in a 4F configuration. Different lens arrangements may be used, provided that an image of the substrate is provided to a detector.

[0035]

[0048] In one embodiment, the lens arrangement allows access to an intermediate pupil plane for spatial frequency filtering. The angular range at which the radiation is incident on the substrate can therefore be selected by defining a spatial intensity distribution in a plane that presents the spatial spectrum of the substrate plane, referred to herein as the (conjugate) pupil plane. In particular, this can be done, for example, by inserting an aperture plate 13 of suitable form between the lenses 12 and 14, in a plane that is a back-projected image of the objective pupil plane. In the illustrated example, the aperture plate 13 has different forms, denoted as 13N and 13S, allowing different illumination modes to be selected. The illumination system of this example forms an off-axis illumination mode. In a first illumination mode, the aperture plate 13N provides off-axis illumination from a direction designated "north" for illustration purposes only. In a second illumination mode, the aperture plate 13S is used to provide a similar illumination from the opposite direction, denoted "south". Other illumination modes are possible by using different apertures. It is desirable for the remainder of the pupil plane to be dark, since unwanted radiation outside the desired illumination mode will interfere with the desired measurement signal.

[0036]

[0049] As shown in FIG. 3B, the target T is positioned with the substrate W substantially perpendicular to the optical axis O of the objective lens 16. When the illumination ray I strikes the target T at an angle off axis O, it gives rise to a zero order ray (solid line 0) and two first order rays (dashed line +1 and dashed line -1). For an overfilled small target T, these rays are just one of many parallel rays covering the area of ​​the substrate containing the metrology target T and other features. Since the aperture in the plate 13 has a finite width (necessary to accept a useful amount of radiation), the incident ray I will actually occupy a range of angles, and the diffracted waves 0 and +1 / -1 will be somewhat spread out. According to the point spread function of the small target, each order +1 and -1 will be further spread out over a range of angles, rather than a single ideal ray as shown. Note that the periodic structure pitch and the illumination angle can be designed or adjusted so that the first order ray entering the objective lens is precisely aligned with the central optical axis. The rays shown in Figures 3A and 3B are shown slightly off-axis simply to make them easier to distinguish in the figures. At least the 0th and +1st orders diffracted by the target on the substrate W are collected by the objective lens 16 and directed back through the prism 15.

[0037]

[0050] Returning to FIG. 3A, both the first and second illumination modes are illustrated by designating diametrically opposite apertures, labeled as North (N) and South (S). If the incident ray I is from the north side of the optical axis, i.e., if the first illumination mode is applied using aperture plate 13N, the +1 diffracted wave, labeled as +1(N), enters the objective lens 16. In contrast, if the second illumination mode is applied using aperture plate 13S, it is the -1 diffracted wave, labeled as 1(S), that enters the lens 16. Thus, in one embodiment, measurements are obtained by measuring the target twice under specific conditions, for example by rotating the target, or by changing the illumination mode, or by changing the imaging mode, in order to obtain the -1 and +1 diffraction order intensities separately. Comparing these intensities for a given target provides a measure of the asymmetry in the target, which can be used as an indicator of a parameter (e.g. overlay) of the lithography process. In the above situation, the illumination mode is changed.

[0038]

[0051] A beam splitter 17 splits the diffracted beam into two measurement branches. In the first measurement branch, an optical system 18 uses the zeroth and first order diffracted beams to form a diffraction spectrum (pupil plane image) of the target on a first sensor 19 (e.g. a CCD or CMOS sensor). Since each diffraction order hits a different spot on the sensor, image processing can compare and contrast the orders. The pupil plane image captured by the sensor 19 can be used to focus the metrology device and / or to normalize the intensity measurements. As described further below, the pupil plane image can also be used for other measurement purposes, such as reconstruction.

[0039]

[0052] In the second measurement branch, the optical system 20, 22 forms an image of the target on the substrate W on a sensor 23 (e.g. a CCD or CMOS sensor). In the second measurement branch, an aperture stop 21 is provided in a plane conjugate with the pupil plane of the objective lens 16. The aperture stop 21 serves to block the zeroth order diffracted beam so that the image of the target formed on the sensor 23 is formed from the −1 or +1 first order beam. Data relating to the images measured by the sensors 19 and 23 are output to an image processor and controller PU, the function of which will depend on the particular type of measurement to be performed. It should be noted that the term “image” is used in a broad sense. If only one of the −1 and +1 orders is present, then images of periodic structure features (e.g. grating lines) will not be formed as such.

[0040]

[0053] The particular configuration of aperture plate 13 and stop 21 shown in Figure 3 are merely examples. In another embodiment, on-axis illumination of the target is used, and an aperture stop with an off-axis aperture is used to pass substantially only one first order diffracted radiation to the sensor. In yet other embodiments, second, third and higher order beams (not shown in Figure 3) can be used for the measurement instead of or in addition to the first order beam.

[0041]

[0054] To make the illumination adaptable to these different types of measurements, the aperture plate 13 may comprise several aperture patterns formed on the circumference of a rotating disk to move the desired pattern into position. It should be noted that the aperture plate 13N or 13S is used to measure the periodic structure of the target oriented in one direction (X or Y depending on the setting). For the measurement of orthogonal periodic structures, a rotation of the target of 90° and 270° may be performed. Different aperture plates are shown in Fig. 3C and Fig. 3D. Fig. 3C shows two further types of off-axis illumination modes. In the first illumination mode of Fig. 3C, the aperture plate 13E provides off-axis illumination from a direction designated as "East" with respect to the aforementioned "North" for the purpose of illustration only. In the second illumination mode of Fig. 3D, the aperture plate 13W is used to provide illumination from a similar but opposite direction named "West". Fig. 3D shows two further types of off-axis illumination modes. In a first illumination mode of Figure 3D, aperture plate 13NW provides off-axis illumination from the directions designated "North" and "West" above. In a second illumination mode, aperture plate 13SE is used to provide illumination from similar but opposite directions designated "South" and "East" above. Use of these devices, as well as many other variations and applications of the devices, are described, for example, in the previously published patent application publications referenced above.

[0042]

[0055] FIG. 3E shows an example of a composite metrology target T formed on a substrate. The composite target comprises four periodic structures (in this case gratings) 32, 33, 34, 35 located close to each other. In one embodiment, the periodic structure layout can be smaller than the measurement spot (i.e., the periodic structure layout is overfilled). Thus, in one embodiment, the periodic structures are positioned close to each other such that they are all within the measurement spot 31 formed by the illumination beam of the metrology device. In that case, all four periodic structures are consequently illuminated simultaneously and imaged simultaneously on the sensors 19 and 23. In an example specific to overlay measurements, the periodic structures 32, 33, 34, 35 are composite periodic structures (e.g. composite gratings) formed by overlapping periodic structures themselves, i.e., the periodic structures are patterned in various layers of a device formed on the substrate W such that at least one periodic structure of one layer overlaps at least one periodic structure of a different layer. Such targets may have outer dimensions in the range of 20 μm×20 μm or in the range of 16 μm×16 μm. Furthermore, all of the periodic structures are used to measure the overlay between a particular layer pair. To facilitate targets being able to measure more than a single layer pair, the periodic structures 32, 33, 34, 35 may have different overlay offsets in bias to facilitate measuring the overlay between the different layers in which different parts of the composite periodic structure are formed. Thus, all of the periodic structures of a target on a substrate are used to measure one layer pair, and all of the periodic structures of another identical target on a substrate are used to measure another layer pair, with the different biases facilitating differentiation between the layer pairs.

[0043]

[0056] Returning to FIG. 3E, the periodic structures 32, 33, 34, 35 may also differ in their orientation to diffract incoming radiation in the X and Y directions, as shown. In one example, the periodic structures 32 and 34 are periodic structures in the X direction with biases of +d, -d, respectively. The periodic structures 33 and 35 may be periodic structures in the Y direction with offsets of +d and -d, respectively. Although four periodic structures are shown, other embodiments may include a larger matrix to obtain the desired accuracy. For example, a 3×3 array of nine composite periodic structures may have biases of -4d, -3d, -2d, -d, 0, +d, +2d, +3d, +4d. Individual images of these periodic structures are distinguishable in the image captured by the sensor 23.

[0044]

[0057] FIG. 3F shows an example of an image that may be formed on and detected by the sensor 23 using the target of FIG. 3E in the apparatus of FIG. 3A and the aperture plate 13NW or 13SE of FIG. 3D. The sensor 19 cannot resolve the different individual periodic structures 32-35, but the sensor 23 can. The dark rectangle represents the field of view of the image on the sensor, in which the illuminated spot 31 on the substrate is imaged in a corresponding circular area 41. In this image, the rectangular areas 42-45 represent the images of the periodic structures 32-35. The target may be positioned between the device product features instead of or in addition to being in the scribe lane. If the periodic structures are located in the device product area, the device features may also be visible at the periphery of this image field. The processor and controller PU processes these images using pattern recognition to identify the individual images 42-45 of the periodic structures 32-35. In this way, the image does not need to be very precisely aligned at any particular location within the sensor frame, which greatly increases the overall throughput of the measurement system.

[0045]

[0058] Once the separate images of the periodic structures have been identified, the intensity of these individual images can be measured, for example by averaging or summing selected pixel intensity values ​​within the identified areas. The intensities and / or other characteristics of the images can be compared to one another. These results can be combined to measure various parameters of the lithography process. Overlay performance is one such parameter.

[0046]

[0059] In a manufacturing process, variations in various process parameters (also referred to as "geometric parameters") can have a significant impact on the design of an appropriate metrology target (or alignment target) to faithfully reflect the device design. Such process parameters that can vary the metrology target or alignment target can include, but are not limited to, sidewall angle (determined, for example, by an etching or developing process), refractive index (of a device layer or resist layer), thickness (of a device layer or resist layer), frequency of incident radiation, etch depth, floor slope, extinction coefficient of a radiation source, coating asymmetry (of a resist layer or device layer), variations in erosion during a chemical mechanical polishing process, and the like. Computational techniques can also be used to define metrology targets for use in a metrology system MET, for example, through a metrology system simulation, or in a target manufacturing process simulation (including, for example, exposing a metrology target using a lithography process, developing a metrology target, etching a target, etc.). An example of a software platform used to design metrology targets includes Design for Control (referred to as "DFC"), which is described in more detail below. Similarly, alignment targets can be defined. Metrology target designs or alignment target designs can be characterized by various parameters. For metrology targets, these parameters can be, for example, target coefficient (TC), stack sensitivity (SS), overlay impact (OV), or the like. Stack sensitivity can be understood as a measure of how much the intensity of a signal changes as, for example, the overlay changes due to diffraction between target (e.g., grating) layers. Target coefficient can be understood as a measure of the signal-to-noise ratio for a particular measurement time as a result of variations in photon collection by the measurement system. In one embodiment, the target coefficient can also be considered as a ratio of stack sensitivity to photon noise, i.e., the signal (i.e., stack sensitivity) can be divided by a measure of photon noise to determine the target coefficient.Overlay impact measures the change in overlay error as a function of target design.

[0047]

[0060] A metrology target design layout may specify one or more design parameters (e.g., geometric dimensions) of the target and may further specify discrete values ​​or ranges of values ​​for the one or more design parameters. Additionally, a user and / or system may impose one or more constraints on one or more design parameters (e.g., pitch vs. trench width, pitch or trench width limits, CD vs. pitch (e.g., CD is less than pitch), etc.) either within the same layer or across multiple layers, based on, for example, the lithography process requiring the target. Alternatively, one or more constraints may be imposed on one or more design parameters for which discrete values ​​or ranges are specified, or on one or more other design parameters. Potential metrology target designs or alignment target designs may be input into a simulation, for example, to determine the feasibility and / or suitability of one or more of the target designs. The constraints may include metrology parameter constraints. For example, in some metrology systems, the physics of the system may impose constraints (e.g., the wavelength of radiation used in the system may constrain the pitch of the target design). Alternatively, the constraints may be process parameter constraints (e.g., constraints that depend on etch type, develop type, resist type, etc.). The terms "target", "target grating" and "target structure" as used herein do not require that the structure be specifically given for the measurement to be performed. Targets include, for example, gratings used in diffraction measurement techniques, but other target types such as box-in-box image based overlay targets may also be used. Metrology targets may be used to determine overlay, CD, focus, dose, etc., and metrology target design layouts may be defined using data structures such as pixel-based data structures or polygon-based data structures. The polygon-based data structures may be described, for example, using the GDSII data format, which is quite common in the chip manufacturing industry. However, any suitable data structure or data format may be used without departing from the scope of the embodiments.

[0048]

[0061] As mentioned above, metrology target design platforms such as DFC can be used in designing metrology targets. In the DFC method, the individual steps of the lithography process are modeled into a single process sequence that simulates the physical substrate processing. The process sequence is collectively responsible for the generation of the device geometry, rather than "building" the device geometry element by element. In some embodiments, the DFC methodology may be a developed computer-aided design (CAD) tool for the automatic generation of metrology targets. Once the lithography process sequence is modeled and added as input, any number of metrology targets can be designed in an efficient manner (e.g., with zero or minimal manual intervention). The number of metrology targets can be in the thousands or even millions. The lithography process model takes into account the characteristics of the lithography equipment. DFC allows the user to execute the steps for designing the metrology target without intervention from the author of the DFC program. A suitable graphic user interface (GUI) is available for setting up, running, reviewing and using the functionality of the DFC program. Since metrology target designs are mostly confined to the simulation domain rather than the real device manufacturing domain, special interfacing with manufacturing tools may not typically be required.

[0049]

[0062] FIG. 4A shows a flow chart listing the main stages of the DFC method. In process P410, the materials to be used in the lithography process are selected. The materials can be selected from a material library interfaced with D4C via a suitable GUI. In process P420, the lithography process is defined by going through each of the process steps and building a computer simulation model for all process sequences. In process P430, the metrology target is defined, e.g. the dimensions and other characteristics of the various features included in the target are entered into the DFC program. For example, if a grating is included in the structure, the number of grating elements, the width of each individual grating element, the spacing between two grating elements, etc. must be defined. In process P440, the 3D geometry is created. This step also takes into account information relevant to the multi-layer target design, e.g. whether there is a relative shift between different layers, etc. This functionality allows for multi-layer target design. In process P450, the final geometry of the designed target is visualized. As will be explained in more detail below, not only is the final geometry visualized, but as the designer applies various steps of the lithography process, the designer can visualize how the 3D geometry is formed and changes due to process-induced effects, e.g., the 3D geometry after resist patterning is different from the 3D geometry after resist removal and etching.

[0050]

[0063] An important aspect of the present disclosure is that it allows target designers to visualize the steps of the method to facilitate their insight and control during modeling and simulation. The DFC software incorporates various visualization tools called "viewers." For example, as shown in FIG. 4B, the designer can view material plots P460 (and also obtain runtime estimation plots) according to the defined lithography process and target. Once the lithography model is created, the designer can view the model parameters via the Model Viewer tool P475. The design layout viewer tool P480 can be used to view the design layout (e.g., a visual rendering of the GDS file). The resist profile viewer tool P485 can be used to view the pattern profile in the resist. The geometry viewer tool P490 can be used to view the 3D structures on the wafer. The pupil viewer tool P495 can be used to view the simulated response on the metrology tool. Those skilled in the art will appreciate that these viewing tools are available to enhance the designer's understanding during design and simulation. One or more of these tools may not be present in some embodiments of the DFC software, while additional viewing tools may be present in some other embodiments.

[0051]

[0064] FIG. 4C shows a flow chart illustrating how the DFC process improves the efficiency of the overall simulation process by reducing the number of metrology targets selected for the actual simulation of the lithography process. As mentioned above, DFC allows the designer to design thousands or even millions of designs. Not all of these designs are robust to variations in the process steps. To select a subset of target designs that can tolerate the process variations, the lithographer can intentionally perturb one or more steps of the defined lithography process, as shown in block P452. The introduction of a perturbation changes the entire process sequence with respect to how it was originally defined. Thus, applying the perturbed process sequence (block P454) also changes the 3D geometry of the designed target. The lithographer selects only the perturbations that show non-zero alterations in the original design targets, creating a subset of selected process perturbations (block P456). The lithography process is then simulated with this subset of process perturbations (P458).

[0052]

[0065] When designing metrology marks, conventional methods may describe the geometric parameters as homogeneous for the metrology marks and fail to consider the geometric variations or surrounding patterns within the marks. However, measurements obtained from such metrology marks may be inaccurate because the variations in the geometric parameters of the individual patterns (e.g., caused by the variations in the manufacturing process) or the presence or absence of the surrounding patterns may significantly affect the measurement performance of the marks.

[0053]

[0066] In the following paragraphs, designing a mark (eg, a metrology mark) based on the local geometry of the mark is described with reference to at least Figures 5 and 6A-6B.

[0054]

[0067] 5 is a block diagram of an exemplary system 400 for designing a mark based on the local geometry of the mark, according to an embodiment of the present disclosure. FIG 6A is a flow diagram of an exemplary method 600 for designing a mark based on the local geometry of the mark, according to an embodiment. The local geometry of the mark can be characterized by one or more of the spatial variation of a geometric parameter in or around the mark, the spatial location of the mark, or the surrounding pattern of the mark.

[0055]

[0068] In process P601, the mark design component 450 obtains a mark construction 602 of a specified mark. In some embodiments, the specified mark may include a metrology mark (e.g., an optical metrology mark) such as target T in FIG. 3E. In some embodiments, the mark construction 602 may be associated with a spatial location 406 of the specified mark in a target design layout 414 and a mark design layout 408. The spatial location 406 and the mark design layout 408 may be provided as input to the mark design component 450, for example, by a user or by any other means. The target design layout 414 may correspond to a design layout for a full chip (e.g., an IC) that includes a final geometry design of several marks (e.g., the specified mark is one of them). The target design layout 414 includes a 3D construction of the mark for the entire chip.

[0056]

[0069] In some embodiments, the target design layout 414 may be generated by a full-chip design component 425 implemented using one or more predictive models, such as using the process described with reference to FIG. 4A. In some embodiments, the full-chip design component 425 may take as input a full-chip design layout 402 and lithography process information 404 to generate the target design layout 414. The full-chip design layout 402 may be in the form of a polygon-based data structure, including the design of the marks as polygons, for example, and described using the GDSII data format. The lithography process information 404 may include various parameters describing the lithography process, such as one or more of the following: lithography equipment settings, materials used in the lithography process, stack information such as number of layers, layer thickness, etch depth, etc., user-specified design constraints such as CD, pitch, etc., process information, or process variations.

[0057]

[0070] In process P602, the mark design component 450 obtains spatial variation 420 of a geometric parameter associated with a mark construction. In some embodiments, the geometric parameters include layer thickness t(x,y), chemical mechanical polishing dishing height d(x,y), etch sidewall angle a(x,y), litho etch CD bias b(x,y), etch floor slope s(x,y), or other such geometric parameters associated with a lithography process. In some embodiments, the mark design component 450 obtains spatial variation 420 of a geometric parameter within a specified mark. In some embodiments, such geometric parameters may vary between patterns. In some embodiments, such geometric parameters may vary within an individual pattern. For example, if a specified mark has several periodic structures, such as the four periodic structures (gratings) 32-35 of mark T in FIG. 3E, the mark design component 450 can obtain spatial variation 420 of a geometric parameter for each pattern in each of the four periodic structures. In some embodiments, the spatial variation 420 is a distribution of the geometric parameter over a range of coordinates (e.g., (x1, y1) to (x2, y2)) corresponding to the coordinates of the pattern in the specified mark. In some embodiments, the spatial variation of the geometric parameter can be obtained from measurement data, empirical data, or experimental data. It can also be obtained by using a model simulating a lithography process, such as the model described at least with reference to FIG. 9, an etch model, a deposition model, or an associated model configured to determine the etch pattern, the deposition pattern, and characteristic values ​​of the respective patterns (e.g., CD, pattern placement error (PPE), edge placement error (EPE), etc.), a CMP model configured to model residues, a development model for simulating a resist development model of a resist layer to obtain characteristics of the development of the resist layer, or other models. The model can be a machine learning (ML) model or a non-ML model (e.g., a physical model, an empirical model, a semi-empirical model).

[0058]

[0071] In some embodiments, the mark design component 450 can determine the geometric parameters based on the target design layout 414 (e.g., generated by the full chip design component 425). For example, the mark design component 450 can extract the geometric parameters by identifying a grid in the target design layout 414 in which the specified mark is located based on the spatial location 406 of the specified mark, and then obtain the spatial variation 420 of the geometric parameters within the identified grid. In some embodiments, the size (e.g., area) of the grid is larger than the size of the specified mark. Because the size of the grid is larger than the specified mark, the mark design component 450 can interpolate the grid (e.g., using known interpolation methods) to obtain the geometric parameters within the specified mark. The geometric parameters can vary between individual patterns within the mark. Additionally, the mark design component 450 can also obtain information about surrounding patterns. For example, the information can include the presence or absence of a pattern (e.g., a metrology mark or a device pattern) within a specified proximate area of ​​the specified mark. In some embodiments, the mark design component 450 may use information about the surrounding pattern when designing a specified mark, since the presence of the surrounding pattern may significantly affect the measurement performance of the mark.

[0059]

[0072] In process P603, the mark design component 450 generates a mark design 424, which is a 3D construction of the specified mark, based on the spatial variation of the geometric parameter 420. In some embodiments, generating the mark design 424 includes determining a geometric design of an individual pattern of the specified mark based on the spatial variation of the geometric parameter 420. The geometric design includes one or more of a CD, a pitch, or a subsegmentation of the individual pattern of the specified mark. While the mark design 424 is generated based on the spatial variation of the geometric parameter 420, the mark design component 450 may also consider the surrounding pattern of the specified mark or the spatial location of the specified mark when generating or optimizing the mark design 424. Such a mark design 424 designed based on the local geometry of the mark (e.g., the spatial variation of the geometric parameter 420 for each pattern of the individual patterns in the mark, the surrounding pattern of the specified mark, or the spatial location of the specified mark) has better measurement performance (better measurement accuracy) compared to a mark designed using a conventional method that does not consider the local geometry of the mark. In some embodiments, generating the mark design 424 may include simulating the measured performance of the specified mark and iteratively adjusting the mark design, as shown in FIG. 6B, until the measured performance meets a threshold performance.

[0060]

[0073] FIG. 6B is a flow diagram of an exemplary method 650 for optimizing a mark design, according to one embodiment. In some embodiments, method 650 is performed as part of process P603 of method 600 of FIG. 6A. In process P651, mark design component 450 calculates a cost function 651 representative of key performance indicators (KPIs), which in turn represent the measurement performance (e.g., optical measurement performance) of a specified mark. In some embodiments, mark design component 450 may calculate cost function 651 using a sensor predictive simulation process or using a model 475 that predicts the measurement performance of the mark (e.g., measurements that can actually be obtained using a sensor of a metrology tool). As mentioned above, model 475 may simulate a measurement process performed by a sensing system mounted on a metrology tool that is separate or separate from the processing equipment, or a sensing system mounted on a processing equipment (e.g., a photolithography tool). For example, the mark design component 450 can input the mark design 424 (e.g., a geometry design of a specified mark) into a sensor prediction model 475, which, when executed, simulates optical measurement parameters 434 that can be obtained from a metrology tool by measuring the specified mark. In some embodiments, the optical measurements 434 can include the intensity, wavelength, and / or phase of the radiation (e.g., of the radiation source of the metrology apparatus of FIG. 3A), the pupil plane size, the amount of radiation in the pupil, etc. The mark design component 450 can generate one or more KPIs based on the optical measurements 434. For example, one KPI can be a swing curve or a color to color bias, which is the difference between measurements obtained using various radiation source wavelengths. The mark design component 450 can then calculate a cost function 651 based on the optical measurement parameters (e.g., for a particular KPI).

[0061]

[0074] In process 652, in some embodiments, the mark design component 450 determines whether an exit condition has been met. In some embodiments, the exit condition is met when the cost function 651 has been minimized or maximized. For example, if the cost function is a KPI such as color-to-color bias, the exit condition is met when the cost function 651 has been minimized (or is below a threshold). In some embodiments, if the exit condition is met, the measurement performance of the mark design 424 may be treated as sufficient and the method 650 may end by outputting the mark design 424. However, if the exit condition is not met (e.g., the cost function 651 is not minimized or maximized), the mark design component 450 may proceed to process P653 and adjust the mark design 424.

[0062]

[0075] In process P653, the mark design component 450 adjusts the mark design 424 to generate an adjusted mark design 424'. In some embodiments, adjusting the mark design 424 includes adjusting a geometry design, such as at least one of a CD, pitch, or subsagmentation of a pattern of the designated marks. The adjustments may or may not vary between individual patterns of the marks. In some embodiments, adjusting the geometry design includes adjusting a spatial location of the designated marks (e.g., changing a spatial location of the designated marks in the target design layout 414). In some embodiments, adjusting the geometry design includes adding or adjusting a mark in an open space between two marks (e.g., to minimize optical crosstalk or lithographic process difficulties due to the open space) (this process is commonly referred to as "dummification"). For example, as shown in FIG. 7, the mark design component 450 can add a mark in an open space 702 between a first mark 701 and a second mark 703.

[0063]

[0076] The optimization method 650 may be an iterative process and may be performed iteratively until an exit condition is met. In some embodiments, the exit condition is met when (a) the cost function 651 is minimized or maximized, (b) a predetermined number of iterations of the method 650 (e.g., operations P651-P653) have been performed, or (c) other such condition. After the method 650 has finished, control may pass to process P603 of the method 600, which outputs the adjusted mark design 424' as the mark design 424.

[0064]

[0077] Although the above paragraphs describe embodiments implemented to design or optimize a mark, embodiments can also be implemented to monitor measurements made using a given mark in addition to or instead of optimizing the given mark. For example, after reconstructing the mark design of a given mark based on the local geometry of the mark (e.g., as described in process P603 of method 600 and without optimizing the mark's geometric design), the mark design component 450 can generate one or more KPIs based on optical measurements simulated for the given mark by the sensor prediction model 475. The mark design component 450 can then determine the difference between the KPI and a KPI threshold (e.g., a value for which the given mark is believed to be optimized). This difference (which can be calculated, for example, as a percentage) can be determined as the amount of correction to be applied to any actual measurements taken using the mark (from a metrology tool) to obtain accurate measurements. For example, if the actual KPI determined based on measurements taken using the mark is X, then a correction to the KPI may be determined as ±Y%, and the mark design component 450 may then output the corrected KPI as X±Y%.

[0065]

[0078] 8 is a block diagram illustrating a computer system 100 that can assist in implementing the systems and methods disclosed herein. The computer system 100 includes a bus 102 or other communication mechanism for communicating information, and a processor 104 (or multiple processors 104 and 105) coupled with the bus 102 for processing information. The computer system 100 also includes a main memory 106, such as a random access memory (RAM) or other dynamic storage device, coupled to the bus 102 for storing information and instructions executed by the processor 104. The main memory 106 may also be used to store temporary variables or other intermediate information during execution of instructions executed by the processor 104. The computer system 100 further includes a read-only memory (ROM) 108 or other static storage device coupled to the bus 102 for storing static information and instructions for the processor 104. A storage device 110, such as a magnetic disk or optical disk, is provided and coupled to the bus 102 for storing information and instructions.

[0066]

[0079] The computer system 100 may be coupled via bus 102 to a display 112, such as a cathode ray tube (CRT) or flat-panel or touch-panel display, for displaying information to a computer user. An input device 114, including alphanumeric and other keys, is coupled to bus 102 for communicating information and command selections to the processor 104. Another type of user input device is a cursor control 116, such as a mouse, trackball, or cursor direction keys, for communicating directional information and command selections to the processor 104 and for controlling cursor movement on the display 112. This input device typically has two degrees of freedom in two axes, a first axis (e.g., x) and a second axis (e.g., y), allowing the device to specify a position in a plane. A touch-panel (screen) display may also be used as an input device.

[0067]

[0080] According to one embodiment, portions of the optimization process may be performed by the computer system 100 in response to the processor 104 executing one or more sequences of one or more instructions contained in the main memory 106. Such instructions may be read into the main memory 106 from another computer-readable medium, such as the storage device 110. Execution of the sequences of instructions contained in the main memory 106 causes the processor 104 to perform the process steps described herein. One or more processors in a multi-processing configuration may also be used to execute the sequences of instructions contained in the main memory 106. In an alternative embodiment, hardwired circuitry may be used in place of or in combination with software instructions. Thus, the description herein is not limited to any specific combination of hardware circuitry and software.

[0068]

[0081] The term "computer-readable medium" as used herein refers to any medium that participates in providing instructions to the processor 104 for execution. Such media can take many forms, including but not limited to non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks, such as the storage device 110. Volatile media include dynamic memory, such as the main memory 106. Transmission media include coaxial cables, copper wire and fiber optics, including the wires that comprise the bus 102. Transmission media can also take the form of acoustic or light waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tape, any other magnetic media, CD-ROMs, DVDs, any other optical media, punch cards, paper tape, any other physical media with patterns of holes, RAM, PROMs, and EPROMs, flash EPROMs, any other memory chips or cartridges, carrier waves as described below, or any other medium from which a computer can read.

[0069]

[0082] Various forms of computer readable media may be involved in carrying one or more sequences of one or more instructions to the processor 104 for execution. For example, the instructions may initially reside on a magnetic disk of a remote computer. The remote computer can load the instructions into its dynamic memory and send the instructions over a telephone line using a modem. A modem local to the computer system 100 can receive the data on the telephone line and use an infrared transmitter to convert the data to an infrared signal. An infrared detector coupled to the bus 102 can receive the data carried in the infrared signal and place the data on the bus 102. The bus 102 carries the data to the main memory 106, from which the processor 104 retrieves and executes the instructions. The instructions received by the main memory 106 may optionally be stored on a storage device 110 either before or after execution by the processor 104.

[0070]

[0083] Computer system 100 also includes a communication interface 118 that is preferably coupled to bus 102. The communication interface 118 provides a two-way data communication coupling to a network link 120 that is connected to a local network 122. For example, the communication interface 118 may be an Integrated Services Digital Network (ISDN) card or a modem to provide a data communication connection to a corresponding type of telephone line. As another example, the communication interface 118 may be a Local Area Network (LAN) card to provide a data communication connection to a compatible LAN. A wireless link may also be implemented. In any such implementation, the communication interface 118 sends and receives electrical, electromagnetic or optical signals that carry digital data streams representing various types of information.

[0071]

[0084] Network link 120 typically provides data communication through one or more networks to other data devices. For example, network link 120 may provide a connection through local network 122 to a host computer 124 or to data equipment operated by an Internet Service Provider (ISP) 126. ISP 126 in turn provides data communication services through the worldwide packet data communication network now commonly referred to as the "Internet" 128. Both local network 122 and Internet 128 use electrical, electromagnetic or optical signals that carry digital data streams. The signals through the various networks and the signals on network link 120 and through communication interface 118, which carry the digital data to and from computer system 100, are exemplary forms of carrier waves transporting the information.

[0072]

[0085] Computer system 100 can send messages and receive data, including program code, through the network(s), network link 120, and communication interface 118. In the Internet example, server 130 might send a requested code for an application program through Internet 128, ISP 126, local network 122, and communication interface 118. One such downloaded application may provide, for example, the lighting optimization of an embodiment. The received code may be executed by processor 104 as received, and / or stored in storage device 110, or other non-volatile storage for later execution. In this manner, computer system 100 can obtain application code in the form of a carrier wave.

[0073]

[0086] An exemplary flow chart for modeling and / or simulating portions of the patterning process is shown in FIG. 9. As will be appreciated, these models can represent different patterning processes and need not include all of the models described below. The source model 1200 represents the optical characteristics of the illumination of the patterning device, including radiant intensity distribution, bandwidth and / or phase distribution. The source model 1200 can represent the optical characteristics of the illumination, including but not limited to the numerical aperture setting, the illumination sigma (σ) setting, and any particular illumination shape (e.g., off-axis radiant shapes such as annular, quadrupole, dipole, etc.), where σ (or sigma) is the outer radial extent of the illuminator.

[0074]

[0087] The projection optics model 1210 represents the optical characteristics of the projection optics, including changes to the radiant intensity distribution and / or phase distribution caused by the projection optics. The projection optics model 1210 can represent the optical characteristics of the projection optics, including aberrations, distortion, one or more refractive indices, one or more physical sizes, one or more physical dimensions, etc.

[0075]

[0088] The patterning device / design layout model 1220 captures how the design features are laid out in the pattern of the patterning device and may include representations of detailed physical characteristics of the patterning device, for example, as described in U.S. Patent No. 7,587,704, which is incorporated by reference in its entirety. In one embodiment, the patterning device / design layout model module 1220 represents the optical characteristics (including changes to the radiant intensity distribution and / or phase distribution caused by a given design layout) of a design layout (e.g., a device design layout corresponding to features of an integrated circuit, memory, electronic device, etc.), which is a representation of the arrangement of features on or formed by the patterning device. Because the patterning devices used in a lithographic projection apparatus are modifiable, it is desirable to separate the optical characteristics of the patterning device from the optical characteristics of the rest of the lithographic projection apparatus, including at least the illumination and projection optics. The goal of the simulation is often to accurately predict, for example, edge placement and CD, which can then be compared to the device design. The device design is typically defined as a pre-OPC patterning device layout and provided in a standardized digital file format such as GDSII or OASIS.

[0076]

[0089] The aerial image 1230 can be simulated from the source model 1200, the projection optics model 1210, and the patterning device / design layout model module 1220. The aerial image (AI) is the radiation intensity distribution at the substrate level. The optical characteristics of the lithographic projection apparatus (e.g. properties of the illumination, the patterning device, and the projection optics) determine the aerial image.

[0077]

[0090] A resist layer on a substrate is exposed by an aerial image, which is transferred to the resist layer as a latent "resist image" (RI). The resist image (RI) can be defined as the spatial distribution of resist solubility in the resist layer. The resist image 1250 can be simulated from the aerial image 1230 using a resist model 1240. A resist model can be used to calculate the resist image from the aerial image, an example of which is described in U.S. Patent Application Publication US2009-0157360, the disclosure of which is incorporated herein by reference in its entirety. A resist model typically relates only to properties of the resist layer (e.g., effects of chemical processes occurring during exposure, post-exposure bake (PEB), and development) to account for such effects of chemical processes occurring during resist exposure, post-exposure bake (PEB), and development, for example, to predict the contour of a resist feature formed on a substrate. In one embodiment, the optical properties of the resist layer (e.g., refractive index, film thickness, propagation, and polarization effects) can be captured as part of the projection optics model 1210.

[0078]

[0091] So, in general, the connection between the optical model and the resist model is the simulated aerial image intensity in the resist layer, resulting from the projection of the radiation onto the substrate, refraction at the resist interfaces, and multiple reflections in the resist film stack. The radiation intensity distribution (aerial image intensity) is transformed into a potential "resist image" by the absorption of the incident energy, which is further modified by diffusion processes and various loading effects. Efficient simulation methods, which are fast enough for full-chip applications, approximate the realistic 3D intensity distribution in the resist stack with a 2D aerial (and resist) image.

[0079]

[0092] In one embodiment, the resist image can be used as an input to a post-pattern transfer process model module 1260. The post-pattern transfer process model module 1260 defines the performance of one or more resist post-development processes (e.g., etch, develop, etc.).

[0080]

[0093] Simulation of the patterning process can predict, for example, the contour, CD, edge placement (e.g., edge placement error), etc. of the resist and / or etched image. Thus, the goal of the simulation is to accurately predict, for example, the edge placement, and / or aerial image intensity gradient, and / or CD, etc. of the printed pattern. These values ​​can be compared to the intended design, for example, to correct the patterning process or to identify where defects are expected to occur. The intended design is generally defined as a pre-OPC design layout, which may be provided in a standardized digital file format, such as GDSII or OASIS or other file formats.

[0081]

[0094] In this manner, the model formulation describes most, if not all, of the known physics and chemistry of the overall process, with each of the model parameters preferably corresponding to a distinct physical or chemical effect. In this manner, the model formulation sets an upper limit on how well the model can be used to simulate the entire manufacturing process.

[0082]

[0095] The concepts disclosed herein may be used for imaging on substrates such as silicon wafers, although it is understood that the disclosed concepts may be used in any type of lithographic imaging system (e.g., those used for imaging on substrates other than silicon wafers).

[0083]

[0096] The terms "optimize" and "optimization" as used herein refer to or mean adjusting a patterning apparatus (e.g., lithographic apparatus), patterning process, etc., such that the deliverable and / or process has more desirable characteristics, such as more accurate projection of a design pattern onto a substrate, a larger process window, etc. Accordingly, the terms "optimize" and "optimization" as used herein refer to or mean a process of identifying one or more values ​​of one or more parameters that result in an improvement (e.g., a local optimum) in at least one relevant metric, as compared to an initial set of one or more values ​​of the one or more parameters. "Optimum" and other related terms should be interpreted accordingly. In one embodiment, the optimization step can be applied iteratively to result in further improvement in one or more metrics.

[0084]

[0097] Aspects of the present invention may be implemented in any convenient form. For example, embodiments may be implemented by one or more suitable computer programs, which may be carried on a suitable carrier medium, which may be a tangible carrier medium (e.g., a disk) or an intangible carrier medium (e.g., a communication signal). Embodiments of the present invention may be implemented using any suitable apparatus, which may take the form of a programmable computer executing a computer program arranged to perform the methods as described herein. Thus, embodiments of the present disclosure may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the present disclosure may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, machine-readable media may include read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, electrical, optical, acoustic or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. Furthermore, firmware, software, routines, instructions may be described herein as performing certain operations. However, it should be understood that such description is merely for convenience and that such operations actually result from computing devices, processors, controllers, or other devices executing firmware, software, routines, instructions, etc.

[0085]

[0098] The embodiments of the present disclosure can be further described by the following clauses. 1. A non-transitory computer readable medium having instructions that, when executed by a computer, cause the computer to perform a method for mark design for use in imaging a pattern on a substrate using a lithographic process in a lithographic apparatus, the method comprising: Obtaining a mark structure; Obtaining a spatial variation of a geometric parameter associated with a mark construct, the spatial variation being associated with a lithography process; and determining a geometric design of the individual patterns of the marks based on the spatial variation of the marks. 2. The computer-readable medium of claim 1, wherein the geometric design is further determined based on a surrounding pattern of the mark. 3. The computer-readable medium of claim 1, wherein determining the geometric design includes determining at least one of a critical dimension, pitch, or subsegmentation of individual patterns of the mark. 4. The computer-readable medium of clause 1, wherein determining the geometric design includes determining spatial positions of marks in the target design to be printed on the substrate. 5. The computer-readable medium of clause 1, wherein determining the geometry design includes iteratively adjusting the geometry design based on predicted measurement performance. 6. Each iteration is (i) calculating a cost function; (ii) determining whether the cost function satisfies specified conditions; and and (iii) adjusting the geometry design based on a determination that the cost function does not satisfy a specified condition. 7. The computer-readable medium of clause 5, wherein iteratively adjusting the geometry design includes adjusting at least one of a critical dimension, pitch or subsegmentation of individual patterns of the marks, or adjusting a spatial position of the marks. 8. The computer-readable medium of clause 5, wherein adjusting the geometric design includes adding or adjusting one or more patterns surrounding the mark. 9. The computer-readable medium of clause 5, wherein the cost function includes one or more performance metrics representative of optical measurement performance of the mark. 10. Calculating the cost function inputting a geometric design of the mark into a first simulation model, the first simulation model being configured to simulate optical measurement parameters obtained using the mark from a measurement tool configured to measure a pattern printed on a substrate; running a first simulation model to obtain optical measurement parameters; and calculating a cost function based on the optical measurement parameters. 11. The computer-readable medium of claim 1, further comprising determining a geometric design of individual patterns of the marks based on the spatial positions of the marks. 12. The computer-readable medium of claim 1, wherein the mark construct comprises a plurality of patterns, each pattern being characterized by a critical dimension, pitch or subsegmentation of the individual pattern. 13. Obtaining a mark construction is inputting a target design layout and design layout variables of the lithography process into a second simulation model configured to generate a three-dimensional (3D) representation of a design that corresponds to the target design layout to be printed on a substrate using the lithography process; 2. The computer-readable medium of claim 1, further comprising: executing a second simulation model to obtain simulation results, the simulation results including a 3D representation of the design. 14. Obtaining spatial variation of geometric parameters is identifying a grid having a mark in a target design layout, the size of the grid being greater than the size of the mark; and obtaining from the simulation results a spatial variation of the geometric parameter on the grid. 15. The computer-readable medium of claim 14, wherein obtaining the spatial variation includes interpolating a grid to obtain the spatial variation of the geometric parameter for each of the individual patterns of the marks. 16. The computer-readable medium of clause 14, wherein determining the geometric design includes using a simulation model to reconstruct individual patterns of the marks based on spatial variations of the geometric parameters and the mark design layout. 17. The computer-readable medium of claim 16, wherein the individual patterns are further reconstructed based on features of the surrounding pattern of the mark. 18. The computer-readable medium of claim 1, wherein the spatial variation of the geometric parameter is obtained using at least one of measurement data, empirical data, experimental or data. 19. The computer-readable medium of clause 1, wherein the geometric parameters include at least one of a layer thickness, a chemical mechanical polishing dishing height, an etch sidewall angle, a litho-etch critical dimension bias, or an etch tilt. 20. The computer-readable medium of claim 1, wherein the geometric parameters vary within each pattern. 21. Obtaining a measurement performance of the mark using the first simulation model; performing a measurement using a measurement tool to obtain a measurement signal, the measurement signal including a set of optical measurement parameters obtained using the mark; 13. The computer-readable medium of claim 1, further comprising: adjusting the measurement signal based on the measurement performance. 22. The computer-readable medium of clause 1, wherein the marks include at least one of metrology marks, overlay marks, or alignment marks. 23. The computer-readable medium of clause 1, further comprising generating a mask pattern based on the mark, the mask pattern comprising a pattern corresponding to a target design layout to be printed on the substrate. 24. The computer readable medium of clause 23, further comprising performing a patterning step using a mask pattern to print a pattern on a substrate via a lithography process. 25. A computer-implemented method for designing marks for use in imaging a pattern on a substrate using a lithographic process in a lithographic apparatus, comprising: Obtaining a mark structure; Obtaining a spatial variation of a geometric parameter associated with a mark construct, the spatial variation being associated with a lithography process; determining a geometric design of the individual patterns of the marks based on the spatial variation of the marks. 26. The method of claim 25, wherein the geometric design is further determined based on a perimeter pattern of the mark. 27. The method of claim 25, wherein determining the geometric design includes determining at least one of a critical dimension, a pitch, or a subsegmentation of individual patterns of the mark. 28. The method of claim 25, wherein determining the geometric design includes determining spatial positions of marks within a target design to be printed on the substrate. 29. The method of claim 25, wherein determining the geometry design includes iteratively adjusting the geometry design based on predicted measurement performance. 30. Each iteration is (iv) calculating a cost function; and (v) determining whether the cost function satisfies specified conditions; and (vi) adjusting the geometry design based on a determination that the cost function does not satisfy a specified condition. 31. The method of claim 29, wherein iteratively adjusting the geometric design includes adjusting at least one of a critical dimension, pitch or subsegmentation of individual patterns of the marks, or adjusting spatial positions of the marks. 32. The method of claim 29, wherein adjusting the geometric design includes adding or adjusting one or more patterns surrounding the mark. 33. The method of clause 29, wherein the cost function includes one or more performance indicators representative of optical measurement performance of the mark. 34. Calculating the cost function is inputting a geometric design of the mark into a first simulation model, the first simulation model being configured to simulate optical measurement parameters obtained using the mark from a measurement tool configured to measure a pattern printed on a substrate; running a first simulation model to obtain optical measurement parameters; 30. The method of claim 29, comprising calculating a cost function based on the optical measurement parameters. 35. The method of claim 25, further comprising determining a geometric design of an individual pattern of marks based on the spatial positions of the marks. 36. The method of claim 25, wherein the mark construct comprises a plurality of patterns, each pattern being characterized by the critical dimension, pitch or subsegmentation of the individual pattern. 37. Acquiring a mark construction is inputting a target design layout and design layout variables of the lithography process into a second simulation model configured to generate a three-dimensional (3D) representation of a design that corresponds to the target design layout to be printed on a substrate using the lithography process; 26. The method of claim 25, comprising: executing a second simulation model to obtain simulation results, the simulation results including a 3D representation of the design. 38. Obtaining the spatial variation of geometric parameters is identifying a grid having a mark in a target design layout, the size of the grid being greater than the size of the mark; and obtaining from the simulation results the spatial variation of the geometric parameter on the grid. 39. The method of claim 38, wherein obtaining the spatial variation includes interpolating a grid to obtain the spatial variation of the geometric parameter for each of the individual patterns of the marks. 40. The method of claim 38, wherein determining the geometric design includes using a simulation model to reconstruct individual patterns of the marks based on spatial variations of the geometric parameters and the mark design layout. 41. The method of claim 40, wherein the individual patterns are further reconstructed based on features of the surrounding patterns of the marks. 42. The method according to clause 25, wherein the spatial variation of the geometric parameter is obtained using at least one of measurement data, empirical data, experimental or data. 43. The method of clause 25, wherein the geometric parameters include at least one of a layer thickness, a chemical mechanical polishing dishing height, an etch sidewall angle, a litho etch critical dimension bias, or an etch floor slope. 44. The method according to clause 25, wherein the geometric parameters vary within each pattern. 45. Obtaining a measurement performance of the mark using the first simulation model; performing a measurement using a measurement tool to obtain a measurement signal, the measurement signal including a set of optical measurement parameters obtained using the mark; 26. The method of claim 25, further comprising adjusting the measurement signal based on the measurement performance. 46. ​​The method of clause 25, wherein the marks include at least one of metrology marks, overlay marks, or alignment marks. 47. The method of clause 25, further comprising generating a mask pattern based on the marks, the mask pattern comprising a pattern corresponding to a target design layout to be printed on the substrate. 48. The method of clause 47, further comprising performing a patterning step using a mask pattern to print a pattern on the substrate via a lithography process. 49. An apparatus for improving imaging of features on a mask onto a substrate during a scanning operation of a lithographic apparatus, comprising: a memory storing a set of instructions; and a processor configured to execute a set of instructions to cause the apparatus to perform a method, the method comprising: Obtaining a mark structure; Obtaining a spatial variation of a geometric parameter associated with a mark construct, the spatial variation being associated with a lithography process; determining a geometric design of an individual pattern of marks based on spatial variations of the marks.

[0086]

[0099] Although the block diagram depicts the illustrated components as separate functional blocks, embodiments are not limited to a system in which the functions described herein are configured as illustrated. The functionality provided by each of the components may be provided by software or hardware modules configured differently than currently illustrated, for example, such software or hardware may be mixed, combined, replicated, partitioned, distributed (e.g., within a data center or geographically), or otherwise configured differently. The functionality described herein may be provided by one or more processors of one or more computers executing code stored on a tangible, non-transitory, machine-readable medium. In some cases, a third-party content delivery network may host some or all of the information communicated over the network, in which case, to the extent information (e.g., content) is said to be provided or provided, the information may be provided by sending instructions to obtain the information from the content delivery network.

[0087]

[0100] Unless otherwise indicated, and as will be apparent from the discussion, discussions throughout this specification using terms such as "processing," "calculating," "calculating," "determining," or similar terms will be understood to refer to specific apparatus operations or processes, such as a special purpose computer or similar special purpose electronic processing / computing device.

[0088]

[0101] The reader should understand that this application describes several inventions. Rather than separating them into multiple independent patent applications, the inventions are grouped together in a single document because their related subject matter makes the filing process more economical. However, the unique advantages and aspects of such inventions should not be confused. It should be understood that in some cases, an embodiment addresses all of the shortcomings described herein, but the invention is useful independently, and some embodiments address only a subset of such problems or provide other unmentioned advantages that would be apparent to one of ordinary skill in the art upon review of this disclosure. Due to cost constraints, some inventions disclosed herein may not be claimed here, but may be claimed in a later application, such as a continuation application, or by amending the claims herein. Similarly, due to space constraints, neither the Abstract nor the Summary of the Invention section of this document should be construed as containing a comprehensive enumeration of all such inventions or all aspects of such inventions.

[0089]

[0102] It should be understood that the description and drawings are not intended to limit the disclosure to the particular forms disclosed, but on the contrary, the invention is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

[0090]

[0103] Modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in light of this description. Thus, the description and drawings should be interpreted as illustrative only and are for the purpose of teaching those skilled in the art the general manner of carrying out the invention. It should be understood that the forms of the invention shown and described herein should be interpreted as examples of embodiments. Elements and materials may be substituted with those shown and described herein, parts and processes may be reversed or omitted, certain features may be utilized independently, or features of the embodiments or embodiments may be combined, all as would be apparent to one skilled in the art after having the benefit of this description. Changes may be made in the elements described herein without departing from the spirit and scope of the invention as set forth in the following claims. The headings used herein are for organizational purposes only and are not used to limit the scope of the description.

[0091]

[0104] As used throughout this application, the word "may" is used in an allowable (i.e., possible) sense rather than a required (i.e., must) sense. Words such as "include," "including," and "includes" mean including but not limited to. As used throughout this application, the singular forms "a," "an," and "the" include plural referents unless otherwise indicated. Thus, for example, reference to "an" element or "a" element includes combinations of two or more elements, notwithstanding the use of other terms or phrases for one or more elements, such as "one or more." As used herein, unless otherwise indicated, the term "or" encompasses all possible combinations unless infeasible. For example, if a component is described as including A or B, the component may include A, or B, or A and B, unless otherwise indicated or infeasible. As a second example, if it is stated that a component may include A, B, or C, unless otherwise stated or infeasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0092]

[0105] For example, terms expressing conditional relations, such as "in response to X, Y," "upon X, Y," "if X, Y," "when X, Y," and the like, encompass causal relations in which the antecedent is a necessary causal condition, the antecedent is a sufficient causal condition, or the antecedent is a contributing causal condition of the outcome (e.g., "upon the obtaining of condition Y, state X occurs" encompasses "X occurs only upon Y" and "X occurs upon Y and Z"). Such conditional relations are not limited to the obtaining of outcomes that immediately follow the antecedent, since some outcomes can be delayed; in conditional sentences, the antecedent is relevant to those outcomes, e.g., the antecedent is relevant to the likelihood of the outcome occurring. A statement in which multiple attributes or features are associated with multiple objects (e.g., one or more processors perform steps A, B, C, and D) encompasses both all such attributes or features associated with all such objects and a subset of attributes or features associated with a subset of attributes or features (e.g., both all processors each perform steps A-D and processor 1 performs step A, processor 2 performs step B and part of step C, and processor 3 performs part of step C and step D), unless otherwise indicated. Furthermore, unless otherwise indicated, a statement that one value or action is "based on" another condition or value encompasses both cases in which that condition or value is the only factor and cases in which that condition or value is one factor among multiple factors. Unless otherwise indicated, a statement that "each" instance of any group has a characteristic should not be construed to exclude cases in which otherwise identical or similar members of the larger group do not have that characteristic, i.e., "each" does not necessarily mean "each and every." References to selections from a range include the endpoints of the range.

[0093]

[0106] In the above description, any process, illustration or block of the flowchart should be understood as representing a module, segment, or portion of code that contains one or more executable instructions for implementing a particular logical function or step in the process; as will be appreciated by those skilled in the art, alternative implementations are included within the scope of the exemplary embodiments of the present developments, in which functions may be performed in an order other than that shown or discussed, including substantially simultaneously or in reverse order, depending on the functionality involved.

[0094]

[0107] To the extent that a particular U.S. patent, U.S. patent application, or other material (e.g., an article) is incorporated by reference, the text of such U.S. patent, U.S. patent application, and other material is incorporated by reference only to the extent that there is no conflict between such material and the descriptions and drawings set forth herein. In the event that such a conflict occurs, such conflicting text in such U.S. patent, U.S. patent application, and other material incorporated by reference is specifically not incorporated by reference herein.

[0095]

[0108] Although specific embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. Indeed, the novel methods, apparatus, and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions, and changes may be made in the form of the methods, apparatus, and systems described herein without departing from the spirit of the present disclosure. The appended claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the present disclosure.

Claims

1. 1. A computer-implemented method for designing a mark for use in imaging a pattern on a substrate using a lithographic process in a lithographic apparatus, comprising: Obtaining a mark structure; obtaining a spatial variation of a geometric parameter associated with the mark construction, the spatial variation being associated with a lithography process; determining a geometric design of an individual pattern of marks based on the spatial variation of the marks; A method comprising:

2. The method of claim 1 , wherein the geometric design is further determined based on a peripheral pattern of the mark.

3. 2. The method of claim 1, wherein determining the geometric design comprises determining at least one of a critical dimension, a pitch, or a subsegmentation of the individual patterns of the mark.

3. The method of claim 1, wherein determining the geometric design comprises determining the spatial position of the mark within a target design to be printed on the substrate.

4. The method of claim 1 , wherein determining the geometry design comprises iteratively adjusting the geometry design based on predicted measurement performance.

5. Each iteration is Calculating a cost function; determining whether the cost function satisfies specified conditions; adjusting the geometry design based on a determination that the cost function does not satisfy the specified condition; and The method of claim 4 , comprising:

6. The method of claim 5 , wherein the cost function comprises one or more performance indicators representative of the optical measurement performance of the mark.

7. Obtaining the mark construct comprises: inputting a target design layout and design layout variables of the lithography process into a second simulation model configured to generate a three-dimensional (3D) representation of a design that corresponds to the target design layout to be printed on the substrate using the lithography process; executing the second simulation model to obtain simulation results, the simulation results including the 3D representation of the design; and The method of claim 1 , comprising:

8. Obtaining the spatial variation of the geometric parameter comprises: identifying a grid in the target design layout having the mark, the size of the grid being greater than the size of the mark; obtaining the spatial variation of the geometric parameter on the grid from the simulation results; The method of claim 1 , comprising:

9. The method of claim 8 , wherein obtaining the spatial variation comprises interpolating the grid to obtain the spatial variation of the geometric parameter for each of the individual patterns of the mark.

10. 2. The method of claim 1, wherein determining the geometric design comprises using the simulation model to reconstruct the individual patterns of the mark based on the spatial variations of the geometric parameters and a mark design layout.

11. The method of claim 10 , wherein the individual patterns are further reconstructed based on features of a surrounding pattern of the mark.

12. 2. The method of claim 1, wherein the spatial variation of the geometric parameters is obtained using at least one of measured data, empirical data, experimental data or data, and the geometric parameters include at least one of a layer thickness, a chemical mechanical polishing dishing height, an etch sidewall angle, a litho etch critical dimension bias, or an etch floor slope.

13. The method of claim 1 , wherein the geometric parameters vary within each pattern.

14. obtaining a measured performance of the mark using a first simulation model; performing a measurement using a measurement tool to obtain a measurement signal, the measurement signal including a set of optical measurement parameters obtained using the mark; adjusting the measurement signal based on the measurement performance; and The method of claim 1 further comprising:

15. 10. The method of claim 1 , wherein the marks comprise at least one of metrology marks, overlay marks, or alignment marks, the method further comprising generating a mask pattern based on the marks, the mask pattern comprising a pattern corresponding to a target design layout to be printed on the substrate.

Images