Photosite circuit using switched operational phases

Abstract

To provide techniques to accurately measure the integration or accumulation of charge, which is measured by photosite readout circuitry, due to a photodiode-generated current.SOLUTION: The photodiode-generated current is generated by a photodiode that forms part of an imaging sensor, as a result of reflected light incident on the photodiode. The techniques described herein address shortcomings of photosite operation by using a series of sequential switching states that function to maintain the charge accumulated during idle sampling times between active detection windows.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of the filing date of U.S. Provisional Application No. 63 / 094,913, filed October 22, 2020, the entire contents of which are incorporated herein by reference.

[0002] Aspects described herein relate generally to image sensors and, more particularly, to image sensors that perform imaging by detecting light reflected from an illuminated target and incident on a photodiode. [Background technology]

[0003] The light detection device may include a photosite that includes (i) a photosite readout circuit connected to a photodiode (PD) for detecting incident light, and (ii) a capacitance for storing charge provided by the photodiode. The capacitance may be (i) embodied as at least one dedicated capacitor and / or (ii) embodied using parasitic capacitance of the PD, transistors, and / or other components of the photosite.

[0004] Dark current is a well-known phenomenon. When referring to a photodiode, dark current refers to the current that flows in the photodiode even when no photons are incident on the device. Dark current in a PD can result from the random generation of electrons and holes in the depletion region of the PD.

[0005] In some cases, it is necessary to provide a photosite having a PD with a relatively high dark current while implementing a capacitor of limited size (which may include discrete components, parasitic capacitance, etc.). In some cases, it is necessary to provide a photosite having a PD with a relatively high dark current while reducing the effect of the dark current on the photosite's output detection signal. In photosites with high dark current accumulation, it is necessary and may be advantageous to reduce the dark current accumulation and related effects.

[0006] Furthermore, with respect to the photosite readout circuit, the image may be collected using electrical signals provided by the photodiode readout circuit. These electrical signals are the result of the aggregation of charges stored in one or more capacitors in response to multiple illumination pulses incident on the PD during the corresponding detection time frame. However, during the idle time between the multiple illumination pulses, the PD may continue to generate current (e.g., due to ambient light and / or inherent dark current). The additional current thus generated may provide additional charge to the capacitor(s) of the photosite readout circuit. This may adversely affect the accuracy of the readout.

[0007] Thus, current light sensing devices suffer from a variety of drawbacks, some of which are discussed above. [Brief description of the drawings]

[0008] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the embodiments and to enable one skilled in the relevant art to make and use the embodiments.

[0009] Exemplary aspects of the present disclosure are now described with reference to the accompanying drawings, in which the drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.

[0010] Non-limiting examples of the embodiments disclosed herein are described below with reference to the attached figures listed after this paragraph. Identical structures, elements or parts appearing in one or more figures may be labeled with the same numerals in all figures in which they appear. Each figure and each description is intended to clearly explain and clarify the embodiments disclosed herein, and should not be considered as limiting in any manner. All figures show devices or flow charts according to examples of the presently disclosed subject matter. The figures are as follows:

[0011] [Figure 1] FIG. 1 shows a schematic of a photosite that includes a photodiode controlled by a voltage controlled current source.

[0012] [Diagram 2] FIG. 2 shows a schematic of a photosite that includes a photodiode controlled by a voltage-controlled current source in a "3T" configuration.

[0013] [Figure 3A] 3A and 3B show a PDD comprising a plurality of photosites and circuitry operable to reduce the effects of dark current. [Figure 3B] 3A and 3B show a PDD comprising a plurality of photosites and circuitry operable to reduce the effects of dark current.

[0014] [Figure 3C] FIG. 3C illustrates a PDD comprising a plurality of photosites and circuitry operable to reduce the effects of dark current.

[0015] [Figure 4]FIG. 4 shows the IV curves of an exemplary photodiode and the expected operating voltages for the PDD.

[0016] [Diagram 5] FIG. 5 shows a control voltage generating circuit connected to a number of reference photosites.

[0017] [Figure 6A] 6A and 6B show a PDD that includes an array of photodiodes and a reference circuit based on multiple photodiodes. [Figure 6B] 6A and 6B show a PDD that includes an array of photodiodes and a reference circuit based on multiple photodiodes.

[0018] [Figure 7] 7 and 8 show PDDs each including photosites and circuitry operable to reduce the effects of dark current. [Figure 8] 7 and 8 show PDDs each including photosites and circuitry operable to reduce the effects of dark current.

[0019] [Figure 9] FIG. 9 shows a PDD with optics, a processor, and additional components.

[0020] [Figure 10] FIG. 10 is a flow chart illustrating a method for compensating for dark current in a photodetector.

[0021] [Figure 11] FIG. 11 is a flow chart illustrating a method for testing a photodetector.

[0022] [Figure 12]FIG. 12 is a flow chart illustrating a method 1200 for testing a photodetector according to an example of the presently disclosed subject matter.

[0023] [Figure 13] FIG. 13 illustrates an exemplary photosite readout circuit architecture according to an embodiment of the present disclosure.

[0024] [Figure 14A] 14A-14D illustrate example switching states of the photosite readout circuit architecture shown in FIG. 13 according to an embodiment of the present disclosure. [Figure 14B] 14A-14D illustrate example switching states of the photosite readout circuit architecture shown in FIG. 13 according to an embodiment of the present disclosure. [Figure 14C] 14A-14D illustrate example switching states of the photosite readout circuit architecture shown in FIG. 13 according to an embodiment of the present disclosure. [Figure 14D] 14A-14D illustrate example switching states of the photosite readout circuit architecture shown in FIG. 13 according to an embodiment of the present disclosure.

[0025] [Figure 15] FIG. 15 illustrates an example of an operational phase during a sampling period including multiple sampling windows according to an embodiment of the present disclosure.

[0026] [Figure 16] FIG. 16 illustrates an electro-optical system according to an embodiment of the present disclosure.

[0027] [Figure 17] FIG. 17 illustrates a process flow according to one or more embodiments of the present disclosure.

[0028] [Figure 18] FIG. 18 illustrates a process flow according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] In the following description, numerous specific details are described in order to fully understand the aspects of the present disclosure. However, it will be apparent to those skilled in the art that the aspects, including structures, systems, and methods, can be practiced without these specific details. The descriptions and representations herein are general means used by those skilled in the art or experienced to most effectively convey the substance of their work to those skilled in the art. In other instances, well-known methods, procedures, components, and circuits have not been described in detail to avoid unnecessarily obscuring the aspects of the present disclosure.

[0030] The embodiments described herein are divided into separate sections for ease of explanation. However, these embodiments may be utilized separately or combined with each other. The first section is directed to addressing problems associated with photodetecting devices (PDDs), in particular, the elimination or reduction of dark current in PDDs. The second section is directed to addressing problems associated with inaccuracies in the readings of photosite readout circuits. The problems arise due to the PD generating current during idle periods between adjacent light pulses, which results in additional charge accumulation during the idle periods.

[0031] <Section I - Circuits for Compensating Dark Current> (A. Overview) In various exemplary embodiments, a photodetector device (PDD) is provided. The photodetector device includes an active photosite, a reference photosite, a first voltage-controlled current circuit, and a control voltage generating circuit. The active photosite includes an active photodiode (PD). The reference photosite includes a reference PD. The first voltage-controlled current circuit includes a voltage-controlled current source or a voltage-controlled current sink. The first voltage-controlled current circuit is connected to the active PD. The control voltage generating circuit is connected to the active voltage-controlled current circuit and the reference photosite, and is used to supply a control voltage to the voltage-controlled current circuit, the control voltage having a voltage level according to the dark current of the reference PD. This can reduce the effect of the dark current of the active PD on the output of the active photosite.

[0032] In some embodiments, the control voltage generating circuit includes an amplifier for providing the control voltage.

[0033] In some embodiments, the voltage controlled current circuit includes a current source.

[0034] In some embodiments, the voltage controlled current circuit includes a current sink.

[0035] In some embodiments, the PDD includes a reference voltage controlled current circuit including a voltage controlled current source or a voltage controlled current sink. The reference voltage controlled current circuit is connected to a reference PD. A first input of the amplifier is provided with a first input voltage. A second input of the amplifier is electrically connected to the reference PD and the reference voltage controlled current circuit.

[0036] In some embodiments, the first voltage controlled current circuit and the reference voltage controlled current circuit are connected to an output of an amplifier, the amplifier generating the control voltage by continuously decreasing the difference between the output of the reference voltage control circuit and the first input voltage.

[0037] In some embodiments, the controlled voltage generating circuit includes an amplifier, and the voltage controlled current circuit includes a current sink connected to the amplifier.

[0038] In some embodiments, the PDD comprises a plurality of active photosites, a plurality of reference photosites, a plurality of first voltage controlled current circuits, and a plurality of reference voltage controlled current circuits. Each of the plurality of active photosites includes an active PD. Each of the plurality of reference photosites includes a plurality of reference PDs. Each of the plurality of first voltage controlled current circuits is coupled to at least one of the plurality of active PDs. Each of the plurality of reference voltage controlled current circuits is coupled to at least one of the plurality of reference PDs. A second input of the amplifier is electrically coupled to each of the plurality of reference PDs. A control voltage is provided to each of the plurality of first voltage controlled current circuits.

[0039] In some embodiments, each of the plurality of active photosites includes a corresponding voltage-controlled current circuit.

[0040] In some embodiments, different active PDs simultaneously generate different levels of dark current, and different reference PDs simultaneously generate different levels of dark current, and the control voltage generation circuit provides the same control voltage to the different active PDs based on averaging the different dark currents of the reference PDs.

[0041] In some embodiments, the PDD includes a plurality of first voltage-controlled current circuits, the plurality of first voltage-controlled current circuits including at least one voltage-controlled current source collectively connected to each active photosite and at least one voltage-controlled current sink collectively connected to each active photosite, the control voltage generating circuit including: (a) a first amplifier connected to the at least one voltage-controlled current source to provide a first control voltage to the plurality of active photosites at a first time, a second amplifier connected to the at least one voltage-controlled current sink to provide a second control voltage to the plurality of active photosites at a second time, and a switching circuit for selecting between providing the first control voltage and providing the second control voltage.

[0042] In some embodiments, the PDD includes a controller for providing a first input voltage, the first input voltage having a level determined as a function of a bias for the active PD.

[0043] In some embodiments, the controller provides a first input voltage such that the bias of the reference PD is approximately (substantially) equal to the bias of the active PD.

[0044] In some embodiments, the PDD includes a physical barrier that prevents light from the field of view of the PDD from reaching the reference PD.

[0045] In some embodiments, the PDD comprises a plurality of photosites and a controller for configuring at least one photosite of the plurality of photosites to operate as either an active photosite or a reference photosite.

[0046] In some embodiments, the PDD includes a plurality of active photosites, a plurality of reference photosites, a plurality of first voltage-controlled current circuits, and a plurality of reference voltage-controlled current circuits. Each of the plurality of active photosites includes an active PD. Each of the plurality of reference photosites includes a plurality of reference PDs. Each of the plurality of first voltage-controlled current circuits is connected to at least one of the plurality of active PDs. Each of the plurality of reference voltage-controlled current circuits is connected to at least one of the plurality of reference PDs. When the PDD operates at a first temperature, the control voltage generation circuit provides a first control voltage to the voltage-controlled current circuit to provide a current at a first level according to the dark currents of the plurality of reference PDs, thereby reducing an effect of the dark current of the active PDs on an output of the active photosites. When the PDD operates at a second temperature higher than the first temperature, the control voltage generation circuit provides a second control voltage to the voltage-controlled current circuit to provide a current at a second level according to the dark currents of the plurality of reference PDs, thereby reducing an effect of the dark current of the active PDs on an output of the active photosites. In this case, the second level is higher (greater) than the first level.

[0047] In some embodiments, the PDD includes a plurality of active photosites, a plurality of reference photosites, a plurality of first voltage-controlled current circuits, a plurality of reference voltage-controlled current circuits, an optical system, a power supply, a readout circuit, a processor, and a memory module. Each of the plurality of active photosites includes an active PD. Each of the plurality of reference photosites includes a plurality of reference PDs. Each of the plurality of first voltage-controlled current circuits is connected to at least one of the plurality of active PDs. Each of the plurality of reference voltage-controlled current circuits is connected to at least one of the plurality of reference PDs. The optical system directs light coming from a field of view of the PDD to the plurality of photosites. The power supply provides power to the active photosites, the reference photosites, and the amplifier. The readout circuit provides detection information in response to detection signals of the active photosites. The processor processes the detection information to provide an image of at least an object in the field of view. The memory module stores at least one of the detection information and the detection signals.

[0048] In some embodiments, the reference PD is a copy of the active PD.

[0049] In some embodiments, the PDD includes a "sample and hold" circuit.

[0050] In some embodiments, the active PD generates a detection signal in response to the incident light and the dark current generated by the active PD. The capacitance of the active photosite collects charge resulting from the detection signal and the current of the voltage-controlled current circuit over a sampling period. The integral of the detection signal over the sampling period may exceed the capacitance of the active photosite.

[0051] B. DETAILED DESCRIPTION OF AN EXEMPLARY EMBODIMENT FIG. 1 illustrates a schematic of an example photosite, numbered 100. Photosite 100 includes a photodetector (e.g., PD) 102 controlled by a voltage-controlled current source (VCCS) 104. Note that, optionally, voltage-controlled current source 104 may be external to photosite 100 (e.g., where a single VCCS 104 supplies current to multiple photosites). VCCS 104 is a dependent current source that supplies a current proportional to a control voltage (labeled VCTRL in the figure). Photosites and PDDs disclosed in this disclosure may include any suitable type of VCCS. Other ("additional") components of photosite 100 (not shown) are generally represented by schematic box 106. When used for sensing, photosites, such as photosite 100, and photodetectors, such as photodetector 102, may also be referred to below as "active" or "non-reference" photosites / photodetectors (to distinguish them from photosites and photodetectors that are used as inputs to determine control voltages for current sources).

[0052] 2 shows another example of a photosite, numbered 100'. Photosite 100' is an example of photosite 100. In photosite 100', other components 106 take the form of a "3T" (three-transistor) structure. Any other suitable circuitry may serve as additional components 106.

[0053] The CCS 104 may be used to supply a current of the same magnitude but in the opposite direction as the dark current generated by the PD 102, thereby canceling (or at least reducing) the dark current. This is particularly useful when the PD 102 has a high dark current. In this way, the charge flowing from the photodiode to the capacitance (which may be caused by one or more capacitors, the parasitic capacitance of the photosite, or a combination thereof, as described above) and the charge resulting from the dark current may be cancelled. It should be noted that supplying a current of approximately equal magnitude to the dark current by the VCCS 104 means that the supplied current does not cancel the actual electrical signal generated by the PD 102 as a result of the detected light incident on the PD 102.

[0054] 3A illustrates a photodetector device 300 according to an example of the presently disclosed subject matter. The PDD 300 includes circuitry that allows the current provided by the VCCS 104 to be controllably matched to the dark current generated by the PD 102, even if the dark current generated is not constant (varying over time). It should be noted that the level of dark current generated by the PD 102 may depend on various parameters, such as operating temperature and the bias applied to the photodiode (which may also vary from time to time).

[0055] The reduction of the effects of dark current within the photosite 100, performed by the PDD 300 (at a stage later than either analog or digital signal processing), allows the use of a relatively small capacitance without saturating the capacitance or reducing the linearity of its response to collected charge.

[0056] The PDD 300 includes a photosite 100 for detecting incident light and a reference photosite 310. The output of the reference photosite 310 is used by additional circuitry (described below) to reduce or eliminate the effects of dark current in the photosite 100. Similar to the photosite 100 (and 100'), the reference photosite 310 includes a PD 302, a VCCS 304, and optionally additional circuitry ("other components," collectively designated 306). In some examples, the reference photosite 310 of the PDD 300 may be equivalent to the photosite 100 of the PDD 300. Optionally, one or more of the components of the photosite 310 may be equivalent to the corresponding components of the photosite 100. For example, the PD 302 may be substantially equivalent to the PD 102. For example, the VCCS 304 may be equivalent to the VCCS 104. Optionally, one or more of the components of the photosite 310 may be different from the components of the photosite 100 (e.g., photodiodes, current sources, additional circuitry). It should be noted that substantially equivalent components of the photosite 100 and the photosite 310 (e.g., photodiodes, current sources, additional circuitry) may be operated in different operating conditions. For example, different biases may be applied to the PDs 102 and 302. For example, different components of the additional components 106 and 306 may be operated using different parameters or selectively connected / disconnected even if their structure is substantially equivalent. For the sake of brevity and clarity, the components of the photosite 310 are numbered 302 (for PD), 304 (for VCCS), and 306 (for additional circuitry). However, this does not imply that these components are different from the components 102, 104, and 106.

[0057] In some examples, the reference adding circuit 306 may be omitted or shut off so as not to affect the determination of the dark current. The PD 102 may be selectively operated (e.g., controlled by a controller such as the controller 338 described below) in reverse bias, forward bias, zero bias, or at least one between two or three of these biases. The PD 302 may be selectively operated (e.g., controlled by a controller such as the controller 338 described below) in reverse bias, forward bias, zero bias, or at least one between two or three of these biases. The PDs 102 and 302 may be operated under approximately the same bias (e.g., about −5V, about 0V, about +0.7V), but this is not necessarily the case (e.g., when testing the photodetector device 300, as described in more detail below). Optionally, a single photosite of the PDD 300 may act as a photosite 100 in some cases (detecting light coming from the field of view (FOV) of the PDD 300) and as a photosite 310 in other cases (the detection signal output of the photosite 310 is used to determine the control voltage of the voltage-controlled current source VCCS of another photosite 100 of the light detection device). Optionally, the role of the "active" photosite used to detect the incident light and the role of the reference photosite may be swapped. The PDD 300 further comprises a control voltage generation circuit 340. The control voltage generation circuit 340 includes at least an amplifier 318 and electrical connections to the photosites of the PDD 300. The amplifier 318 has at least two inputs, a first input 320 and a second input 322. The first input 320 of the amplifier 318 is supplied with a first-input voltage (VFI). The first input voltage may be directly controlled by a controller (which may be implemented in the PDD 300, an external system, or a combination thereof), or may be derived from other voltages in the system (in which case the other voltages may be controlled by the controller).A second input 322 of the amplifier 318 is connected to the cathode of the PD 302 (of the reference photosite 310).

[0058] In a first use case, the PD 102 is maintained at an operating bias between a first voltage (also referred to as an “anode voltage” and denoted as VA) and a second voltage (also referred to as a “cathode voltage” and denoted as VC). The anode voltage may be directly controlled by a controller (which may be implemented in the PDD 300, an external system, or a combination thereof). Alternatively, the anode voltage may be derived from other voltages in the system (in which case the other voltages may be controlled by the controller). The cathode voltage may be directly controlled by a controller (which may be implemented in the PDD 300, an external system, or a combination thereof). Alternatively, the cathode voltage may be derived from other voltages in the system (in which case the other voltages may be controlled by the controller). Each of the anode voltage VA and the cathode voltage VC may be maintained constant in time or may not be maintained constant in time. For example, VA may be supplied by a constant source (e.g., from an external controller via a pad). Depending on the implementation, VC may be approximately constant or may vary over time. For example, if a 3T structure is used for the photosite 100, VC varies over time, for example, due to operation of the additional components 106 and / or current from the PD 102. Optionally, VC may be determined / controlled / influenced by the additional components 106 (rather than the reference circuit).

[0059] The VCCS 104 is used to feed a current to the cathode of the PD 102 to counter the dark current generated by the PD 102. It should be noted that in other cases, the VCCS 104 may feed other currents to achieve other purposes (e.g., to calibrate or test the photodetector device 300). The level of the current generated by the VCCS 104 is controlled in response to the output voltage of the amplifier 318. The control voltage (labeled VCTRL) for controlling the VCCS 104 (as shown) may be equal to the output voltage of the amplifier 318. Alternatively, the VCTRL may be derived from the output voltage of the amplifier 318 (e.g., due to a resistance or impedance between the output of the amplifier 318 and the VCCS 104).

[0060] To cancel (or at least reduce) the effect of the dark current of PD 102 on the output signal of photosite 100, PDD 300 may provide PD 302 with approximately the same bias as PD 102. For example, if PD 302 is approximately the same as PD 102, the same bias may be applied to PD 302 and PD 102. One way to apply the same bias to both PDs (102 and 302) is to apply a voltage VA to the anode of PD 302 (in this case, the applied voltage is denoted as VRPA, where RPA stands for "reference photodiode anode") and a voltage VC to the cathode of PD 302 (in this case, the applied voltage is denoted as VRPC, where RPC stands for "reference photodiode cathode"). Another way to apply the same bias is to apply VRPA=VA+ΔV to the anode of PD 302 and VRPC=VC+ΔV to the cathode of PD 302. Optionally, the anode voltage VA, the reference anode voltage VRPA, or both may be supplied by an external source (e.g., via the PCB to which the PDD 300 is connected).

[0061] As mentioned above, a first input 320 of the amplifier 318 is supplied with a first input voltage VFI. A second input 322 of the amplifier 318 is connected to the cathode of the PD 302. The operation of the amplifier 318 reduces the voltage difference between the two inputs (320 and 322) of the amplifier. This allows the voltage of the second input 322 to approach the same voltage as the control voltage (VFI) applied to the first input. Now, refer to FIG. 3B. In FIG. 3B (the illustrated circuit is equivalent to FIG. 3A), the dark current (hereinafter referred to as DCReference) flowing through the PD 302 is represented by an arrow 352. The current flowing through the PD 302 is equal to the dark current of the PD 102 when the PD 102 is kept in a dark state during that time. The PDD 300 (or a system component connected to or adjacent to the PD 300) may block light toward the PD 302, so that the PD 302 is kept in a dark state. The blocking may be performed by a physical barrier (e.g., an opaque barrier), an optical system (e.g., a bypass lens), an electronic shutter, etc. In the following description, it is assumed that all current flowing through the PD302 is dark current generated by the PD302. Alternatively, if the PD302 receives light (e.g., a low level of known stray light in the system), a current source may be implemented to offset the known light-derived signal. Alternatively, the first input voltage VFI may be calibrated (corrected) to (at least partially) compensate for the stray light. The barrier, optics, or other dedicated components intended to keep light away from the PD302 may be implemented, for example, at the wafer level, connected (e.g., using an adhesive) to the wafer (which may be implemented on the same wafer on which the PDD300 is manufactured), or rigidly connected to the casing on which the wafer is mounted.

[0062] Assume that VFI is constant (or slowly varying). In this case, the output of VCCS304 (represented by arrow 354) should be approximately equal in magnitude to the dark current (DC Reference) of PD302. This means that the voltage is maintained at VFI by VCCS304 providing charge carriers to consume the dark current of PD302. Because the output of VCCS304 is controlled by VCTRL, which is responsive to the output of amplifier 318. Amplifier 318 operates to output the required output. Thus, VCTRL can control the current output by VCCS304, which will be equal in magnitude to the dark current of PD302.

[0063] When PD102 is approximately equal to PD302 and VCCS104 is approximately equal to VCCS304, the output of the amplifier 318 may cause VCCS104 to supply the same level of current (DCReference) to the cathode of PD102. In this case, in order for the output of VCCS104 to cancel the dark current (hereinafter referred to as DCActivePD) generated by PD102, both PD102 and PD302 need to generate similar levels of dark current. In order to provide the same bias to both PDs (102 and 302) (both PDs are maintained in approximately the same condition, e.g., approximately the same temperature, in this case both PDs will generate approximately the same level of dark current), the voltage supplied to the first input of the amplifier 318 is determined according to the anode and cathode voltages of PD102 and the anode voltage of PD302. For example, when VA is equal to VRPA, VFI equal to VC may be supplied to the first input 320. Note that VC is not necessarily determined by the controller, since it may change over time (e.g., VC may be determined as a result of the additional component 106). If PD102 is different from PD302 and / or VCCS104 is different from VCCS304, the output of amplifier 318 may be changed by matching electrical components (not shown) between amplifier 318 and VCCS104. In this case, a related control voltage may be provided to VCCS104 (e.g., if it is known that the dark current flowing through PD102 is linearly correlated with the dark current flowing through PD302, the output of amplifier 318 may be changed according to the linear correlation). Another way to apply the same bias is to apply VRPA=VA+ΔV to the anode of PD302 and VRPC=VC+ΔV to the cathode of PD302.

[0064] FIG. 3C illustrates a photodetector device 300' including multiple photosites 100 according to an example of the presently disclosed subject matter. The PDD 300' includes all the components of the PDD 300 plus an additional photosite 100. The different photosites of the photodetector device 300' are approximately equivalent to each other (e.g., all are part of a two-dimensional photodetector array). Thus, the PDs 302 of the different photosites 100 generate similar dark currents to each other. Thus, the same control voltage VCTRL is provided to all of the VCCSs 104 of the different photosites 100 of the PDD 300'. This allows these VCCSs 104 to cancel (or at least reduce) the effect of the dark current generated by their respective PDs 102. Any of the options discussed above with respect to the PDD 300 apply to the PDD 300' as well.

[0065] In some examples (e.g., when VC is not constant and / or when VC is not known), it is possible to provide (e.g., by a controller) a first input voltage VFI selected to cause PD302 to have a dark current similar to PD102.

[0066] Reference is now made to FIG. 4, which illustrates an IV curve 400 of an exemplary photodiode according to an example of the presently disclosed subject matter. For simplicity of explanation, curve 400 represents the IV curves of both PD302 and PD102. For purposes of explanation, it is assumed that PD302 and PD102 are approximately equal and experience equal anode voltages (i.e., in this explanation, VA=VRPA). The IV curve 400 is relatively flat from voltages 402 to 404. This means that various biases applied to the associated photodiodes from 402 to 404 will result in similar levels of dark current. Assuming that VA is known, when VC is varying within the cathode voltage range, means that the bias at PD102 is limited to voltages 402 to 404. Applying VRPC such that the bias on PD302 is also from voltage 402 to 404 will result in VCCS104 outputting a current close enough to DCActivePD even if PD102 and PD302 are biased differently. VRPC in this case may be within the cathode voltage range, as illustrated by equivalent voltage 414, or outside the cathode voltage range, as illustrated by equivalent voltage 412. However, the bias on PD302 is maintained from 402 to 404. Other configuration variations as described above may be used as well. Note that different biases may be applied to different PD102 and PD302 for other reasons. For example, different biases may be applied as part of testing or calibration of the photodetector array.

[0067] In reality, the different photodiodes (or other components) at different photosites in a light-detecting device are not manufactured identically, and therefore the operation of different photosites is not identical to one another. In a photodiode array, the photodiodes may differ slightly from one another, and the dark currents of the photodiodes may also differ slightly (e.g., due to manufacturing variations, slight temperature differences, etc.).

[0068] FIG. 5 illustrates a control voltage generation circuit 340 connected to a number of reference photosites 310 according to an example of the presently disclosed subject matter (generically designated 500). The circuit of FIG. 5 (also referred to as reference circuit 500) may be used to determine a control voltage (designated VCTRL) of one or more VCCS 104 at one or more corresponding photosites 310 in any of the PDDs 300, 300' and variations of the light-detecting devices described in this disclosure. In particular, the reference circuit 500 may be used to determine a control voltage to cancel (or limit) the effect of dark current at one or more photosites 100 of the light-detecting device based on data collected from a number of reference photosites 310 that are somewhat different (e.g., as a result of manufacturing inaccuracies, slightly different operating conditions, etc.). As discussed above, the dark currents of photodiodes may be similar but different from one another. It should be noted that in some photodiode technologies, photodiodes that are intended to be equivalent may have dark currents that are 1.5 times, 2 times, 4 times, or even greater. The averaging mechanisms described herein can compensate for even such significant differences (e.g., during manufacturing). To average the dark current levels of multiple photosites 310, if an amplifier 318 is connected to multiple reference photosites 310, the photosites 310 are kept in a dark state, for example, using any of the mechanisms described above. The voltages applied to the different VCCSs 304 of the various photosites 310 are shorted together so that all VCCSs 304 receive approximately the same control voltage. The cathode voltages of the different reference PDs 302 are shorted to different nets.In this way, although the currents of the different reference photosites 310 are slightly different from each other (due to the reference photosites 310 being slightly different from each other), the average control voltage supplied to one or more photosites 100 (which may also be slightly different from each other and from the reference photosites 310) of each light-detecting device is sufficiently accurate and in a sufficiently uniform manner to cancel the effect of dark currents on the different photosites 100. Optionally, the output voltage of a single amplifier 318 is supplied to all the photosites 100 and all the reference photosites 310. Optionally, the photodiodes selected for the light-detecting devices have a flat IV response (e.g., as described above with respect to FIG. 4). In this case, the average control voltage described with respect to the reference circuit 500 cancels the dark currents of the different photosites 100 to a very good extent. A non-limiting example of a light-detecting device including multiple reference photosites 310 is shown in FIGS. 6A and 6B. In this example, the averaged output signal of the reference photosites 310 is used to modify the output signal of the active photosites 100 (e.g., to reduce the effect of dark current on the output signal). Different configurations, shapes, and numerical ratios may be applied to the reference photosites 310 and the active photosites 100 in a single photodetector device. For example, in a rectangular photodetector array containing row-wise and column-wise arranged photosites, an entire row of photosites (e.g., 1000 photosites) or a portion of a row or column of photosites may be used as the reference photosites 310 (optionally kept dark). In this case, the remainder of the array receives a control signal based on averaging the output of the row of reference photosites. This method of generating the control current significantly reduces the effect of dark current by eliminating the average dark current, leaving only the photosite-to-photosite variation.

[0069] 6A and 6B show a photodetector device including an array of multiple photodiode-based photosites and a reference circuit according to an example of the presently disclosed subject matter. PDD 600 (shown in FIG. 6A) and PDD 600' (shown in FIG. 6B, which is a variation of PDD 600) include all the components of PDD 300, plus additional photosite 100 and photosite 310. Optionally, the different photosites of photodetector device 600 (and individually of PDD 600') are substantially equivalent to each other. Any of the options discussed above with respect to PDD 300 and PDD 300' and circuit 500 are also applicable to PDD 600 and PDD 600'.

[0070] 6A shows a light-detecting device 600. The light-detecting device 600 comprises a light-sensitive region 602 with (an array of) a number of photosites 100 (which are exposed to external light during operation of the light-detecting device 600), a region 604 with a number of reference photosites 310 that are kept dark (at least during the measurement of the reference current, and optionally at all times), and a control voltage generating circuit 340, which further includes a controller 338. The controller 338 may control the operation of the amplifier 318, the voltage supplied to the amplifier 318, and / or the operation of the reference photosites 310. Optionally, the controller 338 may also control the operation of the photosites 100 and / or other components of the PDD 600. The controller 338 may control both the active photosites 100 and the reference photosites 310 to operate under the same operating conditions (e.g., managing bias, exposure time, readout regime). It should be noted that any functionality of controller 338 may be embodied by an external controller (e.g., another processor of the electro-optical system in which the light-sensing device is located, or an auxiliary system such as a controller of an autonomous vehicle in which the light-sensing device is located). Optionally, controller 338 may be embodied as one or more processors implemented on the same wafer as other components of PDD 600 (e.g., photosites 100 and 310, amplifier 318). Optionally, controller 338 may be embodied as one or more processors on a printed circuit board (PCB) connected to the wafer. Alternatively, any other suitable controller may be embodied as controller 338.

[0071] FIG. 6B illustrates a light-detecting device 600' according to an example of the presently disclosed subject matter. The light-detecting device 600' is similar to the device 600, but with components arranged in a different orientation. The internal details of the different photosites are not shown in FIG. 6B. Also illustrated in FIG. 6B is a readout circuit 610. The readout circuit 610 is used to read out the detection signals from the photodetectors 100 for further processing (e.g., noise reduction for image processing), for storage, or for other uses. For example, the readout circuit 610 can sequentially and temporarily arrange the readouts of the different photosites 100 (possibly after some processing by one or more processors of the light-detecting device, not shown) before providing the readouts for further processing, storage, or other operations. Optionally, the readout circuit 610 may be embodied as one or more units fabricated on the same wafer as the other components of the PDD 600 (e.g., the photosites 100 and 310, the amplifier 318). Optionally, the readout circuit 610 may be embodied as one or more units on a printed circuit board (PCB) connected to the wafer. Alternatively, other suitable readout circuits may be embodied as the readout circuit 610. It should be noted that a readout circuit such as the readout circuit 610 may be implemented in any of the photodetector devices described in this disclosure (e.g., PDD 300, 700, 800, and 900). Examples of analog signal processing that may be performed in the photodetector device (e.g., by the readout circuit 610 or by one or more processors of the respective photodetector device) prior to optional signal digitization include gain correction (amplification), offset, and binning (combining output signals from two or more photosites). Digitization of readout data may be performed in the photodetector device or may be performed external to the photodetector device.

[0072] Optionally, the PDD 600 (or any other photodetector device disclosed in this disclosure) may include a sampling circuit. The sampling circuit samples the output voltage of the amplifier 318 and / or the control voltage VCTRL (if different) and holds that voltage level for at least a specified minimum period. The sampling circuit may be located anywhere between the output of the amplifier 318 and one or more of the VCCSs 104 (e.g., at location 620). Any suitable sampling circuit may be used. In some examples, an example circuit may include a “sample and hold” switch. Optionally, the sampling circuit may be used only some of the time. In this case, a direct real-time readout of the control voltage is performed at other times. For example, using a sampling circuit may be beneficial when the magnitude of the dark current in the system changes slowly and the photosites 310 are shaded only some of the time.

[0073] 7 and 8 show other light-detecting devices according to examples of the presently disclosed subject matter. In the light-detecting devices described above (e.g., 300, 300', 600, 600'), voltage-controlled current sources were used for both the active photosite 100 and the reference photosite 310. A current source is one example of a voltage-controlled current circuit that can be used in the disclosed light-detecting devices. Another type of voltage-controlled current circuit that can be used is a voltage-controlled current sink. The amount of current absorbed by the voltage-controlled current sink is controlled by a control voltage provided to the voltage-controlled current sink. For example, a current sink may be used when the bias on the PD (102, 302) is in the opposite direction to that in the examples described above. More generally, whenever a voltage-controlled current source is described above (104, 304), this component can be replaced with a voltage-controlled current sink (labeled 704, 714, respectively). It should be noted that when a current sink is used instead of a current source, it may be necessary to use different types of components or circuits in other portions of each photodetector device. For example, an amplifier 318 used with a VCCS 104 and 304 will differ in power, size, etc. from an amplifier 718 used with a voltage controlled current sink 704 and 714. To distinguish between photosites that include a voltage controlled current sink instead of a VCCS, reference numbers 100' and 310' are used corresponding to photosites 100 and 300 described above.

[0074] 7, PDD 700 includes a voltage controlled current circuit (in both photosite 100' and photosite 310') that is a voltage controlled current sink. Instead of amplifier 318, a suitable amplifier 718 is used. All the variations described above for the current source are equally applicable to the current sink.

[0075] In FIG. 8, the PDD 800 includes both types of voltage-controlled current circuits, i.e., both voltage-controlled current sources 104 and 314 and voltage-controlled current sinks 704 and 714, along with matched amplifiers 318 and 718. This allows, for example, the photodiodes of the PDD 800 to be operated in either forward or reverse bias. At least one switch (or other selection mechanism) may be used to select whether the VCCS-based reference circuit or the voltage-controlled current sink-based reference circuit is to be activated / deactivated. The selection mechanism may be used, for example, to prevent the two feedback regulators from operating "against" each other (e.g., when operating with a near-zero bias applied to the photodiodes). Any of the options, explanations, or variations described with respect to any of the photodetector devices (e.g., 300, 300', 600, 600') described above are also applicable to the PDDs 700 and 800. In particular, the PDDs 700 and 800 may include multiple photosites 100' and / or multiple reference photosites 310', similar to those described above (eg, with respect to Figures 5, 6A, and 6B).

[0076] It should be noted that in any of the above-mentioned light detection devices, one or more photosites (e.g., of a light detection array) may be optionally controllable to be selectively used as reference photosites 310 (e.g., at some times) or as normal photosites 100 (e.g., at other times). The photosites may include the necessary circuitry to operate in both roles. This may be employed, for example, when the same light detection device is used in different types of electro-optical systems. As an example, one system may require the accuracy of averaging 1000-4000 reference photosites 310, while another system may require less accuracy that may be achieved by averaging 1-100 reference photosites 310. In another example, averaging of the control voltages based on some (or all) of the photosites may be performed when the entire photodetector array is darkened and stored in a sample-and-hold circuit as described above. In one or more subsequent frames, all of the photosites may be used to detect FOV data using the determined control voltages.

[0077] Please note that in the above description, for simplicity, it is assumed that the anode side of all photodiodes in each photodetection array is connected to a known (and possibly controlled) voltage, and that the detection signals and the VCCS and additional circuit connections are made on the cathode side. Optionally, PDs 102 and 302 can be connected in the opposite manner (such as when readout is made on the anode side).

[0078] It should be noted that for all of the above-mentioned light detection devices (e.g., 300, 600, 700, 800), the photosites, readout circuitry, reference circuitry, and other above-mentioned components (as well as any additional components, if required) may be implemented on a single wafer, on multiple wafers, on one or more PCBs, or on other suitable types of circuitry connected to the photosites, etc.

[0079] 9 illustrates a PDD 900 according to an example of the presently disclosed subject matter. The PDD 900 may employ any combination of features from one or more of the light detection devices described above and may further include additional components. For example, the PDD 900 may include any one or more of the following components:

[0080] At least one light source 902 operable to emit light into the FOV of the PDD 900. A portion of the light from the light source 902 is reflected by an object in the FOV, captured by the photosites 100 in the light sensitive region 602 (which are exposed to external light upon operation of the light detection device 900), and used to generate an image or another model of the object. Any suitable type of light source may be used (e.g., pulsed, continuous, modulated, LED, laser). Optionally, operation of the light source 902 may be controlled by a controller (e.g., controller 338).

[0081] A physical barrier 904 for keeping a region 604 of the detector array dark. The physical barrier 904 may be part of the detector array or may be located outside of the detector array. The physical barrier 904 may be fixed or movable (e.g., a moving shutter). Note that other types of darkening mechanisms may also be used. Optionally, the physical barrier 904 (or other darkening mechanism) may darken different portions of the detector array at different times. Optionally, if configurable, the operation of the barrier 904 may be controlled by a controller (e.g., controller 338).

[0082] Ignored photosites 906. Note that not all photosites in the light detection array are necessarily used for detection (photosites 100) or for reference (photosites 310). For example, some photosites may be in areas that are not fully darkened and not fully illuminated, and therefore are ignored in generating an image (or other type of output generated in response to the detection signal of photosite 100). Optionally, different photosites may be ignored by the PDD 900 at different times.

[0083] At least one processor 908 for processing detection signals output by the photosite 100. Such processing may include, for example, signal processing, image processing, spectroscopic analysis, etc. Optionally, the results of the processing by the processor 908 may be used to modify the operation of the controller 338 (or another controller). Optionally, the controller 338 and the processor 908 may be embodied as a single processing unit. Optionally, the results of the processing by the processor 908 may be provided, for example, via a communication module 912, to any one or more of: (i) a tangible memory module 910 (for storage or later retrieval) for an external system (e.g., a remote server or a vehicle computer of the vehicle in which the PDD 900 is installed), (ii) a display 914 for displaying images or other types of results (e.g., graphs, spectroscopic text results), and (iii) other types of output interfaces (e.g., a speaker, not shown), etc. It should be noted that, optionally, signals from the photosites 310 may also be processed by the processor 908, for example, to assess the condition of the PDD 900 (eg, operability, temperature).

[0084] A memory module 910 that stores at least one of (i) the detection signals output by the active photosites or (e.g., if different) the detection signals output by the readout circuit 610, and (ii) the detection information generated by the processor 908 by processing the detection signals.

[0085] A power source 916 (e.g., a battery, an AC power adapter, a DC power adapter) that may provide power to the light source, amplifier, or other components of the light-detecting device.

[0086] A rigid casing 918 (or any other type of structural support).

[0087] Optics 920 for directing light from the light source 902 (if implemented) into the FOV and / or for directing light coming from the FOV into the active photosites 100. The optics may include, for example, lenses, mirrors (fixed or movable), prisms, filters, etc.

[0088] As described above, the photo-detecting device can be used to adjust the control voltage that determines the level of the current provided by at least one first voltage-controlled current circuit (VCCC) 104 to account for different operating conditions of the photo-detecting device. This can change the level of the dark current generated by at least one PD 102. For example, consider a photo-detecting device including a plurality of photosites 100 and a plurality of photosites 320. When the photo-detecting device operates at a first temperature, the control voltage generating circuit 340 provides a control voltage to the voltage-controlled current circuit to provide a current at a first level according to the dark current of the plurality of reference PDs 302. This can reduce the effect of the dark current of the active PD 102 on the output of the active photosite 100. On the other hand, when the photo-detecting device operates at a second temperature (higher than the first temperature), the control voltage generating circuit 340 provides a control voltage to the voltage-controlled current circuit to provide a current at a second level according to the dark current of the plurality of reference PDs 302. This reduces the effect of the dark current of the active PD 102 on the output of the active photosite 100. In this case, the magnitude of the second level is set to be greater than the magnitude of the first level.

[0089] 10 is a flow chart of a method 1000 for compensating dark current in a photodetector according to an example of the presently disclosed subject matter. The method 1000 is performed in a photodetector device including at least: (a) a plurality of active photosites, each including at least one active PD; (b) at least one reference photosite including a reference PD; (c) at least one first VCCC connected to the one or more active PDs; (d) at least one reference VCCC connected to the one or more reference PDs; and (e) a control voltage generation circuit connected to the active VCCC and the reference VCCC. For example, the method 1000 may be performed in any of the PDDs 300', 600, 600', 700, and 800 (the latter two implementations including multiple active photosites). It should be noted that the method 1000 may include performing any operation or function described with respect to any component of the various above-mentioned PDDs.

[0090] The method 1000 includes at least stages 1010 and 1020. Stage 1010 includes generating a control voltage based on the level(s) of the dark current of at least one reference PD. The control voltage generates a current in at least one reference VCCC that, when supplied to the at least one reference VCCC, reduces the effect of the dark current of the reference photodiode on the output of the reference photosites. Stage 1020 includes generating a current in at least one first VCCC that reduces the effect of the dark current of the active photodiode on the output of the plurality of active photosites by supplying a control voltage to the at least one first VCCC. VCCC is an abbreviation for "Voltage Controlled Current Circuit" and is implemented as a voltage controlled current source or a voltage controlled current sink.

[0091] Optionally, stage 1010 is implemented using an amplifier that is part of the control voltage generation circuit. In this case, stage 1010 includes providing a first input voltage to a first input of the amplifier, while a second input of the amplifier is electrically connected to a reference photodiode and a reference voltage control current circuit. The amplifier may be used to generate the control voltage by continuously decreasing the difference between the output of the reference voltage control circuit and the first input voltage. Optionally, both the first VCCC(s) and the reference VCCC(s) are connected to the output of the amplifier.

[0092] If the light detection device includes multiple different reference photodiodes generating different levels of dark current, stage 1010 may include generating a single control voltage based on averaging the different dark currents of the reference photodiodes.

[0093] The method 1000 may include preventing light from the field of view of the light detection device from reaching the reference photodiode (eg, using a physical barrier or bypass optics).

[0094] The method 1000 may include sampling the output of the active photosites after the effects of dark current have been reduced, and generating an image based on the sampled output.

[0095] FIG. 11 is a flow chart illustrating a method 1100 for compensating dark current in a photodetector device (PDD) according to an example of the presently disclosed subject matter. The method 1100 has two phases that are performed at different temperature regimes. A first group of stages (1110-1116) is performed when the PDD operates at a first temperature (T1). A second group of stages (1120-1126) is performed when the PDD operates at a second temperature (T2) that is higher than the first temperature. The degree to which the first and second temperatures differ may be different in different embodiments or examples of the method 1100. For example, the temperature difference may be at least 5° C., at least 10° C., at least 20° C., at least 40° C., at least 100° C., etc. Of note, the method 1100 may also be effective with even smaller temperature differences (e.g., less than 1° C.). It should be noted that each of the first and second temperatures may be embodied as a temperature range (e.g., a span of 0.1°C, 1°C, 5°C, or higher). Any temperature within the second temperature range (e.g., by the ranges described above) is higher than any temperature within the first temperature range. Optionally, method 1000 may be performed in any of the PDDs (300, 600, etc.) described above. It should be noted that method 1100 may include performing any operation or function described with respect to any component of the various PDDs described above. It should also be noted that the PDD for method 1100 may include any combination of components described with respect to any one or more of the PDDs described above.

[0096] The reference refers to stages executed when the PDD operates at a first temperature (which may be a first temperature range). Stage 1110 includes determining a first control voltage based on a dark current of at least one reference PD of the PDD. Stage 1112 includes generating a first dark current counter current at a first VCCC at the active photosite by providing a first control voltage to a first VCCC connected to at least one active PD of the active photosite of the PDD. Stage 1114 includes generating a first detection current by the active PD in response to (a) the incidence of light from an object in the field of view of the PDD on the active PD and (b) the dark current generated by the active PD. Stage 1116 includes compensating for the effect of the dark current on the first detection signal by outputting a first detection signal by the active photosite in response to the first detection current and a first dark current counter current (cancellation current), the first detection signal having a magnitude less than the first detection current. Method 1100 may include optional stage 1118 of generating at least one first image of the FOV of the PDD based on a plurality of first detection signals from a plurality of photosites (optionally all of the photosites) of the PDD. Stage 1118 may be performed while the PDD is at the first temperature, or may be performed at a later time.

[0097] The stages 1120 and 1122 refer to stages that are performed when the PDD operates at a second temperature (which may be a second temperature range). Stage 1120 includes determining a second control voltage based on a dark current of at least one reference PD of the PDD. Stage 1122 includes generating a second dark current counter current at the first VCCC in the active photosite by providing the second control voltage to the first VCCC. Stage 1124 includes generating a second detection current by the active PD in response to (a) the incidence of light from the object on the active PD and (b) the dark current generated by the active PD. Stage 1126 includes compensating for the effect of the dark current on the second detection signal by outputting a second detection signal by the active photosite in response to the second detection current and the second dark current counter current, the magnitude of the second detection signal being less than the second detection current. The magnitude of the second dark current counter current is greater than the magnitude of the first dark current counter current and may be any ratio greater than one. For example, the ratio may be at least two or significantly higher (e.g., one, two, three, or more orders of magnitude). Method 1100 may include an optional stage 1128 of generating at least one second image of the FOV of the PDD based on a plurality of second detection signals from a plurality of photosites (optionally all photosites) of the PDD. Stage 1128 may be performed when the PDD is at the second temperature or may be performed at a later time.

[0098] Optionally, a first level (L1) of radiation from the object incident on the active photodiode at a first time (t1) when the first dark current counter current occurs is approximately equal to a second level (L2) of radiation from the object incident on the active photodiode at a second time (t2) when the second dark current counter current occurs. In this case, the magnitude of the second detected signal is approximately equal to the magnitude of the first detected signal. Optionally, it is noted that a PDD according to the present disclosure may be used to detect a signal level that is significantly lower (e.g., one, two, or even less) than the level of dark current generated by the photodiode at a particular operating temperature. Thus, the method 1100 may be used to generate similar levels of output signals at two different temperatures where the dark current is two or more orders of magnitude higher than the detected signal and significantly different from each other (e.g., two times different, ten times different).

[0099] Optionally, the determination of the first control voltage and the determination of the second control voltage are performed by a control voltage generating circuit including at least one amplifier having an input electrically connected to (i) a reference photodiode and (ii) a reference voltage controlled current circuit connected to the reference photodiode.

[0100] Optionally, the method 1100 may further include providing a first input voltage to another input of the amplifier, the level of which is determined in response to a bias for the active photodiode. Optionally, the method 1100 may include providing the first input voltage such that the bias for the reference photodiode is approximately the same as the bias for the active photodiode. Optionally, the method 1100 may include determining the first control voltage and the second control voltage based on different dark currents of the reference photodiodes of the light-detecting device. Providing the first control voltage includes providing the same first control voltage to the multiple first voltage-controlled current circuits, where each of the multiple first voltage-controlled current circuits is connected to at least one active photodiode of the multiple active photodiodes of the light-detecting device having different dark currents. Providing the second control voltage includes providing the same second control voltage to the multiple first voltage-controlled current circuits when the multiple active photodiodes further have different dark currents.

[0101] Optionally, the different active photodiodes simultaneously produce different levels of dark current. And the different reference photodiodes simultaneously produce different levels of dark current. The control voltage generation circuitry provides the same control voltage to the different active photodiodes based on averaging the different dark currents of the second photodiodes. Optionally, method 1100 may include using a dedicated optical system to direct light from the field of view to the multiple active photodiodes of the light-detecting device and to prevent light from the field of view from reaching the multiple reference photodiodes of the light-detecting device.

[0102] The PDD is operated at a first temperature T1. In step 1010, a first control voltage VCTRL1 is determined based on the dark current of at least one reference PD of the PDD. In step 1020, VCTRL1 is supplied to a first voltage controlled current circuit (VCCC1) connected to at least one active PD of the PDD, thereby generating a first dark counter current DC1COUNTERING in VCCC1 to counter the dark current in the active photosite. In step 1030, the active PD generates a first detection current D1DETECTION in response to (i) the light emitted or reflected from an object in the PDD's FOV and incident on the active PD, and (ii) the dark current generated by the active PD. In step 1040, the active photosite outputs a first detection signal (the magnitude of the first detection signal is smaller than the magnitude of D1DETECTION) in response to D1DETECTION and DC1COUNTERING.

[0103] The PDD is operated at a second temperature T2 at least 10° C. higher than T1. In step 1050, a second control voltage VCTRL2 is determined based on the dark current of at least one reference PD of the PDD. In step 1060, VCTRL2 is provided to VCCC1 to generate a second dark counter current DC2COUNTERING in VCCC1 that counters the dark current in the active photosite. DC2COUNTERING is at least twice as large as DC1COUNTERING. In step 1070, the active PD generates a second detection current D2DETECTION in response to (i) the light emitted or reflected from objects in the PDD's FOV and incident on the active PD, and (ii) the dark current generated by the active PD. In step 1080, the active photosite outputs a second detection signal in response to D2DETECTION and DC2COUNTERING (the magnitude of the second detection signal is smaller than the magnitude of D2DETECTION).

[0104] 11 is a flow chart showing how a device such as device 300 can be used to calibrate / test the device. For example, the reference voltage of the reference circuit can be set to force very high currents (positive or negative) through all photosites. In this case, a very bright or very dark overall image can be forced (in a "real" sensing array) regardless of the ambient lighting (possibly in real-time operation, without the need to control the environment). This can be employed, for example, to periodically test individual photosites.

[0105] For example, a first current can be applied to the reference circuit, forcing the capacitance of all photosites 301 to fully charge and sampling the charge to determine whether one or more photosites are defective. Similarly, a second current can be applied to the reference circuit, forcing all "real" capacitors to fully discharge and sampling the charge to determine whether one or more photosites are defective.

[0106] FIG. 12 is a flow chart illustrating a method 1200 for testing a photodetector device according to an embodiment of the presently disclosed subject matter. For example, the testing may be performed by any of the photodetector devices described above. That is, the same circuits and architectures described above as useful for reducing the effects of dark current can additionally be used to test the detection paths of different photosites in real time. Optionally, the testing may be performed during periods when the PDD is in an operational mode (i.e., not in a test mode). In some implementations, some photosites may be tested (with or without compensation for dark current) during periods when they are exposed to ambient light from the FOV, even when other photosites of the same PDD are capturing actual images of the FOV. It is noted that, although the method 1200 may optionally be performed by other types of PDDs. It is also noted that the method 1200 may optionally be performed using similar circuits or architectures as those described with respect to the PDDs described above, but that the photodiodes may not have high dark currents and dark current reduction may not be required or performed. Although the method 1200 is described as being applied to a single photosite, it may also be applied to multiple photosites of a PDD, or to all of the multiple photosites.

[0107] Stage 1210 of method 1200 includes providing a first voltage to a first input of an amplifier of a control voltage generating circuit. A second input of the amplifier is connected to a reference photodiode and to a second current circuit providing a current at a level governed by the output voltage of the amplifier. This allows the amplifier to generate a first control voltage for a first current circuit of a photosite of a light-detecting device. With reference to the examples described with respect to the previous figures, the amplifier may be amplifier 318 or amplifier 718, and the photosite may be photosite 310 or photosite 310'. Examples of what first voltages may be provided to the first input are described below.

[0108] A stage 1220 of the method 1200 includes reading a first output signal of the photosite, the first output signal being generated by the photosite in response to a current produced by the first current circuit and a photodiode of the photosite.

[0109] A stage 1230 of the method 1200 includes causing the amplifier to produce a second control voltage for the first current path by providing a second voltage to a first input of the amplifier that is different from the first input of the amplifier. Examples of what second voltages may be provided are described below.

[0110] A stage 1240 of the method 1200 includes reading a second output signal of the photosite, the second output signal being generated by the photosite in response to the current produced by the first current circuit and the photodiode of the photosite.

[0111] A stage 1250 of the method 1200 includes determining a defect state of a detection path of the light-detecting device based on the first output signal and the second output signal. The detection path includes photosites and readout circuitry associated with the photosites. Examples of what types of defects may be detected using different combinations of the first and second voltages are described below.

[0112] A first example includes using at least one of the first and second voltages to attempt to saturate the photosite (e.g. by supplying a very high current by the VCCS to the capacitance of the photosite regardless of the actual detection level). Failure to saturate the photosite (e.g. receiving a detection signal that is not white - which may be completely black or halftone) indicates a problem with the associated photosite or with further components of its readout path (e.g. photosite amplifier, sampler, analog-to-digital converter, etc.). In such a case, the first voltage (for example) causes the amplifier to generate a control voltage. In this case, the first current circuit can saturate the photosite. Determining the fault condition at stage 1250 in such a case may include determining that the detection path of that photosite is malfunctioning in response to determining that the first output signal is not saturated. The second voltage in such a case may be a voltage that does not cause saturation of the photosite (which, for example, causes no current in the VCCS, compensates only for dark current, and prevents current from being collected by the capacitance). The test for whether the photosite detection path is saturated can be performed in real time.

[0113] When attempting to saturate one or more of the photosites to test the PDD, the method 1200 may include reading a first output signal during a period in which the photosite is exposed to ambient light in a first detection frame of the light detection device. The determination of the malfunction state is performed after previously determining that the detection path is operable in response to reading a saturation output signal in a second detection frame that is earlier (previous) than the first frame. For example, during operation of the PDD (e.g., during video capture), a photosite may be determined to be faulty if a saturation attempt fails after a successful saturation attempt at a previous time in the same operation. Testing may be performed in test frames that are not part of the video, or may be performed on individual photosites whose saturation output is ignored (e.g., pixel colors corresponding to these photosites may be interpolated from adjacent pixels in the frames in which these photosites are tested, and these photosites are treated as unavailable for this span of frames).

[0114] A second example includes using at least one of the first and second voltages to attempt to deplete the photosite (e.g. by supplying a very high counter current to the capacitance of the photosite, regardless of the actual detection level, by the VCCS). Failure to deplete the photosite (e.g. receiving a non-black detection signal - which may be completely white or half-tone) indicates a problem with the associated photosite, or with further components of its readout path. In such a case, the second voltage (for example) causes the amplifier to generate a second control voltage. In this case, the first current circuit may be caused to deplete the detection signal resulting from the field light incident on the photosite. Determining the fault condition at stage 1250 in such a case may include determining that the detection path is malfunctioning in response to determining that the second output signal is not depleted. The first voltage in such a case may be a voltage that does not cause saturation of the photosite (which may, for example, cause the VCCS to generate a current to compensate only for the dark current and saturate the capacitance). Testing whether a photosite's detection pathway is exhausted can be performed in real-time (eg, without darkening each photosite).

[0115] When attempting to deplete one or more photosites to test the PDD, the method 1200 may include reading the second output signal during a period when the photosites are exposed to ambient light in a third detection frame of the light detection device, the determination of the malfunction condition being performed after previously determining that the detection path is operational in response to reading a depleted output signal in a fourth detection frame that is earlier than the third frame.

[0116] Yet another example of using method 1200 to test photosites using application of multiple control voltages includes applying more than two voltages. For example, three or more different voltages may be applied to the first input of the amplifier at different times (e.g., in different frames). In such a case, stage 1250 may include determining a defect state of the detection path of the PDD based on the first output signal, the second output signal, and at least one other output signal corresponding to the three or more voltages applied to the first input of the amplifier. For example, three, four, or more different voltages may be applied to the first input of the amplifier at different times (e.g., each voltage is monotonically greater than the previous voltage). Output signals of the same photosite corresponding to different voltages may be tested to correspond to the voltages applied (e.g., the output signals also monotonically increase in magnitude).

[0117] An example of using method 1200 to test a portion (or possibly all) of a PDD includes: (i) reading at least two output signals from each of a plurality of photosites of the PDD in response to at least two different voltages supplied to an amplifier of each photosite; (ii) determining an operational status for at least one first detection path based on the at least two output signals output by at least one photosite associated with the respective first detection path; and (iii) determining a malfunctioning status for at least one second detection path based on the at least two output signals output by at least one other photosite associated with the respective second detection path.

[0118] Optionally, but not required, method 1200 may be performed in conjunction with a designated test target (e.g., black target, white target) when the PDD is shielded from ambient light and / or when using designated lighting (e.g., dedicated interior lighting of known size, etc.).

[0119] Optionally, stage 1250 may be replaced by a determination of the operating state of the detection path. This may be employed, for example, to calibrate different photosites of a PDD to the same level. For example, when the PDD is darkened and there is no dedicated target or dedicated lighting, the same voltages may be supplied to the VCCS of the different photosites. The different output signals of the different photosites may be compared to each other (at one or more different voltages supplied to the first input of the amplifier). Based on the comparison, correction values ​​may be assigned to the detection paths of the different photosites. The correction values ​​may result in similar output signals for similar lighting levels (simulated by the currents contained by the VCCS of the different photosites). For example, it may be determined that the output of photosite A should be multiplied by 1.1 to output a calibrated output signal to photosite B. For example, it may be determined that a delta signal ΔS should be added to the output of photosite C to output a calibrated output signal to photosite D.

[0120] This (and similar) technique can be used for calibration and testing. This means that the same cathode voltage is supplied to both photodiodes in both the operational (i.e., light detection) mode and other modes (e.g., calibration mode and / or test mode, described below). The operating bias (in the operational mode) is a particular value of the first input voltage VFI. Examples of test methods include the following examples:

[0121] Example 1: (a) change the first input voltage VFI / Vy to different values, (b) check if each photosite always receives a different output level, (c) test the readout circuit / readout path.

[0122] Example 2: Check for bad photosites: (a) change the first input voltage VFI / Vy to very high / very low, (b) check which photosites remain unchanged / sufficiently black / white.

[0123] <Section II - Photosite Readout Circuit Architecture to Prevent Charge Aggregation During Idle Periods> The embodiments described in this section are directed to the operation and architecture of a photosite that collects light from an environment, particularly reflected light of a pulsed light source. For example, such a photosite may be used to capture an image of an environment by illuminating an object with an illumination pulse generated by a light source, similar to the method described in section I above with respect to the electro-optical system of FIG. 9. The illumination pulse is reflected by one or more objects in the environment, and the reflected light is incident on one or more photodiodes of the photosite. This causes a photodiode-generated current to be generated by each photodiode. The illumination pulse may be timed or otherwise synchronized with what are referred to herein as detection windows, readout windows, or sampling windows. The windows may be a series of sampling windows that exist within a larger sampling period, such as an imaging frame. Thus, a photodiode-generated current is generated during each of the aforementioned sampling windows. As a result, the charge stored on the capacitor(s) identified by one or more photosite readout circuits is measured during these sampling windows. Alternatively, the charge may be measured at the end of the larger sampling period, as described in more detail below.

[0124] As described in more detail below, the electro-optical system and / or the imaging sensor may comprise one or more photosite readout circuits. Each photosite readout circuit is implemented with an amplifier and one or more capacitors forming part of the amplifier feedback path. Optionally, the collection of the charge generated by one or more photodiodes may be aided by the parasitic capacitance of other components of the photosite. It should be noted that wherever a capacitor is mentioned below, the parasitic capacitance may be used for charge collection as well. The amplifier is connected to the photodiode such that, during operation of the photosite, the amplifier outputs an electrical signal representative of the integration or accumulation of charge on the capacitor due to the photodiode generated current. Thus, the electrical signal in each frame indicates the amount of light captured by the photosite readout circuit in the respective frame (i.e., over each of a series of multiple sampling windows of that frame). From this overview of operation, it is clear that the accumulation of charge during idle periods (i.e., between multiple sampling windows in each frame) may lead to an erroneous accumulation of charge. As a result, the electrical signal may erroneously indicate the amount of light captured by the photosite readout circuit in each frame. This can lead to saturation of the photosite capacitance, or other deleterious consequences.The architecture and operation of the photosite readout circuitry described in this section is intended to address such problems.

[0125] FIG. 13 illustrates an exemplary photosite readout circuit architecture according to an embodiment of the present disclosure. The photosite readout circuit 1301 illustrated in FIG. 13 together with a connected photodiode 1308 form what is referred to as a "photosite" 1300 throughout this section. FIG. 13 and many of the following examples are examples of a photosite including a single photodiode. However, it should be noted that, optionally, the photosite 1300 may include multiple photodiodes 1308 read out by a single photosite readout circuit 1301. Any place in the following description that relates to a photosite readout circuit 1301 connected to a single photodiode 1308, the photosite readout circuit may also be connected to read out multiple photodiodes 1808, even if not explicitly stated. In such a case, the different photodiodes 1308 may be read out in parallel (i.e., simultaneously), at different times (e.g., in different sampling windows), or in any other suitable manner by a single photosite readout circuit 1301. The photosite 1300 may be implemented as part of an imaging sensor and / or electro-optical system as described herein and may belong to any suitable number of photosites. By way of example, the sensor may be part of a camera, a Lidar sensor, a spectrometer, etc. In various embodiments, different photosite readout circuits 1301 may share one or more photodiodes 1308. Alternatively, each of the various photosite readout circuits 1301 may be identified as a dedicated photodiode 1308.

[0126] Further, in various embodiments, the photodiode 1308 may be integrated as part of the photosite readout circuitry 1301 (e.g., on the same wafer, silicon, chip, etc.) or may be integrated as a separate component (e.g., on a separate wafer, silicon, chip, etc.). In any case, the photodiode 1308 is configured to produce a photodiode-generated current in response to the incidence of light of a particular wavelength or range of wavelengths. This may depend on the particular implementation of the imaging sensor and / or electro-optical system of which the photosite 1300 forms a part. For example, as discussed above, the incident light may be identified as illumination pulses reflected from various objects in the environment. Thus, for example, the photodiode 1308 may produce a photodiode-generated current in response to incident light having a wavelength identified as short-wave infrared (SWIR). SWIR is typically considered to be in the wavelength range of 0.9-1.7 μm, but may also be classified as 0.7-2.5 μm. However, these wavelengths are provided by way of example only, and the embodiments described herein are not limited to operation within these particular wavelength ranges.

[0127] The photosite readout circuit 1301 includes an amplifier 1302. The amplifier 1302 includes two input terminals 1304 and 1306 and an output terminal 1307. The amplifier 1302 may be implemented as any suitable type of amplifier, such as an operational amplifier. Additional connections such as power supply pins and rails are not shown for simplicity. However, the amplifier 1302 may utilize power supply rails of any suitable voltage or voltage range depending on the particular application. As shown in FIG. 13, one input terminal of the amplifier 1302 is connected to a photodiode 1308 at point A to which one or more photodiodes 1308 may be connected. This input terminal therefore represents a photodiode signal input 1304. The other input terminal of the amplifier 1302 is connected to a reference signal at point B to which a source providing the reference signal (e.g., as described below) may be connected. This input terminal therefore represents a reference signal input 1306. The output terminal of the amplifier 1302 is identified as an amplifier output 1307. As will be explained in more detail below, the output terminal is connected to two separate, selectively connected feedback paths.

[0128] Thus, the amplifier 1302 is configured to receive at the photodiode signal input 1304 a signal generated by the photodiode 1308. As described herein, in this example, the signal may represent a photodiode-generated current generated in response to light of a particular wavelength incident on the photodiode 1308. The signal may also include additional components, such as a dark current generated by the photodiode 1308 during a sampling window. The amplifier 1302 is also configured to receive a reference signal generated by an external reference signal source. The reference signal may be a voltage reference or a current reference. Thus, the reference signal represents either a current level or a voltage level maintained by the reference signal source. In some cases, the reference voltage or reference current is used to bias the photosite readout circuit 1301 by bringing the transistors specified for the amplifier 1302 to an operating point. Furthermore, regardless of whether the reference signal is a reference voltage level or a reference current level, the reference signal causes a reference voltage level to be formed at point B of the photosite readout circuit 1301. The reference voltage level is also generated at point A by a virtual short between the input terminals of amplifier 1302. As shown in Fig. 13, the reference voltage level at point A of photosite readout circuit 1301 generates a bias for photodiode 1308 by connection of photodiode signal input 1304. For example, any of the above-mentioned methods for providing a reference signal (e.g., using one or more reference photosites) may be employed to provide a reference signal to amplifier 1302.

[0129] The reference signal may be generated by any suitable method. The reference signal may be determined by a controller (which may be integrated as part of the photosite readout circuitry 1301, similar to the photodiode 1308, or may be located externally). The controller may optionally vary the amplitude of the reference signal for different sampling windows and / or for larger sampling periods (e.g., per frame) depending on the operating conditions (e.g., ambient light levels, temperature, etc.). The controller controlling the reference signal level may be identified, for example, as controller 338. As described above in section I, the reference signal may be identified as the output of the reference photosite 310. Alternatively, as described in more detail in this section, the controller may be identified as controller 1602. The reference signal may be generated by any suitable reference source (e.g., a reference signal generating source). Such reference sources include known techniques for generating reference signals.

[0130] Regardless of how the reference signal is generated and regardless of whether the reference signal represents a reference current or a reference voltage, the amplifier 1302 can provide an output voltage proportional to the integral of the input voltage. For example, as described above in this section, the photodiode-generated current results in the accumulation of charge on the capacitor 1314 in each sampling window. This charge is converted to a voltage across the two terminals of the capacitor 1314. Thus, as described in more detail below in this section, at the end of a particular accumulated sampling period (e.g., a frame), which may include a series of multiple sampling windows, the voltage at point C is read out via a readout circuit.

[0131] In FIG. 13, for the sake of simplicity, the readout circuit is not shown. However, the readout circuit may be integrated as part of the photosite readout circuit 1301 or may be located external to the photosite readout circuit 1301. The readout circuit may be implemented, for example, as the readout circuit 610 described above in Section I. Alternatively, as described in more detail in this section, the readout circuit may be implemented as any suitable component configured to perform these functions, including known techniques of readout circuit implementation (e.g., readout circuit 1650 described in more detail below with reference to FIG. 16). Thus, the photosite readout circuit 1301 described herein may include both the amplifier 1302 and associated interconnects and components. These components function to generate a voltage or another electrical signal indicative of the amount of light captured by the photosite readout circuit 1301 in one or more sampling windows. As described in more detail throughout this section, the photosite readout circuit 1301 may include additional circuit components identified as readout circuits that function to actually measure or read out the voltage generated in one or more sampling windows. As described in more detail below, the number of sampling windows, which are periods over which charge is cumulatively collected for readout, may be determined by resetting the charge in capacitor 1314 prior to the first sampling window (initial sampling window) in the sequence of sampling windows for readout.

[0132] As shown in FIG. 13, in order to perform measurements of the generated voltage while reducing or eliminating the contribution of the photodiode generated current in the idle time window, the photosite readout circuit 1301 may use two separate feedback paths to the amplifier 1302. Each of these feedback paths is selectively connected or disconnected via the connected switching components 1310, 1312. Different combinations of the states of the switching components 1301, 1312 result in different respective switching states and corresponding operating phases. As will be described in more detail below, this use of two separate selectively connected feedback paths ensures that the capacitor 1314 retains charge during off or idle periods while maintaining the photodiode 1308 at a specified bias. In this way, the accumulation of ambient or dark current due to the parasitic capacitance of the photodiode 1308 can be prevented. The output of the amplifier 1302 can also be maintained at the operating point of the amplifier.

[0133] For example, a first feedback path may include a switching component 1310 and a connection located between the photodiode signal input 1304 and the amplifier output 1307. A second feedback path may include a switching component 1312, a capacitor 1314, and a connection located between the photodiode signal input 1304 and the amplifier output 1307. Note that while capacitor 1314 is illustrated as a single component, this is by way of example and not limitation. Note that capacitor 1314 may represent the equivalent capacitance of any suitable number and / or configuration of capacitors depending on the desired implementation.

[0134] Each of the switching components 1310, 1312 may be implemented as any suitable number and / or type of electronically controlled switches, such as field effect transistors or any suitable type of transistor. As such, the switching components 1310, 1312 may be alternatively referred to herein as the “reset switch 1310” and the “integration switch 1312”, respectively, and may also be referred to as “switches”. Thus, as described in further detail in this section, the states of the switching components 1310, 1312 may be electronically controlled by a controller. In this manner, the first switching component 1310 is configured to selectively connect or disconnect a first feedback path that directly connects the photodiode signal input 1304 and the amplifier output 1307 to each other. The second switching component 1312 is configured to selectively connect or disconnect a second feedback path that connects the photodiode signal input 1304 and the amplifier output 1307 to each other via the capacitor 1314.

[0135] In this example, the photosite 1300 also operates by detecting light incident on the photodiode 1308. The light is converted into a measured voltage across the capacitor 1314 as a result of accumulated charge. Each frame (or other suitable sampling period) may include a series of sampling windows, each of which may be synchronized with the reception of a light pulse at the photodiode 1308. These sampling windows may also be referred to herein as detection windows. During the light collection operation of the photosite 1300 (alternatively referred to herein as the "integration phase"), charge is accumulated on the capacitor 1314 according to the photodiode-generated current in each detection window. However, the time between each detection window (e.g., the time during which an emitted light pulse reflected from an object within a predetermined detection range originating from the photosite is not expected to be received at the photodiode 1308) is considered an idle period. Ideally, during the idle period, the photodiode generated current should not contribute to further accumulation of charge on the capacitor 1314, and the accumulated charge should be maintained and not decreased. In this case, the voltage accumulated on the capacitor 1314 accurately represents the amount of light captured by the photosite readout circuit 1301 in each of a set of sampling windows corresponding to a desired incident light pulse. The sampling windows may also be specified as a single frame or other suitable sampling period. The voltage accumulated in the detection window may also represent dark current and noise collected throughout the detection window. However, it is possible to at least partially mitigate such charge collection, for example as described above with respect to the light detection device 300.

[0136] As described in more detail below, this goal is better achieved by synchronizing the specific switching states and respective operational phases of the photosite readout circuit 1301 to a schedule of detection windows. As shown in each of Figures 14A-14D, each switching state represents a unique switching state. As shown in Figures 14A-14D, each switching state represents a unique combination of the respective conductivity states of the switching components 1310, 1312 (e.g., binary conductivity states of "on" or "close" vs. "off" or "open"). As described herein, the transitions between the different conductivity states of the switching components 1310, 1312 may be controlled by a controller.

[0137] For example, as shown in FIG. 14A, one of these operation phases is identified as a reset phase of the photosite readout circuit 1301. In the reset phase, the photosite readout circuit 1301 is in a reset switching state. The reset switching state shown in FIG. 14A corresponds to each of the switching components 1310, 1312 being closed or shorted. In the reset phase, the capacitor 1314 is discharged through the first feedback path. Thus, the output voltage at point C is initialized or reset to a predetermined reset voltage value. This predetermined reset voltage value may be any suitable predetermined voltage value, such as, for example, 0 volts. As another example, the predetermined reset voltage value may be a reference voltage provided by a reference signal at the reference signal input 1306. If the reference signal represents a current value, the predetermined reset voltage value may be a function of the reference current and / or may be proportional to the reference current.

[0138] In other words, the reset phase of operation is applied before (and optionally after) a particular sampling period. The reset phase serves to fully discharge the capacitor 1314 such that a predetermined reset voltage value is provided by the amplifier 1302 at point A according to a reference signal provided to the other input of the amplifier 1302. The reference signal may represent a reference voltage or current (e.g., constant, predetermined, or controllably varied). As described herein (e.g., with respect to the photodetector device 300), the reference signal may be optionally set by the controller. During the reset phase, any photodiode-generated current provided by the photodiode 1308 is compensated by the amplifier 1302 such that the voltage at point A is maintained (e.g., according to the reference signal).

[0139] Reference is now made to FIG. 15. FIG. 15 illustrates an example of operational phases in a sampling period including multiple detection windows according to an embodiment of the present disclosure. In FIG. 15, a reset phase is shown to be used at the beginning of a sampling period (e.g., a frame). Thus, the example sampling period illustrated in FIG. 15 may represent a single frame as described herein. The frame in the example of FIG. 15 includes three sampling windows for simplicity. However, it should be noted that depending on the particular application, a frame may include any suitable number of sampling windows, either less than three or more (e.g., 2-10, on the order of tens, or on the order of hundreds, etc.).

[0140] The sampling period depicted in FIG. 15 shows three graphs overlaying each operational phase and the associated charge accumulated on the capacitor over multiple sampling windows, according to embodiments described herein. With reference to FIG. 15, when the graph is in a high position (e.g., in response to a logic high value of the associated control signal), it is assumed that the switching components 1310, 1312 are set to an "on" (also referred to as "closed" or "conductive") state. Furthermore, when the graph is in a low position (e.g., in response to a logic low value of the associated control signal), it is assumed that the switching components 1310, 1312 are set to an "off" (also referred to as "open" or "non-conductive") state. Thus, the top two graphs represent the logic values ​​of the control signals for each of the switching components 1310 (middle graph) and 1312 (top graph) over time during the sampling period. Meanwhile, the bottom graph shows the accumulation of voltage on the capacitor 1314 over time during the sampling period.

[0141] Thus, as shown in FIG. 15, before the photosite readout circuit 1301 performs sampling or measurement in the sampling period, an initial reset phase first resets the voltage at point A to a predetermined reset voltage value. The subsequent sequential operation phase after the reset phase is shown in FIG. 14B. In the example of FIG. 14B, the photosite readout circuit 1301 is set to an integration switching state. It should be noted that, optionally, the photosite readout circuit 1301 may be switched to a transition phase between the reset phase and the integration phase. However, this is not necessarily the case. The integration switching state shown in FIG. 14B corresponds to (i) the switching component 1310 being open, thereby blocking the first feedback path located between the photodiode signal input 1304 and the amplifier output 1307, and (ii) the switching component 1312 being closed or shorted, thereby connecting the second feedback path located between the photodiode signal input 1304 and the amplifier output 1307 via the capacitor 1314. In this integration phase, setting the first and second feedback paths in the integration switching state results in a build-up of voltage on capacitor 1314 .

[0142] FIG. 15 illustrates multiple integration phases, each of which corresponds to (e.g., is synchronized with) a different detection window within the sampling period. In each detection window, charge is collected in the capacitor 1314 as a result of the photodiode-generated current of the photodiode 1308. Again, in this example, each detection window may be synchronized with a period during which any suitable number of light pulses generated by the light source described herein are received by the photodiode 1308 (i.e., the light pulses are incident on the photodiode 1308). Although the integration phases and corresponding detection windows are referred to herein with respect to the reception of a single light pulse at the photodiode 1308, this is by way of example and not limitation. The integration phases and corresponding detection windows may represent any suitable number of light pulses (e.g., a condensed train of pulses emitted together within a short time span, the pulses being shorter than the intended detection range of the system (e.g., 200 meters)) incident on the respective photodiode 1308. Thus, as described herein, each integration phase is considered to be a "light gathering" mode of operation of the photosite readout circuit 1301. As described herein, the integration time, i.e., detection window time, of each light pulse may be determined by the controller. Thus, for example, the controller may use a priori knowledge of the timing of the source light pulse and the range of distances that are of interest to be captured depending on the particular implementation (e.g., from 10m to 100m) to thus synchronize the integration phases of the photosite readout circuit 1301 based on a trigger signal that initiates light emission, or the like.

[0143] In Fig. 14C, the next sequential operation phase after the integration phase is shown. In the example of Fig. 14C, the photosite readout circuit 1301 is set to a transition switching state. The transition switching state shown in Fig. 14C corresponds to both switching components 1310, 1312 being open, thereby (i) blocking the first feedback path located between the photodiode signal input 1304 and the amplifier output 1307, and (ii) blocking the second feedback path located between the photodiode signal input 1304 and the amplifier output 1307 via the capacitor 1314. As shown in Fig. 15, a transition phase may be used between the integration phase and the hold phase and / or between the hold phase and the integration phase. This prevents both feedback paths from being on at the same time. As a result, the accumulated charge on the capacitor 1314 is prevented from being discharged through the first feedback path when not desired (i.e., the undesired occurrence of a reset switching state is prevented). The hold phase is so named because the accumulated charge on the capacitor 1314 is held (i.e., maintained) during this period. Note that this period may therefore be used as a hold period between adjacent detection windows, as illustrated by the first two hold phases in the example of FIG. 15. However, a period identified as a hold phase may also be identified as a readout phase in which a readout circuit reads out the voltage value of the capacitor 1314, as illustrated by the last hold phase in the example of FIG. 15. Thus, as described herein, a hold phase may be identified by either a maintain operation (i.e., a hold operation) or a readout operation.

[0144] In Fig. 14D, the next sequential operation phase of the transition phase is shown. In the example of Fig. 14D, the photosite readout circuit 1301 is set to a hold switching state. The hold switching state shown in Fig. 14D corresponds to (i) switching component 1310 being closed, thereby connecting a first feedback path located between the photodiode signal input 1304 and the amplifier output 1307, and (ii) switching component 1312 being open, thereby blocking a second feedback path located between the photodiode signal input 1304 and the amplifier output 1307 via the capacitor 1314. As shown in Fig. 15, the hold phase is also used during the adjacent integration phase to hold or maintain the integrated charge on the capacitor 1314 so that the readout circuit can read out the voltage value. It should be noted that the voltage value thus read out may alternatively be referred to as the detection signal. Furthermore, it should be noted that the transition phases between the integrate and hold phases and / or between the hold and integrate phases may, but need not, be very short in time (e.g., from 1 nanosecond to 1 microsecond) depending on the toggle speed capabilities of the particular system in which the photosite readout circuit 1301 is implemented.

[0145] The configuration of switching components 1310, 1312 shown for the hold phase in Fig. 14D ensures that the accumulated charge on capacitor 1314 is maintained. An approximately constant voltage on photodiode 1308 (assuming that the voltage on the other terminal of photodiode 1308 is kept constant or synchronized to the change in the reference signal supplied to amplifier 1302) is realized by amplifier 1302 as a result of the first feedback path, i.e., the direct connection between photodiode signal input 1304 and amplifier output 1307. The voltage at point A is held approximately constant during the hold phase (due to the operation of amplifier 1302 based on the approximately constant reference signal during that period). Thus, the voltage at the terminal (e.g. "plate") of capacitor 1314 connected to photodiode 1308 is also held constant, even though photodiode 1308 continues to emit a current (e.g. "dark current" due to ambient light incident on photodiode 1308, etc.). 14D ensures that any additional undesired current emitted by the photodiode 1308 does not contribute to further accumulation of charge on the capacitor 1314, since the voltage on the capacitor 1314 is either read out or simply maintained until the next detection window.

[0146] In this example too, the voltage on the capacitor 1314 may be collected (e.g. read out) by the photosite readout circuitry over a series of detection windows. In such a case, as shown in FIG. 15, the hold phase serves to maintain the voltage on the capacitor 1314 during each of the series of detection windows. As a result, the next integration phase results in further accumulation or integration of the voltage on the capacitor 1314. In this way, the setting of the first and second feedback paths in the hold switching state serves to simultaneously maintain a predetermined or constant voltage or current bias (e.g. zero bias, reverse bias, etc.) on the photodiode 1308. As a result, ambient or dark currents can be prevented from accumulating on the parasitic capacitance of the diode. In this example too, this is a result of the use of a reference signal as described above. In this example too, the use of a reference signal can generate a reference voltage or reference current at the reference signal input 1306 of the amplifier 1302. Thus, at the same time, the setting of the hold switching state maintains the output of the amplifier 1302 at its operating point, e.g. a predetermined voltage or current reference value. As described herein, the voltage or current reference value is set by the controller using a reference signal.

[0147] If the voltage on the capacitor 1314 is read out in a hold phase identified by the end of a larger sampling period (e.g., a frame), the photosite readout circuit 1301 can operate according to another reset phase to start sampling in the next series of frames. The voltage on the capacitor 1314 may be read out in the hold phase at the end of a frame. Alternatively, optionally, the voltage may be read out both before and after the reset phase at the end of a frame. For example, at the end of a particular frame, the voltage on the capacitor 1314 may be first read out in the hold phase shown in FIG. 14D to obtain a first voltage value. The first voltage value may be used as the detection signal for that particular frame. However, optionally, the voltage on the capacitor 1314 may also be read out in a reset phase shown in FIG. 14A (which may occur after other phases such as a transition phase) to obtain a second voltage value, e.g., 0 volts or a predetermined reference voltage value as described herein. According to such operation, the difference between these two signals (i.e., the first voltage measured before the reset phase and the second voltage measured after draining the capacitor 1314) indicates the amount of light captured by the photodiode 1308 in the associated frame.

[0148] Table 1 below outlines each switching state of the photosite readout circuit 1301 and the corresponding phase of operation. [Table 1]

[0149] To give various examples, the duration of each cycle (e.g., the period between two readouts of the photosite readout circuit 1301), as well as the duration of any of the above-mentioned phases shown in Table 1 and described in further detail herein, may be any suitable duration depending on the particular application. For example, the period between each cycle may be from 0.01 seconds to 0.1 seconds (which may correspond to 10 to 100 frames per second, respectively). As another example, the integration phase duration (e.g., per pulse) may be from 0.1 microseconds to 2.0 microseconds (e.g., depending on the desired detection range). As yet another example, the transition phase duration may be from 1 nanosecond to 1,000 nanoseconds (e.g., depending on the switching technique). As yet another example, the hold phase duration may be from 1 microsecond to 100 milliseconds (e.g., depending on the desired number of pulses, the laser emission frequency, FOV illumination considerations (e.g., whether the entire FOV is illuminated simultaneously or partially illuminated), etc.). As an additional example, the duration of the reset phase may be any suitable duration depending on the particular frame rate, application, and duration of each of the cycles discussed above (e.g., 100 nanoseconds to 100 microseconds). Of course, any of the exemplary durations of each operational phase of the photosite readout circuit 1301 shown in Table 1 and described herein may be shorter or longer depending on the particular application, technology implemented, etc.

[0150] It should be noted that the accumulated voltage may be read out during any one of the hold phases shown in FIG. 15, which correspond to the hold switching states shown in FIG. 14D. Again, the sampling periods shown in FIG. 15 may represent sampling or detection windows identified as frames of the image sensor. The image sensor may operate over a series of frames. Alternatively, charge may be read out from the photosite according to a timing that is not related to the transition between frames (e.g., twice per frame, or with a different frequency than adjacent photosites, if present). Thus, the final hold phase shown in FIG. 15 may be used to read out the sum of the voltage accumulated over the sampling windows. Then, before performing sampling in the next frame, the photosite readout circuit 1301 may be set to a reset switching state (not shown in FIG. 15) to reset the value of the voltage accumulated on the capacitor 1314 to zero or other predetermined voltage value, as described above. Optionally, the voltage on the capacitor 1314 may be read out again during this reset switching state. In this manner, the imaging sensor of which the photosite 1300 forms a part is configured to accumulate a voltage on the capacitor 1314 in each of a set of successive frames by sequentially operating through a reset switching state, an integrate state, a transition state, and a readout state, as shown in FIG.

[0151] It should further be noted that the voltage on capacitor 1314 may alternatively or additionally be read out during other operational phases (i.e., switching states) of photosite readout circuit 1301. For example, as indicated by the "potential readout" label in Figure 15, the voltage on capacitor 1314 may be read out during an integration phase in addition to or instead of during the hold phase described above. This may be particularly useful, for example, during development, testing, calibration, etc., to assess the charge accumulated on capacitor 1314 over a particular time within a particular detection window.

[0152] FIG. 16 illustrates an electro-optical system according to an embodiment of the present disclosure. The electro-optical system 1600 may employ any combination of configurations derived from any one or more of the light detection devices described above with reference to Section I. Additionally or alternatively, the electro-optical system 1600 may include any suitable number of photosites 1300 (e.g., 1, 2-10, 10-100, 100-10,000, 10,000-1,000,000, 1M-10M, etc.) as described herein. The photosites may be collectively operated as an imaging sensor 1601 employed by the electro-optical system 1600 to perform imaging according to any suitable wavelength type. In an embodiment, the imaging sensor 1601 is configured to detect light incident on one or more photodiodes 1308 according to a SWIR imaging sensor. Such imaging systems can output images of objects within their field of view (e.g., SWIR images), three-dimensional (3D) mapping of objects within their FOV (e.g., LIDAR maps, SWIR LIDAR maps), and the like.

[0153] For example, the imaging sensor 1601 may include any suitable number of photosites 1300. Each of the photosites 1300 includes a photosite readout circuit similar or identical to the photosite readout circuit 1301 shown in FIG. 13. Thus, the imaging sensor 1601 may include any suitable number N of photosites, which are described in this section and identified as the photosites 1300 shown in FIG. 13. Of course, each of the photosites 1300, the photosite readout circuit 1301, and the photodetector 1308 shown in FIG. 16 may include separate or integrated components. Thus, the imaging sensor 1601 may be identified as a detector array, each of which includes the photosites 1300 described in this section. Additionally, the detector array may include other photosites that are not shown in FIG. 16 for simplicity. For example, the detector array, which is identified as the imaging sensor 1601, may include any suitable number of photosites 1300. Additionally, the detection array may include any suitable number of reference photosites that are maintained in a dark state at least part of the time during operation, such as the reference photosites 310 identified by region 604 described above with reference to FIG. 9 in Section I. The reference photosites may, but do not necessarily, include the photosite readout circuitry 1301 (e.g., to demonstrate a compensation response to dark current). Optionally, the imaging sensor 1601 may include both (i) the photosites 1300 and (ii) other types of photosites that do not include the two feedback paths described with respect to the photosite readout circuitry 1301.

[0154] Thus, the imaging sensor 1601 may be specified by any suitable number of pixels. Each pixel corresponds to at least one (and possibly more) of the photosites 1300. Furthermore, a single photosite 1300 may include multiple photodiodes 1308. These photodiodes 1308 may be of the same type or different types. Thus, a photosite may be considered as the basic unit from which a "pixel value" is read out during each sampling period (e.g., frame). However, a pixel may include multiple photodiodes 1308. Thus, there is not necessarily a 1:1 relationship between photodiodes 1300 and pixels. As an example (e.g., in low light conditions), an image pixel may be based on the output of two, four, etc. adjacent photosites 1300. This technique of grouping multiple adjacent photosites in this way is known as "binning." Thus, the output of each photosite 1300 may represent the light incident on any suitable number of corresponding photodiodes. The output of each of the photosites 1300 used by the imaging sensor 1601 may be read individually (eg, in different frames) or may be combined in any suitable manner.

[0155] For example, although not shown in FIG. 16 for simplicity, the electro-optical system 1600 may comprise any of the components and / or functions of the PDD 900 or other embodiments described in Section I above. For example, the reference signal described herein with reference to FIG. 13 may be generated and / or determined in response to a reference photosite electrical signal output by a reference photosite of a detection array to which the photodiode 1308 belongs, the reference photosite being shielded from ambient light. The reference signal may be generated for each of the photosite readout circuits 1301 at any suitable time (e.g., each frame) using a reference signal received from one of a plurality of reference photosites, each connected or otherwise assigned, as described above in Section I. The reference signal generated by the reference photosite may be adjusted for any suitable period of time based on any suitable condition, such as temperature or other operating conditions. For example, the reference signal generated by the reference photosite may be maintained at a constant value during some periods of time (e.g., each detection window within a frame) but adjusted during other periods of time (e.g., between successive frames). As a result, the magnitude (eg, current or voltage value) of the reference signal may be varied between two or more successive frames or other suitable sampling periods.

[0156] The electro-optical system 1600 may further include a light source 1604 configured to emit light into a field of view (FoV) of the electro-optical system 1600. A portion of the light of the light source 1604 is reflected by objects in the FoV and captured by the photosites 1300, which are exposed to external light during operation of the electro-optical system 1600. The electro-optical system 1600 uses the light thus detected by the imaging sensor 1601 to generate an image or another model of the object. The light source 1604 may be implemented as any suitable type of light source (e.g., a pulsed light source, a continuous light source, a modulated light source, an LED, a laser, etc.). The operation of the light source 1604 may be controlled by a controller 1602, which may be implemented as the controller 338 described above in Section I herein or any suitable type of controller described in more detail below.

[0157] As discussed herein, the controller 1602 may further control each of the photosites 1300. This includes controlling the amplifier 1302, the voltage and / or current provided as a reference signal to the amplifier 1302, the switching states of the switching components 1310, 1302, etc. The controller 1602 may further control the operation of any suitable components of the electro-optical system 1600. The controller 1602 may be implemented, for example, as any suitable type of controller device, microcontroller, processing circuit, processor, hardware component, executable instructions, or combinations thereof. To provide an additional example, the controller 1602 may be implemented as one or more processors fabricated on the same wafer as the electro-optical system 1600 and / or other components of the imaging sensor 1601 (e.g., the photosites 1300). As another example, the controller 1602 may be implemented as one or more processors on a printed circuit board (PCB) connected to the wafer.

[0158] The electro-optical system 1600 may further include a processor 1608 configured to process the detection signal (e.g., accumulated voltage) output by the photosites 1300. Such processing may include, for example, signal processing, image processing, spectroscopic analysis, etc. Optionally, the results of the processing by the processor 1608 may be used to modify the operation of the controller 1602 (or another controller). Optionally, the controller 1602 and the processor 1608 may be implemented as a single processing unit.

[0159] The electro-optical system 1600 may include a memory 1610. The memory may be of any suitable size and type (e.g., non-volatile memory, RAM, etc.). The electro-optical system 1600 may store the results of the processing of the processor 1608 in the memory 1610 (e.g., for storage or later retrieval) for an external system (e.g., a remote server, or a vehicle computer of a vehicle in which the electro-optical system 1600 is mounted, etc.) via the communication circuitry 1612. Additionally or alternatively, the results of the processing stored in the memory 1610 may be transmitted to a display 1614 for display. The display may display images or other types of results (e.g., graphs, text results of a spectrometer). The results of the processing may be transmitted to other types of output interfaces (e.g., a speaker, not shown), etc. It should be noted that, optionally, signals from the photosite 1300 may be processed by the processor 1608, for example, to evaluate the status (e.g., operability, temperature) of the imaging sensor 1601.

[0160] The electro-optical system 1600 may include a power source 1616 (e.g., a battery, an AC power adapter, a DC power adapter, etc.) that can provide power to the photosite 1300 or other components of the electro-optical system 1600.

[0161] The electro-optical system 1600 may include an optical system 1620 that directs light from the light source 1604 to the FOV and / or directs light from the FOV to the photosites 1300. The optical system may include, for example, lenses, mirrors (fixed or movable), prisms, filters, etc.

[0162] The electro-optical system 1600 may include a reference signal generating circuit 1640. The reference signal generating circuit 1640 may be coupled to one or more photosites 1300. The reference signal generating circuit 1640 may be implemented as the control voltage generating circuit 340 described above with reference to Section I. Alternatively, the reference signal generating circuit 1640 may be implemented by any suitable number and / or type of hardware components to provide reference current or voltage signals to the reference signal inputs 1306 of the amplifiers 1302 of one or more photosites 1300 constituting the imaging sensor 1601. For example, the reference signal generating circuit 1640 may be implemented as any suitable type of voltage-controlled and / or current-controlled voltage or current source (e.g., VCCS, CCCS, CCVS, VCVS, etc.). As another example, the reference signal generating circuit 1640 may generate a reference signal in response to a reference photosite electrical signal output by a reference photosite of the detector array, as described above. Again, in this example, the reference signal may be a voltage or current signal that is maintained at the same voltage or current level during a particular sampling period (e.g., each detection window in a frame), although the reference signal may be adjusted at other periods (e.g., between frames). The reference signal may be generated to have characteristics (e.g., current or voltage magnitude) that are selected at a particular time based on particular operating conditions such as ambient light levels, temperature, etc. The reference signal generation circuit 1640 may be controlled by the controller 1602.

[0163] The electro-optical system 1600 may include a readout circuit 1640. The readout circuit 1640 may be implemented as the readout circuit 610 described above with reference to Section I. Alternatively, the readout circuit 1640 may be implemented by any suitable number and / or type of hardware components for reading out the detection signals (e.g., accumulated voltages) from the photosites 1300, for providing the detection signals to the controller 1602 and / or processor 1608 for further processing (e.g., to reduce noise for image processing purposes), for storing the detection signals in memory 1610, or for any other suitable purpose.

[0164] For example, the readout circuit 1650 may temporally sequence the readouts (e.g., accumulated voltage values) of the different photosites 1300 sequentially (e.g., after some processing by one or more processors 1608) before providing the readouts for further processing, storage, or other operations. The readout circuit 1650 may be implemented as one or more components fabricated on the same wafer as other components of the electro-optical system 1600 (e.g., the photosites 1300). Optionally, the readout circuit 1650 may be implemented as one or more components on a printed circuit board (PCB) connected to the wafer. It is noted that a readout circuit such as the readout circuit 1650 may be implemented in any of the light detection devices (e.g., the PDDs 300, 700, 800, and 900) described in Section I above. The readout circuit 1650 may be implemented as a microcontroller, a processing circuit, a processor, a hardware component, executable instructions, or a combination thereof.

[0165] For example, the readout circuitry 1650 may include one or more analog-to-digital converters (ADCs) and / or components for analog signal processing to digitize the detection signal. Additionally or alternatively, the readout circuitry 1650 may perform weighting (amplification), offsetting, and / or binning (combining output signals coming from two or more photosites 1300). The digitization of the detection signal may be performed in the electro-optical system 1600. Alternatively, the readout circuitry 1650 may be external to the electro-optical system 1600. In this case, the readout circuitry may perform the same functions as described herein.

[0166] Again, in this example, the imaging sensor 1601 may include any suitable number of photosite readout circuits 1301, as described above. Each of the photosite readout circuits 1301 of the imaging sensor 1601 may accumulate a voltage on a respective capacitor 1314 during each sampling window in a larger overall sampling period (e.g., a frame). As described in further detail herein, the controller 1602 may, for example, control the switching state of each of the photosites 1300 of the imaging sensor 1601, or the switching state of an organized subset, such as a row or column. Additionally, a readout circuit 1650 may be coupled to each of the photosites 1300 and respective photosite readout circuits 1301 implemented by the imaging sensor 1601. Thus, as described herein, the readout circuit 1650 is configured to measure the accumulation of voltage on the respective capacitor 1314 of the photosite readout circuits 1301 during any hold phase.

[0167] In either case, the controller 1602 may optionally function to synchronize the switching states of any suitable portion of the photosites 1300 of the imaging sensor 1601 for each sampling window and / or for a series of sampling periods (e.g., a series of frames). This synchronization may function to control each of the photosites 1300 of the imaging sensor 1601 in a manner similar to that described above with reference to FIG. 15, i.e., by sequentially operating each one of the sets of photosites 1300 (e.g., rows, columns, etc.) according to a reset switching state, an integration state, a transition state, and a readout state as shown in FIG. 15. To achieve this, the controller 1602 may be configured to control a respective set of switches (e.g., 1310, 1312) identified for each photosite 1300 implemented by the imaging sensor 1601. In this case, the switching state operation of the entire photosite readout circuit 1301 or a given group thereof (e.g., rows, columns, etc.) may be synchronized with one another. For example, the controller 1602 may control the switching state of the entire photosite readout circuits 1301 or a given group thereof (e.g. rows, columns, etc.), such that each of the photosite readout circuits 1301 can be operated simultaneously with each other according to a reset phase, an integration phase, a transition phase, and / or a hold phase.

[0168] Thus, the controller 1602 may control the switching states of each of the readout circuits 1301 implemented by the imaging sensor 1601 according to any suitable pattern, schedule, etc. based on a particular application. For example, the controller 1602 may control the timing of each of the readout circuits 1301 implemented by the imaging sensor 1601 to facilitate a line-by-line (e.g., row-by-row or column-by-column) reset, exposure, and readout sequence. This may be employed as part of an implementation of the imaging sensor 1601 according to a rolling shutter. As another example, the controller 1602 may control each of the readout circuits 1301 implemented by the imaging sensor 1601 using a global reset and integration sequence. In this case, the switching states of each of the readout circuits 1301 may be synchronized with each other. However, the measured voltages on the capacitors of each of the photosite readout circuits 1301 may be read out line-by-line (e.g., row-by-row or column-by-column). This may be employed as part of an implementation of the imaging sensor 1601 according to a global shutter.

[0169] FIG. 17 illustrates a process flow according to an example of the disclosure. Referring to FIG. 17, the process flow 1700 may be a computer-implemented method executed by and / or otherwise associated with one or more processors (processing circuits) and / or storage devices. These processors and / or storage devices may be associated with one or more computing components identified as an electro-optical device (e.g., one or more components of the electro-optical device 1600 illustrated in FIG. 16, such as the controller 1602, the readout circuit 1650, the processor 1608, etc.). Optionally, the process flow 1700 may be executed by one or more of such components by using dedicated hardware and / or by reading executable instructions stored in a suitable memory or other storage device (e.g., the memory 1610). Various processes of the flow 1700 may be executed in combination and / or shared with one or more of the components of the electro-optical device 1600 illustrated in FIG. 16 or other suitable components of other devices not illustrated.

[0170] When executing machine-readable instructions or other suitable instructions, one or more of the components described herein may execute instructions stored on other computer-readable storage media (not shown) that may be locally stored and / or may be part of the processing circuitry itself. Process flow 1700 may include alternative or additional steps not shown in FIG. 17 for simplicity, or may be performed in an order different from that shown in FIG.

[0171] Flow 1700 may represent, for example, a method of operating a sensor (e.g., imaging sensor 1601) that includes a photosite readout circuit (e.g., photosite readout circuit 1301) that includes an amplifier (e.g., amplifier 1302) having a photodiode signal input (e.g., photodiode signal input 1304), a reference signal input (e.g., reference signal input 1306), and an amplifier output (e.g., amplifier output 1307).

[0172] Process flow 1700 may include controlling activation of a light source to generate multiple light pulses (block 1701). This may include, for example, controller 1602 controlling light source 1604 to generate multiple light pulses of any suitable wavelength, as described herein. As further described below, the generation and timing of the light pulses in this embodiment may be controlled in parallel and / or synchronously with other acts of process flow 1700 shown in FIG.

[0173] The process flow 1700 may include controlling a plurality of switches (block 1702A) to selectively connect or disconnect a first feedback path connecting the photodiode signal input and the amplifier output, and to selectively connect or disconnect a second feedback path connecting the photodiode signal input to the amplifier output via a capacitor. This may include, for example, the controller 1602 controlling the state of the switching components 1310, 1312 with one or more electrical control signals, as described above with reference to FIG. 13. The first feedback path may represent a direct connection (not including the capacitor 1314) between the photodiode signal input 1304 and the amplifier output 1307. The second feedback path may represent a connection including the capture 1314 between the photodiode signal input 1304 and the amplifier output 1307. As described herein and further below, an example of controlling a plurality of switches may include setting the photosite readout circuit 1301 to various switching states as shown in FIGS. 14A-14D to operate according to corresponding operational phases as shown in FIG. 15.

[0174] The process flow 1700 may further include acquiring a photodiode-generated current (block 1704) during a first phase corresponding to a first switching state, resulting in the accumulation of a voltage on the capacitor 1314. As described herein, the photodiode-generated current may be acquired by one or more of the photodiode readout circuits 1301 forming part of the imaging sensor 1601. For example, this first switching state may correspond to an integration phase shown in FIG. 14B, during which the first feedback path is disconnected and the second feedback path is connected.

[0175] Additionally, as described above, each of the photosite readout circuits 1301 of the imaging sensor 1601 may be configured to perform sampling over a series of detection windows in an overall larger sampling period, such as a frame. The process flow 1700 may include determining whether the sampling period (e.g., a frame) has ended (block 1706). If not, the flow 1700 may repeat the act of controlling the plurality of switches (block 1702A). This may include, for example, setting the photosite readout circuit 1301 to a transition switching state, a hold switching state, and another transition switching state between adjacent detection windows, and then setting the photosite readout circuit 1301 to an integration switching state to continue receiving the photodiode-generated current for the duration of the integration phase corresponding to the next detection window (block 1704), as described above with reference to FIG. 15. Thus, blocks 1702A, 1704, and 1706 may be repeated for any suitable number of successive detection windows.

[0176] In this manner, the imaging sensor 1601 may be operated (e.g., by the controller 1602) to cause the photosite readout circuit 1301 to accumulate a voltage on the capacitor 1314 during each of the set of distinct detection windows. Thus, as shown in FIG. 15, the photosite readout circuit 1301 may be set to a hold switching state during each of adjacent (e.g., a set) of the set sequences of distinct detection windows. As discussed herein, each of the sequences of detection windows may correspond to a sampling period during which one or more reflections of the plurality of light pulses are incident on the photodiode 1308. Thus, the act of controlling the light source to generate light pulses as described above (block 1701) may include synchronizing the generation of the light pulses to each of the reset, integration, transition, and hold phases based on a predetermined detection range associated with the sensor 1601. For example, using knowledge of a predetermined range (e.g., maximum range) for the target object, the time at which light is expected to reach the photosite 1308 may be calculated from the time at which one or more respective light pulses are generated. This time may be used as the basis for the operation of the photosite readout circuit 1301 in the integration phase. As an example, this calculation may be performed using Equation 1 below: Equation 1: T=2(d / v) It is represented by:

[0177] In Equation 1, T represents the time it takes for each light pulse to reach the photosite 1308. d represents the desired predetermined range between the photodiode 1308 and the target object to be detected. v represents the speed of light in air or relevant medium. The constant 2 is used due to the light traveling towards the target object and then reflecting back to the photodiode 1308.

[0178] On the other hand, if the sampling period (e.g., frame) has ended ("Y" in block 1706), another act (block 1702A) of controlling the plurality of switches is performed. However, in this case, the photosite readout circuit 1301 may be set to a transition switching state and a hold switching state before measuring (block 1708) the accumulation of voltage on the capacitor 1314. Thus, the measurement (block 1708) may include accumulating a voltage on the capacitor 1314 during a second phase corresponding to the second switching state. The accumulated voltage may include, for example, the voltage at point C of the photosite readout circuit 1301 shown in FIG. 13. The second switching state may correspond, for example, to the hold phase shown in FIG. 14D. In the hold phase, the first feedback path is connected and the second feedback path is disconnected. Also in this example, as described above, during measurement (block 1708), connecting the first feedback path maintains the bias voltage at the photodiode signal input 1304 at a constant voltage level while maintaining voltage accumulation on the capacitor 1314.

[0179] In either example, once the measurement (block 1708) is completed, another act of controlling a number of switches (block 1702A) is performed. In this case, however, the photosite readout circuit 1301 may be set to a transition switching state and a hold switching state before being set to a reset switching state in which both the first and second feedback paths are connected (or, optionally, directly to the reset switching state). Again, in this example, the reset switching state may correspond to the voltage on the capacitor being reset to 0 volts or another suitable voltage value. The reset switching state may correspond to the next sampling period (e.g., the next frame). Thus, blocks 1702A, 1704, 1706, 1702B, and 1708 may be repeated for any suitable number of successive sampling periods (e.g., frames). In this manner, the sensor 1601 may operate sequentially according to a reset phase, an integration phase, a transition phase, and a hold phase to measure the accumulated voltage on the capacitor 1314 in each of a successive set of frames.

[0180] Thus, the act of measuring the accumulated voltage on the capacitor 1314 during the hold phase (block 1708) may represent measuring the accumulated voltage on the capacitor 1314 at the end of a particular frame in the set of consecutive frames. This measurement may include another measurement (not shown) that occurs after a reset phase, in which case the voltage on the capacitor 1314 at the end of the frame is reset to 0 volts or other predetermined value. That is, although only one measurement block (1708) is shown in FIG. 17, as described above, the measurement may include two separate measurements. One measurement, for example, during the hold phase (e.g., at the end of the frame). The other measurement is during the reset phase (e.g., before the next series of frames begins). In this case, the difference between the two read detection signals is used as the measurement. Note that the measurement is indicative of the amount of detectable light incident on the photodiode during a series of detection windows (but not between detection windows). Thus, a measurement of the accumulated voltage on the capacitor 1314 during a particular frame may be determined using the difference between the accumulated voltage on the capacitor 1314 during the hold phase and the accumulated voltage on the capacitor 1314 during the reset phase. Again, this difference indicates the amount of light captured by the photosite readout circuit 1301 during that particular frame. Of course, the measurement of the accumulated voltage on the capacitor 1314 (block 1708) is not limited to only at the end of each frame. As illustrated by the potential readout periods in FIG. 15, the measurement of the accumulated voltage may be read during any hold phase.

[0181] FIG. 18 illustrates a process flow according to one or more embodiments of the present disclosure. With reference to FIG. 18, the process flow 1800 may be a computer-implemented method that may be performed by and / or otherwise associated with one or more processors (processing circuits) and / or storage devices. These processors and / or storage devices may be associated with one or more computing components identified as an electro-optical device (e.g., one or more components of the electro-optical device 1600 shown in FIG. 16, such as the controller 1602, the readout circuit 1650, the processor 1608, etc.). Optionally, the process flow 1800 may be performed by one or more of such components using dedicated hardware and / or by reading executable instructions stored in a suitable memory or other storage device (e.g., the memory 1610). Various processes of the process flow 1800 may be performed in combination with and / or shared with one or more of the components of the electro-optical device 1600 shown in FIG. 16 or with other suitable components of other devices not shown. The various processes of process flow 1800 may be performed in combination and / or shared with one or more of the components of the photosite reading circuit 1301 shown in FIG. 13, or with other suitable components of other devices not shown.

[0182] When executing machine-readable or other suitable instructions, one or more of the components described herein may execute instructions stored on another computer-readable storage medium (not shown), which may be locally stored and / or may be part of the processing circuitry itself. Process flow 1800 may include alternative or additional steps not shown in FIG. 18 for simplicity, or may be performed in an order different from that shown in FIG.

[0183] Flow 1800 may, for example, represent a method for detecting light collected by one or more photodiodes, such as photodiode 1308. Flow 1800 may, for example, be associated with photosite readout circuitry 1301 as shown and described in this section with reference to FIG.

[0184] Process flow 1800 may include controlling activation of a light source to generate multiple light pulses (block 1801). This may include, for example, controller 1602 controlling light source 1604 to generate multiple light pulses of any suitable wavelength, as described herein. As further described below, the generation and timing of the light pulses in this embodiment may be controlled in parallel and / or synchronously with other acts of process flow 1800 shown in FIG.

[0185] Flow 1800 may include continuously providing a photodiode generated current generated by a photodiode to a first input (e.g., photodiode signal input 1304) of an amplifier (e.g., amplifier 1302) while providing a reference signal to a second input (e.g., reference signal input 1306) of the amplifier (block 1802). The various blocks making up process flow 1800 shown in FIG. 18 may occur simultaneously with the continuously providing photodiode generated current (i.e., any combination of one or more of stages 1804, 1806, 1808, 1810, 1812, and 1814 may be performed simultaneously with the performance of stage 1802), may occur in the order shown, or may occur in any other suitable order.

[0186] The process flow 1800 may include connecting (block 1804) a second feedback path located between an amplifier output (e.g., amplifier output 1307) and a photodiode signal input of the amplifier through a capacitor (e.g., capacitor 1314) during a first detection period to collect a first charge on the capacitor corresponding to an integral of the photodiode generated current during the first detection period. For example, the first detection period may include a detection window corresponding to the photodiode readout circuit 1302 (shown in FIG. 14B) operating according to an integration phase and corresponding switching state. As described herein, the first detection period may be synchronized (e.g., by the controller 1602) with the emission of one or more first light pulses (e.g., by the light source 1604) toward the target (e.g., one or more first light pulses corresponding to the first detection period).

[0187] The flow 1800 may include, for example, after collecting a first charge on the capacitor (block 1804), disconnecting the second feedback path (block 1806) and connecting the amplifier output to the photodiode signal input via the first feedback path that does not include the capacitor (block 1086) during a first idle period. This first idle period may correspond to the photodiode readout circuit 1302 operating according to a hold phase and corresponding switching states, as shown in FIG. 14D.

[0188] The flow 1800 may include, after the first idle period, connecting the second feedback path (block 1808) during a second detection period to collect a second charge on the capacitor corresponding to an integral of the photodiode-generated current during the second detection period. The second detection period may include a next series of detection windows corresponding to the photodiode readout circuit 1302 (shown in FIG. 14B) operating according to a next integration phase and corresponding switching state, for example, as shown in FIG. 14B. For example, as shown in FIG. 15, the first detection period may correspond to one of the multiple integration phases. Meanwhile, the second detection period may correspond to a subsequent (e.g., adjacent or next) integration phase within the sampling period. As described herein, the second detection period may be synchronized (e.g., by the controller 1602) with the emission (e.g., by the light source 1604) of at least one second light pulse toward the target (e.g., at least one second light pulse corresponding to the second detection period). Thus, the first charge and the second charge may each correspond to an accumulation of charge due to a photodiode-generated current as a result of at least one first light pulse and at least one second light pulse being reflected from the target and incident on the photodiode 1308.

[0189] The flow 1800 may include, after collecting the second charge on the capacitor, disconnecting the second feedback path (block 1810) and connecting the amplifier output to the photodiode signal input via the first feedback path (block 1810) during a second idle period. The second idle period may correspond to the photodiode readout circuit 1302 operating according to a next hold phase and corresponding switching state, for example, as shown in FIG. 14D. For example, the first idle period corresponds to one of the hold phases shown in FIG. 15. Meanwhile, the second idle period may correspond to a subsequent (e.g., adjacent, next, or somewhat later) hold phase within the sampling period.

[0190] The act of disconnecting the second feedback path during the first idle period and during the second idle period (blocks 1806, 1810) may include disconnecting the capacitor 1314 from the photodiode generated current. In this manner, the hold phase may also function to prevent saturation of the capacitor 1314 due to the photodiode generated current during the first idle period and the second idle period. Additionally, as described herein, connecting the amplifier output to the photodiode signal input via the first feedback path during the first idle period and during the second idle period (blocks 1806, 1810) maintains an operating bias on the photodiode 1308 during each of the first idle period and the second idle period (e.g., during the two hold phases).

[0191] The flow 1800 may include connecting the capacitor to a readout circuit (block 1812) for sampling a first electrical signal from the capacitor having a magnitude corresponding to the sum of the first charge and the second charge during a second idle period. This connection may include, for example, a photodiode readout circuit 1301 operating according to a next hold phase as described above for block 1810. Furthermore, this connection may include a readout circuit (e.g., readout circuit 1650) for measuring an electrical signal representative of the voltage on the capacitor 1314 during this next hold phase. The transition and hold phases of operation between successive detection windows ensure that the charge stored on the capacitor 1314 does not decrease. Thus, the voltage on the capacitor 1314 measured during the next hold phase represents the sum or aggregation of the voltages stored on the capacitor 1314 during all previous detection windows since the most recent reset phase.

[0192] Flow 1800 may include, for example, determining an amount of light incident on the photodiode during the first and second detection periods based on the first electrical signal (block 1814). Again, in this example, the charge stored on capacitor 1314 does not decrease between adjacent detection windows. Thus, the first electrical signal represents an aggregate of (e.g., is proportional to or a predetermined function of) the total amount of light incident on photodiode 1308 during a previous detection window (e.g., a previous integration phase).

[0193] In this example, as described above with reference to FIG. 15, the photosite readout circuit 1301 may repeat the process of sequentially alternating between the integration, transfer and hold phases over a number of detection windows that may constitute a portion of a larger sampling period (e.g., a frame). Additionally, the photosite readout circuit 1301 may be set to a reset phase at the end of the sampling period. Thus, although not shown in FIG. 18 for simplicity, the flow 1800 may further include depleting the voltage applied to the capacitor 1314 after the second idle period by electrically connecting the first terminal of the capacitor 1314 to the second terminal of the capacitor 1314. This may be achieved, for example, by closing the switching element 1310 during a reset switching state as shown in FIG. 14A.

[0194] Additionally, although not shown in FIG. 18 for brevity, the process flow 1800 may further include sampling, by a readout circuit (e.g., readout circuit 1650), a second electrical signal indicative of a voltage at at least one terminal of the capacitor 1314 when the first and second terminals are connected. In other words, the readout circuit 1650 may read out a voltage level during a reset switching state in which the voltage should be reset to 0 volts or other predetermined voltage value. Doing so allows the readout circuit 1650 to measure a "baseline" of the voltage stored on the capacitor 1314 when no light is incident on the photodiode 1308. Thus, the act of determining the amount of light incident on the photodiode during the first and second detection periods (block 1814) may be further based on the second electrical signal by taking a difference between the first electrical signal measured during the second idle period (i.e., the hold phase) and the second electrical signal measured after the second idle period (e.g., during the reset phase).

[0195] Even in this example, the detection window referred to herein may comprise a portion of a longer sampling period (e.g., a frame), which may alternatively be referred to herein as a detection frame. Thus, process flow 1800 may be repeated for each detection frame. This may include, for example, performing blocks 1802-1814 to (i) determine a first amount of light incident on photodiode 1308 in a first detection frame, (ii) determine a second amount of light incident on photodiode 1308 in a second detection frame that is later than the first detection frame, (iii) determine a third amount of light incident on photodiode 1308 in a third detection frame that is later than the first detection frame, etc.

[0196] As part of this repeated process, the process flow 1800 may further include providing a first reference signal to a second input (e.g., reference signal input 1306) of an amplifier (e.g., amplifier 1302) in a first frame, the first reference signal being determined in response to a first reference photosite electrical signal output by a reference photosite of the detector array to which the photodiode belongs, the reference photosite being shielded from ambient light, as described above with respect to FIG. 16. Then, in a subsequent second frame, a different second reference signal may be provided to the second input, the second reference signal being determined in response to a second reference photosite electrical signal output by the reference photosite. Then, in a subsequent third frame, a different third reference signal may be provided to the second input, the third reference signal being determined in response to a third reference photosite electrical signal output by the reference photosite. As described herein, this process may be performed by the controller 1602 to cause the reference signal generating circuit 1640 to provide different reference signals based on temperature or other operating conditions. This process may be repeated any suitable number of times over a series of frames. In this case, the reference signal is adjusted on a frame-by-frame basis as described herein.

[0197] (Multiple examples) The following examples relate to various aspects of the presently disclosed subject matter.

[0198] Example 1. The light detection device includes an active photosite including an active photodiode, a reference photosite including a reference photodiode, a first voltage-controlled current circuit including a voltage-controlled current source or a voltage-controlled current sink, and a control voltage generating circuit. The first voltage-controlled current circuit is connected to the active photodiode. The control voltage generating circuit is connected to the active voltage-controlled current circuit and the reference photosite. The control voltage generating circuit is used to supply a control voltage having a voltage level according to the dark current of the reference photodiode to the voltage-controlled current circuit. This can reduce the effect of the dark current of the active photodiode on the output of the active photosite.

[0199] Example 2. In the photodetector device of Example 1 above, the control voltage generating circuit includes an amplifier for supplying the control voltage.

[0200] Example 3. In the photodetector device of any combination of the above examples 1 and 2, the photodetector device includes a reference voltage controlled current circuit including a voltage controlled current source or a voltage controlled current sink, and the reference voltage controlled current circuit is connected to a reference photodiode. A first input voltage is supplied to a first input section of the amplifier. A second input section of the amplifier is electrically connected to the reference photodiode and the reference voltage controlled current circuit.

[0201] Example 4. In the photodetector device of any combination of the above examples 1 to 3, the first voltage control current circuit and the reference voltage control current circuit are connected to the output of an amplifier. The amplifier generates a control voltage by continuously decreasing the difference between the output of the reference voltage control circuit and the first input voltage.

[0202] Example 5. In the photodetection device of any combination of the above examples 1 to 4, the photodetection device includes a plurality of active photosites, a plurality of reference photosites, a plurality of first voltage-controlled current circuits, and a plurality of reference voltage-controlled current circuits. Each of the plurality of active photosites includes an active photodiode. Each of the plurality of reference photosites includes a plurality of reference photodiodes. Each of the plurality of first voltage-controlled current circuits is connected to at least one of the plurality of active photodiodes. Each of the plurality of reference voltage-controlled current circuits is connected to at least one of the plurality of reference photodiodes. A second input of the amplifier is electrically connected to each of the plurality of reference photodiodes. A control voltage is supplied to each of the plurality of first voltage-controlled current circuits.

[0203] Example 6. In a photodetection device of any combination of Examples 1 to 5 above, different active photodiodes simultaneously generate different levels of dark current, different reference photodiodes simultaneously generate different levels of dark current, and the control voltage generation circuit supplies the same control voltage to the different active photodiodes based on averaging the different dark currents of the reference photodiodes.

[0204] Example 7. In the photodetector device of any combination of the above examples 1 to 6, the photodetector device includes a plurality of first voltage-controlled current circuits, the plurality of first voltage-controlled current circuits including at least one voltage-controlled current source collectively connected to each active photosite, and at least one voltage-controlled current sink collectively connected to each active photosite. The control voltage generating circuit includes (i) a first amplifier connected to the at least one voltage-controlled current source for supplying a first control voltage to the plurality of active photosites at a first time, (ii) a second amplifier connected to the at least one voltage-controlled current sink for supplying a second control voltage to the plurality of active photosites at a second time, and (iii) a switching circuit for selecting between supplying the first control voltage and supplying the second control voltage.

[0205] Example 8. In the photodetection device of any combination of the above examples 1 to 7, the photodetection device further includes a controller for supplying a first input voltage having a level determined corresponding to a bias in the active photodiode.

[0206] Example 9. In the photodetection device of any combination of the above examples 1 to 8, the controller supplies a first input voltage such that the bias on the reference photodiode is approximately the same as the bias on the active photodiode.

[0207] Example 10. In the photodetection device of any combination of Examples 1 to 9 above, the photodetection device includes a physical barrier that prevents light from the field of view of the photodetection device from reaching the reference photodiode.

[0208] Example 11. In the photodetection device of any combination of the above examples 1 to 10, the photodetection device includes a plurality of photosites and a controller. The controller sets at least one of the plurality of photosites to operate as an active photosite or a reference photosite.

[0209] Example 12. In the photodetection device of any combination of the above examples 1 to 11, the photodetection device includes a plurality of active photosites, a plurality of reference photosites, a plurality of first voltage-controlled current circuits, and a plurality of reference voltage-controlled current circuits. Each of the plurality of active photosites includes an active photodiode. Each of the plurality of reference photosites includes a plurality of reference photodiodes. Each of the plurality of first voltage-controlled current circuits is connected to at least one of the plurality of active photodiodes. Each of the plurality of reference voltage-controlled current circuits is connected to at least one of the plurality of reference photodiodes. When the photodetection device operates at a first temperature, the control voltage generation circuit supplies a first control voltage to the voltage-controlled current circuit to supply a first level of current in response to the dark currents of the plurality of reference photodiodes. This can reduce the influence of the dark currents of the active photodiodes on the output of the active photodiodes. When the photodetection device operates at a second temperature higher than the first temperature, the control voltage generation circuit supplies a second control voltage to the voltage-controlled current circuit to supply a second level of current higher than the first level in response to the dark currents of the plurality of reference photodiodes. This reduces the effect of the dark current of the active photodiode on the output of the active photodiode.

[0210] Example 13. In the light detection device of any combination of the above examples 1 to 12, the light detection device includes a plurality of active photosites, a plurality of reference photosites, a plurality of first voltage controlled current circuits, a plurality of reference voltage controlled current circuits, an optical system, a power supply, a readout circuit, a processor, and a memory module. Each of the plurality of active photosites includes an active photodiode. Each of the plurality of reference photosites includes a plurality of reference photodiodes. Each of the plurality of first voltage controlled current circuits is connected to at least one of the plurality of active photodiodes. Each of the plurality of reference photosites is connected to at least one of the plurality of reference photodiodes. The optical system directs light from a field of view of the light detection device to the plurality of photosites, and the power supply provides power to the active photodiodes, the reference photodiodes, and the amplifier. The readout circuit provides detection information in response to detection signals of the active photodiodes. The processor processes the detection information to provide an image of at least an object in the field of view. The memory module stores at least one of the detection information and the detection signals.

[0211] Example 14. The photosite readout circuit comprises an amplifier, a first switch and a second switch. The amplifier has a photodiode signal input, a reference signal input and an amplifier output. The first switch is configured to selectively connect or disconnect a first feedback path connecting the photodiode signal input and the amplifier output. The second switch is configured to selectively connect or disconnect a second feedback path connecting the photodiode signal input to the amplifier output via a capacitor. The photodiode signal input is configured to obtain a photodiode generated current that results in a voltage build-up on the capacitor when the photosite readout circuit is in a first switching state. When the photosite readout circuit is in a second switching state, the voltage build-up on the capacitor is maintained. In the first switching state, the first switch disconnects the first feedback path and the second switch connects the second feedback path. In the second switching state, the first switch connects the first feedback path and the second switch disconnects the second feedback path.

[0212] Example 15. In the photosite readout circuit of Example 14 above, connecting the first feedback path in the second switching state maintains the bias voltage at the photodiode signal input at a constant voltage level while maintaining the voltage build-up on the capacitor.

[0213] Example 16. In any combination of the photosite readout circuits of Examples 14 to 15, in a third switching state, the first switch connects the first feedback path and the second switch connects the second feedback path, the third switching state corresponding to the voltage on the capacitor being reset to 0 volts.

[0214] Example 17. In any combination of the photosite readout circuits of Examples 14 to 16, the photosite readout circuits are configured to store a voltage on a capacitor during each detection window of the set of distinct detection windows, and the first switch and the second switch operate the photosite readout circuit according to a second switching state between adjacent detection windows of the set of distinct detection windows.

[0215] Example 18. In any combination of the photosite readout circuit of Examples 14 to 17 above, the photosite readout circuit is part of an image sensor. The photosite readout circuit is configured to store a voltage on a capacitor in each frame of a set of frames by sequentially operating according to a first switching state, a second switching state, and a third switching state. The sequential operation of the first switching state, the second switching state, and the third switching state is synchronized with at least one other photosite readout circuit of the image sensor.

[0216] Example 19. In any combination of photosite readout circuits in above examples 14 to 18, the photosite readout circuits belong to a plurality of photosite readout circuits of a shortwave infrared (SWIR) imaging sensor.

[0217] Example 20. The electro-optical system comprises a plurality of photosite readout circuits, a controller and a readout circuit. Each of the plurality of photosite readout circuits comprises an amplifier and a plurality of switches. The amplifier has a photodiode signal input, a reference signal input and an amplifier output. The plurality of switches are configured to (i) selectively connect or disconnect a first feedback path connecting the photodiode signal input to the amplifier output and (ii) selectively connect or disconnect a second feedback path connecting the photodiode signal input to the amplifier output via a capacitor. The photodiode signal input is configured to acquire a photodiode generated current that results in a voltage build-up on the capacitor when the photosite readout circuit is in a first switching state. The voltage build-up on the capacitor is maintained when the photosite readout circuit is in a second switching state. The controller is configured to control, for each of the plurality of photosites, the plurality of switches to (i) operate the electro-optical system during a first switching state by blocking the first feedback path and connecting the second feedback path, and (ii) operate the electro-optical system during a second switching state by connecting the first feedback path and blocking the second feedback path. The readout circuit is configured to measure, for each of the plurality of photosites, a voltage accumulation on the capacitor during one of the first switching state or the second switching state.

[0218] Example 21. In the electro-optical system of Example 20 above, in each of the multiple photosite readout circuits, connecting the first feedback path of each photosite readout circuit in the second switching state maintains the bias voltage at the photodiode signal input of each photosite readout circuit at a constant voltage level while maintaining voltage accumulation on the capacitor of each photosite readout circuit.

[0219] Example 22. In the electro-optical system of any combination of the above Examples 20 to 21, the controller is configured to operate the electro-optical system in a third switching state in which the switches in each of the photosite readout circuits of the plurality of photosite readout circuits are controlled to connect the first feedback path of each photosite readout circuit to the second feedback path of each photosite readout circuit, thereby connecting the photodiode signal input of each photosite readout circuit to the amplifier output of each photosite readout circuit, and the third switching state corresponds to the voltage on the capacitor of each photosite readout circuit being reset to 0 volts.

[0220] Example 23. In any combination of the electro-optical system of Examples 20 to 22 above, the electro-optical system further comprises a light source configured to generate a plurality of light pulses. Each photosite readout circuit of the plurality of photosite readout circuits is configured to accumulate a voltage on a capacitor of the respective photosite readout circuit during a respective sequence of detection windows. Each sequence of the detection windows corresponds to a sampling period during which each of the plurality of light pulses is incident on a photodiode connected to the respective photosite readout circuit.

[0221] Example 24. In the electro-optical system of any combination of the above Examples 20 to 23, between adjacent detection windows in the series of detection windows, each of the plurality of photosite readout circuits operates according to a second switching state.

[0222] Example 25. In the electro-optical system of any combination of Examples 20 to 24 above, the plurality of photosite readout circuits are part of an imaging sensor, and the controller is configured to cause each of the plurality of photosite readout circuits to accumulate a voltage on a capacitor of the respective photosite readout circuit in each of a set of successive frames by sequentially operating the imaging sensor according to a first switching state, a second switching state, and a third switching state.

[0223] Example 26. In the electro-optical system of any combination of Examples 20 to 25 above, the controller is configured to control each of a plurality of switches identified by each of the plurality of photosite readout circuits to synchronize operation of each photosite readout circuit according to a first switching state and the second switching state.

[0224] Example 27. A method for operating a sensor including a photosite readout circuit including an amplifier having a photodiode signal input, a reference signal input and an amplifier output, the method comprising controlling a plurality of switches to selectively connect or disconnect (i) a first feedback path connecting the photodiode signal input and the amplifier output and (ii) a second feedback path connecting the photodiode signal input to the amplifier output via a capacitor, the method comprising acquiring a photodiode generated current resulting in a voltage build-up on the capacitor during a first phase corresponding to a first switching state, the first switching state corresponding to the first feedback path being blocked and the second feedback path being connected, the method comprising measuring the voltage build-up on the capacitor during one of the first phase or a second phase corresponding to a second switching state, the second switching state corresponding to the first feedback path being connected and the second feedback path being blocked.

[0225] Example 28. In the method of Example 27 above, connecting the first feedback path in the second switching state maintains the bias voltage at the photodiode signal input at a constant voltage level while maintaining voltage accumulation on the capacitor.

[0226] Example 29. In any combination of the methods of Examples 27-28 above, the method further includes operating the sensor in a third phase corresponding to a third switching state by connecting the first feedback path and the second feedback path with the plurality of switches, the third switching state corresponding to the voltage on the capacitor being reset to 0 volts.

[0227] Example 30. In any combination of the method of Examples 27-29 above, the method further includes operating the sensor to accumulate a voltage on a capacitor during each of a series of distinct detection windows, where the photosite readout circuitry is set to a second switching state between adjacent detection windows of the series of distinct detection windows.

[0228] Example 31. In any combination of the methods of Examples 27 to 30 above, the method further includes sequentially operating the sensor according to a first switching state, a second switching state, and a third switching state to accumulate a voltage on the capacitor in each of the successive sets of frames.

[0229] Example 32. In any combination of the methods of Examples 27 to 31 above, measuring the voltage accumulation on the capacitor includes measuring the voltage accumulation on the capacitor during the second phase at an end of a first frame of the set of frames, and measuring the voltage on the capacitor being reset to 0 volts during the third phase at the end of the first frame, where a difference in the voltage accumulation on the capacitor between the second phase and the third phase indicates an amount of light captured by the photosite readout circuitry during the first frame.

[0230] Example 33. In any combination of the methods of Examples 27-32 above, the method further includes controlling activation of the light source to generate a plurality of light pulses and operating the sensor to accumulate a voltage on a capacitor during each of a series of detection windows, where each of the series of detection windows corresponds to a sampling period during which each of the plurality of light pulses is incident on a photodiode coupled to the photodiode signal input.

[0231] Example 34. In any combination of the methods of Examples 27 to 33 above, controlling activation of the light source includes synchronizing generation of the multiple light pulses into a first phase, a second phase, and a third phase based on a predetermined detection range associated with the sensor.

[0232] Example 35. A method of detecting light collected by a photodiode, the method comprising: continuously supplying a photodiode generated current generated by the photodiode to a first input of an amplifier while supplying a reference signal to a second input of the amplifier. During the continuous supply of the photodiode generated current, the method comprises: during a first detection period, connecting a second feedback path located between an output of the amplifier and a signal input of the photodiode via a capacitor, and collecting a first charge on the capacitor corresponding to an integral of the photodiode generated current during the first detection period. After collecting the first charge on the capacitor, the method comprises: during a first idle period, disconnecting the second feedback path and connecting the amplifier output to the photodiode signal input via the first feedback path not including a capacitor. After the first idle period, the method comprises connecting the second feedback path during a second detection period, and collecting a second charge on the capacitor corresponding to an integral of the photodiode generated current during the second detection period. After collecting the second charge on the capacitor, the method comprises: disconnecting the second feedback path and connecting the amplifier output to the photodiode signal input via the first feedback path during a second idle period. The method includes connecting the capacitor to a readout circuit during a second idle period and sampling a first electrical signal from the capacitor having a magnitude corresponding to the sum of the first charge and the second charge, and determining an amount of light incident on the photodiode during the first detection period and the second detection period based on the first electrical signal.

[0233] Example 36. In the method of Example 35 above, the method includes, after a second idle period, electrically connecting a first terminal of the capacitor to a second terminal of the capacitor to deplete a voltage on the capacitor, and sampling by a readout circuit a second electrical signal indicative of a voltage on the at least one terminal of the capacitor when the first and second terminals are connected. The act of determining an amount of light incident on the photodiode during the first and second detection periods is further based on the second electrical signal.

[0234] Example 37. In any combination of the methods of Examples 35 to 36 above, the method further includes synchronizing the first detection period with emission of the first light pulse toward the target and synchronizing the second detection period with emission of the second light pulse toward the target. The first charge and the second charge correspond to the light of the first light pulse and the light of the second light pulse, respectively, reflected from the target toward the photodiode.

[0235] Example 38. In the method of any combination of Examples 35 to 37 above, the act of disconnecting the second feedback path during the first idle period and the second idle period includes disconnecting the capacitor from the photodiode-generated current to prevent saturation of the capacitor due to the photodiode-generated current during at least the second idle period.

[0236] Example 39. In the method of any combination of Examples 35 to 38 above, the act of connecting the amplifier output to the photodiode signal input via the first feedback path during the first idle period maintains an operating bias of the photodiode during the first idle period.

[0237] Example 40. In any combination of the methods of Examples 35 to 39 above, the method includes repeating the method of claim 22 to determine a first amount of light incident on the photodiode in a first detection frame, determine a second amount of light incident on the photodiode in a second detection frame subsequent to the first detection frame, determine a third amount of light incident on the photodiode in a third detection frame subsequent to the first detection frame, apply to a second input of the amplifier in the first frame a first reference signal determined in response to a first reference photosite electrical signal output by a reference photosite of a detection array to which the photodiode belongs, apply to the second input in the second frame a second reference signal determined in response to a second reference photosite electrical signal output by the reference photosite, and apply to the second input in the third detection frame a third reference signal determined in response to a third reference photosite electrical signal output by the reference photosite. The first reference signal, the second reference signal, and the third reference signal are different from one another.

[0238] The apparatus as shown and described.

[0239] The method as shown and described.

[0240] (Conclusion) Although the present disclosure has been described in terms of specific embodiments and generally related methods, modifications and permutations of the embodiments and methods will be apparent to those skilled in the art. For example, optionally, a single photosite may include more than a single photodiode, for example, if different spectral filters are placed in front of the different photodiodes. If different photodiodes (e.g., for different ranges) are used, separate feedback circuits may be implemented for all photodiodes of the same type. It should be understood that the present disclosure is not limited by the specific embodiments described herein, but should be limited only by the scope of the appended claims.

[0241] Unless otherwise specified, the use of the word "and / or" between the last two members of a list of options for selection indicates that the selection of one or more of the listed options is appropriate and may be made.

[0242] It should be understood that when a claim or the specification refers to "a" or "an" element, the reference is not to be interpreted as the absence of one of the element.

[0243] All references mentioned herein are incorporated by reference in their entirety to the same extent as if each reference was specifically and individually indicated to be incorporated by reference. In addition, citation or identification of a reference in this application shall not be construed as an admission that the reference is available as prior art to the present disclosure.

[0244] The above description of the specific embodiments sufficiently reveals the general nature of the present disclosure so that others can easily modify and / or adapt the specific embodiments for various applications by applying knowledge within the art without undue experimentation and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments based on the teachings and guidance provided herein. It should be understood that the terms or phrases used herein are for the purpose of explanation and not for the purpose of limitation. Therefore, the terms or phrases used herein should be interpreted by those skilled in the art in light of the teachings and guidance.

[0245] References herein to "one embodiment," "an embodiment," "exemplary embodiment," and the like indicate that the embodiment being described may include a particular configuration, structure, or characteristic, but not all embodiments necessarily include the particular configuration, structure, or characteristic. Moreover, these phrases do not necessarily refer to the same embodiment. Moreover, when a particular configuration, structure, or characteristic is described in connection with one embodiment, it is contemplated that it is within the knowledge of one of ordinary skill in the art to affect that configuration, structure, or characteristic in connection with other embodiments, whether or not this is explicitly stated.

[0246] The exemplary embodiments described herein are presented for purposes of illustration and not limitation. Other exemplary embodiments are possible, and modifications to the exemplary embodiments may be made. Thus, this specification is not intended to limit the disclosure. Rather, the scope of the disclosure is defined only by the following claims and their equivalents.

[0247] Each aspect may be implemented as hardware (e.g., circuitry), firmware, software, or any combination thereof. Each aspect may be implemented as machine-readable instructions stored on a machine-readable medium that may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, electrical signals, optical signals, acoustic signals, or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and the like. Furthermore, firmware, software, routines, instructions may be described herein as performing certain actions. However, it should be understood that such description is merely for convenience and that in reality, the actions result from a computing device, processor, controller, or other device executing the firmware, software, routines, instructions, etc. Furthermore, variations of the implementation may be performed by a general-purpose computer.

[0248] For purposes of the description herein, the term "processing circuitry" or "processor circuitry" should be understood to mean circuitry(s), processor(s), logic, or a combination thereof. For example, a circuitry may include analog circuitry, digital circuitry, state machine logic, other configurations of electronic hardware, or a combination thereof. A processor may include a microprocessor, a digital signal processor (DSP), or other hardware processor. A processor may be "hard-coded" with instructions to perform the corresponding function(s) according to the aspects described herein. Alternatively, a processor may access an internal memory and / or an external memory to retrieve instructions stored in the memory. The instructions, when executed by a processor, perform the corresponding function(s) associated with the processor and / or perform one or more functions and / or operations associated with the operation of a component having a processor therein.

[0249] In one or more of the exemplary embodiments described herein, the processing circuitry may include a memory for storing data and / or instructions. The memory may be any known volatile and / or non-volatile memory, including, for example, read only memory (ROM), random access memory (RAM), flash memory, magnetic storage media, optical disks, erasable programmable read only memory (EPROM), and programmable read only memory (PROM). The memory may be non-removable, removable, or a combination of both.

Claims

1. A photosite readout circuit, comprising: an amplifier having a photodiode signal input, a reference signal input, and an amplifier output; a first switch configured to selectively connect or disconnect a first feedback path connecting the photodiode signal input and the amplifier output; a second switch configured to selectively connect or disconnect a second feedback path connecting the photodiode signal input to the amplifier output through a capacitor; having the photodiode signal input is configured to receive a photodiode generated current that results in a build-up of a voltage on the capacitor when the photosite readout circuit is in a first switching state; maintaining a voltage build-up on the capacitor when the photosite readout circuit is in a second switching state; In the first switching state, the first switch interrupts the first feedback path and the second switch connects the second feedback path; In the second switching state, the first switch connects the first feedback path and the second switch interrupts the second feedback path. Photosite readout circuit.

2. 2. The photosite readout circuit of claim 1, wherein in the second switching state, the connection of the first feedback path maintains voltage accumulation on the capacitor while a bias voltage at the photodiode signal input is maintained at a constant voltage level.

3. 2. The photosite readout circuit of claim 1, wherein in a third switching state, the first switch connects the first feedback path and the second switch connects the second feedback path, the third switching state corresponding to a voltage on the capacitor being reset to zero volts.

4. 2. The photosite readout circuit of claim 1, wherein the photosite readout circuit is configured to store a voltage on the capacitor in each detection window of a set of individual detection windows, and the first switch and the second switch operate the photosite readout circuit according to the second switching state between each of adjacent detection windows of the set of individual detection windows.

5. 5. The photosite readout circuit of claim 4, wherein the photosite readout circuit is part of an imaging sensor and is configured to operate sequentially according to the first switching state, the second switching state, and the third switching state to store a voltage on the capacitor in each of a set of a series of a plurality of frames, the sequential operation of the first switching state, the second switching state, and the third switching state being synchronized with at least one other photosite readout circuit of the imaging sensor.

6. 2. The photosite readout circuit of claim 1, wherein said photosite readout circuit belongs to a plurality of photosite readout circuits of a short wave infrared (SWIR) imaging sensor.

7. 1. An electro-optical system comprising: a plurality of photosite readout circuits, each photosite readout circuit belonging to the plurality of photosite readout circuits: an amplifier having a photodiode signal input, a reference signal input, and an amplifier output; and a plurality of switches configured to selectively connect or disconnect (i) a first feedback path coupling the photodiode signal input to the amplifier output and (ii) a second feedback path coupling the photodiode signal input to the amplifier output via a capacitor, the photodiode signal input being configured to receive a photodiode generated current that results in a build-up of voltage on the capacitor when the photosite readout circuit is in a first switching state, and wherein the build-up of voltage on the capacitor is maintained when the photosite readout circuit is in a second switching state; a plurality of photosite readout circuits having a controller configured to control, for each of the plurality of photosite readout circuits, the plurality of switches to: (i) operate the electro-optical system by blocking the first feedback path and connecting the second feedback path during the first switching state; and (ii) operate the electro-optical system by connecting the first feedback path and blocking the second feedback path during the second switching state. a readout circuit configured to measure, for each of the plurality of photosite readout circuits, a voltage accumulation on the capacitor during one of the first switching state or the second switching state; An electro-optical system having

8. 8. The electro-optical system of claim 7, wherein for each photosite readout circuit of the plurality of photosite readout circuits, in the second switching state, the connection of the first feedback path of the respective photosite readout circuit maintains voltage accumulation on the capacitor of the respective photosite readout circuit while a bias voltage at the photodiode signal input of the respective photosite readout circuit is maintained at a constant voltage level.

9. 8. The electro-optical system of claim 7, wherein the controller is configured to control the switches to operate the electro-optical system in a third switching state for each photosite readout circuit of the plurality of photosite readout circuits, coupling the photodiode signal input of each photosite readout circuit to the amplifier output of each photosite readout circuit by connecting the first feedback path of the respective photosite readout circuit and the second feedback path of the respective photosite readout circuit, the third switching state corresponding to a voltage on the capacitor of each photosite readout circuit being reset to 0 volts.

10. 8. The electro-optical system of claim 7, further comprising a light source configured to generate a plurality of light pulses, each photosite readout circuit of the plurality of photosite readout circuits configured to accumulate a voltage on the capacitor of the respective photosite readout circuit in each of a series of a plurality of detection windows, each detection window of the series of a plurality of detection windows corresponding to a sampling period during which each of the plurality of light pulses is incident on a photodiode coupled to a respective photosite readout circuit.

11. 11. The electro-optical system of claim 10, wherein between each adjacent detection window of the series of detection windows, each photosite readout circuit of the plurality of photosite readout circuits operates according to the second switching state.

12. 10. The electro-optical system of claim 9, wherein the plurality of photosite readout circuits are part of an imaging sensor, and the controller is configured to cause each photosite readout circuit of the plurality of photosite readout circuits to accumulate a voltage on the capacitor of each photosite readout circuit in each of a set of successive frames by sequentially operating the imaging sensor according to the first switching state, the second switching state, and the third switching state.

13. 8. The electro-optical system of claim 7, wherein the controller is configured to control a respective plurality of switches identified by each of the plurality of photosite readout circuits to synchronize operation of each photosite readout circuit according to the first switching state and the second switching state.

14. 1. A method of operating a sensor including a photosite readout circuit including an amplifier having a photodiode signal input, a reference signal input, and an amplifier output, comprising: controlling a plurality of switches to (i) selectively connect or disconnect a first feedback path coupling the photodiode signal input and the amplifier output, and (ii) selectively connect or disconnect a second feedback path coupling the photodiode signal input to the amplifier output via a capacitor; receiving a photodiode generated current resulting in a build-up of a voltage on the capacitor during a first phase corresponding to a first switching state, the first switching state corresponding to the first feedback path being disconnected and the second feedback path being connected; measuring a voltage accumulation on the capacitor during one of the first phase or a second phase corresponding to a second switching state, the second switching state corresponding to the first feedback path being connected and the second feedback path being disconnected; The method according to claim 1,

15. 15. The method of claim 14, wherein in the second switching state, the connection of the first feedback path maintains voltage accumulation on the capacitor while a bias voltage at the photodiode signal input is maintained at a constant voltage level.

16. operating the sensor in a third phase corresponding to a third switching state by connecting the first feedback path and the second feedback path with the plurality of switches, the third switching state corresponding to a voltage on the capacitor being reset to 0 volts; 15. The method of claim 14 further comprising:

17. operating the sensor to accumulate a voltage on the capacitor during each of a series of discrete detection windows, the photosite readout circuit being set to the second switching state between each of adjacent detection windows in the series of discrete detection windows; 15. The method of claim 14 further comprising:

18. operating the sensor sequentially according to the first switching state, the second switching state, and the third switching state to store a voltage on the capacitor in each of a series of a plurality of sets of frames; 20. The method of claim 16 further comprising:

19. 20. The method of claim 18, wherein the measuring the voltage accumulation on the capacitor comprises: measuring the voltage accumulation on the capacitor during the second phase at an end of a first frame of the set of consecutive frames; and measuring the voltage on the capacitor at the end of the first frame during the third phase being reset to 0 volts, wherein a difference in the voltage accumulation on the capacitor between the second phase and the third phase represents an amount of light captured by the photosite readout circuitry in the first frame.

20. controlling activation of a light source to generate a plurality of light pulses; operating the sensor to accumulate a voltage on the capacitor during each of a series of a plurality of detection windows, each detection window of the series corresponding to a sampling period during which each of a plurality of light pulses is incident on a photodiode connected to the photodiode signal input; 15. The method of claim 14 further comprising:

21. 21. The method of claim 20, wherein the controlling the activation of the light source comprises synchronizing the generation of the plurality of light pulses to the first phase, the second phase, and the third phase based on a predetermined detection range associated with the sensor.

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