Self-aligned gate endcap (SAGE) architecture with reduced cap

Abstract

SOLUTION: To provide an integrated circuit structure including a first fin, a first epitaxial source or drain structure above the first fin and having a first conductivity type, a second fin laterally spaced from the first fin, a second epitaxial source or drain structure above the second fin and having a second conductivity type opposite the first conductivity type, a gate endcap wall between the first fin and the second fin and laterally spaced from the first fin and the second fin, a trench isolation structure laterally adjacent the lower portion of the first fin, the lower portion of the second fin, and the lower portion of the gate endcap wall and having a lower surface below the lowermost surface of the gate endcap wall, and a local conductive interconnect above the first epitaxial source or drain structure, above the gate endcap wall, and above the second epitaxial source or drain structure.SELECTED DRAWING: Figure 7A

Description

[Technical field]

[0001] Embodiments of the present disclosure are in the field of semiconductor devices and processes, and in particular, a self-aligned gate endcap (SAGE) architecture with reduced or eliminated cap, and a method for fabricating a self-aligned gate endcap (SAGE) architecture with reduced or eliminated cap. [Background technology]

[0002] For the past few decades, the scaling of features in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to ever smaller features allows for an increased density of functional units in the limited real estate of a semiconductor chip. For example, shrinking transistor dimensions allows more memory or logic devices to be packed onto a chip, increasing the capacity of the manufactured products. However, the drive for ever greater capacity is not without challenges. There is an ever-increasing need to optimize the performance of each device.

[0003] In the fabrication of integrated circuit devices, as device dimensions continue to shrink, multi-gate transistors such as tri-gate transistors have become more prevalent. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and enabling a less complex tri-gate fabrication process.

[0004] However, multi-gate transistors cannot be scaled without consequences. As the dimensions of these building blocks of microelectronic circuits decrease, and as the number of very many building blocks manufactured in a given area increases, the constraints on the lithographic processes used to pattern these building blocks become severe. In particular, there may be a trade-off between the critical dimensions of features patterned in the semiconductor stack and the spacing between such features. [Brief description of the drawings]

[0005] [Figure 1] 1A shows a plan view contrasting adjacent integrated circuit structures of a conventional architecture having relatively wide spacing (left side (a)) with adjacent integrated circuit structures of a self-aligned gate endcap (SAGE) architecture having relatively narrow spacing according to an embodiment of the present disclosure (right side (b)).

[0006] [Diagram 2] FIG. 1 illustrates a top view of a conventional layout including fin-based semiconductor devices including end-to-end spacing.

[0007] [Diagram 3] 1A-1C show cross-sectional views through a fin contrasting a conventional architecture (left side (a)) and a self-aligned gate endcap (SAGE) architecture according to an embodiment of the present disclosure (right side (b)).

[0008] [Figure 4A] 1 shows cross-sectional views of key process steps in a conventional FinFET or Tri-Gate process fabrication scheme. [Figure 4B] 1 shows cross-sectional views of key process steps in a conventional FinFET or Tri-Gate process fabrication scheme. [Figure 4C] 1 shows cross-sectional views of key process steps in a conventional FinFET or Tri-Gate process fabrication scheme. [Figure 4D] 1 shows cross-sectional views of key process steps in a conventional FinFET or Tri-Gate process fabrication scheme.

[0009] [Figure 5A] 1A-1D illustrate cross-sectional views of key process steps of a self-aligned gate endcap (SAGE) process fabrication scheme for a FinFET or Tri-gate device according to an embodiment of the present disclosure. [Figure 5B] 1A-1D illustrate cross-sectional views of key process steps of a self-aligned gate endcap (SAGE) process fabrication scheme for a FinFET or Tri-gate device according to an embodiment of the present disclosure. [Figure 5C] 1A-1D illustrate cross-sectional views of key process steps of a self-aligned gate endcap (SAGE) process fabrication scheme for a FinFET or Tri-gate device according to an embodiment of the present disclosure. [Figure 5D] 1A-1D illustrate cross-sectional views of key process steps of a self-aligned gate endcap (SAGE) process fabrication scheme for a FinFET or Tri-gate device according to an embodiment of the present disclosure.

[0010] [Figure 6] 1 illustrates a layout of a 6T SRAM cell area with self-aligned gate endcap (SAGE) walls according to an embodiment of the present disclosure.

[0011] [Figure 7A] 1A-1D show cross-sectional views of channel regions of an integrated circuit structure without an etched self-aligned gate endcap (SAGE) wall cap (left) and with a partially etched SAGE wall cap (right) according to an embodiment of the present disclosure.

[0012] [Figure 7B] 1A-1D show cross-sectional views of the channel region of an integrated circuit structure without an etched SAGE wall cap (left) and with a fully etched SAGE wall cap (right) according to an embodiment of the present disclosure.

[0013] [Figure 7C] 1A-1D show cross-sectional views of the channel regions of an integrated circuit structure without an etched SAGE wall cap (left) and an integrated circuit structure with a combination of partially etched and fully etched SAGE wall caps (right) in accordance with an embodiment of the present disclosure.

[0014] [Figure 7D] 1 shows a cross-sectional view through a source or drain region of an integrated circuit structure without an etched SAGE wall cap (left) and with a partially etched SAGE wall cap (right) according to an embodiment of the present disclosure.

[0015] [Figure 8A] 1 illustrates a cross-sectional view of a non-planar semiconductor device having a multiple self-aligned gate endcap (SAGE) isolation structure architecture according to an embodiment of the present disclosure.

[0016] [Figure 8B] 8B illustrates a plan view of the semiconductor device of FIG. 8A along axis aa' according to an embodiment of the present disclosure.

[0017] [Figure 9A] 1A-1D illustrate cross-sectional views of key process steps in a self-aligned gate endcap (SAGE) process fabrication scheme for another FinFET or Tri-Gate device according to an embodiment of the present disclosure. [Figure 9B] 1A-1D illustrate cross-sectional views of key process steps in a self-aligned gate endcap (SAGE) process fabrication scheme for another FinFET or Tri-Gate device according to an embodiment of the present disclosure. [Figure 9C] 1A-1D illustrate cross-sectional views of key process steps in a self-aligned gate endcap (SAGE) process fabrication scheme for another FinFET or Tri-Gate device according to an embodiment of the present disclosure.

[0018] [Figure 10] 1 illustrates a computing device according to one implementation of an embodiment of the present disclosure.

[0019] [Figure 11] 1 illustrates an interposer including one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] A self-aligned gate end cap (SAGE) architecture with reduced or eliminated cap and a method for manufacturing the self-aligned gate end cap (SAGE) architecture with reduced or eliminated cap are described. In the following description, numerous specific details are set forth, such as specific integration and material forms, to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as the design layout of integrated circuits, are not described in detail in order not to unnecessarily obscure the embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0021] Certain terminology may be used in the following description for reference purposes only and therefore is not intended to be limiting. For example, terms such as "upper," "lower," "upper," and "lower" refer to directions in the drawings to which reference is made. Terms such as "front," "rear," "back," and "side" describe the orientation and / or location of parts of a component within any frame of reference while remaining consistent. This will be made clear by reference to the text describing the component being described and the associated drawings. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0022] The embodiments described herein may relate to semiconductor processes and structures at the substrate end of line (FEOL). FEOL is the first part of integrated circuit (IC) manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned into a semiconductor substrate or layer. FEOL generally encompasses everything up to but not including the deposition of metal interconnect layers. After the last FEOL step, the result is typically a wafer with isolated (e.g., free of any wires) transistors.

[0023] The embodiments described herein may relate to semiconductor processes and structures at the back-end of the interconnect (BEOL). BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., one or more metallization layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-package connections. In the BEOL part of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. In modern IC processes, more than 10 metal layers can be added at the BEOL.

[0024] The embodiments described below may be applied to FEOL processes and structures, BEOL processes and structures, or both FEOL and BEOL processes and structures. In particular, while exemplary processing schemes may be illustrated using FEOL process scenarios, such approaches may also be applied to BEOL processes. Similarly, while exemplary processing schemes may be illustrated using BEOL process scenarios, such approaches may also be applied to FEOL processes.

[0025] One or more embodiments of the present disclosure relate to a semiconductor structure or device having one or more gate endcap structures. Additionally, a method for fabricating a gate endcap isolation structure in a self-aligned manner is also described. In one or more embodiments, a self-aligned gate endcap (SAGE) cap reduction is performed using a highly selective high-k dielectric material (HiK) etching process. The embodiments described herein may address issues associated with scaling end-to-end spacing of diffusions in ultra-scaling process technologies.

[0026] To provide broad context, state of the art approaches rely on gate end-to-end (poly cut) lithographic scaling to define the minimum technology gate diffusion overlap. The minimum technology gate diffusion overlap is a key factor in the diffusion end-to-end spacing. The associated gate line (poly cut) process is typically limited by lithography, alignment, and etch bias considerations, which ultimately set the minimum diffusion end-to-end distance. Other approaches, such as contact-over-active-gate (COAG) architectures, have worked to improve such diffusion spacing characteristics. However, there remains significant room for improvement in this technology area.

[0027] To provide a basis for highlighting the advantages of embodiments of the present disclosure, it should first be understood that advantages of the Self-Aligned Gate Endcap (SAGE) architecture over non-SAGE approaches may include achieving higher layout density, particularly diffusion scaling to diffusion spacing. By way of example, Figure 1 illustrates a plan view of adjacent integrated circuit structures of a conventional architecture having relatively wide spacing (left side (a)) contrasted with adjacent integrated circuit structures of a SAGE architecture having relatively narrow spacing according to embodiments of the present disclosure (right side (b)).

[0028] 1(a), the layout 100 includes a first integrated circuit structure 102 and a second integrated circuit structure 104, which are based on semiconductor fins 106 and 108, respectively. Each device 102 and 104 has a gate electrode 110 or 112, respectively. Additionally, each device 102 and 104 has a trench contact (TCN) 114 or 116, respectively, at the source and drain regions of the fins 106 and 108, respectively. Gate vias 118 and 120 and trench contact vias 119 and 121 are also shown.

[0029] 1(a), gate electrodes 110 and 112 each have a relatively wide end cap region 122 that is located away from the corresponding fins 106 and 108. TCNs 114 and 116 each have a relatively large end-to-end spacing 124 that is also located away from the corresponding fins 106 and 108, respectively.

[0030] Meanwhile, referring to the right side (b) of Figure 1, layout 150 includes a first integrated circuit structure 152 and a second integrated circuit structure 154, which are based on semiconductor fins 156 and 158, respectively. Each device 152 and 154 has a gate electrode 160 or 162, respectively. Additionally, each device 152 and 154 has a trench contact (TCN) 164 or 166, respectively, at the source and drain regions of fins 156 and 158, respectively. Gate vias 168 and 170 and trench contact vias 169 and 171 are also shown.

[0031] 1(b), gate electrodes 160 and 162 have relatively narrow end cap regions that are spaced apart from corresponding fins 156 and 158, respectively. Each TCN 164 and 166 has a relatively narrow end-to-end spacing 174 that is also spaced apart from corresponding fins 156 and 158, respectively.

[0032] To provide further context, scaling of gate endcap and trench contact (TCN) endcap regions is a significant contributor to the area and density improvement of transistor layouts. Gate and TCN endcap regions refer to the overlap of gate and TCN of diffusion regions / fins of a semiconductor device. As an example, FIG. 2 shows a top view of a conventional layout 200 including a fin-based semiconductor device including end-to-end spacing.

[0033] 2, a first semiconductor device 202 and a second semiconductor device 204 are based on semiconductor fins 206 and 208, respectively. Each device 202 and 204 has a gate electrode 210 or 212, respectively. Additionally, each device 202 and 204 has a trench contact (TCN) 214 or 216, respectively, at the source and drain regions of the fins 206 and 208, respectively. The gate electrodes 210 and 212 and the TCNs 214 and 216 each have an end cap region that is located away from the corresponding fin 206 and 208, respectively.

[0034] Referring back to FIG. 2, typically, the dimensions of the gate and TCN end caps must include a margin for mask alignment errors to ensure robust transistor operation against worst case mask misalignment, leaving an end-to-end spacing 218. Therefore, another important design rule that is critical to improve transistor layout density is the spacing between two adjacent end caps facing each other. However, the parameter "2*end cap + end-to-end spacing" is becoming increasingly difficult to scale using lithographic patterning to meet the scaling requirements of new technologies. In particular, the additional end cap length required to account for mask alignment errors also increases the gate capacitance value due to the longer overlap length between the TCN and gate electrode, thereby increasing the dynamic power consumption of the product and degrading performance. Conventional solutions have focused on improving alignment margins and patterning or improving resolution to enable the reduction of both the end cap dimensions and the end cap to end cap spacing.

[0035] According to an embodiment of the present disclosure, an approach is described that provides for self-aligned gate endcap (SAGE) and TCN overlap of a semiconductor fin without any mask alignment considerations. In one such embodiment, disposable spacers are fabricated on the semiconductor fin sidewalls, which determine the gate endcap and contact overlap dimensions. The spacer-defined endcap process allows the gate and TCN endcap regions to be self-aligned to the semiconductor fin, and thus does not require extra endcap length to account for mask misalignment. Furthermore, the approach described herein does not necessarily require lithographic patterning at a stage that was previously required, since the gate and TCN endcap / overlap dimensions remain fixed, resulting in improved (i.e., reduced) device-to-device variations in electrical parameters.

[0036] According to one or more embodiments of the present disclosure, scaling is achieved by reducing gate endcap overlap for diffusion by constructing SAGE walls. As an example, Figure 3 shows a cross section through a fin contrasting a conventional architecture (left side (a)) with a self-aligned gate endcap (SAGE) architecture (right side (b)) according to an embodiment of the present disclosure.

[0037] 3(a), an integrated circuit structure 300 includes a substrate 302 having a fin 304 protruding therefrom. The height (H Si ) 306 is set by an isolation structure 308 that laterally surrounds the bottom of the fin 304. Gate structures may be formed above the integrated circuit structure 300 for device fabrication. However, disruptions in such gate structures are addressed by increasing the spacing between the fins 304.

[0038] 3(b), an integrated circuit structure 350 includes a substrate 352 having a fin 354 protruding therefrom. The height (H Si ) 356 is set by an isolation structure 358 that laterally surrounds the bottom of the fin 354. Isolation SAGE walls 360 (which may include a hard mask thereon as shown) are included between adjacent fins 354 within isolation structure 358. The distance between isolation SAGE wall 360 and the immediately adjacent fin 354 defines a gate endcap spacing 362. Gate structures may be formed above integrated circuit structure 350 between isolation SAGE walls 360 to fabricate devices. Such gate structure separation is imposed by isolation SAGE walls 360. Because isolation SAGE walls 360 are self-aligned, constraints from conventional approaches may be minimized, allowing for more aggressive diffusion into the diffusion spacing. Furthermore, because the gate structure includes separation at all locations, individual gate structure portions may be layer connected by local interconnects formed above isolation SAGE walls 360.

[0039] To provide a side-by-side comparison, FIGS. 4A-4D show cross-sectional views of key process steps in a conventional FinFET or Tri-gate process fabrication scheme, and FIGS. 5A-5D show cross-sectional views of key process steps in a self-aligned gate endcap process fabrication scheme for a FinFET or Tri-gate device according to an embodiment of the present disclosure.

[0040] 4A and 5A, a bulk semiconductor substrate 400 or 500, such as a bulk single crystal silicon substrate, is provided having a fin 402 or 502, respectively, etched therein. In an embodiment, the fin is formed directly in the bulk substrate 400 or 500 and is thus continuous with the bulk substrate 400 or 500. It should be understood that shallow trench isolation structures may be formed between the fins in the substrate 400 or 500. With reference to FIG. 5A, a hard mask layer 504, such as a silicon nitride hard mask layer, and a pad oxide layer 506, such as a silicon dioxide layer, remain on the fin 502 after patterning to form the fin 502. With reference to FIG. 4A, however, such hard mask layer and pad oxide layer have been removed.

[0041] With reference to Figure 4B, a dummy or permanent gate dielectric layer 410 is formed on the exposed surface of the semiconductor fin 402, with a dummy gate layer 412 formed above the resulting structure, while with reference to Figure 5B, a dummy or permanent gate dielectric layer 510 is formed on the exposed surface of the semiconductor fin 502, with a dummy spacer 512 formed adjacent the resulting structure.

[0042] Referring to FIG. 4C, patterning is performed to cut the gate endcap, forming isolation regions 414 in the resulting patterned dummy gate end 416. In a conventional process scheme, a larger gate endcap must be fabricated to account for gate mask misalignment, as illustrated by the arrowed region 418. Meanwhile, referring to FIG. 5C, by providing an isolation layer above the structure of FIG. 5B, a self-aligned isolation region 514 is formed, for example, by deposition and planarization. In such an embodiment, the self-aligned gate endcap process does not require extra space for mask alignment, as compared in FIGS. 4C and 5C.

[0043] Referring to FIG. 4D, the dummy gate electrode 412 of FIG. 4C is replaced with a permanent gate electrode. If a dummy gate dielectric layer is used, such dummy gate dielectric layer may also be replaced by a permanent gate dielectric layer in this process. In the illustrated embodiment, a dual metal gate replacement process is performed to provide an N-type gate electrode 420 above the first semiconductor fin 402A and a P-type gate electrode 422 above the second semiconductor fin 402B. The N-type gate electrode 420 and the P-type gate electrode 422 are formed between the isolation regions 414, but form a P / N junction 424 where they meet. The exact location of the P / N junction 424 may vary depending on the misalignment, as illustrated by the arrowed region 426.

[0044] Meanwhile, referring to FIG. 5D, the hard mask layer 504 and the pad oxide layer 506 are removed and the dummy spacer 514 of FIG. 5C is replaced with a permanent gate electrode. If a dummy gate dielectric layer is used, such a dummy gate dielectric layer may also be replaced by a permanent gate dielectric layer in this process. In the illustrated embodiment, a dual metal gate replacement process is performed to provide an N-type gate electrode 520 above the first semiconductor fin 502A and a P-type gate electrode 522 above the second semiconductor fin 502B. The N-type gate electrode 520 and the P-type gate electrode 522 are formed between and separated by the gate end cap isolation structures 514.

[0045] Referring again to FIG. 4D, a local interconnect 440 may be fabricated to contact the N-type gate electrode 420 and the P-type gate electrode 422 to provide a conductive path around the P / N junction 424. Similarly, referring to FIG. 5D, a local interconnect 540 may be fabricated to contact the N-type gate electrode 520 and the P-type gate electrode 522 to provide a conductive path above the intervening isolation structure 514. Referring to both FIG. 4D and FIG. 5D, a hard mask 442 or 542 may be formed on the local interconnect 440 or 540, respectively. Referring specifically to FIG. 5D, in an embodiment, the continuity of the local interconnect 540 is interrupted by a dielectric plug 550 when a break is required at the electrical contact along the gate line.

[0046] According to one or more embodiments of the present disclosure, a self-aligned gate endcap (SAGE) process scheme includes the formation of a gate / trench contact endcap that is self-aligned to the fin without requiring extra length to account for mask misalignment. Thus, the embodiments may be implemented to enable area reduction of transistor layouts. The embodiments described herein may include the fabrication of a gate endcap isolation structure, which may also be referred to as a gate wall, an isolation gate wall, or a SAGE wall.

[0047] In another embodiment, a SAGE cap reduction, such as a high-k cap etch, is performed to reduce or remove the SAGE wall caps.

[0048] To provide context, the above-mentioned self-aligned gate edge (SAGE) architecture can be implemented for continuous cell height scaling while overcoming limitations in edge placement errors of lithography processes. As an example, FIG. 6 shows a layout of a 6T SRAM cell area with SAGE walls according to an embodiment of the present disclosure.

[0049] 6, a 6T SRAM layout 600 has a cell area with a cell height 602 and a cell length 604 within a SAGE wall 612. Within the cell area are a pair of fins (or nanowire stacks) 606. An active gate 608 and a non-active gate 610 are above the pair of fins (or nanowire stacks) 606.

[0050] As a benefit of the SAGE walls 612 in the 6T SRAM layout 600, the architecture can be implemented to remove the extra 10 nm margin for gate edge misalignment due to the lower walls. However, the SAGE walls 612 may need to withstand many different process sequences. To minimize the variations, a very durable material may be required at least as the cap of the SAGE walls. In one embodiment, such a cap is made of a high-k material such as hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium-zirconium oxide, HfNO, ZrNO, or HfZrNO. Such a material may be essential for process controllability. However, the high-k material and the associated tall gate metal layer may add a huge cost in the margin of capacitance associated with the active power. Any high-k material surrounding the channel and gate may contribute to the total capacitance. Therefore, it is important to reduce the high-k component as much as possible in the SAGE walls, which may be a balancing challenge.

[0051] In previous approaches, the lower portion of the SAGE wall is replaced with a low-k material. However, the upper high-k cap remains a significant contributor to capacitance near the device. According to one or more embodiments of the present disclosure, the unwanted high-k portion of the SAGE structure is reduced or removed after the gate and trench contact (TCN) metals are formed. The high-k (HiK) portion can be reduced or removed using a HiK etch process that is selective to Si, SiGe, oxide, nitride, and metal.

[0052] Benefits of implementing one or more embodiments described herein may include reducing capacitance while retaining the benefits of cell height scaling using SAGE, allowing optimal PPA (power, performance and area). It should be understood that the HiK etched in the SAGE post metal gate (MG) process or trench contact (TCN) process can be detected by XSEM and / or TEM. In an embodiment, at the channel location, the HiK portion of the SAGE structure is etched out or reduced or removed after the metal gate process is finished. Similarly, at the source or drain location, the HiK portion of the SAGE structure is etched out or reduced or removed after the TCN metal process. The etching process may be selective to the metal gate portion and / or the trench contact portion.

[0053] In a first example, FIG. 7A shows a cross-sectional view of a channel region of an integrated circuit structure without an etched SAGE wall cap (left side) and an integrated circuit structure with a partially etched SAGE wall cap (right side) in accordance with an embodiment of the present disclosure.

[0054] Referring to the left side of FIG. 7A, an integrated circuit structure 700 without an etched SAGE wall cap includes a substrate 702 having a fin 704 thereon or thereover. A lower portion of the fin 704 is surrounded by a shallow trench isolation structure 706, and an upper portion of the fin 704 protrudes above the shallow trench isolation structure 706. A gate stack 708 is respectively above one or more fins 704, e.g., above each of a pair of fins 704. Each gate stack 708 may include a gate dielectric, such as a high-k gate dielectric, and a metal gate electrode having an exposed top surface. SAGE walls 710 are on the sides and between the gate stacks 708. Each SAGE wall 710 has a high-k dielectric cap layer 714 on a low-k dielectric wall 712. The high-k dielectric cap layer 714 has a top surface 715 and a bottom surface 713. The local conductive interconnect 716 electrically couples the exposed upper surfaces of the metal gate electrodes of adjacent gate stacks 708 and extends above the intervening SAGE walls (middle portions 710). The local conductive interconnect 716 has a top surface 719 and a bottom surface 717. The bottom surface 717 of the local conductive interconnect 716 is below the top surface 715 of the high-k dielectric cap layer 714 of the SAGE walls 710.

[0055] Referring to the right side of FIG. 7A, an integrated circuit structure 720 with a partially etched SAGE wall cap includes a substrate 702 having a fin 704 thereon or thereover. A lower portion of the fin 704 is surrounded by a shallow trench isolation structure 706, and an upper portion of the fin 704 protrudes above the shallow trench isolation structure 706. A gate stack 708 is respectively above one or more fins 704, e.g., above each of a pair of fins 704. Each gate stack 708 may include a gate dielectric, such as a high-k gate dielectric, and a metal gate electrode having an exposed top surface. SAGE walls 722 are on the sides and between the gate stacks 708. Each SAGE wall 722 has a high-k dielectric cap layer 724 on the low-k dielectric wall 712. The high-k dielectric cap layer 724 has a top surface 725.

[0056] Referring again to the right side of FIG. 7A, according to an embodiment of the present disclosure, an integrated circuit structure 720 includes a first gate electrode (left side 708) above a first semiconductor fin (one of a pair of fins 704 on the left side). A second gate electrode (right side 708) is above the second semiconductor fin (one of a pair of fins 704 on the right side). A gate end cap isolation structure (middle portion 722) is between the first gate electrode (left side 708) and the second gate electrode (right side 708). The gate end cap isolation structure 722 has a high-k dielectric cap layer 724 on the low-k dielectric wall 712. A local interconnect 726 is on the first gate electrode (left side 708), on the high-k dielectric cap layer (middle portion 724), and on the second gate electrode (right side 708). The local interconnect 726 has a bottom surface 727 above a top surface 725 of the high-k dielectric cap layer (middle portion 724).

[0057] In one embodiment, the first gate electrode (left side 708) and the second gate electrode (right side 708) each have a top surface that is coplanar with a top surface 725 of the high-k dielectric cap layer (middle portion 724) of the gate endcap isolation structure (middle portion 722). In one embodiment, a local interconnect 726 electrically connects the first gate electrode (left side 708) and the second gate electrode (right side 708). In one embodiment, the gate endcap isolation structure (middle portion 722) includes a vertical seam in its center within the low-k dielectric wall 712, e.g., as described below in connection with FIG. 9C.

[0058] In a second example, FIG. 7B shows a cross-sectional view of the channel region of an integrated circuit structure without an etched SAGE wall cap (left side) and an integrated circuit structure with a fully etched SAGE wall cap (right side) in accordance with an embodiment of the present disclosure.

[0059] Referring to the left side of FIG. 7B, an integrated circuit structure 700 without etched SAGE wall caps is as described above in connection with FIG. 7A. Referring to the right side of FIG. 7B, an integrated circuit structure 730 with fully etched / removed SAGE wall caps includes a substrate 702 having a fin 704 thereon or thereover. A lower portion of the fin 704 is surrounded by a shallow trench isolation structure 706, and an upper portion of the fin 704 protrudes above the shallow trench isolation structure 706. A gate stack 708 is respectively above one or more fins 704, e.g., above each of a pair of fins 704. Each gate stack 708 may include a gate dielectric, such as a high-k gate dielectric, and a metal gate electrode having an exposed top surface. SAGE walls 732 are on the sides and between the gate stacks 708. Each SAGE wall 732 includes only a low-k dielectric wall 734. The local conductive interconnect 736 electrically couples the exposed top surfaces of the metal gate electrodes of adjacent gate stacks 708 and extends above the intervening SAGE walls (middle portions 732). In one embodiment, the bottom surface of the local conductive interconnect is planar throughout the local conductive interconnect 736, as shown.

[0060] In a third example, FIG. 7C shows a cross-sectional view of the channel region of an integrated circuit structure without an etched SAGE wall cap (left side) and an integrated circuit structure with a combination of partially etched and fully etched SAGE wall caps (right side) in accordance with an embodiment of the present disclosure.

[0061] Referring to the left side of FIG. 7C, an integrated circuit structure 700 without etched SAGE wall caps is as described above in connection with FIG. 7A. Referring to the right side of FIG. 7C, an integrated circuit structure 740 with both partially etched and fully etched SAGE wall caps includes a substrate 702 having a fin 704 thereon or thereover. A lower portion of the fin 704 is surrounded by a shallow trench isolation structure 706, and an upper portion of the fin 704 protrudes above the shallow trench isolation structure 706. A gate stack 708 is respectively above one or more fins 704, e.g., above each of a pair of fins 704. Each gate stack 708 may include a gate dielectric, such as a high-k gate dielectric, and a metal gate electrode having an exposed top surface. SAGE walls 742A are on the sides of the gate stacks 708, and SAGE walls 742B are between the gate stacks 708. Each SAGE wall 742A has a high-k dielectric cap layer 744 on the low-k dielectric wall. The high-k dielectric cap layer 744 has a top surface 745 and a bottom surface 743. The SAGE wall 742B has only a low-k dielectric wall 746. A local conductive interconnect 748 electrically couples the exposed top surfaces of the metal gate electrodes of adjacent gate stacks 708 and extends above the intervening SAGE wall 742B. The local conductive interconnect 748 has a bottom surface 742 and a top surface 749. The bottom surface 742 of the local conductive interconnect 748 is coplanar with the bottom surface 743 of the high-k dielectric cap layer 744. The top surface 749 of the local conductive interconnect 748 is above the top surface 745 of the high-k dielectric cap layer 744 of the SAGE wall 742A. In one embodiment, the bottom surface 742 of the local conductive interconnect 748 is planar across the entirety of the local conductive interconnect 748, as shown.

[0062] FIG. 7D shows a cross-sectional view through a source or drain region of an integrated circuit structure without an etched SAGE wall cap (left) and an integrated circuit structure with a partially etched SAGE wall cap (right) in accordance with an embodiment of the present disclosure.

[0063] Referring to the left side of FIG. 7D, an integrated circuit structure 750 without an etched SAGE wall cap includes a substrate 702 having a fin 704 thereon or thereover. A lower portion of the fin 704 is surrounded by a shallow trench isolation structure 706, and an upper portion of the fin 704 protrudes above the shallow trench isolation structure 706. A conductive trench contact 756 is above each of the one or more fins 704, e.g., above an epitaxial source or drain structure 752 / 754 above each of a pair of fins 704. The epitaxial source or drain structures 752 and 754 may have opposite electrical conductivity. SAGE walls 710 flank and between the conductive trench contacts 756. Each SAGE wall 710 has a high-k dielectric cap layer 714 on a low-k dielectric wall 712. The local conductive interconnect 758 electrically couples the exposed top surfaces of adjacent conductive trench contacts 756 and extends above the intervening SAGE walls (middle portions 710). The local conductive interconnect 716 has a bottom surface below the top surface of the high-k dielectric cap layer 714 of the SAGE walls 710.

[0064] Referring to the right side of FIG. 7D, an integrated circuit structure 760 with a partially etched SAGE wall cap includes a substrate 702 having a fin 704 thereon or thereover. A lower portion of the fin 704 is surrounded by a shallow trench isolation structure 706, and an upper portion of the fin 704 protrudes above the shallow trench isolation structure 706. A conductive trench contact 756 (which may be included in a dielectric 757) is above each of the one or more fins 704, e.g., above an epitaxial source or drain structure 752 / 754 above each of a pair of fins 704. The epitaxial source or drain structures 752 and 754 may have opposite electrical conductivity. SAGE walls 722 flank and between the conductive trench contacts 756. Each SAGE wall 722 has a high-k dielectric cap layer 724 on the low-k dielectric wall 712. The high-k dielectric cap layer 724 has a top surface 725. The local conductive interconnect 762 electrically couples the exposed top surfaces of adjacent conductive trench contacts 756 and extends above the intervening SAGE walls (middle portions 722). The local conductive interconnect 762 has a bottom surface 761 and a top surface 763. The bottom surface 761 of the local conductive interconnect 762 is above the top surface 725 of the high-k dielectric cap layer 724 of the SAGE walls 722. In one embodiment, the bottom surface 761 of the local conductive interconnect 762 is planar throughout the local conductive interconnect 762, as shown.

[0065] Referring again to the right side of FIG. 7D, according to an embodiment of the present disclosure, an integrated circuit structure 760 includes a first trench contact (left side 756) over a first epitaxial structure 752 over a first semiconductor fin (one of the fins 704 of the left fin pair). A second trench contact (right side 756) is over a second epitaxial structure 754 over a second semiconductor fin (one of the fins 704 of the right fin pair). A gate endcap isolation structure (middle portion 722) is between the first trench contact (left side 756) and the second trench contact (right side 756). The gate endcap isolation structure (middle portion 722) has a high-k dielectric cap layer 724 on the low-k dielectric wall 712. The local interconnect 756 is on the first trench contact (756 on the left), on the high-k dielectric cap layer 724, and on the second trench contact (756 on the right). The local interconnect 762 has a bottom surface 761 above the top surface 725 of the high-k dielectric cap layer 724.

[0066] In one embodiment, the first trench contact (left side 756) and the second trench contact (right side 756) each have a top surface that is coplanar with the top surface 725 of the high-k dielectric cap layer 724 of the gate endcap isolation structure (middle portion 722). In one embodiment, a local interconnect 762 electrically connects the first trench contact (left side 756) and the second trench contact (right side 756). In one embodiment, the gate endcap isolation structure (middle portion 722) includes a vertical seam in its center within the low-k dielectric wall 712, e.g., as described below in connection with FIG. 9C.

[0067] In another aspect, the SAGE walls may vary in width, location, and function for different devices. In an exemplary implementation, system-on-chip (SoC) process technology typically requires support of standard logic (e.g., low voltage, thin oxide) and I / O (e.g., high voltage, thick oxide) transistors. The distinction between standard logic and high voltage (HVI / O) devices may be achieved by a multi-oxide process sequence, where logic transistors receive a thin high performance oxide and I / O devices receive a thick oxide capable of withstanding higher voltages. As process technology scales, logic devices scale aggressively in dimensions, creating manufacturing challenges associated with the formation of dual oxides. According to one or more embodiments of the present disclosure, a high voltage endcap process is combined with an ultra-scaling FinFET transistor architecture to provide a multi-self-aligned endcap process in which at least some, if not all, of the SAGE structures are fabricated without fin endcaps.

[0068] To provide context, as technology nodes scale smaller, narrow endcap logic devices experience an increasing lack of geometric space to accommodate defect-free dual oxide processes that may be required for high-voltage transistor fabrication. Current approaches rely on a single, unscaled endcap space to accommodate a single logic oxide process. However, such processes may not be compatible with the large scaled geometries that support dual oxide high-voltage SoC technologies, since the endcap space may be insufficient to accommodate both oxides (gate dielectrics).

[0069] According to embodiments of the present disclosure, scaling limitations imposed by the requirement to fill high-voltage gates with both high-voltage oxide and logic oxide are addressed. In particular, as logic dimensions decrease, the endcap space in high-voltage (HV) devices becomes insufficiently narrow to fill both oxides. In embodiments, different endcap spaces between logic transistors and high-voltage transistors are fabricated with SAGE architecture, respectively. The endcaps of the logic transistors are ultra-scaled by using a self-aligned endcap architecture, and the high-voltage transistors have wider endcaps to accommodate the thicker gate dielectric. Either or both types of endcaps can be fabricated without fin endcaps according to embodiments described herein.

[0070] One or more embodiments described herein may relate to or be referred to as a multi-directional-unidirectional endcap process flow for ultra-scaling logic endcaps. To provide context, in a typical SAGE flow, a single endcap spacer is deposited to form a self-aligned endcap that separates the fins from the SAGE walls. The embodiments described herein may include the formation of different sacrificial spacer thicknesses between the logic and HV gates. The self-aligned endcap walls are then formed. Different spacer widths are selected to be thicker in the high voltage areas, and a standard thickness is used in the logic areas. The different spacer widths may allow the high voltage oxide to be successfully deposited without sacrificing density in the logic areas. In an embodiment, the different spacer thicknesses follow the intended HV oxide thickness.

[0071] As an example of a completed device, Figure 8A shows a cross-sectional view of a non-planar semiconductor device having a multiple self-aligned gate endcap isolation structure architecture according to an embodiment of the present disclosure, and Figure 8B shows a top view along axis a-a' of the structure of Figure 8A according to an embodiment of the present disclosure.

[0072] Referring to FIG. 8A, a semiconductor structure 800 includes a non-planar active region (e.g., a fin structure each including a protruding fin portion 804 and a sub-fin region 805) formed in a trench isolation layer 806 from a substrate 802. In an embodiment, the fin structure is a plurality of fin lines forming a lattice structure, such as a tight pitch lattice structure. In one such embodiment, the tight pitch is not directly achievable by conventional lithography. For example, a pattern based on conventional lithography may be formed first, but the pitch may be divided into two using spacer mask patterning as known in the art. Furthermore, the original pitch may be divided into four by a second spacer mask patterning. Thus, the lattice fin pattern may have lines spaced at a constant pitch and having a constant width. The pattern may be manufactured by pitch division into two or pitch division into four, or by other pitch division approaches. Each of the illustrated individual fins 804 may represent a corresponding individual fin, or may represent multiple fins at a particular location.

[0073] A gate structure 808 overlies the overhanging portion 804 of the non-planar active area and overlies a portion of the trench isolation layer 806. As shown, the gate structure 808 includes a gate electrode 850 and a gate dielectric layer 852. In one embodiment, although not shown, the gate structure 808 may include a dielectric cap layer.

[0074] The gate structures 808 are separated by narrow self-aligned gate endcap (SAGE) isolation structures or walls 820, 821A or 821B. The SAGE walls 820 each have a width. In an embodiment, the SAGE wall 821A has a width greater than the respective width of the SAGE walls 820, and the SAGE wall 821B has a width less than the respective width of the SAGE walls 820. The different widths of the SAGE walls may be associated with different device types, as described in the exemplary embodiments herein. It should be understood that the variation in width of the SAGE walls is reconfigurable. Also, in other embodiments, the widths are all the same. Each of the SAGE walls 820, 821A or 821B may include one or more of the local interconnects 854 or dielectric plugs 899 formed thereon. In an embodiment, each of the SAGE walls 820, 821A or 821B is recessed below a top surface 897 of the trench isolation layer 806, as illustrated in FIG. 8A.

[0075] According to an embodiment of the present disclosure, SAGE wall 821A is formed at the location of the cut fin. In a particular embodiment, SAGE wall 821A is formed above cut portion 869 of the fin, as shown. In an embodiment, SAGE walls 820, 821A and 821B are fabricated after the fin cutting process.

[0076] In an exemplary embodiment, the semiconductor structure 800 includes a first plurality of semiconductor fins (fin or fins 804 in region 870A) above the substrate 802 and protruding through a top surface 897 of the trench isolation layer 806, and a first gate structure (gate structure 808 in region 870A) above the first plurality of semiconductor fins. A second plurality of semiconductor fins (fin or fins 804 in region 870B) is above the substrate 802 and protruding through a top surface 897 of the trench isolation layer 806, and a second gate structure (gate structure 808 in region 870B) is above the second plurality of semiconductor fins. A gate endcap isolation structure (to the left of the SAGE wall 820) is between and in contact with the first and second gate structures. A semiconductor fin of the first plurality of semiconductor fins closest to the gate endcap isolation structure (from region 870A) is farther away from the gate endcap isolation structure than a semiconductor fin of the second plurality of semiconductor fins closest to the gate endcap isolation structure (from region 870B).

[0077] In an embodiment, region 870A is an I / O region and region 870B is a logic region. As shown, in one such embodiment, a second logic region 870C is adjacent to logic region 870B and is electrically connected to logic region 870B by local interconnect 854. Another region 870D may be a location where additional logic or I / O regions may be placed. The embodiments described herein may include different spacing from the SAGE walls (e.g., wider spacing from SAGE wall 821B and left hand side 820 of region 870A), or may include SAGE walls of different widths (e.g., narrower 821B vs. 820 vs. wider 821A), or both different spacing from the SAGE walls and different widths of SAGE walls. In an embodiment, the I / O regions have a larger spacing between the SAGE walls than the logic regions. In an embodiment, wider SAGE walls are between adjacent logic regions than between adjacent I / O regions.

[0078] The gate contact 814 and an overlying gate contact via 816 can also be seen in this perspective along with an overlying metal interconnect 860, all in an interlayer dielectric stack or layer 870. As can also be seen from the perspective of Figure 8A, in one embodiment, the gate contact 814 is above a non-planar active region. As also shown in Figure 8A, there is a boundary 880 in the doping profile between the protruding fin portion 804 and the sub-fin region 805, although other embodiments do not include such a boundary in the doping profile between these regions.

[0079] Referring to FIG. 8B, a gate structure 808 is shown above the protruding fin portion 804 and separated by a self-aligned gate endcap isolation structure 820. In an embodiment, the gate structure 808 forms one of a plurality of parallel gate lines forming a lattice structure, such as a tight pitch lattice structure. In one such embodiment, the tight pitch is not directly achievable by conventional lithography. For example, a pattern based on conventional lithography may be formed first, but the pitch may be divided by two using spacer mask patterning as known in the art. Furthermore, the original pitch may be divided by four by a second spacer mask patterning. Thus, the lattice gate pattern may have lines spaced at a constant pitch and with a constant width. The pattern may be fabricated by pitch division by two or pitch division by four, or by other pitch division approaches.

[0080] 8B, the source and drain regions 804A and 804B of the protruding fin portion 804 are shown in this perspective view, but it should be understood that these regions overlap the trench contact structure. In one embodiment, the source and drain regions 804A and 804B are doped portions of the original material of the protruding fin portion 804. In another embodiment, the material of the protruding fin portion 804 is removed and replaced with another semiconductor material, for example by epitaxial growth. In either case, the source and drain regions 804A and 804B may extend below the height of the trench isolation layer 806, i.e., into the sub-fin region 805.

[0081] In an embodiment, the semiconductor structure 800 includes a non-planar device, such as, but not limited to, a FinFET or a tri-gate device. In such an embodiment, the corresponding semiconductor channel region is comprised of or formed in a three-dimensional object. In one such embodiment, the gate structure 808 surrounds at least a top surface and a pair of sidewalls of the three-dimensional object.

[0082] The substrate 802 may be made of a semiconductor material that can withstand the manufacturing process and in which charge can be transferred. In an embodiment, the substrate 802 is a bulk substrate made of a crystalline silicon, silicon / germanium, or germanium layer doped with charge carriers, such as, but not limited to, phosphorus, arsenic, boron, or combinations thereof, to form the active region 804. In one embodiment, the concentration of silicon atoms in the bulk substrate 802 is greater than 97%. In another embodiment, the bulk substrate 802 is made of an epitaxial layer grown on a separate crystalline substrate, for example, a silicon epitaxial layer grown on a bulk silicon single crystal substrate doped with boron. Alternatively, the bulk substrate 802 may be made of a III-V material. In an embodiment, the bulk substrate 802 is comprised of a III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, gallium indium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. In one embodiment, the bulk substrate 802 is comprised of a III-V material and the charge carrier dopant impurity atoms are, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0083] The trench isolation layer 806 may be comprised of any suitable material that ultimately electrically isolates or contributes to the isolation of portions of a permanent gate structure from the underlying bulk substrate, or isolates active areas formed in the underlying bulk substrate, such as isolating the active areas of a fin. For example, in one embodiment, the trench isolation layer 806 is comprised of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0084] The self-aligned gate end cap isolation structures 820, 821A and 821B may be of any suitable material or materials that electrically isolate or contribute to the isolation of portions of the ultimately permanent gate structure from one another. Exemplary materials or combinations of materials include single material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or combinations of materials include multi-layer stacks having a bottom silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and a top portion of a high dielectric constant material such as hafnium oxide. Additional examples are described below in connection with Figures 9A-9C.

[0085] The gate structure 808 may comprise a gate electrode stack including a gate dielectric layer 852 and a gate electrode layer 850. In an embodiment, the gate electrode of the gate electrode stack comprises a metal gate and the gate dielectric layer comprises a high-k material.

[0086] In an exemplary embodiment, the gate structure 808 in region 870A includes a first gate dielectric 852 conformal to the first plurality of semiconductor fins and laterally adjacent to and in contact with a first side (left hand 820) of the gate end cap isolation structure. The second gate stack in region 870B includes a second gate dielectric 852 conformal to the second plurality of semiconductor fins and laterally adjacent to and in contact with a second side of the gate end cap isolation structure opposite the first side of the gate end cap isolation structure. In one embodiment, the first gate dielectric is thicker than the second gate dielectric, as illustrated in FIG. 8A. In one embodiment, the first gate dielectric has more dielectric layers (e.g., layers 852A and 852B) than the second gate dielectric (e.g., only layer 852). In an embodiment, the gate dielectric in region 870A is an I / O gate dielectric and the gate dielectric in region 870B is a logic gate dielectric.

[0087] In an embodiment, the gate dielectric in region 870B is made of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, lead zinc niobate, or combinations thereof. Additionally, a portion of the gate dielectric layer may include a layer of native oxide formed from some upper layer of the substrate 802. In an embodiment, the gate dielectric layer is made of an upper high-k portion and a lower portion made of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is made of an upper portion of hafnium oxide and a lower portion of silicon dioxide or silicon oxynitride. In an embodiment, the upper high-k portion is made of a "U" shaped structure including a lower portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the upper surface of the substrate. In an embodiment, the gate dielectric in region 870A includes a layer of non-native silicon oxide in addition to a layer of high-k material. The layer of non-native silicon oxide may be formed using a CVD process and may be formed below or above the layer of high-k material. In an exemplary embodiment, a layer of non-native silicon oxide (e.g., layer 852A) is formed below a layer of high-k material (e.g., layer 852B).

[0088] In one embodiment, the gate electrode is comprised of a metal layer, such as, but not limited to, a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In a specific embodiment, the gate electrode is comprised of a non-work function setting fill material formed above a metal work function setting layer. In some implementations, the gate electrode may be comprised of a "U" shaped structure with a lower portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the upper surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a flat layer that is substantially parallel to the upper surface of the substrate and does not include sidewall portions substantially perpendicular to the upper surface of the substrate. In further implementations of the present disclosure, the gate electrode may be comprised of a combination of U-shaped and planar, non-U-shaped structures. For example, the gate electrode may be comprised of one or more U-shaped metal layers formed above one or more planar, non-U-shaped layers.

[0089] The spacers associated with the gate electrode stack may be made of any suitable material that ultimately electrically isolates or contributes to the isolation of the permanent gate structure from adjacent conductive contacts, such as self-aligned contacts, etc. For example, in one embodiment, the spacers are made of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0090] The local interconnect 854, the gate contact 814, the overlying gate contact via 816, and the overlying metal interconnect 860 may be comprised of a conductive material. In an embodiment, one or more of the contacts or vias are comprised of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy, such as an intermetallic alloy or a metal-semiconductor alloy (e.g., a silicide material, etc.). A common example is the use of copper structures that may or may not include a barrier layer (such as a Ta or TaN layer) between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect line may include a barrier layer, a stack of different metals or alloys, etc.

[0091] In an embodiment (not shown), providing structure 800 involves the formation of a contact pattern that is substantially perfectly aligned with an existing gate pattern, but eliminates the use of a lithography step with very tight alignment tolerances. In one such embodiment, this approach allows for the use of an inherently highly selective wet etch (e.g., versus a conventionally implemented dry or plasma etch) to create the contact openings. In an embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithography step. In one such embodiment, the present approach allows for the elimination of the need for a separate critical lithography step to create the contact pattern, as used in conventional approaches. In an embodiment, the trench contact grid is formed between the poly (gate) lines, rather than being separately patterned. For example, in one such embodiment, the trench contact grid is formed after the gate grid patterning and prior to the gate grid cutting.

[0092] Additionally, the gate structure 808 may be fabricated by a replacement gate process. In such a scheme, dummy gate material, such as polysilicon or silicon nitride pillar material, may be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, rather than being carried over from a previous process. In an embodiment, the dummy gate is removed by a dry or wet etching process. In one embodiment, the dummy gate is made of polycrystalline silicon or amorphous silicon and is removed by a dry etching process including the use of SF6. In another embodiment, the dummy gate is made of polycrystalline silicon or amorphous silicon and is removed by a wet etching process including the use of NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is made of silicon nitride and is removed by a wet etching process including an aqueous phosphoric acid solution.

[0093] In an embodiment, one or more approaches described herein substantially contemplate a dummy and replacement gate process in combination with a dummy and replacement contact process to arrive at structure 800. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for a high temperature anneal of at least a portion of the permanent gate stack. For example, in such a specific embodiment, the anneal of at least a portion of the permanent gate structure is performed at a temperature greater than about 600 degrees Celsius, for example, after the gate dielectric layer is formed. The anneal is performed prior to the formation of the permanent contact.

[0094] Referring again to FIG. 8A, in an embodiment, a semiconductor device has a contact structure that contacts a portion of a gate electrode formed above an active region. Typically, prior to (e.g., in addition to) forming a gate contact structure (such as a via) above the active portion of the gate and in the same layer as the trench contact via, one or more embodiments of the present disclosure include first using a gate-aligned trench contact process. Such a process may be implemented to form trench contact structures for the manufacture of semiconductor structures, e.g., integrated circuits. In an embodiment, a trench contact pattern is formed to match an existing gate pattern. Meanwhile, conventional approaches typically include additional lithography processes with critical alignment of the lithographic contact pattern to the existing gate pattern, combined with selective contact etching. For example, conventional processes may include patterning of a poly(gate) grid along with separate patterning of contact features.

[0095] It should be understood that SAGE walls of varying widths may be fabricated, as illustrated in Figures 8A and 8B. It should also be understood that fabrication of the gate endcap isolation structure may lead to seam formation within the gate endcap isolation structure. It should also be understood that a stack of dielectric layers may be used to form the SAGE walls. It should also be understood that the gate endcap isolation structure may vary in composition depending on the spacing of adjacent fins. As an example that encompasses all such aspects, Figures 9A-9C show cross-sectional views of key process steps in another self-aligned gate endcap process fabrication scheme for FinFET or tri-gate devices according to embodiments of the present disclosure.

[0096] 9A , the group of fins 900 has a spacing 906. The group of fins 900 is adjacent to a fin 902 at a larger spacing 904. A sacrificial spacer 916 is formed adjacent a sidewall of the top of each of the multiple semiconductor fins 900 and 902.

[0097] Referring to FIG. 9B, a plurality of gate end cap isolation structures 926 and 950 are formed between sacrificial spacers 916. For purposes of this description, at least some of the SAGE walls shown are fabricated after the fin saw process. In an embodiment, as shown, each of the plurality of gate end cap isolation structures 926 formed between the spacings 906 includes a lower dielectric portion 928 and a dielectric cap 930 on the lower dielectric portion 928. In an embodiment, the plurality of gate end cap isolation structures 926 are formed by depositing and then recessing a first dielectric material, such as a silicon nitride layer, to provide the lower dielectric portion 928. The deposition process, in one embodiment, may be a conformal process that provides a seam 932 in the lower dielectric portion 928. Thus, in an embodiment, each of the plurality of gate end cap isolation structures 926 includes a vertical seam 932 at a center within the gate end cap isolation structure 926. A dielectric cap material, such as a metal oxide material (e.g., hafnium oxide), is then formed in the recessed area above the lower dielectric portion 928. The dielectric cap material may be planarized to form the dielectric cap 930 or may be grown upward to provide the dielectric cap 930 directly.

[0098] Referring again to FIG. 9B, in an embodiment, the gate endcap isolation structure 926 is between the semiconductor fins with a spacing 906, and the gate endcap isolation structure 950 is between the semiconductor fins with a spacing 904. The gate endcap isolation structure 926 has a width that is narrower than the corresponding width of the gate endcap isolation structure 950. In one embodiment, the gate endcap isolation structure 926 has an overall composition that is different from the overall composition of the gate endcap isolation structure 950. In one such embodiment, the gate endcap isolation structure 950 further includes a third dielectric layer 956, such as a silicon oxide layer, on a lower portion of the lower dielectric portion 952 and in its sidewalls. Additionally, a dielectric cap 954 is on the third dielectric layer 956. In an embodiment, as illustrated in FIG. 9B, the sidewalls of the lower dielectric portion 952 have a top surface that is approximately coplanar with a top surface of the third dielectric layer 956, and the dielectric cap 954 has a substantially planar bottom surface. In another embodiment, the sidewalls of the lower dielectric portion 952 have a top surface below the top surface of the third dielectric layer 956, and the dielectric cap 954 extends further down above the location of the sidewalls. In yet another embodiment, the sidewalls of the lower dielectric portion 952 have a top surface above the top surface of the third dielectric layer 956, and the dielectric cap 954 extends further down above the third dielectric layer 956.

[0099] In an embodiment, the deposition process of the third dielectric layer 956 is a conformal process that, in one embodiment, provides a vertical seam 958 in the third dielectric layer 956. However, in another embodiment, the seam 958 is not formed in the wider features, but is formed in the narrower features (e.g., seam 932 described above). It should be understood that the lower dielectric portions 928 and 952 may be of the same material, such as silicon nitride, and may be formed simultaneously with one another. It should also be understood that the dielectric caps 930 and 954 may be of the same material, such as hafnium oxide, and may be formed simultaneously with one another. Although omitted from structure 926, the third dielectric layer 956 of structure 950 may be formed by conformal deposition throughout the structure, but the lower dielectric portion 928 is excluded from structure 926 because it substantially fills the space 906 in a first deposition process that does not completely fill the space 904.

[0100] 9C, the sacrificial spacers 916 are removed. In an embodiment, the sacrificial spacers 916 are removed by a wet or dry etching process. In an embodiment, the patterning of the stack layers above the fins is also removed to provide the fins 900' and 902'.

[0101] Referring again to FIG. 9C, in an embodiment, the gate endcap isolation structure 926 or 950 is in a corresponding recess below a top surface of the trench isolation layer. In an embodiment, the gate endcap isolation structure 926 or 950 includes a lower dielectric portion and a dielectric cap on the lower dielectric portion. In an embodiment, the gate endcap isolation structure 926 or 950 includes a vertical seam in the center within the second gate endcap isolation structure. In an embodiment, the first gate endcap isolation structure 926 differs in overall composition from the overall composition of the second gate endcap isolation structure 950, for example, by including additional filler dielectric material.

[0102] In an embodiment in which the gate endcap isolation structure 926 or 950 includes a lower dielectric portion and a dielectric cap on the lower dielectric portion, the gate endcap isolation structure 926 or 950 may be formed by first depositing and then recessing a first dielectric material, such as a SiN, SiCN, SiOCN, SiOC, or SiC layer, to provide the lower dielectric portion. In one embodiment, the first dielectric material is a silicon nitride layer. A dielectric cap material, such as a metal oxide material (e.g., hafnium oxide, hafnium-aluminum oxide, or aluminum oxide), is then formed in the recessed area above the lower dielectric portion. In one embodiment, the metal oxide material is hafnium oxide. In another embodiment, the dielectric cap material is a low-k dielectric material. The dielectric cap material may be planarized to form the dielectric cap or may be grown upward to directly provide the dielectric cap.

[0103] One or more embodiments described above relate to cap reduction or removal for SAGE walls of FinFET devices. It should be understood that other embodiments may include applying such approaches to fins consisting of alternating layers of two dissimilar semiconductor materials (e.g., Si and SiGe, or SiGe and Ge). One of the pair of dissimilar semiconductor materials can then be removed in the gate region, thereby providing a nanowire / nanoribbon channel for the gate-all-around device. In embodiments, the approach to gate-all-around devices is similar to the above-mentioned approach to FinFETs, with the addition of a release step of the nanowires / ribbons in the gate region.

[0104] In embodiments, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxide (e.g., silicon dioxide (SiO2)), doped silicon oxide, fluorinated silicon oxide, carbon-doped silicon oxide, various low-k dielectric materials known in the art, and combinations thereof. ILD materials can be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition methods.

[0105] In embodiments, as also used throughout this specification, metal line or interconnect line material (and via material) is comprised of one or more metals or other conductive structures. A common example is the use of copper lines and structures that may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect line may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, and the like. Thus, the interconnect line may be a single material layer or may be formed from multiple layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, may be used to form the interconnect line. In embodiments, the interconnect lines are made of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Mo, Ag, Au, or alloys thereof, and are sometimes referred to in the art as traces, wires, lines, metals, or simply interconnects.

[0106] In an embodiment, as also used throughout this specification, the hardmask material, cap layer, or plug is made of a different dielectric material than the interlayer dielectric material. In an embodiment, different hardmask, cap, or plug materials may be used in different regions to provide different growth or etch selectivities to each other and to the underlying dielectric and metal layers. In some embodiments, the hardmask layer, cap, or plug layer includes a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hardmask, cap, or plug layers known in the art may be used. The hardmask, cap, or plug layer may be formed by CVD, PVD, or other deposition methods.

[0107] In an embodiment, as also used throughout this specification, the lithography process is performed using 193 nm immersion lithography (i193), EUV and / or EBDW lithography, etc. Positive or negative resists may be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In certain such embodiments, the topography masking portion is a carbon hard mask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer.

[0108] The embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphic processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories may be manufactured. Additionally, integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the art. For example, they may be used in computer systems (e.g., desktops, laptops, servers), mobile phones, personal electronic devices, and the like. The integrated circuits may be coupled with buses and other components in the system. For example, a processor may be coupled with a memory, a chipset, and the like by one or more buses. Each of the processor, memory, and chipset may potentially be manufactured using the approaches disclosed herein.

[0109] 10 illustrates a computing device 1000 according to one implementation of an embodiment of the present disclosure. The computing device 1000 houses a board 1002. The board 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006. The processor 1004 is physically and electrically coupled to the board 1002. In some implementations, the at least one communication chip 1006 is also physically and electrically coupled to the board 1002. In further implementations, the communication chip 1006 is part of the processor 1004.

[0110] Depending on the application, computing device 1000 may include other components that may or may not be physically and electrically coupled to board 1002. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, Global Positioning System (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0111] The communications chip 1006 enables wireless communications for the transfer of data to and from the computing device 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data through the use of modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated devices do not include any wires, which in some embodiments may not. The communications chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and beyond. The computing device 1000 may include multiple communication chips 1006. For example, a first communication chip 1006 may be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip 1006 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, and Ev-DO.

[0112] The processor 1004 of the computing device 1000 includes an integrated circuit die packaged within the processor 1004. The integrated circuit die of the processor 1004 may include one or more structures, such as a self-aligned gate endcap (SAGE) structure constructed according to implementations of embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that may be stored in registers and / or memory.

[0113] The communications chip 1006 also includes an integrated circuit die packaged within the communications chip 1006. The integrated circuit die of the communications chip 1006 may include one or more structures, such as a self-aligned gate endcap (SAGE) structure, constructed in accordance with implementations of embodiments of the present disclosure.

[0114] In a further implementation, another component contained within computing device 1000 may include an integrated circuit die that includes one or more structures such as a self-aligned gate endcap (SAGE) structure constructed in accordance with an implementation of an embodiment of the present disclosure.

[0115] In various implementations, computing device 1000 may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further implementations, computing device 1000 may be any other electronic device that processes data.

[0116] FIG. 11 illustrates an interposer 1100 that includes one or more embodiments of the present disclosure. The interposer 1100 is an intervening substrate used to bridge a first substrate 1102 and a second substrate 1104. The first substrate 1102 may be, for example, an integrated circuit die. The second substrate 1104 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. In general, the purpose of the interposer 1100 is to spread connections to a wider pitch or to reroute connections to different connections. For example, the interposer 1100 may bond an integrated circuit die to a ball grid array (BGA) 1106 that may then be bonded to the second substrate 1104. In some embodiments, the first substrate and the second substrate 1102 / 1104 are attached to opposite sides of the interposer 1100. In other embodiments, the first substrate and the second substrate 1102 / 1104 are attached to the same side of the interposer 1100. And in further embodiments, three or more substrates are interconnected by the interposer 1100.

[0117] The interposer 1100 may be formed of a polymeric material such as epoxy, fiberglass reinforced epoxy, ceramic material, or polyimide, etc. In further implementations, the interposer 1100 may be formed of alternating rigid or flexible materials, which may include the same materials mentioned above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0118] The interposer 1100 may include metal interconnects 1108 and vias 1110, including but not limited to through silicon vias (TSVs) 1112. The interposer 1100 may further include embedded devices 1114, including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on the interposer 1100. According to an embodiment of the present disclosure, an apparatus or process disclosed herein may be used in the manufacture of the interposer 1100 or components included in the interposer 1100.

[0119] Accordingly, embodiments of the present disclosure include self-aligned gate endcap (SAGE) architectures with reduced or eliminated caps, and methods for fabricating self-aligned gate endcap (SAGE) architectures with reduced or eliminated caps.

[0120] The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Specific implementations and examples of the disclosure are described herein for illustrative purposes, but various equivalent modifications are possible within the scope of the disclosure, as those skilled in the art will recognize.

[0121] These variations may be made to the disclosure in light of the detailed description above. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and claims. Rather, the scope of the disclosure should be determined solely by the following claims, which should be construed in accordance with established doctrines of claim interpretation.

[0122] Exemplary embodiment 1: An integrated circuit structure includes a first gate electrode above a first semiconductor fin. A second gate electrode is above a second semiconductor fin. A gate endcap isolation structure is between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a high-k dielectric cap layer on the low-k dielectric wall. A local interconnect is on the first gate electrode, on the high-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottom surface above a top surface of the high-k dielectric cap layer.

[0123] Exemplary embodiment 2: the integrated circuit structure as described in exemplary embodiment 1, wherein the first gate electrode and the second gate electrode each have a top surface coplanar with a top surface of the high-k dielectric cap layer of the gate endcap isolation structure.

[0124] Exemplary Embodiment 3: The integrated circuit structure of Exemplary Embodiment 1 or 2, wherein the local interconnect electrically connects the first gate electrode and the second gate electrode.

[0125] Exemplary embodiment 4: The integrated circuit structure of exemplary embodiment 1, 2 or 3, wherein the gate endcap isolation structure includes a vertical seam in the center within the low-k dielectric wall.

[0126] Exemplary embodiment 5: An integrated circuit structure includes a first trench contact over a first epitaxial structure over a first semiconductor fin. A second trench contact is over a second epitaxial structure over a second semiconductor fin. A gate endcap isolation structure is between the first trench contact and the second trench contact, the gate endcap isolation structure having a high-k dielectric cap layer on the low-k dielectric wall. A local interconnect is over the first trench contact, over the high-k dielectric cap layer, and over the second trench contact, the local interconnect having a bottom surface above a top surface of the high-k dielectric cap layer.

[0127] Exemplary embodiment 6: The integrated circuit structure as described in exemplary embodiment 5, wherein the first trench contact and the second trench contact each have a top surface coplanar with a top surface of the high-k dielectric cap layer of the gate endcap isolation structure.

[0128] Exemplary embodiment 7: The integrated circuit structure of exemplary embodiment 5 or 6, wherein the local interconnect electrically connects the first trench contact and the second trench contact.

[0129] Exemplary embodiment 8: The integrated circuit structure of exemplary embodiment 5, 6 or 7, wherein the gate endcap isolation structure includes a vertical seam in the center within the low-k dielectric wall.

[0130] Exemplary embodiment 9: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure. The integrated circuit structure includes a first gate electrode above a first semiconductor fin. A second gate electrode is above a second semiconductor fin. A gate end cap isolation structure is between the first gate electrode and the second gate electrode, the gate end cap isolation structure having a high-k dielectric cap layer on the low-k dielectric wall. A local interconnect is on the first gate electrode, on the high-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottom surface above a top surface of the high-k dielectric cap layer.

[0131] Exemplary embodiment 10: The computing device of exemplary embodiment 9, further comprising a memory coupled to the board.

[0132] Exemplary embodiment 11: The computing device of exemplary embodiment 9 or 10, further comprising a communications chip coupled to the board.

[0133] Exemplary embodiment 12: The computing device of exemplary embodiment 9, 10 or 11, further comprising a camera coupled to the board.

[0134] Exemplary embodiment 13: The computing device of exemplary embodiment 9, 10, 11 or 12, wherein the component is a packaged integrated circuit die.

[0135] Exemplary embodiment 14: The computing device of exemplary embodiment 9, 10, 11, 12 or 13, wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desktop computer, a server, and a set-top box.

[0136] Exemplary embodiment 15: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure. The integrated circuit structure includes a first trench contact over a first epitaxial structure over a first semiconductor fin. A second trench contact is over a second epitaxial structure over a second semiconductor fin. A gate end cap isolation structure is between the first trench contact and the second trench contact, the gate end cap isolation structure having a high-k dielectric cap layer on the low-k dielectric wall. A local interconnect is over the first trench contact, over the high-k dielectric cap layer, and over the second trench contact, the local interconnect having a bottom surface above a top surface of the high-k dielectric cap layer.

[0137] Exemplary embodiment 16: The computing device of exemplary embodiment 15, further comprising a memory coupled to the board.

[0138] Exemplary embodiment 17: The computing device of exemplary embodiment 15 or 16, further comprising a communications chip coupled to the board.

[0139] Exemplary embodiment 18: The computing device of exemplary embodiment 15, 16 or 17, further comprising a camera coupled to the board.

[0140] Exemplary embodiment 19: The computing device of exemplary embodiment 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0141] Exemplary embodiment 20: The computing device of exemplary embodiment 15, 16, 17, 18 or 19, wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desktop computer, a server, and a set-top box. Other possible aspects [Item 1] a first gate electrode over the first semiconductor fin; a second gate electrode over the second semiconductor fin; a gate endcap isolation structure between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a high-k dielectric cap layer on a low-k dielectric wall; a local interconnect on the first gate electrode, on the high-k dielectric capping layer, and on the second gate electrode, the local interconnect having a bottom surface above a top surface of the high-k dielectric capping layer; 1. An integrated circuit structure comprising: [Item 2] 2. The integrated circuit structure of claim 1, wherein the first gate electrode and the second gate electrode each have a top surface coplanar with the top surface of the high-k dielectric cap layer of the gate endcap isolation structure. [Item 3] Item 1. The integrated circuit structure of item 1, wherein the local interconnect electrically connects the first gate electrode and the second gate electrode. [Item 4] Item 2. The integrated circuit structure of item 1, wherein the gate endcap isolation structure has a vertical seam centered within the low k dielectric wall. [Item 5] a first trench contact over the first epitaxial structure over the first semiconductor fin; a second trench contact over the second epitaxial structure over the second semiconductor fin; and a gate endcap isolation structure between the first trench contact and the second trench contact, the gate endcap isolation structure having a high-k dielectric cap layer on a low-k dielectric wall; a local interconnect on the first trench contact, on the high-k dielectric capping layer, and on the second trench contact, the local interconnect having a bottom surface above a top surface of the high-k dielectric capping layer; 1. An integrated circuit structure comprising: [Item 6] 6. The integrated circuit structure of claim 5, wherein the first trench contact and the second trench contact each have a top surface coplanar with the top surface of the high-k dielectric cap layer of the gate endcap isolation structure. [Item 7] Item 6. The integrated circuit structure of item 5, wherein the local interconnect electrically connects the first trench contact and the second trench contact. [Item 8] Item 6. The integrated circuit structure of item 5, wherein the gate endcap isolation structure has a vertical seam centered within the low k dielectric wall. [Item 9] Board and a component coupled to the board, the component including an integrated circuit structure; A computing device comprising: The integrated circuit structure comprises: a first gate electrode over the first semiconductor fin; a second gate electrode over the second semiconductor fin; a gate endcap isolation structure between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a high-k dielectric cap layer on a low-k dielectric wall; a local interconnect on the first gate electrode, on the high-k dielectric capping layer, and on the second gate electrode, the local interconnect having a bottom surface above a top surface of the high-k dielectric capping layer; 1. A computing device comprising: [Item 10] 10. The computing device of claim 9, further comprising a memory coupled to the board. [Item 11] 10. The computing device of claim 9, further comprising a communications chip coupled to the board. [Item 12] 10. The computing device of claim 9, further comprising a camera coupled to the board. [Item 13] 10. The computing device of claim 9, wherein the component is a packaged integrated circuit die. [Item 14] 10. The computing device of claim 9, wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desktop computer, a server, and a set-top box. [Item 15] Board and a component coupled to the board, the component including an integrated circuit structure; A computing device comprising: The integrated circuit structure comprises: a first trench contact over the first epitaxial structure over the first semiconductor fin; a second trench contact over the second epitaxial structure over the second semiconductor fin; and a gate endcap isolation structure between the first trench contact and the second trench contact, the gate endcap isolation structure having a high-k dielectric cap layer on a low-k dielectric wall; a local interconnect on the first trench contact, on the high-k dielectric capping layer, and on the second trench contact, the local interconnect having a bottom surface above a top surface of the high-k dielectric capping layer; 1. A computing device comprising: [Item 16] Item 16. The computing device of item 15, further comprising a memory coupled to the board. [Item 17] Item 16. The computing device of item 15, further comprising a communications chip coupled to the board. [Item 18] Item 16. The computing device of item 15, further comprising a camera coupled to the board. [Item 19] Item 16. The computing device of item 15, wherein the component is a packaged integrated circuit die. [Item 20] Item 16. The computing device of item 15, wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desktop computer, a server, and a set-top box.

Claims

1. A first fin; a first epitaxial source or drain structure overlying the first fin and having a first conductivity type; a second fin spaced laterally from the first fin; a second epitaxial source or drain structure overlying the second fin and having a second conductivity type opposite the first conductivity type; a gate endcap wall between and laterally spaced from the first fin and the second fin; a trench isolation structure laterally adjacent a lower portion of the first fin, a lower portion of the second fin, and a lower portion of the gate endcap wall, the trench isolation structure having a lower surface below a lowermost surface of the gate endcap wall; a local conductive interconnect above the first epitaxial source or drain structure, above the gate endcap wall, and above the second epitaxial source or drain structure; 1. An integrated circuit structure comprising:

2. a second gate endcap wall spaced laterally from a side of the first fin opposite the gate endcap wall; The integrated circuit structure of claim 1 further comprising:

3. a third gate endcap wall spaced laterally from a side of the second fin opposite the gate endcap wall; The integrated circuit structure of claim 2 further comprising:

4. 4. The integrated circuit structure of claim 3, wherein the second gate endcap wall and the third gate endcap wall each have a dielectric cap layer.

5. a first conductive trench contact in a vertical direction between the first epitaxial source or drain structure and the local conductive interconnect; 5. The integrated circuit structure of claim 1 further comprising:

6. a second conductive trench contact in a vertical direction between the second epitaxial source or drain structure and the local conductive interconnect; The integrated circuit structure of claim 5 further comprising:

7. The integrated circuit structure of claim 1 , wherein the local conductive interconnect is in contact with the gate endcap wall.

8. A first fin; an N-type epitaxial source or drain structure overlying the first fin; a second fin spaced laterally from the first fin; a P-type epitaxial source or drain structure overlying the second fin; a gate endcap wall between and laterally spaced from the first fin and the second fin; a first trench isolation region between a bottom portion of the first fin and the gate endcap wall; a second trench isolation region between a lower portion of the second fin and the gate endcap wall, wherein a bottom surface of the gate endcap wall does not extend beyond a bottom surface of the first trench isolation region and a bottom surface of the second trench isolation region; a conductor above the N-type epitaxial source or drain structure, above the gate endcap wall, and above the P-type epitaxial source or drain structure; 1. An integrated circuit structure comprising:

9. a second gate endcap wall spaced laterally from a side of the first fin opposite the gate endcap wall; The integrated circuit structure of claim 8 further comprising:

10. a third gate endcap wall spaced laterally from a side of the second fin opposite the gate endcap wall; 10. The integrated circuit structure of claim 9 further comprising:

11. 11. The integrated circuit structure of claim 10, wherein the second gate endcap wall and the third gate endcap wall each have a dielectric cap layer.

12. a first conductive trench contact in a vertical direction between the N-type epitaxial source or drain structure and the conductive body; 12. The integrated circuit structure of claim 8, further comprising:

13. A second conductive trench contact is formed vertically between the P-type epitaxial source or drain structure and the conductive body. The integrated circuit structure of claim 12 further comprising:

14. A first nanowire; a first epitaxial source or drain structure coupled to the first nanowire and having a first conductivity type; a second nanowire spaced laterally from the first nanowire; a second epitaxial source or drain structure coupled to the second nanowire and having a second conductivity type opposite the first conductivity type; a gate endcap wall between and laterally spaced from the first nanowire and the second nanowire; a trench isolation structure laterally adjacent a lower portion of the gate endcap wall and having a lower surface below a lower surface of the gate endcap wall; a local conductive interconnect above the first epitaxial source or drain structure, above the gate endcap wall, and above the second epitaxial source or drain structure; 1. An integrated circuit structure comprising:

15. a second gate endcap wall laterally spaced from a side of the first nanowire opposite the gate endcap wall; 15. The integrated circuit structure of claim 14 further comprising:

16. a third gate endcap wall laterally spaced from a side of the second nanowire opposite the gate endcap wall; 20. The integrated circuit structure of claim 15 further comprising:

17. 17. The integrated circuit structure of claim 16, wherein the second gate endcap wall and the third gate endcap wall each have a dielectric cap layer.

18. a first conductive trench contact in a vertical direction between the first epitaxial source or drain structure and the local conductive interconnect; 18. The integrated circuit structure of claim 14, further comprising:

19. a second conductive trench contact in a vertical direction between the second epitaxial source or drain structure and the local conductive interconnect; 20. The integrated circuit structure of claim 18 further comprising:

20. 20. The integrated circuit structure of claim 14, wherein the local conductive interconnect is in contact with the gate endcap wall.

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