Apparatus comprising comparator devices and operating method therefor

Abstract

To provide an apparatus comprising comparator devices and an operating method therefor.SOLUTION: An apparatus is provided, comprising at least a first comparator device configured to compare a first input current with a first reference current and, based on the comparison, to output a first output current to a second comparator device. The first output current corresponds to a difference between the first reference current and the first input current if the first input current is smaller than the first reference current, and the first output current corresponds to a difference between the first input current and the first reference current if the first input current is greater than or equal to the first reference current.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to an apparatus comprising at least one first comparator device configured to compare a first input current with a first reference current. The present disclosure further relates to a method for operating such an apparatus. Summary of the Invention [Means for solving the problem]

[0002] An exemplary embodiment relates to an apparatus comprising at least one first comparator device configured to compare a first input current with a first reference current and to output a first output current to a second comparator device based on the comparison, where if the first input current is smaller than the first reference current, the first output current corresponds to the difference between the first reference current and the first input current, and if the first input current is equal to or greater than the first reference current, the first output current corresponds to the difference between the first input current and the first reference current. In further exemplary embodiments, this makes it possible to provide, for example, a current-based, e.g. current-driven, analog-to-digital converter device and / or to avoid abrupt changes in the value of at least the first output current. For example, a comparator device of the apparatus can be provided at each stage of the analog-to-digital converter device.

[0003] In a further exemplary embodiment, it is contemplated that an apparatus comprises n comparator devices, wherein a kth (k=1, ..., n-1) comparator device is configured to compare a kth input current available or supplied with a kth reference current and, based on the comparison, output a kth output current to the (k+1)th comparator device, wherein if the kth input current is smaller than the kth reference current, the kth output current corresponds to a difference between the kth reference current and the kth input current, and if the kth input current is equal to or greater than the kth reference current, the kth output current corresponds to a difference between the kth input current and the kth reference current.

[0004] In further exemplary embodiments, it is contemplated that at least the first comparator device, e.g., some or all of the n comparator devices, are configured to output a comparison result, e.g., in the form of a binary signal, based on the comparison. In further exemplary embodiments, where the apparatus is usable or used to provide, e.g., an analog-to-digital converter device, the comparison result may, e.g., characterize a bit of a binary value.

[0005] In a further illustrative embodiment, it is contemplated that the first comparator device comprises a first circuit node for receiving a first input current and a first reference current device, the first reference current device being configured to derive a first reference current from the first circuit node, for example a kth (k=1, ..., n) comparator device comprising a respective first circuit node for receiving the kth input current and a kth reference current device, the kth reference current device being configured to derive the kth reference current from the first circuit node of the kth comparator device.

[0006] In further exemplary embodiments, it is contemplated that, for example, when the first input current is smaller than the first reference current, the first reference current device is configured to provide, at least temporarily, the first output current, and, for example, when the kth input current is smaller than the kth reference current, the kth reference current device is configured to provide, at least temporarily, the kth output current.

[0007] In further exemplary embodiments, it is contemplated that the first comparator device comprises a first differential current providing device, e.g., when the first input current is greater than or equal to the first reference current, the first differential current providing device is configured to provide a first output current, at least temporarily, and that, e.g., the kth comparator device comprises a kth differential current providing device, e.g., when the kth input current is greater than or equal to the kth reference current, the kth differential current providing device is configured to provide a kth output current, at least temporarily.

[0008] In a further exemplary embodiment, it is contemplated that the first comparator device comprises a second circuit node for outputting the first output current to the second comparator device, e.g., the kth comparator device comprises a second circuit node for outputting the kth output current to the (k+1)th comparator device.

[0009] In a further exemplary embodiment, an element for potential isolation is provided between the first circuit node and the second circuit node, and for example, it is contemplated that the element for potential isolation comprises at least one of the following elements: a) a diode, b) a transistor, so that in a further exemplary embodiment, for example, signals or potentials related to respective comparison results of mutually connected comparator devices can be isolated from each other.

[0010] In further exemplary embodiments, it is contemplated that the first comparator device comprises a third circuit node for receiving the first input current, for example the kth comparator device comprises a third circuit node for receiving the kth input current. In further exemplary embodiments, it is contemplated that the second circuit node of the first comparator device is connectable or connected to the third circuit node of the second comparator device, thereby for example being able to provide the first output current of the first comparator device as a second input current to the second comparator device. In further exemplary embodiments, this principle can also be applied to multiple further, for example all, comparator devices of the apparatus.

[0011] In a further exemplary embodiment, an element for potential isolation is provided between the first circuit node and the third circuit node, for example it is contemplated that the element for potential isolation comprises a transistor, for example a field effect transistor configured as a source follower. This allows for potential isolation of, for example, serially connected comparator devices connected to one another, which can improve the accuracy of the operation of, for example, an optional current mirror device in at least one of the comparator devices when used.

[0012] In a further exemplary embodiment, it is contemplated that the first reference current device comprises a transistor, for example a field effect transistor, and the load path of the transistor is connected between the first circuit node of the first comparator device and the first reference potential. This allows the reference current to be efficiently provided in the further exemplary embodiment. In a further exemplary embodiment, the current strength of the reference current can be predetermined or influenced by at least one of the following factors: a) control of the transistor; b) a dimension of at least one component of the transistor, for example the gate width in the case of a field effect transistor.

[0013] In a further exemplary embodiment, it is contemplated that the first differential current providing device comprises a first transistor, e.g., a field effect transistor, and the load path of the first transistor is connected between the second circuit node of the first comparator device and the one or above first reference potentials.

[0014] In a further exemplary embodiment, it is contemplated that the first transistor of the first differential current providing device is controllable based on the potential of the first circuit node of the first comparator device, i.e., for example, based on the comparison result of the first comparator device. For example, the first transistor of the first differential current providing device can form a current mirror device together with the second transistor of the first differential current providing device, which current mirror device is controllable, for example, based on the potential of the first circuit node of the first comparator device, for example, by the third transistor of the first differential current providing device. In this way, as soon as the first input current exceeds the first reference current, thus causing a potential change at the first circuit node, it can be effectively caused that the first transistor of the first differential current providing device provides the first output current from then on.

[0015] Further exemplary embodiments relate to an analog / digital converter device, for example a current-driven analog / digital converter device, comprising at least one apparatus according to the embodiment. In further exemplary embodiments, each one comparator device of the apparatus can correspond to one stage of the analog / digital converter device. Thus, in further exemplary embodiments, a multi-stage, for example n-stage (n>1), analog / digital converter device can be realized based on the apparatus comprising n comparator devices, for example electrically connected in series with each other, for example a first output current of a first comparator device can be provided as a second input current to a second comparator device, and so on.

[0016] In a further exemplary embodiment, it is contemplated that at least one apparatus as defined in any one of claims 2 to 12 is configured, wherein each of the n comparator devices is associated with a value setting of the analog-to-digital converter device, and each reference current of the n comparator devices is respectively associated with a value setting of each comparator device.

[0017] In further exemplary embodiments, different reference currents, e.g. for different comparator devices, or stages of an analog-to-digital converter device, may be provided by at least one of: a) separate reference current sources; b) current mirror devices.

[0018] In a further exemplary embodiment, an analog / digital converter device is configured to convert the first input current into a digital, e.g., binary, quantity, where it is contemplated, for example, that the digital quantity has a Gray coding.

[0019] In a further exemplary embodiment, it is contemplated that a transcoding device is provided, the transcoding device being configured to transcode Gray-coded digital quantities into binary-coded quantities.

[0020] Further exemplary embodiments relate to a computing device, e.g. for determining a scalar product, e.g. a vector matrix multiplier, e.g. a dot product engine, comprising a matrix of elements having controllable electrical resistance and at least one analog-to-digital converter device according to an embodiment.

[0021] A further exemplary embodiment relates to a method for operating an apparatus comprising at least one first comparator device configured to compare a first input current with a first reference current and output a first output current to a second comparator device based on the comparison, where if the first input current is less than the first reference current, the first output current corresponds to a difference between the first reference current and the first input current, and if the first input current is equal to or greater than the first reference current, the first output current corresponds to a difference between the first input current and the first reference current, the method comprising the steps of comparing the first input current with the first reference current and outputting the first output current to the second comparator device.

[0022] Further exemplary embodiments relate to the use of an apparatus according to an embodiment, and / or an analog-to-digital converter device according to an embodiment, and / or a computing device according to an embodiment, and / or a method according to an embodiment for at least one of the following: a) converting a current to a binary value; b) performing binary coding; c) performing Gray coding; d) providing, for example, a fully current-driven analog-to-digital converter; e) avoiding abrupt changes in the value of at least a first output current.

[0023] Further features, possible applications and advantages of the invention will become apparent from the following description of exemplary embodiments of the invention as illustrated in the figures of the drawing, in which all features described or illustrated, individually or in any combination, form the subject of the invention, regardless of their summary or their relationship in the claims, and regardless of their expression or illustration in the text or in the drawings. [Brief description of the drawings]

[0024] [Figure 1] FIG. 1 is a simplified schematic block diagram according to an example embodiment. [Diagram 2] 1 is a simplified schematic flow chart according to an exemplary embodiment; [Diagram 3] 1 is a simplified schematic flow chart according to an exemplary embodiment; [Figure 4A] FIG. 4A is a simplified schematic block diagram according to an example embodiment. [Figure 4B] FIG. 4B is a simplified schematic block diagram according to an example embodiment. [Figure 5A] FIG. 5A is a simplified schematic block diagram according to an example embodiment. [Figure 5B] FIG. 5B is a simplified schematic block diagram according to an example embodiment. [Figure 6] FIG. 2 is a simplified schematic circuit diagram according to an example embodiment. [Figure 7] FIG. 2 is a simplified schematic timing diagram according to an example embodiment. [Figure 8] FIG. 2 is a simplified schematic circuit diagram according to an example embodiment. [Figure 9] FIG. 1 is a simplified schematic block diagram according to an example embodiment. [Figure 10] FIG. 2 is a simplified schematic circuit diagram according to an example embodiment. [Figure 11] FIG. 2 is a simplified schematic circuit diagram according to an example embodiment. [Figure 12] FIG. 1 is a simplified schematic block diagram according to an example embodiment. [Figure 13] 1 is a schematic diagram illustrating a mode of use according to an exemplary embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] An exemplary embodiment (FIG. 1) provides an apparatus 100 comprising at least one first comparator device 110-1 configured to compare a first input current I_in-1 with a first reference current I_ref-1 (see also block 200 according to FIG. 2) and to output a first output current I_out-1 to a second comparator device 110-2 (FIG. 1) based on the comparison 200 (see also block 202 according to FIG. 2), where the first input current I_in-1 is compared to the first reference current I_ref-1. The device 100 relates to a first output current I_out-1 corresponding to the difference I_ref-1-I_in-1 between the first reference current I_ref-1 and the first input current I_in-1 when the first input current I_in-1 is smaller than the first reference current I_ref-1, and the first output current I_out-1 corresponding to the difference I_in-1-I_ref-1 between the first input current I_in-1 and the first reference current I_ref-1 when the first input current I_in-1 is equal to or greater than the first reference current I_ref-1. In further exemplary embodiments, this makes it possible to provide, for example, a current-based, for example current-driven, analog-to-digital converter device and / or to avoid at least abrupt changes in the value of the first output current. For example, each stage of the analog-to-digital converter device can be provided with a comparator device 110-1, 110-2, ... of the device 100.

[0026] In further exemplary embodiments, various circuit-technical implementations of the device 100, which is shown in a simplified and schematic manner by way of example in Fig. 1, are conceivable. Thus, for example, the first output current I_out-1 can be a positive or negative current (both current directions are possible), for example depending on the circuit-technical implementation. Thus, the "output" of the output current I_out-1 can include the output of a positive or negative current. This can also apply to further output currents (described below), such as, for example, further comparator devices 110-2, ...

[0027] In a further exemplary embodiment (FIG. 1), the second comparator device 110-2 comprises a similar function to the first comparator device 110-1, e.g., a first output current I_out-1 of the first comparator device 110-1 generates an input current I_in-2 of the second comparator device 110-2, etc. According to a further exemplary embodiment, the above-mentioned principles are applicable for n>1 comparator devices (see the vertical dot symbols in FIG. 1).

[0028] Thus, in a further exemplary embodiment, the apparatus 100 comprises n (n≧2) comparator devices 110-1, 110-2, ..., 110-n, such that the k-th (k=1, ..., n-1) comparator device 110-k compares the k-th available or supplied input current I_in-k with the k-th reference current I_ref-k (see also block 210 according to FIG. 3 ) and outputs the k-th output current I_out-k to the (k+1)-th comparator device (not shown) based on the comparison 210 (see also block 212 according to FIG. 3 ). It is intended that when the kth input current I_in-k is smaller than the kth reference current I_ref-k, the kth output current I_out-k corresponds to the difference I_ref-k-I_in-k between the kth reference current I_ref-k and the kth input current I_in-k, and when the kth input current I_in-k is equal to or greater than the kth reference current I_ref-k, the kth output current I_out-k corresponds to the difference I_in-k-I_ref-k between the kth input current I_in-k and the kth reference current I_ref-k.

[0029] In a further exemplary embodiment (FIG. 1), it is contemplated that at least the first comparator device 110-1, e.g. some or all of the n comparator devices 110-1, ..., 110-n, are configured to output a comparison result VE-1 (FIG. 2), VE-k (FIG. 3), e.g. in the form of a binary signal, based on the comparison 200, 210. In a further exemplary embodiment, e.g. where the apparatus 100 is usable or used to provide an analog-to-digital converter device, the comparison result VE-1, VE-k may characterize bits of a binary value, for example.

[0030] In a further illustrative embodiment (FIG. 4A), it is contemplated that the first comparator device 110-1 comprises a first circuit node 112-1-N1 for receiving a first input current I_in-1 and a first reference current device 114-1 configured to derive a first reference current I_ref-1 from the first circuit node 112-1-N1, for example to a first reference potential BP1-1 of the first comparator device 110-1.

[0031] In a further exemplary embodiment (FIG. 4B), it is contemplated that the kth comparator device 110-k (k=1, ..., n) comprises a respective first circuit node 112-k-N1 for receiving the kth input current I_in-k and a kth reference current device 114-k, the kth reference current device 114-k being configured to derive the kth reference current I_ref-k from the first circuit node 112-k-N1 of the kth comparator device 110-k, for example to a first reference potential BP1-k of the kth comparator device 110-k.

[0032] In a further exemplary embodiment (FIG. 4A), it is contemplated that, for example, when the first input current I_in-1 is smaller than the first reference current I_ref-1, the first reference current device 114-1 is configured to, at least temporarily, provide the first output current I_out-1, and, for example, when the kth input current I_in-k is smaller than the kth reference current I_ref-k, the kth reference current device (FIG. 4B) is configured to, at least temporarily, provide the kth output current I_out-k.

[0033] In a further exemplary embodiment (FIG. 5A), it is contemplated that the first comparator device 110-1 comprises a first differential current providing device 115-1, and when the first input current I_in-1 is greater than or equal to the first reference current I_ref-1, the first differential current providing device 115-1 is configured to provide, at least temporarily, a first output current I_out-1, e.g., the kth comparator device 110-k (k=1, ..., n) (FIG. 5B) comprises a kth differential current providing device 115-k, and when, e.g., the kth input current I_in-k is greater than or equal to the kth reference current I_ref-k, the kth differential current providing device 115-k is configured to provide, at least temporarily, the kth output current I_out-k.

[0034] In a further exemplary embodiment (FIG. 5A), it is contemplated that the first comparator device 110-k has a second circuit node 112-1-N2 for outputting the first output current I_out-1 to the second comparator device 110-2, and that, for example, the kth comparator device 110-k (FIG. 5B) has a second circuit node 112-k-N2 for outputting the kth output current I_out-k to the (k+1)th comparator device (not shown).

[0035] In further exemplary embodiments (FIGS. 5A, 5B), an element 116-1 or 116-k for potential isolation is provided between the first circuit node 112-1-N1 or 112-k-N1 and the second circuit node 112-1-N2 or 112-k-N2, and it is contemplated that the element 116-1, 116-k for potential isolation comprises at least one of the following elements: a) a diode; b) a transistor. In this way, in further exemplary embodiments, signals or potentials associated with the respective comparison results of the mutually connected comparator devices, which occur at the circuit nodes 112-1-N1 or 112-k-N1 and 112-1-N2 or 112-k-N2, can be isolated from each other.

[0036] In a further illustrative embodiment (FIG. 5A), it is contemplated that the first comparator device 110-1 has a third circuit node 112-1-N3 for receiving the first input current I_in-1, and that, for example, the kth comparator device 110-k (FIG. 5B) has a third circuit node 112-k-N3 for receiving the kth input current I_in-k.

[0037] In a further exemplary embodiment, it is contemplated that the second circuit node 112-1-N2 of the first comparator device 110-1 can be connected or is connected to a third circuit node (not shown) of the second comparator device 110-2, thereby, for example, being able to provide the first output current I_out-1 of the first comparator device 110-1 as a second input current I_in-2 to the second comparator device 110-2. In a further exemplary embodiment, this principle can also be applied to multiple further, e.g., all, comparator devices 110-1, ..., 110-n of the apparatus 100 (FIG. 1).

[0038] In further exemplary embodiments (FIGS. 5A, 5B), an element 117-1 or 117-k for potential isolation is provided between the first circuit node 112-1-N1 or 112-k-N1 and the third circuit node 112-1-N3 or 112-k-N3, for example, it is contemplated that the element for potential isolation comprises a transistor, for example a field effect transistor configured as a source follower (see, for example, element 117-1a according to FIG. 6). This allows for potential isolation of, for example, mutually connected, for example series-connected comparator devices, which can improve the accuracy of the operation of, for example, an optional current mirror device in at least one of the comparator devices when used.

[0039] 6 shows a simplified circuit diagram of an apparatus 100a according to a further exemplary embodiment, with two comparator devices 110-1, 110-2 connected in series with each other as an example. Optionally, the apparatus 100a comprises further comparator devices (not shown in FIG. 6) and / or other components, which are represented by dashed lines on the right side of FIG. 6.

[0040] The apparatus 100a according to FIG. 6 is capable of supplying an input current to the third circuit node 112-1-N3 of the first comparator device 110-1 as a first input current I_in-1 for the first comparator device 110-1, and the first comparator device 110-1 compares the first input current I_in-1 with a first reference current I_ref-1 and provides a potential characterizing the comparison result as an output signal out1 to the first circuit node 112-1-N1.

[0041] In a further exemplary embodiment (FIG. 6), it is contemplated that the first reference current device 114-1 comprises a transistor 114-1a, e.g. a field effect transistor, with the load path (drain-source path) of the transistor 114-1a being connected between the first circuit node 112-1-N1 of the first comparator device 110-1 and the first reference potential BP1-1. This allows the first reference current I_ref-1 to be efficiently provided in the further exemplary embodiment. In the further exemplary embodiment, the current strength of the first reference current I_ref-1 can be predetermined or influenced by at least one of the following factors: a) control of the transistor 114-1a; b) a dimension of at least one component of the transistor 114-1a, e.g. a gate width in the case of a field effect transistor.

[0042] In a further exemplary embodiment, the transistor 114-1a may be part, eg, an output, of a current mirror device that provides the first reference current I_ref-1. In a further illustrative embodiment (FIG. 6), it is intended that the first differential current providing device 115-1 comprises a first transistor 115-1a, e.g., a field effect transistor, and the load path of the first transistor 115-1a is connected between the second circuit node 112-1-N2 of the first comparator device 110-1 and one or the above first reference potentials BP1-1.

[0043] In a further illustrative embodiment, it is contemplated that the first transistor 115-1a of the first differential current providing device 115-1 is controllable based on the potential of the first circuit node 112-1-N1 of the first comparator device 110-1, i.e., for example, based on the comparison result of the first comparator device 110-1.

[0044] For example, the first transistor 115-1a of the first differential current providing device 115-1 may form a current mirror device together with the second transistor 115-1b of the first differential current providing device 115-1, which current mirror device is controllable, for example, by the third transistor 115-1c of the first differential current providing device 115-1 based on, for example, the potential of the first circuit node 112-1-N1 of the first comparator device 110-1. In this way, as soon as the first input current I_in-1 exceeds the first reference current I_ref-1, thus causing a potential change at the first circuit node 112-1-N1, it may be effectively caused that the first transistor 115-1a of the first differential current providing device 115-1 provides the first output current I_out-1 thereafter.

[0045] Further aspects of the operation of the comparator device 110-1, for example according to FIG. 6, will now be described with reference also to FIG. At time t0, the first input current I_in-1 is zero, after time t0, the first input current I_in-1 increases, for example linearly here (see curve K1), until time t1. Curve K2 characterizes the first output current I_out-1 of the first comparator device 110-1 according to FIG. 6. As can be seen from FIG. 7, the first output current K2 is equal to the first reference current I_ref-1 at time t0 and then decreases linearly to zero until time t01, when the first input current I_in-1 (K1) exceeds the first reference current I_ref-1. The output signal out1 at the first circuit node 112-1-N1 (see curve K3 according to FIG. 7) has a first state, for example logic 1, between t0 and t01, for example based on the first operating voltage potential BP1-1 of the first comparator device.

[0046] As soon as the first input current I_in-1 (K1) exceeds the first reference current I_ref-1 (see time t01 according to FIG. 7), the output signal out1 (K3) goes to a second state, e.g. logic 0, and the first output current I_out-1 (K2) increases accordingly while the first input current I_in-1 (K1) continues to increase until time t1. It can be seen that even during the state transition of the output signal out1 (K3) (see time t01 for example), no abrupt change in the first output current K2 occurs, and the temporal change in the first output current K2 is based on the temporal change in the first input current K1.

[0047] 6 is in a conducting state during a time period from t0 to t01 and in a blocking state during a time period from t01 to t10. In a further exemplary embodiment, the first differential current providing device 115-1 may provide the first output current I_out-1 while the diode 116-1 is blocking.

[0048] Here, the first comparator device 110-1 according to Fig. 6 is realized by a p-channel field effect transistor, for example of MOSFET type, and the second comparator device 110-2 according to Fig. 6 is realized by an n-channel MOSFET. In a further exemplary embodiment, such an alternating implementation of the MOSFETs of the successive comparator devices 110-1, 110-2, ... of the arrangement 100a can be advantageous, since it requires fewer components than an embodiment in which all the transistors of the comparator devices 110-1, 110-2, ... are of the same type (for example p-type or n-type). Furthermore, it allows to reduce the number of cross-flows between adjacent comparator devices.

[0049] The function of the second comparator device 110-2 according to FIG. 6 substantially corresponds to the function of the first comparator device 110-1 according to FIG. 6, with the difference that the MOSFET of the second comparator device 110-2 is now for example of the n-channel type.

[0050] For example, it is contemplated that the second reference current device 114-2 comprises a transistor 114-2a, e.g., a field effect transistor, and the load path (drain-source path) of the transistor 114-2a is connected between the first circuit node 112-2-N1 of the second comparator device 110-2 and the first reference potential BP1-2. This can effectively provide the second reference current I_ref-2 in a further exemplary embodiment. In a further exemplary embodiment, the current strength of the second reference current I_ref-2 can be predetermined or influenced by at least one of the following factors: a) control of the transistor 114-2a; b) a dimension of at least one component of the transistor 114-2a, e.g., a gate width in the case of a field effect transistor.

[0051] In a further illustrative embodiment (FIG. 6), it is intended that the second differential current providing device 115-2 comprises a first transistor 115-2a, e.g., a field effect transistor, and the load path of the first transistor 115-2a is connected between the second circuit node 112-2-N2 of the second comparator device 110-2 and one or the above first reference potentials BP1-2.

[0052] In a further illustrative embodiment, it is contemplated that the first transistor 115-2a of the second differential current providing device 115-2 is controllable based on the potential of the first circuit node 112-2-N1 of the second comparator device 110-2, i.e., for example based on the comparison result of the second comparator device 110-2 (see output signal out2).

[0053] For example, the first transistor 115-2a of the second differential current providing device 115-2 may form a current mirror device together with the second transistor 115-2b of the second differential current providing device 115-2, which current mirror device is controllable, for example, by the third transistor 115-2c of the second differential current providing device 115-2, for example, based on the potential of the first circuit node 112-2-N1 of the second comparator device 110-2. In this way, as soon as the second input current I_in-2 exceeds the second reference current I_ref-2, thus causing a potential change at the first circuit node 112-2-N1, it may be effectively caused that the first transistor 115-2a of the second differential current providing device 115-2 provides the second output current I_out-2 thereafter.

[0054] In a further exemplary embodiment, the device 100a according to Fig. 6 may comprise, for example, a third comparator device (not shown here), which is designed, for example, similar to the first comparator device 110-1 and is realized, for example, by a p-channel MOSFET, like the first comparator device 110-1. In a further exemplary embodiment, the device 100a according to Fig. 6 may also comprise, for example, a fourth comparator device (not shown here), which is designed, for example, similar to the second comparator device 110-2 and is realized, for example, by an n-channel MOSFET, like the second comparator device 110-2, and so on, where an alternating implementation of successive comparator devices 110-1, 110-2 by MOSFETs of different types (p-channel, n-channel) may be advantageous.

[0055] 8 shows a simplified circuit diagram according to an exemplary embodiment. A resistor R1 is connected in series with a load path of two transistors, here for example MOSFETs T1 (for example a p-channel MOSFET) and T2 (for example an n-channel MOSFET), between reference potentials BP1, BP2.

[0056] The first reference potential Ref_P applied inter alia to the gate electrode of the MOSFET T1 can be used for example to control the gate electrode of the transistor 114-1a according to Fig. 6 (and / or for controlling further gate electrodes of further transistors for providing reference currents to other comparator devices, for example also realized by p-channel MOSFETs). As long as several transistors for providing reference currents to different comparator devices have the same reference potential Ref_P applied to their gate electrodes, the current strength of the reference current provided by the respective transistor can be effected for example by adjustment of the gate width of the respective gate electrode.

[0057] The second reference potential Ref_N, which is notably applied to the gate electrode of the MOSFET T2 according to Fig. 8, can for example be used to control the gate electrode of the transistor 114-2a according to Fig. 6 (and / or to control further gate electrodes of further transistors for providing reference currents to other comparator devices, for example also realized by n-channel MOSFETs). As long as several transistors for providing reference currents to different comparator devices have the same reference potential Ref_N applied to their gate electrodes, the current strength of the reference current provided by the respective transistor can for example be effected by adjustment of the gate width of the respective gate electrode.

[0058] Therefore, in a further exemplary embodiment, it is possible (and sufficient) to use two reference potentials Ref_P, Ref_N to control the transistors providing the respective reference currents.

[0059] For example, transistors T1, T2 may be used to form respective current mirror devices with corresponding transistors 114-1a, 114-2a, . . . of the comparator device to provide the reference currents.

[0060] For example, transistor T1 can form a current mirror device together with transistor 114-1a to provide a first reference current I_ref-1. For example, transistor T2 can form a current mirror device together with transistor 114-2a to provide a second reference current I_ref-2, and so on. For example, in the context of an analog-to-digital converter device, a reference potential can also be used for multiple different comparator devices by scaling the gate widths of the respective reference currents I_ref-1, I_ref-2, ... for transistors 114-1a, 114-2a that provide to the various comparator devices, for example according to a value setting of the respective comparator device.

[0061] Resistor R1 (FIG. 8) can in a further exemplary embodiment be used to adjust, for example, the current flowing through transistors T1, T2, whereby, for example, a reference current can be determined.

[0062] Instead of supplying current to each of the transistors 114-1a, 114-2a, ... for providing the reference currents I_ref-1, I_ref-2, ... by a circuit according to FIG. 8, for example, each of the respective transistors 114-1a, 114-2a, ... for providing the reference currents I_ref-1, I_ref-2, ... can be individually controlled or can be part of a (e.g. different) current mirror device, and so on.

[0063] In a further exemplary embodiment, switching elements, e.g. transistors, of the target system, e.g. transistors of the computing device 10 according to Fig. 12, may be used to provide the reference potentials Ref_P, Ref_N, as further described below with respect to Fig. 12, according to a further exemplary embodiment.

[0064] A further exemplary embodiment (FIG. 9) relates to an analog / digital converter device 1000 comprising at least one apparatus 100b according to an embodiment, for example a current-driven analog / digital converter device 1000. For example, the apparatus 100b may comprise an arrangement 100 according to FIG. 1 and / or an arrangement 100a according to FIG. 6, for example successive comparator devices 110-1, 110-2, ... being realized alternately by p-channel MOSFETs (see element 110-1 according to FIG. 6) and n-channel MOSFETs (see element 110-2 according to FIG. 6), respectively.

[0065] In a further exemplary embodiment (FIG. 9), each one comparator device of the apparatus can correspond to one stage of the analog-to-digital converter device. Thus, in a further exemplary embodiment, a multi-stage, e.g. n-stage (n≧1), analog-to-digital converter device 1000 can be realized based on the apparatus 100b, here comprising n=6 comparator devices 110-1, ..., 110-6, which are, for example, electrically connected in series with each other and can, for example, provide a first output current I_out-1 of the first comparator device 110-1 (FIG. 6) as a second input current I_in-2 to the second comparator device 110-2, and so on.

[0066] The output signals of the comparator devices 110-1, ..., 110-6, which characterize the comparison result between the respective input currents I_in-1, I_in-2, ... and the respective reference currents I_ref-1, I_ref-2, ..., are represented by the reference characters C1, C2, C3, C4, C5, C6 in Figure 9 and summed to obtain a binary value C.

[0067] In a further exemplary embodiment (FIG. 9), it is contemplated that each of the n comparator devices 110-1, ..., 110-6 is associated with a value setting of the analog-to-digital converter device 1000, and each of the n comparator devices 110-1, ..., 110-6 has a reference current associated with a value setting of the respective comparator device. For example, the second reference current I_ref-2 can be half as large as the first reference current I_ref-1, for example, the third reference current can be half as large as the second reference current I_ref-2, and so on.

[0068] In further exemplary embodiments, the same criteria may alternatively be used for at least some stages of the analog-to-digital converter device 1000 (see FIG. 8 above), e.g. the gate widths of the associated transistors 114-1a, 114-2a, ... being configured differently to, e.g., achieve different value settings of the different comparator devices 110-1, 110-2, ...

[0069] In a further exemplary embodiment (FIG. 9), different reference currents can be provided, e.g. for different comparator devices 110-1, 110-2, ... or stages of the analog-to-digital converter device 1000, by at least one element of: a) separate reference current sources; b) current mirror devices.

[0070] In a further exemplary embodiment (FIG. 9), an analog / digital converter device 1000 is configured to convert the first input current I_in-1 into a digital, for example binary, quantity C, for example the digital quantity being intended to have a Gray coding (the Hamming distance of adjacent code words is 1). In a further exemplary embodiment, the Gray coding is advantageously obtained by the configuration of the apparatus 100, 100a, 100b according to the embodiment.

[0071] In a further exemplary embodiment (FIG. 9), a transcoding device TK is provided, which is configured to transcode a Gray-coded digital quantity C into a binary-coded quantity C′.

[0072] 10 shows a simplified circuit diagram of an exemplary transcoding device TK according to an exemplary embodiment with a number of logic gates A1, A2, A3, A4, A5, A6, which is supplied with the individual numerical values ​​of the Gray-coded quantity C and transcodes it into a binary-coded quantity C' having numerical values ​​OC1, OC2, OC3, OC4, OC5, OC6.

[0073] For example, the binary coded output signals OC2, OC3, OC4, OC5, OC6 (ie except for the signal OC1) are available at the non-inverted outputs of the respective logic gates of the transcoding device TK.

[0074] As an example, each logic gate of the transcoding device TK, except for the first logic gate A1 to which the signal C1 is supplied, receives an additional signal as an input signal from an adjacent logic gate (on the left in FIG. 10), e.g., logic gates A1, A3, A6 associated with "even" bits receive inverted output signals from the other logic gates as shown in FIG. 10, and logic gates A2, A5 associated with "odd" bits receive non-inverted output signals from the other logic gates as shown in FIG. 10.

[0075] FIG. 11 shows a schematic circuit diagram of an apparatus 100c, which comprises at least two comparator devices 110-1', 110-2' similar to FIG. Instead of the diode 116-1 according to FIG. 6, the element 116-1′ for potential isolation according to FIG. 11 is configured as a transistor, which in a further exemplary embodiment provides a smaller voltage drop in the “conduction direction” than the diode 116-1 (e.g. a MOSFET with a relatively small R_DS_on, i.e. a relatively small drain-source resistance in the switched-on state), so that in a further exemplary embodiment a smaller supply voltage can be used and thus smaller power losses can be achieved.

[0076] In a further exemplary embodiment, the transistor 116-1' may be controlled based on the potential at the circuit node 112-1-N1 by, for example, a multi, here for example, triple inverter INV.

[0077] In further exemplary embodiments, the transistor 116-1′ can also be controlled, for example, by a simple inverter, but in further exemplary embodiments the triple inverter INV is preferred, since it can, for example, have a better time behavior (for example, faster switching times) and can, for example, process higher frequency signals.

[0078] In further exemplary embodiments, an inverted or non-inverted Gray-coded output signal can also be obtained in the region of the inverter INV, which provides a further degree of freedom for optional transcoding into another code, for example a binary code. The differential current providing device 115-1' according to Fig. 11 comprises transistors 115-1d, 115-1e, which together with the transistor 115-1a form a current mirror device. The transistor 115-1e can be considered or configured in further exemplary embodiments as, for example, a source follower circuit providing a relatively stable voltage for the drain electrode of the transistor 115-1d, which in further exemplary embodiments can further increase the stability and accuracy of the current mirror device.

[0079] In a further illustrative embodiment, the gate electrode of transistor 115-1d is “peripheral” to transistor 115-1e, as shown in FIG. 11, i.e., directly connected to, for example, circuit node 112-1-N1, which in a further illustrative embodiment enables operation at a relatively low power supply voltage.

[0080] In a further exemplary embodiment, the comparator device 110-1' may comprise a further transistor 114-1b, for example to further increase the accuracy of the comparator device 110-1'. The transistor 114-1b may also be connected, for example, as a source follower, for example to provide stable operating conditions for the comparator device 110-1', for example independent of the voltage at the output.

[0081] In a further exemplary embodiment, a circuit 114' is provided that provides a control voltage for the first reference current device 114-1 based on, for example, a first reference current I_ref-1'. A further comparator device 110-2' according to FIG. 11 has a similar function to the comparator device 110-1', but is realized by means of n-channel MOSFETs instead of p-channel MOSFETs.

[0082] A further exemplary embodiment (FIG. 12) relates to a computing device 10 for determining, for example, a scalar product, for example a vector matrix multiplier, for example a dot product engine, comprising a matrix M of elements having controllable electrical resistance (for example memristors or ferroelectric field effect transistors) and at least one analog / digital converter device 1000a, 1000b, 1000c according to an embodiment. The analog / digital converter device 1000a, 1000b, 1000c comprises, for example, the configuration 1000 according to FIG.

[0083] For example, at least one analog / digital converter device 1000a, 1000b, 1000c according to the exemplary embodiment can be used for current measurements (see currents Ia, Ib, Ic) on at least one column of the matrix M, in particular on the "high side", i.e. in the region of relatively large potentials, e.g. operating voltage potentials (see potential source V4) different from the ground potential GND.

[0084] In further exemplary embodiments, the computing device 10 can be used for example for machine learning (ML) methods or applications in the field of artificial intelligence, such as a hardware accelerator for training deep neural networks (DNNs).

[0085] In a further exemplary embodiment, switching elements, e.g., transistors, of the computing device 10 can be used to provide reference potentials Ref_P, Ref_N for the comparator devices 110-1, 110-2, ... of the analog-to-digital converter devices 1000a, 1000b, 1000c (see also FIG. 8).

[0086] For example, in the matrix M, for example individual columns of transistors (indicated in FIG. 12 by the dashed rectangles COL with rounded corners) can be provided, where the transistors of this column COL are for example programmable or programmed to respective predefined values, for example all "1", whereby this column COL outputs a current I_max corresponding to the maximum current that the matrix M can drive. From the maximum current I_max, for example at least one reference voltage or at least one reference potential for the comparator devices 110-1, 110-2, ... of the analog-to-digital converter devices 1000a, 1000b, 1000c can then be derived.

[0087] Instead of programming all the transistors of a column COL to "1", in further exemplary embodiments, for example only a portion of the transistors of a column COL can be programmed to "1".

[0088] In further exemplary embodiments, for example, FeFETs can be used as transistors in a column COL to provide at least one reference potential, and component-related offset and / or drift effects within the region of the matrix M can be offset or compensated for each other.

[0089] A further exemplary embodiment (FIG. 2) relates to a method for operating an apparatus comprising at least one first comparator device 110-1 (FIG. 1) configured to compare a first input current with a first reference current and to output a first output current I_out-1 to a second comparator device 110-2 based on the comparison, where if the first input current is smaller than the first reference current, the first output current corresponds to a difference between the first reference current and the first input current, and if the first input current is equal to or greater than the first reference current, the first output current corresponds to a difference between the first input current and the first reference current, the method comprising the steps of comparing 200 (FIG. 2) the first input current with the first reference current and outputting 202 the first output current to the second comparator device.

[0090] Further exemplary embodiments (FIG. 13) relate to the use 300 of the apparatus 100, 100a, 100b, 100c according to the embodiments and / or the analog / digital converter device 1000, 1000a, 1000b, 1000c according to the embodiments and / or the computing device 10 according to the embodiments and / or the method according to the embodiments for at least one of the following elements: a) converting the current to a binary value 301; b) performing binary coding 302; c) performing Gray coding 303; d) providing, for example, a fully current-driven analog / digital converter 304; e) avoiding sudden changes in the value of at least the first output current 305.

[0091] Further exemplary aspects and advantages according to further exemplary embodiments are set forth below. In further exemplary embodiments, the apparatus according to the embodiments or the A / D converter device according to the embodiments has a relatively low power consumption.

[0092] In further exemplary embodiments, configurations 100a, 100b, 100c, 1000, 1000a, 1000b, 1000c are scalable, i.e., the resolution can be extended by i bits, for example, by adding i (i=1, 2, 3, ...) stages or comparator devices.

[0093] In further exemplary embodiments, the arrangements 100a, 100b, 100c, 1000, 1000a, 1000b, 1000c have a temperature compensation function, for example with respect to the generation of the reference current.

[0094] In a further exemplary embodiment, the A / D converter device does not require an additional electrical energy supply, as it can for example be powered by the input current. In further exemplary embodiments, the A / D converter device may be, for example, fully current driven, which may be faster compared to voltage controlled operation.

[0095] In further exemplary embodiments, principles according to embodiments allow for constructing compact A / D converter devices with relatively few components or building blocks. For example, in a further exemplary embodiment, an A / D converter device having 8-bit resolution can be designed using approximately 112 MOSFETs, which is approximately less than ½ MOSFET per numerical step.

[0096] In further exemplary embodiments, the A / D converter device, for example, operates fully asynchronously, does not require a clock signal and / or repetition, and is therefore relatively fast. In a further exemplary embodiment, the reference potentials Ref_N, Ref_P can be used to precisely specify the reference currents and thus the switching thresholds for state changes of the output signals out1, out2, ... independently of one another. Furthermore, the reference potentials Ref_N, Ref_P can be used for multiple comparator devices. Information about assistance and support The project leading to this application has been funded by the ECSEL (Joint Undertaking) Joint Venture under grant agreement No. 826655. The Joint Undertaking receives support from the European Union's Horizon 2020 research and innovation programme, as well as from Belgium, France, Germany, the Netherlands and Switzerland. [Explanation of symbols]

[0097] BP1-1 First reference potential C Digital quantity I_in-1 First input current I_in-k kth input current I_out-1 First output current I_out-k kth output current I_ref-1 First reference current I_ref-k kth reference current M matrix S1-BW Binary Value VE-1, VE-k comparison results 10. Computing Devices 100;100a;100b;100c equipment 110-1, 110-2, 110-n comparator devices 112-1-N1; 112-k-N1 First circuit node 112-1-N2;112-k-N2 Second circuit node 112-1-N3;112-k-N3 Third circuit node 114-1 First Reference Current Device 114-1a Transistor 114-k kth reference current device 115-1 First differential current providing device 115-1a First transistor 115-k kth differential current providing device 116-1;116-k Elements for potential isolation 117-1;117-k Elements for potential isolation 117-1a Transistor 200 Compare, Receive 202 Output 210 Compare, receive 300 uses 301 Converting current to binary value 302 Binary Coding Execution 303 Gray coding implementation 304 Providing analog / digital converters 305 Avoiding sudden changes in the value of the first output current 1000; 1000a, 1000b, 1000c Analog to Digital Converter Devices

Claims

1. An apparatus (100; 100a; 100b; 100c) comprising at least one first comparator device (110-1) configured to compare (200) a first input current (I_in-1) with a first reference current (I_ref-1) and output (202) a first output current (I_out-1) to a second comparator device (110-2) based on said comparison (200), wherein said first input current (I_in-1) is greater than said first reference current (I_ref-1). the first output current (I_out-1) corresponds to a difference between the first reference current (I_ref-1) and the first input current (I_in-1) if the first input current (I_in-1) is smaller than the first reference current (I_ref-1), and the first output current (I_out-1) corresponds to a difference between the first input current (I_in-1) and the first reference current (I_ref-1) if the first input current (I_in-1) is equal to or greater than the first reference current (I_ref-1).

2. The system includes n comparator devices (110-1, 110-2, ..., 110-n), and the k-th (k=1, ..., n-1) comparator device is configured to compare (210) a k-th available or supplied input current (I_in-k) with a k-th reference current (I_ref-k) and, based on the comparison (210), output a k-th output current (I_out-k) to the (k+1)-th comparator device, and the k-th input current (I_in-k) is greater than the k-th reference current (I_ref-k).

2. The apparatus (100; 100a; 100b; 100c) of claim 1, wherein the kth output current (I_out-k) corresponds to a difference between the kth reference current (I_ref-k) and the kth input current (I_in-k) if the kth input current (I_in-k) is less than the kth reference current (I_ref-k), and wherein the kth output current (I_out-k) corresponds to a difference between the kth input current (I_in-k) and the kth reference current (I_ref-k) if the kth input current (I_in-k) is greater than or equal to the kth reference current (I_ref-k).

3. The apparatus (100; 100a; 100b; 100c) according to claim 1 or 2, wherein at least the first comparator device (110-1), e.g. some or all of the n comparator devices (110-1, 110-2, ..., 110-n), are configured to output a comparison result (VE-1, VE-k) based on the comparison (200; 210), e.g. in the form of a binary signal.

4. The first comparator device (110-1) comprises a first circuit node (112-1-N1) for receiving (200) the first input current (I_in-1) and a first reference current device (114-1), the first reference current device (114-1) being configured to derive the first reference current (I_ref-1) from the first circuit node (112-1-N1), for example, a kth comparator device (110-k) receiving the kth input current (I The apparatus (100; 100a; 100b; 100c) of any one of claims 1 to 3, further comprising a respective first circuit node (112-k-N1) for receiving (210) a kth reference current (I_ref-k) from the first circuit node (112-k-N1) of the kth comparator device (110-k), and a kth reference current device (114-k), the kth reference current device (114-k) configured to derive the kth reference current (I_ref-k) from the first circuit node (112-k-N1) of the kth comparator device (110-k).

5. The apparatus (100; 100a; 100b; 100c) of claim 4, wherein the first reference current device (114-1) is configured, at least temporarily, to provide the first output current (I_out-1), e.g. when the first input current (I_in-1) is smaller than the first reference current (I_ref-1), and wherein the kth reference current device (114-k) is configured, at least temporarily, to provide the kth output current (I_out-k), e.g. when the kth input current (I_in-k) is smaller than the kth reference current (I_ref-k).

6. The apparatus (100; 100a; 100b; 100c) according to any one of claims 1 to 5, wherein the first comparator device (110-1) comprises a first differential current providing device (115-1), for example configured to provide the first output current (I_out-1) when the first input current (I_in-1) is greater than or equal to the first reference current (I_ref-1), for example the kth comparator device (110-k) comprises a kth differential current providing device (115-k), for example configured to provide the kth output current (I_out-k) when the kth input current (I_in-k) is greater than or equal to the kth reference current (I_ref-k).

7. The apparatus (100; 100a; 100b; 100c) according to any one of claims 4 to 6, wherein the first comparator device (110-1) comprises a second circuit node (112-1-N2) for outputting the first output current (I_out-1) to the second comparator device (110-2), e.g. the kth comparator device (110-k) comprises a second circuit node (112-k-N2) for outputting the kth output current (I_out-k) to the (k+1)th comparator device.

8. The device (100; 100a; 100b; 100c) of claim 7, wherein an element (116-1; 116-k) for potential isolation is provided between the first circuit node (112-1-N1; 112-k-N1) and the second circuit node (112-1-N2; 112-k-N2), e.g. the element (116-1; 116-k) for potential isolation comprises at least one of the following elements: a) a diode, b) a transistor.

9. The apparatus (100; 100a; 100b; 100c) according to any one of claims 4 to 8, wherein the first comparator device (110-1) comprises a third circuit node (112-1-N3) for receiving (200) the first input current (I_in-1), e.g. the kth comparator device (110-k) comprises a third circuit node (112-k-N3) for receiving the kth input current (I_in-k).

10. The device (100; 100a; 100b; 100c) according to claim 9, wherein an element (117-1; 117-k) for potential isolation is provided between the first circuit node (112-1-N1; 112-k-N1) and the third circuit node (112-1-N3; 112-k-N3), e.g. the element (117-1; 117-k) for potential isolation comprises a transistor (117-1a), e.g. a field effect transistor configured as a source follower.

11. The apparatus (100; 100a; 100b; 100c) according to any one of claims 4 to 10, wherein the first reference current device (114-1) comprises a transistor (114-1a), e.g. a field effect transistor, the load path of the transistor (114-1a) being connected between the first circuit node (112-1-N1) of the first comparator device (110-1) and a first reference potential (BP1-1).

12. The apparatus (100; 100a; 100b; 100c) according to any one of claims 7 to 11, wherein the first differential current providing device (115-1) comprises a first transistor (115-1a), e.g. a field effect transistor, the load path of the first transistor (115-1a) being connected between the second circuit node (112-1-N2) of the first comparator device (110-1) and one or the first reference potentials (BP1-1).

13. An analog / digital converter device (1000; 1000a, 1000b, 1000c), for example a current-driven analog / digital converter device (1000; 1000a, 1000b, 1000c), comprising at least one apparatus (100; 100a; 100b; 100c) according to any one of claims 1 to 12.

14. An analog to digital converter device (1000; 1000a; 1000b; 1000c) according to claim 13, wherein at least one apparatus (100; 100a; 100b; 100c) according to any one of claims 2 to 12 is configured, wherein each of n comparator devices (110-1, 110-2, ..., 110-n) is associated with a value setting of said analog to digital converter device (1000; 1000a, 1000b, 1000c), and wherein each reference current (I_ref-1, I_ref-2, ..., I_ref-k, ..., I_ref-n) of said n comparator devices (110-1, 110-2, ..., 110-n) is respectively associated with a value setting of said respective comparator device (110-1, 110-2, ..., 110-n).

15. The analog to digital converter device (1000; 1000a, 1000b, 1000c) of claim 13 or 14, wherein the analog to digital converter device (1000; 1000a, 1000b, 1000c) is configured to convert the first input current (I_in-1) into a digital, e.g. binary, quantity (C), e.g. the digital quantity (C) has a Gray code.

16. A computing device (10), e.g. for determining a scalar product, e.g. a vector matrix multiplier, e.g. a dot product engine, comprising a matrix (M) of elements having controllable electrical resistance and at least one analogue / digital converter device (1000; 1000a, 1000b, 1000c) according to any one of claims 13 to 15.

17. A method for operating an apparatus (100; 100a; 100b; 100c) comprising at least one first comparator device (110-1) configured to compare (200) a first input current (I_in-1) with a first reference current (I_ref-1) and to output (202) a first output current (I_out-1) to a second comparator device (110-2) based on said comparison (200), wherein if said first input current (I_in-1) is less than said first reference current (I_ref-1), then said first output current (I_out-1) is greater than said first reference current (I_ref-1). a first output current (I_out-1) corresponding to a difference between the first input current (I_in-1) and the first reference current (I_ref-1), and if the first input current (I_in-1) is greater than or equal to the first reference current (I_ref-1), the first output current (I_out-1) corresponds to a difference between the first input current (I_in-1) and the first reference current (I_ref-1), comparing (200) the first input current (I_in-1) with the first reference current (I_ref-1); and outputting (202) the first output current (I_out-1) to a second comparator device (110-2).

18. a) converting (301) the currents (I_in-1; Ia, Ib, Ic) into binary values ​​(S1-BW); b) performing a binary coding (302); c) performing a Gray coding (303); d) providing (304), for example a fully current-driven analog-to-digital converter (1000; 1000a, 1000b, 1000c); e) preventing sudden changes in the value of at least a first output current (I_out-1, I_out-2, ..., I_out-n-1). An apparatus (100; 100a; 100b; 100c) according to any one of claims 1 to 12, and / or an analogue / digital converter device (1000; 1000a, 1000b, 1000c) according to any one of claims 13 to 15, and / or a computing device (10) according to claim 16, and / or use of a method (300) according to claim 17 for at least one element of the avoidance (305).

Images