Printed circuit board
By processing inorganic substrates with tapered core portions and insulating layers within a frame, the challenges of high-density circuit formation and warpage control in printed circuit boards are addressed, resulting in efficient and cost-effective multilayer boards.
Patent Information
- Application Number
- JP2024158277
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-11-23
- Filing Date
- 2024-09-12
- Publication Date
- 2025-06-04
AI Technical Summary
Existing printed circuit boards face challenges in forming high-density fine circuits with high yield and low cost, while also maintaining effective warpage control.
The solution involves cutting an inorganic substrate with through vias to form core portions with tapered outer surfaces, which are then disposed within a frame and filled with insulating layers to create unit substrates. These substrates are further processed to form multilayer printed circuit boards with insulating and wiring layers.
This approach enables the production of printed circuit boards that achieve high-density fine circuits with improved yield and reduced costs, while also enhancing warpage control.
Smart Images
Figure 2025085064000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a printed circuit board.
Background Art
[0002] Recently, as the market has changed from a business centered on conventional mobile devices to a market centered on high-capacity servers, the amount of data has increased rapidly, and the situation is that servers, networks, and storage are increasing more rapidly. Therefore, new high-multi-layer structures of substrates are expanding, and FOMCM (Fan-out multi chip module), FOEB (Fan-out Embedded Bridge), EMIB (Embedded multi-die interconnect bridge), etc. have been developed. On the other hand, in order to meet the high-capacity server market, at the substrate level, many companies are trying to develop with 2.1D as the ultimate goal. However, since the number of layers of general printed circuit boards is basically high-multi-layer and fine circuits are applied, there are limitations in solving problems from the viewpoints of actual yield and cost.
Summary of the Invention
Problems to be Solved by the Invention
[0003] One of several objects of the present invention is to provide a printed circuit board capable of forming high-density fine circuits with high yield and low cost.
[0004] Another one of several objects of the present invention is to provide a printed circuit board excellent in warpage control.
Means for Solving the Problems
[0005] One of the solutions proposed through the present invention is, first, to cut an inorganic substrate containing silicon or ceramic and having through vias formed therein to form a plurality of core portions having a tapered outer surface, then to respectively dispose the plurality of core portions within a plurality of through portions of a frame, then to respectively fill the plurality of through portions with a first insulating layer, and then to cut the frame to form a plurality of unit substrates. Next, an insulating layer, a wiring layer, and the like are formed on the unit substrates to manufacture a multilayer printed circuit board.
[0006] For example, a printed circuit board according to an example that can be manufactured by the above-described solution includes an inorganic substrate, a through via penetrating the inorganic substrate, a first insulating layer covering at least a part of the outer surface of the inorganic substrate, a second insulating layer disposed on the upper surfaces of the inorganic substrate and the first insulating layer, a third insulating layer disposed on the lower surfaces of the inorganic substrate and the first insulating layer, a first wiring layer disposed on the upper surface of the second insulating layer, and a second wiring layer disposed on the lower surface of the third insulating layer. The inorganic substrate includes silicon or ceramic, and the inorganic substrate can have a structure in which the width of the upper end portion and the width of the lower end portion are different in cross section.
Advantages of the Invention
[0007] As one of the various advantages of the present invention, it is possible to provide a printed circuit board capable of forming a high-density fine circuit with a high yield and a low cost.
[0008] As another one of the various advantages of the present invention, it is possible to provide a printed circuit board excellent in warp control.
Brief Description of the Drawings
[0009]
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DETAILED DESCRIPTION OF THE INVENTION
[0010] Hereinafter, the present invention will be described with reference to the accompanying drawings. The shape, size, etc. of the elements in the drawings can be exaggerated or reduced for clearer explanation.
[0011] Electronic device FIG. 1 is a block diagram schematically showing an example of an electronic device system.
[0012] Referring to the drawings, the electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also combined with other electronic components described later to form various signal lines 1090.
[0013] Examples of chip-related components 1020 include, but are not limited to, memory chips such as volatile memories (e.g., DRAM), non-volatile memories (e.g., ROM), and flash memories; application processor chips such as central processors (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and application-specific ICs (ASICs). Needless to say, other different forms of chip-related electronic components may also be included. Also, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in a package form including the above-described chips and electronic components.
[0014] Examples of network-related components 1030 include, but are not limited to, Wi-Fi (such as the IEEE 802.11 family), WiMAX (such as the IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and any other wireless and wired protocols designated for future use. Needless to say, network-related components 1030 may be combined with chip-related components 1020 and with each other.
[0015] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (Low Temperature Co-Firing Ceramics), EMI (Electro Magnetic Interference) filters, MLCC (Multi-Layer Ceramic Condensers), etc. However, it is not limited thereto, and passive elements in the form of chip components used for other different applications may also be included. Needless to say, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030 with each other.
[0016] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected or not connected to the main board 1010. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, a battery 1080, etc. However, it is not limited thereto, and it may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a CD (compact disk), a DVD (digital versatile disk), etc. Needless to say, other electronic components used for various applications depending on the type of the electronic device 1000 may also be included.
[0017] The electronic device 1000 may be, for example, a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an Automotive device, etc. However, it is not limited to these, and needless to say, any other electronic device that processes data may be used.
[0018] FIG. 2 is a perspective view schematically showing an example of an electronic device.
[0019] Referring to the drawings, the electronic device may be, for example, a smart phone 1100. Inside the smart phone 1100, a motherboard 1110 is housed, and various components 1120 are physically and / or electrically connected to such a motherboard 1110. Also, other components that are or are not physically and / or electrically connected to the motherboard 1110, such as a camera module 1130 and / or a speaker 1140, are housed inside. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but it is not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board with built-in active components and / or passive components. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and needless to say, it may be other electronic devices as described above.
[0020] Printed Circuit Board FIG. 3 is a cross-sectional view schematically showing an example of a printed circuit board.
[0021] Referring to the drawings, a printed circuit board 100A according to an example includes a core layer 111, a first insulating layer 112 covering at least a part of the outer surface of the core layer 111, a through via 131 penetrating the core layer 111, a second insulating layer 113 disposed on each of the upper sides of the core layer 111 and the first insulating layer 112, a third insulating layer 114 disposed on each of the lower sides of the core layer 111 and the first insulating layer 112, a first wiring layer 121 disposed on the upper surface of the second insulating layer 113, a second wiring layer 122 disposed on the lower surface of the third insulating layer 114, a first connection via 132 penetrating the second insulating layer 113 and connecting the through via 131 and the first wiring layer 121 to each other, and a second connection via 133 penetrating the third insulating layer 114 and connecting the through via 131 and the second wiring layer 122 to each other. Optionally, it can further include a capacitor 140 including a plurality of conductive trenches 141 respectively penetrating a part of the core layer 111.
[0022] On the one hand, the core layer 111 can include an inorganic substrate 111a. At this time, the inorganic substrate 111a can include silicon or ceramic. Therefore, it can basically have excellent flatness, which can be more advantageous in high-density circuits with fine pitches. Also, since it has higher rigidity than a general organic substrate, it can be more advantageous in warpage control. Further, the core layer 111 can be provided in unit units in which the through vias 131 are formed, and can have a structure in which the width of the upper end portion and the width of the lower end portion are different on the cross section by cutting. Also, the core layer 111, for example, the inorganic substrate 111a, may have a width of the upper end portion smaller than the width of the lower end portion on the cross section, and the outer surface of the core layer 111, for example, the inorganic substrate 111a, may be substantially inclined. For example, the outer surface of the core layer 111, for example, the inorganic substrate 111a, can have a substantially tapered shape. Also, the outer surface of the core layer 111, for example, the inorganic substrate 111a, may be covered by the first insulating layer 112 and not be exposed to the outside. Also, the second insulating layer 113 and the third insulating layer 114 can be laminated on the core layer 111, for example, the inorganic substrate 111a and the first insulating layer 112 to further improve flatness. Therefore, it can be more advantageous in forming high-density fine circuits with fine pitches. Such a printed circuit board 100A can more easily provide, for example, a network board or a high-performance package board. For example, the printed circuit board 100A can be used as a 2.xD level FCB (Flip Chip Board) substrate.
[0023] Note that the core layer 111 can further include inorganic insulating films 111b-1 and 111b-2 that cover at least a part of each of the upper and lower surfaces of the inorganic substrate 111a. For example, the inorganic substrate 111a may be a silicon substrate, and the inorganic insulating films 111b-1 and 111b-2 may include an oxide film 111b-1 and / or a nitride film 111b-2. As a non-limiting example, the core layer 111 can include a silicon substrate as the inorganic substrate 111a, and the inorganic insulating films 111b-1 and 111b-2 are disposed on the inorganic substrate 111a, SiO 2It can include an oxide film 111b-1 containing etc., and a nitride film 111b-2 disposed on the inorganic oxide film 111b-1 and containing SiN etc. On the other hand, since the outer surface of the inorganic substrate 111a can include a cut surface, it can be separated from the inorganic insulating films 111b-1 and 111b-2 and can be in direct contact with the first insulating layer 112. Further, the inorganic substrate 111a can have a through hole H in which a through via 131 is disposed, and the inorganic insulating films 111b-1 and 111b-2 can extend between the inorganic substrate 111a and the through via 131 and cover at least a part of the wall surface of the through hole H. Thus, by forming the inorganic insulating films 111b-1 and 111b-2 on the inorganic substrate 111a, the surface of the inorganic substrate 111a can be protected, an insulating region can be provided, and a short circuit of the through via 131 can be prevented.
[0024] On the other hand, the through via 131 can include a first metal layer 131a disposed on the inorganic insulating films 111b-1 and 111b-2 in the through hole H, and a second metal layer 131b filling at least a part of the through hole H on the first metal layer 131a. The first metal layer 131a may be a seed layer, and for example, it may be formed by electroless plating or sputtering. The first metal layer 131a can contain titanium (Ti), copper (Cu), etc., but is not limited thereto. The second metal layer 131b may be a plating layer, and for example, it may be formed by electrolytic plating. The second metal layer 131b can contain copper (Cu), but is not limited thereto. The second metal layer 131b may be wider in cross section than the first metal layer 131a. The through via 131 may be, for example, a TSV (Through Silicon Via) etc., formed in the core layer 111 and capable of providing an electrical connection path between the upper / lower sides of the core layer 111. The through via 131 can have a columnar shape in cross section. For example, the side surface of the through via 131 may be substantially perpendicular to the upper and lower surfaces of the through via 131, but is not limited thereto, and may be an hourglass shape etc. as required.
[0025] Note that the first to third insulating layers 112, 113, and 114 can each contain an organic insulating material. For example, the first insulating layer 112 can contain UR (Underfil Resin), EMC (Epoxy Molding Compound), TIM (Thermal Interface Material), etc. according to the required characteristics. Also, the second and third insulating layers 113, 114 can contain PPG (Prepreg), ABF (Ajinomoto Build-up Film), etc. for wiring formation. Therefore, the first insulating layer 112 can have an interlayer boundary with each of the second and third insulating layers 113, 114. On the other hand, before forming the second and third insulating layers 113, 114, the first insulating layer 112 can be planarized together with the core layer 111, whereby the upper and lower surfaces of the first insulating layer 112 can be substantially coplanar with the upper and lower surfaces of the core layer 111, respectively. If necessary, the first insulating layer 112 can contain the same organic insulating material as the second insulating layer 113 and / or the third insulating layer 114. In this case, there may be no interlayer boundary by integrating with the second insulating layer 113 and / or the third insulating layer 114. For example, when forming the second insulating layer 113 and / or the third insulating layer 114, the first insulating layer 112 can be formed together.
[0026] On the other hand, the first and second connection vias 132, 133 can each be in direct contact with the through via 131. For example, the first connection via 132 can be in direct contact with the upper surface of the through via 131. Also, the second connection via 133 can be in direct contact with the lower surface of the through via 131. For example, since it may be difficult to ensure adhesion on the upper and lower surfaces of the core layer 111, a wiring layer including a pad pattern, etc. may not be formed. On the other hand, the first and second connection vias 132, 133 can have a tapered shape in opposite directions. For example, the first connection via 132 may have a width at the upper end portion wider than that at the lower end portion in cross section, and the second connection via 133 may have a width at the lower end portion wider than that at the upper end portion in cross section, but it is not limited to this.
[0027] In addition, each of the plurality of conductive trenches 141 can penetrate a part of the core layer 111 from the upper surface of the core layer 111, for example, the inorganic substrate 111a. Alternatively, conversely, each of the plurality of conductive trenches 141 can penetrate a part of the core layer 111 from the lower surface of the core layer 111, for example, the inorganic substrate 111a. The plurality of conductive trenches 141 can overlap at least a part of each other in a direction perpendicular to the trench direction in the plane. Therefore, a capacitor 140 can be formed in the core layer 111 in this way. For example, the capacitor 140 can include a DTC (Deep Trench Capacitor). In this way, since the capacitor 140 can be designed in the core layer 111 as needed, it is not necessary to separately mount a capacitor on the core layer 111.
[0028] Hereinafter, with reference to the drawings, the components of the printed circuit board 100A according to an example will be described in more detail.
[0029] The core layer 111 can include an inorganic substrate 111a and inorganic insulating films 111b-1 and 111b-2. The inorganic substrate 111a can include an inorganic insulating material. The inorganic insulating material may be, for example, silicon or ceramic. For example, the inorganic substrate 111a may be a silicon substrate or a ceramic substrate. Silicon can include pure silicon (Si). The ceramic can include, for example, alumina (Al 2 O 3 ), aluminum nitride (AlN), silicon carbide (SiC), silicon nitride (Si 3 N 4 ), etc., but is not limited thereto. The inorganic insulating films 111b-1 and 111b-2 can include an oxide film 111b-1 containing SiO 2 etc. and a nitride film 111b-2 containing SiN etc., but is not limited thereto.
[0030] The first insulating layer 112 can include an organic insulating material. The organic insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or the like. Optionally, it can further include an inorganic filler and / or an organic filler. For example, the first insulating layer 112 can include UR (Underfil Resin), EMC (Epoxy Molding Compound), TIM (Thermal Interface Material), etc., according to the required characteristics. However, it is not limited thereto, and optionally, the first insulating layer 112 may include the same organic insulating material as the second insulating layer 113 and / or the third insulating layer 114 described later.
[0031] The second and third insulating layers 113 and 114 can each include an organic insulating material. The organic insulating material can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material containing an inorganic filler, an organic filler, and / or glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) together with the resin. For example, the organic insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film), PPG (Prepreg), etc., but it is not limited thereto, and other polymer materials may also be used. Also, the organic insulating material may be a photosensitive insulating material such as PID (Photo Imageable Dielectric), and may include an adhesive sheet such as BS (Bonding Sheet).
[0032] The first and second wiring layers 121 and 122 can each contain a metal. The metal can include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it can contain copper (Cu), but is not limited thereto. The first and second wiring layers 121 and 122 can each perform various functions according to the design. For example, it can include a signal pattern, a power pattern, a ground pattern, etc. These patterns can each have various forms such as a line, a plane, a pad, etc. The first and second wiring layers 121 and 122 can each contain an electroless plating layer (or electroless copper) and an electroplating layer (or electroplated copper). Alternatively, it can contain a metal foil (or copper foil) and an electroplating layer (or electroplated copper). Alternatively, it can contain a metal foil (or copper foil), an electroless plating layer (or electroless copper), and an electroplating layer (or electroplated copper). Instead of the electroless plating layer (or electroless copper), a sputtering layer may be included, or both may be included as needed.
[0033] The through via 131 can contain a metal. The metal can include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it can contain copper (Cu), but is not limited thereto. The through via 131 can penetrate between the upper and lower surfaces of the core layer 111. The upper and lower surfaces of the through via 131 can be substantially coplanar with the upper and lower surfaces of the core layer 111, respectively. The through via 131 can perform various functions according to the design. For example, it can include a ground via, a power via, a signal via, etc. The through via 131 can have a generally circular or elliptical shape on the plane, but is not limited thereto. For example, from the perspective of ensuring adhesion due to an increase in the specific surface area, it can also have a generally flower shape on the plane.
[0034] The first and second connection vias 132 and 133 can each contain metal. The metal can include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it can include copper (Cu), but is not limited thereto. The first and second connection vias 132 and 133 can each include a filled via that fills the via hole, but can also include a conformal via disposed along the wall surface of the via hole. The first and second connection vias 132 and 133 can perform various functions according to the design. For example, it can include a ground via, a power via, a signal via, etc. The first and second connection vias 132 and 133 can each include an electroless plating layer (or electroless copper) and an electroplating layer (or electroplated copper). Instead of the electroless plating layer (or electroless copper), a sputtering layer may be included, or both may be included as necessary.
[0035] The capacitor 140 can include a DTC (Deep Trench Capacitor). For example, the capacitor 140 can include a plurality of conductive trenches 141. Each of the plurality of conductive trenches 141 can contain metal. The metal can include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The capacitor 140 can be electrically connected to at least a part of the first wiring layer 121 and / or the second wiring layer 122 via connection vias and the like.
[0036] Figures 4a to 4d are process cross-sectional views schematically showing an example of the manufacture of the printed circuit board of FIG. 3.
[0037] Referring to FIG. 4a, a core layer 111 with through vias 131 formed therein can be prepared. For example, an inorganic substrate 111a containing silicon or ceramic can be prepared. Next, through holes H can be formed in the inorganic substrate 111a by various methods such as laser processing, mechanical processing, and chemical processing. Next, inorganic insulating films 111b-1 and 111b-2 including oxide films 111b-1 and / or nitride films 111b-2 covering the surface of the inorganic substrate 111a and the wall surfaces of the through holes H can be formed by processes such as vapor deposition and coating. Next, a first metal layer 131a can be formed on the wall surfaces of the through holes H by electroless plating, sputtering, or the like. Next, a second metal layer 131b filling at least a part of the through holes H can be formed on the first metal layer 131a by electrolytic plating or the like. On the other hand, the seed layer and / or plating layer on the upper and lower surfaces of the core layer 111 can be removed by etching or the like. Next, the core layer 111 with through vias 131 formed therein can be cut in unit units. Thereby, a plurality of core layers 111 with inclined outer surfaces can be formed in unit units. For example, a plurality of core portions in unit units can be formed.
[0038] Referring to FIG. 4b, a core layer 111 with through vias 131 formed therein and an inclined outer surface can be disposed in the through hole 210H of the frame 210. For example, after attaching an adhesive tape 220 that closes the lower side of the through hole 210H to the lower side of the frame 210, the core layer 111 with through vias 131 formed therein can be adhered onto the tape 220 exposed from the through hole 210H. The frame 210 can include various substances such as metals and organic insulating materials. For example, the frame 210 can have a multilayer substrate structure formed using a CCL (Copper Clad Laminate) or the like, but is not limited thereto. The frame 210 may have the form of a jig. The tape 220 may be a heat-resistant tape such as polyimide (PI), but is not limited thereto.
[0039] Referring to FIG. 4c, the remaining space of the through-hole 210H can be filled with the first insulating layer 112. Thereby, the inclined outer surface of the core layer 111 can be covered by the first insulating layer 112. At this time, planarization can be performed as necessary. The first insulating layer 112 can be formed by an underfill process, an ink cap process, a lamination process, or the like.
[0040] Referring to FIG. 4d, the tape 220 can be removed. Also, by a lamination process or the like, the second and third insulating layers 113 and 114 can be formed on the upper and lower sides of the core layer 111 and the first insulating layer 112, respectively. Next, after forming via holes in the second and third insulating layers 113 and 114, the plating process is advanced to form the first and second wiring layers 121 and 122 and the first and second connection vias 132 and 133. Next, the frame 210 can be removed. The frame 210 can be removed in the singulation process.
[0041] Through a series of processes, the printed circuit board 100A according to the above-described example can be manufactured. Since other contents are substantially the same as those described in the printed circuit board 100A according to the above-described example, redundant explanations thereof are omitted.
[0042] FIGS. 5a and 5b are process perspective views schematically showing an example in the case where a plurality of core portions in unit units are arranged in a frame having a plurality of through portions.
[0043] Referring to FIG. 5a, the frame 210 can have a plurality of through portions 210H, and the core layer 111 in unit units after being cut using the process of FIG. 4b described above, for example, the core portions can be arranged in the through portions 210H.
[0044] Referring to FIG. 5b, unit core layers 111, for example, core portions, can be arranged in substantially the same form in a plurality of through portions 210H. Thereafter, a plurality of unit substrates can be manufactured in the frame 210 using the processes of FIGS. 4c and 4d described above, and a plurality of printed circuit boards 100A can be obtained by a singulation process.
[0045] Through a series of processes, a plurality of printed circuit boards 100A can be manufactured. Since other contents are substantially the same as those described in the printed circuit board 100A and its manufacturing method according to the above example, redundant explanations thereof are omitted.
[0046] FIGS. 6 and 7 are cross-sectional views schematically showing modified examples of the printed circuit board of FIG. 3.
[0047] Referring to FIG. 6, the printed circuit board 100B according to the modified example includes, on the printed circuit board 100A according to the above-described example, one or more first build-up insulating layers 151 disposed on the upper surface of the second insulating layer 113, one or more first build-up wiring layers 152 disposed on or within one or more first build-up insulating layers 151, respectively, one or more first build-up via layers 153 each penetrating at least one of the one or more first build-up insulating layers 151, one or more second build-up insulating layers 161 disposed on the lower surface of the third insulating layer 114, one or more second build-up wiring layers 162 disposed on or within one or more second build-up insulating layers 161, respectively, one or more second build-up via layers 163 each penetrating at least one of the one or more second build-up insulating layers 161, a first resist layer 171 disposed on the upper surface of the topmost first build-up insulating layer 151 among the one or more first build-up insulating layers 151 and covering at least a part of the topmost first build-up wiring layer 152 among the one or more first build-up wiring layers 152, and a second resist layer 172 disposed on the lower surface of the lowermost second build-up insulating layer 161 among the one or more second build-up insulating layers 161 and covering at least a part of the lowermost second build-up wiring layer 162 among the one or more second build-up wiring layers 162. The first resist layer 171 can have a plurality of first openings h1 that expose at least a part of the topmost first build-up wiring layer 152. The second resist layer 172 can have a plurality of second openings h2 that expose at least a part of the lowermost second build-up wiring layer 162. Thus, the printed circuit board 100B according to the modified example can include the printed circuit board 100A according to the above-described example as a core substrate, and can be a multilayer substrate further including build-up structures on the upper and lower sides of the core substrate, respectively. For example, it may be a multilayer substrate having a substantially symmetric structure.
[0048] Referring to FIG. 7, a printed circuit board 100C according to another modification example includes, in the printed circuit board 100A according to the above-described example, one or more first build-up insulating layers 151 disposed on the upper surface of the second insulating layer 113, one or more first build-up wiring layers 152 respectively disposed on or within the one or more first build-up insulating layers 151, one or more first build-up via layers 153 respectively penetrating at least one of the one or more first build-up insulating layers 151, a first resist layer 171 disposed on the upper surface of the topmost first build-up insulating layer 151 among the one or more first build-up insulating layers 151 and covering at least a part of the topmost first build-up wiring layer 152 among the one or more first build-up wiring layers 152, and a second resist layer 172 disposed on the lower surface of the third insulating layer 114 and covering at least a part of the second wiring layer 122. The first resist layer 171 can have a plurality of first openings h1 that respectively expose at least a part of the topmost first build-up wiring layer 152. The second resist layer 172 can have a plurality of second openings h2 that respectively expose at least a part of the second wiring layer 122. In this way, the printed circuit board 100C according to another modification example can include the printed circuit board 100A according to the above-described example as a core substrate, and can be a multilayer substrate further including a build-up structure only on the upper side of the core substrate. For example, it may be a multilayer substrate with an asymmetric structure.
[0049] Hereinafter, with reference to the drawings, the components of the printed circuit boards 100B and 100C according to the modification examples will be described in more detail.
[0050] The one or more first and second build-up insulating layers 151 and 161 can each contain an insulating material. The insulating material can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material containing an inorganic filler, an organic filler, and / or glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) together with these resins. For example, the insulating material may include a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film), PPG (Prepreg), or may include a photosensitive insulating material such as PID (Photo Imageable Dielectric). In addition, other polymer materials such as PI (Polyimide), COP (Cyclo olefin polymer), etc. may also be used. The one or more first and second build-up insulating layers 151 and 161 can contain substantially the same insulating material as each other, but are not limited thereto and can also contain different insulating materials.
[0051] One or more first and second build-up wiring layers 152 and 162 can each contain metal. The metal can include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it can contain copper (Cu), but is not limited thereto. One or more first and second build-up wiring layers 152 and 162 can each perform various functions according to the design. For example, it can include a signal pattern, a power pattern, a ground pattern, etc. These patterns can each have various forms such as lines, planes, pads, etc. One or more first and second build-up wiring layers 152 and 162 can each contain an electroless plating layer (or electroless copper) and an electrolytic plating layer (or electroplated copper). Alternatively, it can contain a metal foil (or copper foil) and an electrolytic plating layer (or electroplated copper). Alternatively, it can contain a metal foil (or copper foil), an electroless plating layer (or electroless copper), and an electrolytic plating layer (or electroplated copper). Instead of the electroless plating layer (or electroless copper), a sputtering layer may be included, or both may be included as necessary.
[0052] The one or more first and second build-up via layers 153 and 163 can each contain metal. The metal can include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it can contain copper (Cu), but is not limited thereto. The one or more first and second build-up via layers 153 and 163 can each include filled vias that fill via holes, or can also include conformal vias disposed along the wall surfaces of the via holes. The one or more first and second build-up via layers 153 and 163 can perform various functions according to the design. For example, it can include ground vias, power vias, signal vias, etc. Each of the one or more first build-up via layers 153 can have a tapered shape in the cross-section that is opposite to each of the one or more second build-up via layers 163. The one or more first and second build-up via layers 153 and 163 can each include an electroless plating layer (or electroless copper) and an electroplating layer (or electroplated copper). Instead of the electroless plating layer (or electroless copper), a sputtering layer may be included, or both may be included as needed.
[0053] The first and second resist layers 171 and 172 can include, but are not limited to, a liquid or film-type solder resist, and other types of insulating materials such as ABF (Ajinomoto Build-up Film) may be used. A surface treatment layer can be formed on the patterns exposed in the plurality of first and second openings h1 and h2, respectively, as needed. The surface treatment layer can be formed by electrolytic gold plating, electroless gold plating, OSP (Organic Solderability Preservative), or electroless tin plating, electroless silver plating, electroless nickel plating / immersion gold plating, DIG (Direct Immersion Gold) plating, HASL (Hot Air Solder Leveling), etc., but is not limited thereto. Alternatively, metal bumps may be formed on the patterns exposed in the plurality of first and second openings h1 and h2, respectively, as needed. The metal bumps can include, but are not limited to, UBM (Under Bump Metal).
[0054] Since the other contents are substantially the same as those described in the printed circuit board 100A according to the above example, duplicate descriptions thereof are omitted.
[0055] FIG. 8 is a cross-sectional view schematically showing another example of a printed circuit board, and FIGS. 9 and 10 are cross-sectional views schematically showing modified examples of the printed circuit board of FIG. 8, respectively.
[0056] Referring to FIGS. 8 to 10, a printed circuit board 100D according to another example and printed circuit boards 100E and 100F according to modified examples thereof can further include a third wiring layer 123 disposed on the upper surface of a core layer 111, for example, an inorganic substrate 111a, connected to a through via 131, and at least partially embedded in a second insulating layer 113, and a fourth wiring layer 124 disposed on the lower surface of the core layer 111, for example, the inorganic substrate 111a, connected to the through via 131, and at least partially embedded in a third insulating layer 114. A first connection via 132 can penetrate the second insulating layer 113 and connect the first and third wiring layers 121 and 123 to each other. A second connection via 133 can penetrate the third insulating layer 114 and connect the second and fourth wiring layers 122 and 124 to each other. Thus, the printed circuit board 100D according to another example and the printed circuit boards 100E and 100F according to modified examples thereof can further include third and fourth wiring layers 123 and 124 disposed on the upper and lower surfaces of the core layer 111, for example, the inorganic substrate 111a, respectively, and in direct contact with the through via 131. This can enable a more diverse wiring design. For example, the degree of freedom in design can be increased.
[0057] Hereinafter, with reference to the drawings, the components of a printed circuit board 100D according to another example and printed circuit boards 100E and 100F according to modified examples thereof will be described in more detail.
[0058] The third and fourth wiring layers 123 and 124 can each contain metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. Preferably, it can contain copper (Cu), but is not limited thereto. The third and fourth wiring layers 123 and 124 can each perform various functions according to the design. For example, it can include a signal pattern, a power pattern, a ground pattern, etc. These patterns can each have various forms such as a line, a plane, a pad, etc. The third and fourth wiring layers 123 and 124 can each contain an electroless plating layer (or electroless copper) and an electroplating layer (or electroplated copper). Alternatively, it can contain a metal foil (or copper foil) and an electroplating layer (or electroplated copper). Alternatively, it can contain a metal foil (or copper foil), an electroless plating layer (or electroless copper), and an electroplating layer (or electroplated copper). Instead of the electroless plating layer (or electroless copper), a sputtering layer can be included, or both can be included as necessary.
[0059] The other contents are substantially the same as those described in the printed circuit board 100A according to the above example and the printed circuit boards 100B and 100C according to its modified examples, so the duplicate description thereof is omitted.
[0060] FIG. 11 is a cross-sectional view schematically showing still another example of a printed circuit board, and FIGS. 12 and 13 are cross-sectional views schematically showing modified examples of the printed circuit board of FIG. 11, respectively.
[0061] Referring to FIGS. 11 to 13, a printed circuit board 100G according to still another example and printed circuit boards 100H and 100I according to modified examples thereof may further include one or more intermediate insulating layers 181 disposed between the core layer 111 and the second insulating layer 113, for example, between the inorganic substrate 111a and the second insulating layer 113, one or more intermediate wiring layers 182 respectively disposed on or in the one or more intermediate insulating layers 181, and one or more intermediate layer via layers 183 respectively penetrating at least one of the one or more intermediate insulating layers 181. The first insulating layer 112 can further cover at least a part of each outer surface of the one or more intermediate insulating layers 181. In this way, the printed circuit board 100G according to still another example and the printed circuit boards 100H and 100I according to modified examples thereof can further form an intermediate build-up structure on the core layer 111, for example, on the inorganic substrate 111a. For example, each of the core portions of the above-described unit units can further include an intermediate build-up structure and can be disposed in the through portion of the above-described frame in a state where the intermediate build-up structure is formed. As a result, more diverse wiring designs may be possible. For example, the degree of freedom in design can be increased.
[0062] Hereinafter, with reference to the drawings, the components of the printed circuit board 100G according to still another example and the printed circuit boards 100H and 100I according to modified examples thereof will be described in more detail.
[0063] One or more intermediate insulating layers 181 can each contain an insulating material. The insulating material can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material containing an inorganic filler, an organic filler, and / or glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) together with these resins. For example, the insulating material may include a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film), PPG (Prepreg), or may include a photosensitive insulating material such as PID (Photo Imageable Dielectric). Also, other polymer materials such as PI (Polyimide), COP (Cyclo olefin polymer), etc. may be used. One or more intermediate insulating layers 181 can contain substantially the same insulating material as each other, but are not limited thereto and can also contain different insulating materials.
[0064] One or more intermediate wiring layers 182 can each contain a metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. Preferably, it can contain copper (Cu), but is not limited thereto. One or more intermediate wiring layers 182 can each perform various functions according to the design. For example, it can include a signal pattern, a power pattern, a ground pattern, etc. These patterns can each have various forms such as a line, a plane, a pad, etc. One or more intermediate wiring layers 182 can each contain an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electroplated copper). Alternatively, it can contain a metal foil (or copper foil) and an electrolytic plating layer (or electroplated copper). Alternatively, it can contain a metal foil (or copper foil), an electroless plating layer (or chemical copper), and an electrolytic plating layer (or electroplated copper). Instead of the electroless plating layer (or chemical copper), a sputtering layer may be included, or both may be included as necessary.
[0065] One or more intermediate via layers 183 can each contain a metal. The metal can include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it can include copper (Cu), but is not limited thereto. One or more intermediate via layers 183 can each include a filled via that fills the via hole, or can also include a conformal via disposed along the wall surface of the via hole. One or more intermediate via layers 183 can perform various functions according to the design. For example, it can include ground vias, power vias, signal vias, etc. One or more intermediate via layers 183 can have a tapered shape in the same direction as each other in cross-section. One or more intermediate via layers 183 can each include an electroless plating layer (or electroless copper) and an electrolytic plating layer (or electroplated copper). Instead of the electroless plating layer (or electroless copper), a sputtering layer may be included, or both may be included as necessary.
[0066] The other contents are substantially the same as those described in the printed circuit board 100A according to the above example and the printed circuit boards 100B, 100C according to its modifications, and the printed circuit board 100D according to the other example above and the printed circuit boards 100E, 100F according to its modifications, so the duplicate description thereof is omitted.
[0067] FIG. 14 is a cross-sectional view schematically showing still another example of a printed circuit board, and FIGS. 15 and 16 are cross-sectional views schematically showing modifications of the printed circuit board of FIG. 14, respectively.
[0068] Referring to FIGS. 14 to 16, a printed circuit board 100J according to still another example and printed circuit boards 100K and 100L according to modified examples thereof can further include a frame 210 that covers at least a part of the outer surface of the first insulating layer 112. The second insulating layer 113 can be further extended and disposed above the frame 210. For example, at least a part of the upper surface of the frame 210 can be further covered. The third insulating layer 114 can be further extended and disposed below the frame 210. For example, at least a part of the lower surface of the frame 210 can be further covered. The frame 210 can be disposed so as to substantially continuously surround the outer surface of the first insulating layer 112, and the first insulating layer 112 can be disposed so as to substantially continuously surround the outer surface of the core layer 111. In this way, for substrate characteristics, warpage control, etc., the singulation process can also be performed so that the frame 210 used as a jig in the above-described process remains on the outermost side. As a result, a printed circuit board 100J according to still another example and printed circuit boards 100K and 100L according to modified examples thereof can further include a frame 210 that covers at least a part of the outer surface of the first insulating layer 112.
[0069] Since the other contents are substantially the same as those described in the printed circuit board 100A according to the above-described example and the printed circuit boards 100B and 100C according to modified examples thereof, duplicate descriptions thereof are omitted.
[0070] FIG. 17 is a cross-sectional view schematically showing still another example of a printed circuit board, and FIGS. 18 and 19 are cross-sectional views schematically showing modified examples of the printed circuit board of FIG. 17, respectively.
[0071] Referring to FIGS. 17 to 19, the printed circuit board 100M according to still another example and the printed circuit boards 100N and 100O according to its modified examples may further include a frame 210 that covers at least a part of the outer surface of the first insulating layer 112. The second insulating layer 113 can be further extended and disposed above the frame 210. For example, at least a part of the upper surface of the frame 210 can be further covered. The third insulating layer 114 can be further extended and disposed below the frame 210. For example, at least a part of the lower surface of the frame 210 can be further covered. The frame 210 can be disposed so as to substantially continuously surround the outer surface of the first insulating layer 112, and the first insulating layer 112 can be disposed so as to substantially continuously surround the outer surface of the core layer 111. In this way, for the sake of substrate characteristics, warpage control, etc., the singulation process can also be performed so that the frame 210 used as a jig in the above-described process remains on the outermost side. As a result, the printed circuit board 100M according to still another example and the printed circuit boards 100N and 100O according to its modified examples may further include a frame 210 that covers at least a part of the outer surface of the first insulating layer 112.
[0072] The other contents are substantially the same as those described in the printed circuit board 100A according to the above-described example and the printed circuit boards 100B, 100C according to its modified examples, and the printed circuit board 100D according to the above-described other example and the printed circuit boards 100E, 100F according to its modified examples. Therefore, the duplicate description thereof is omitted.
[0073] FIG. 20 is a cross-sectional view schematically showing still another example of a printed circuit board, and FIGS. 21 and 22 are cross-sectional views schematically showing modified examples of the printed circuit board of FIG. 20, respectively.
[0074] Referring to FIGS. 20 to 22, the printed circuit board 100P according to still another example and the printed circuit boards 100Q and 100R according to modified examples thereof can further include a frame 210 that covers at least a part of the outer surface of the first insulating layer 112. The second insulating layer 113 can be further extended and disposed above the frame 210. For example, at least a part of the upper surface of the frame 210 can be further covered. The third insulating layer 114 can be further extended and disposed below the frame 210. For example, at least a part of the lower surface of the frame 210 can be further covered. The frame 210 can be disposed so as to substantially continuously surround the outer surface of the first insulating layer 112, and the first insulating layer 112 can be disposed so as to substantially continuously surround the outer surface of the core layer 111. Thus, for the purpose of substrate characteristics, warpage control, etc., the singulation process can also be performed so that the frame 210 used as a jig in the above-described process remains on the outermost side. As a result, the printed circuit board 100P according to still another example and the printed circuit boards 100Q and 100R according to modified examples thereof can further include a frame 210 that covers at least a part of the outer surface of the first insulating layer 112.
[0075] The other contents are substantially the same as those described in the printed circuit board 100A according to one example described above and the printed circuit boards 100B, 100C according to modified examples thereof, and the printed circuit board 100G according to still another example described above and the printed circuit boards 100H, 100I according to modified examples thereof. Therefore, the duplicate description thereof is omitted.
[0076] In the present invention, the expression "cover" can include not only the case of covering entirely but also the case of covering at least a part, and further can include not only the case of directly covering but also the case of indirectly covering. Also, the expression "fill" can include not only the case of completely filling but also the case of filling at least a part or generally filling, for example, the case where there are some voids or voids. Also, the expression "surround" can include not only the case of completely surrounding but also the case of generally surrounding. Further, "exposing" can include not only the case of completely exposing but also the case of exposing at least a part, and "exposure" can mean exposing from embedding the said structure. For example, an opening exposing a pad means exposing the pad from a resist layer, and a surface treatment layer or the like can be further disposed on the exposed pad.
[0077] In the present invention, it can be judged including substantially process errors, position deviations, errors at the time of measurement, etc. generated in the manufacturing process. For example, "substantially perpendicular" can include not only the case of being completely perpendicular but also the case of being almost perpendicular. Also, "substantially coplanar" can include not only the case of existing on exactly the same plane but also the case of existing on almost the same plane.
[0078] In the present invention, "the same insulating material" can mean not only the case of being exactly the same insulating material but also including the same type of insulating material. Therefore, although the composition of the insulating material is substantially the same, these specific composition ratios may be slightly different.
[0079] In the present invention, the meaning in the cross-section can mean the cross-sectional shape when the object is cut perpendicularly, or the cross-sectional shape when the object is viewed in a side view. Also, the meaning on the plane can mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed in a top view or a bottom view.
[0080] In the present invention, terms such as "lower side", "lower part", and "lower surface" are used, for the sake of convenience, to mean downward with reference to the cross-section of the drawing, and terms such as "upper side", "upper part", and "upper surface" are used to mean the opposite direction. However, this is only a definition of direction for the sake of explanation, and it goes without saying that the scope of rights in the claims is not particularly limited by the description of such direction, and the concept of up / down can be changed at any time.
[0081] In the present invention, the term "connected" includes not only being directly connected but also being indirectly connected via an adhesive layer or the like. Further, the term "electrically connected" includes both the case of being physically connected and the case of not being connected. Furthermore, expressions such as "first" and "second" are used to distinguish one component from another component, and do not limit the order and / or importance of the said component. In some cases, within the scope not departing from the scope of rights, the first component may be named the second component, and similarly, the second component may be named the first component.
[0082] In the present invention, thickness, width, length, depth, etc. can be measured with a scanning microscope or an optical microscope, etc. with reference to the cross-section obtained by polishing or cutting the printed circuit board. The cut cross-section can be a vertical cross-section or a horizontal cross-section, and each numerical value can be measured with reference to the required cut cross-section. When the numerical values are not constant, the numerical value can be determined as the average value of the values measured at any five points.
[0083] In the present invention, the expression "an example" used does not mean the same embodiment as each other, but is provided to emphasize and explain each different unique feature. However, the above-mentioned example does not exclude being realized in combination with the features of another example. For example, even if the matter described in a specific example is not described in another example, in another example, as long as there is no description contrary to or contradictory to that matter, it can be understood as an explanation related to another example.
[0084] The terms used in the present invention are used merely for the purpose of illustration and are not intended to limit the present invention. At this time, singular expressions include plural expressions unless the context clearly indicates a different meaning.
Explanation of Signs
[0085] 1000: Electronic device 1010: Main board 1020: Chip-related components 1030: Network-related components 1040: Other components 1050: Camera 1060: Antenna 1070: Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Motherboard 1120: Components 1121: Component package 1130: Camera module 1140: Speaker 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K, 100L, 100M, 100N, 100O, 100P, 100Q, 100R: Printed circuit board 111: Core layer 112, 113, 114: Insulating layer 111a: Inorganic substrate 111b-1: Inorganic insulating film (oxide film) 111b-2: Inorganic insulating film (nitride film) 121, 122, 123, 124: Wiring layer 131: Through via 132, 133: Connection via 140: Capacitor 141: Conductive trench 151, 161: Build-up insulating layer 152, 162: Build-up wiring layer 153, 163: Build-up via layer 171, 172: Resist layer 181: Intermediate insulating layer 182: Intermediate wiring layer 183: Intermediate via layer 210: Frame 210H: Through-hole 220: Tape H: Through-hole h1, h2: Opening
Claims
1. An inorganic substrate; a through via penetrating the inorganic substrate; A first insulating layer covering at least a portion of an outer surface of the inorganic substrate; a second insulating layer disposed on an upper surface of the inorganic substrate and the first insulating layer; a third insulating layer disposed on a lower surface of the inorganic substrate and a lower surface of the first insulating layer; a first wiring layer disposed on an upper surface of the second insulating layer; a second wiring layer disposed on a lower surface of the third insulating layer; the inorganic substrate comprises silicon or ceramic; A printed circuit board, wherein the inorganic substrate has a width different between an upper end and a lower end in cross section.
2. The inorganic substrate has a cross-sectional width at an upper end that is smaller than a cross-sectional width at a lower end, The printed circuit board of claim 1 , wherein the inorganic substrate has an outer surface that is sloped.
3. The inorganic insulating film further includes an inorganic insulating film covering at least a portion of each of an upper surface and a lower surface of the inorganic substrate, an outer surface of the inorganic substrate is spaced apart from the inorganic insulating film; The printed circuit board of claim 1 , wherein an outer surface of the inorganic substrate is in contact with the first insulating layer.
4. The printed circuit board according to claim 3 , wherein the inorganic insulating film comprises an oxide film disposed on the inorganic substrate and a nitride film disposed on the oxide film.
5. the inorganic substrate has a through hole in which the through via is disposed, The printed circuit board according to claim 3 , wherein the inorganic insulating film extends between the inorganic substrate and the through via and further covers at least a portion of a wall surface of the through hole.
6. 6. The printed circuit board of claim 5, wherein the through via includes a first metal layer disposed on the inorganic insulating film within the through hole, and a second metal layer on the first metal layer filling at least a portion of the through hole and having a wider cross section than the first metal layer.
7. The printed circuit board of claim 1 , wherein the first, second and third insulating layers each comprise an organic insulating material.
8. the first insulating layer has an interlayer boundary with each of the second insulating layer and the third insulating layer; 8. The printed circuit board of claim 7, wherein the upper and lower surfaces of the first insulating layer are coplanar with the upper and lower surfaces, respectively, of the inorganic substrate.
9. The printed circuit board of claim 7 , wherein the first insulating layer is integrated with at least one of the second insulating layer and the third insulating layer without an interlayer boundary.
10. a first connection via that penetrates the second insulating layer and connects the through via and the first wiring layer to each other; The printed circuit board according to claim 1 , further comprising: a second connection via that penetrates the third insulating layer and connects the through via and the second wiring layer to each other.
11. a third wiring layer disposed on the upper surface of the inorganic substrate, connected to the through via, and at least a portion of which is embedded in the second insulating layer; a fourth wiring layer disposed on the lower surface of the inorganic substrate, connected to the through via, and at least a portion of which is embedded in the third insulating layer; a first connection via that penetrates the second insulating layer and connects the first wiring layer and the third wiring layer to each other; The printed circuit board according to claim 1 , further comprising: a second connection via penetrating the third insulating layer and connecting the second wiring layer and the fourth wiring layer to each other.
12. one or more intermediate insulating layers disposed between the inorganic substrate and the second insulating layer; one or more intermediate wiring layers disposed on or within the one or more intermediate insulating layers; and one or more intermediate via layers each penetrating at least one of the one or more intermediate insulating layers; The printed circuit board of claim 11 , wherein the first insulating layer further covers at least a portion of an outer surface of each of the one or more intermediate insulating layers.
13. one or more first build-up insulating layers disposed on an upper surface of the second insulating layer; one or more first build-up wiring layers disposed on or within the one or more first build-up insulating layers; one or more first build-up via layers each penetrating at least one of the one or more first build-up insulating layers; one or more second build-up insulating layers disposed on a lower surface of the third insulating layer; one or more second build-up wiring layers disposed on or within the one or more second build-up insulating layers; one or more second build-up via layers each penetrating at least one of the one or more second build-up insulating layers; a first resist layer disposed on an upper surface of a first build-up insulation layer that is disposed on the uppermost side of the one or more first build-up insulation layers, and covering at least a portion of the first build-up wiring layer that is disposed on the uppermost side of the one or more first build-up wiring layers; a second resist layer disposed on a lower surface of a second build-up insulation layer disposed at the lowest side of the one or more second build-up insulation layers, and covering at least a portion of the second build-up wiring layer disposed at the lowest side of the one or more second build-up wiring layers, the first resist layer has a plurality of first openings each exposing at least a part of a first build-up wiring layer disposed on the uppermost side, The printed circuit board according to claim 1 , wherein the second resist layer has a plurality of second openings each exposing at least a portion of the second build-up wiring layer disposed on the lowermost side.
14. one or more first build-up insulating layers disposed on an upper surface of the second insulating layer; one or more first build-up wiring layers disposed on or within the one or more first build-up insulating layers; one or more first build-up via layers each penetrating at least one of the one or more first build-up insulating layers; a first resist layer disposed on an upper surface of a first build-up insulation layer that is disposed on the uppermost side of the one or more first build-up insulation layers, and covering at least a portion of the first build-up wiring layer that is disposed on the uppermost side of the one or more first build-up wiring layers; a second resist layer disposed on a lower surface of the third insulating layer and covering at least a portion of the second wiring layer; the first resist layer has a plurality of first openings each exposing at least a part of a first build-up wiring layer disposed on the uppermost side, The printed circuit board according to claim 1 , wherein the second resist layer has a plurality of second openings each exposing at least a portion of the second wiring layer.
15. a frame covering at least a portion of an outer surface of the first insulating layer; the second insulating layer is disposed so as to extend further onto an upper surface of the frame; The printed circuit board of claim 1 , wherein the third insulating layer is disposed so as to extend further onto a lower surface of the frame.
16. 10. The printed circuit board of claim 1 further comprising a capacitor comprising a plurality of conductive trenches each extending from a top surface or a bottom surface of the inorganic substrate through a portion of the inorganic substrate.