Feedback loop for controlling pulsed voltage waveform

Abstract

To solve the critical technological challenge of reliably manufacturing high aspect ratio features, which is essential for next-generation ultra-large-scale and extreme large-scale integration in semiconductor devices.SOLUTION: The present disclosure describes a feedback loop that can be used to maintain a substantially constant sheath voltage and thereby generate a single-energy IEDF on the substrate surface. Therefore, the system described herein ultimately enables precise control over the shape of the IEDF and the profile of the features formed on the substrate surface.SELECTED DRAWING: Figure 1B

Description

[Technical Field]

[0001] FIELD OF THE INVENTION

[0001] Embodiments described herein relate generally to plasma processing chambers used in semiconductor manufacturing, and more particularly to apparatus and methods for controlling the supply of power to a plasma formed in a plasma processing chamber. [Background technology]

[0002]

[0002] Reliably fabricating high aspect ratio features is one of the key technological challenges in the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. One method for forming high aspect ratio features is to use a plasma-assisted etching process (e.g., a reactive ion etch (RIE) plasma process) to form high aspect ratio openings in a material layer (e.g., a dielectric layer) of a substrate. In a typical RIE plasma process, a plasma is formed in an RIE processing chamber, and ions from the plasma are accelerated toward the surface of the substrate to form openings in a material layer disposed below a mask layer formed on the surface of the substrate.

[0003] A typical reactive ion etching (RIE) plasma processing chamber includes a radio frequency (RF) bias generator. The RF bias generator supplies an RF voltage to a "powered electrode" (e.g., bias electrode), more commonly referred to as a "cathode," such as a metal base plate embedded in an "electrostatic chuck" (ESC) assembly. The powered electrode is capacitively coupled to the processing system's plasma through a thick layer of dielectric material (e.g., ceramic material) that is part of the ESC assembly. Application of an RF voltage to the powered electrode forms an electron-repulsive plasma sheath (also called a "cathode sheath") at the processing surface of a substrate placed on the substrate support surface of the ESC assembly during processing. The nonlinear, diode-like nature of the plasma sheath causes rectification of the applied RF field, resulting in a direct current (DC) voltage drop (i.e., a "self-bias") appearing between the substrate and the plasma, making the substrate potential negative with respect to the plasma potential. This voltage drop determines the average energy of plasma ions accelerated toward the substrate and, therefore, the etch anisotropy. More specifically, ion directionality, feature profile, and etch selectivity relative to mask and stop layers are controlled by the ion energy distribution function (IEDF). In a plasma with RF bias, the IEDF typically has two peaks: one at low energy and one at high energy, with some ion population between them. The presence of ion population between the two peaks of the IEDF reflects the fact that the voltage drop between the substrate and plasma oscillates with the RF bias frequency. When using a lower-frequency (e.g., 2 MHz) RF bias generator to achieve higher self-bias voltages, the energy difference between these two peaks can be significant. Furthermore, the etching profile resulting from ions at the low-energy peak is more isotropic, which can result in curvature of the etched feature walls.Compared to high-energy ions, low-energy ions are less effective at reaching the bottom corners of etched features (e.g., due to charging effects), but cause less sputtering of mask material. This is important in high-aspect ratio etch applications, such as hard mask opening or dielectric mold etching. As feature sizes continue to decrease and aspect ratios increase, while feature profile control requirements become more stringent, it is more desirable to have a well-controlled IEDF at the substrate surface during processing.

[0004] A pulsed voltage waveform generator (PVWG) can be used to generate a pulsed voltage waveform at an electrode embedded in an electrostatic chuck (ESC) assembly in a semiconductor plasma chamber to maintain a specific substrate voltage waveform and control the sheath voltage and IEDF at a substrate during plasma processing. When a semiconductor plasma chamber is used as a load, real-time changes in the load (e.g., plasma density flow, chamber wall conditions, substrate temperature, degree and state of chemical dissociation) can cause difficulties in controlling the generated waveform. Therefore, real-time information about the waveform can be very useful for making real-time adjustments to PVWG control parameters (e.g., charging voltage of a DC power supply or pulse width controlled by an arbitrary waveform generator) and thus maintaining a predetermined voltage waveform regardless of load changes. Such real-time measurement and analysis performed in conjunction with real-time control are often referred to as "closed feedback loop operation." However, certain difficulties arise in measuring and analyzing pulsed voltage waveforms due to their very high amplitude (e.g., several kV to tens of kV, as frequently encountered in plasma processing) and the complex characteristics of loads such as semiconductor plasma chambers. When the PVWG is connected to a complex load (which may include series and / or parallel combinations of discrete capacitive, inductive, resistive, and nonlinear elements (e.g., a plasma sheath at the substrate surface in a process chamber), as well as dispersive elements (e.g., a section of a transmission line)), the resulting waveform may have a much more complex structure than theoretically predicted (expected) waveform and may contain high-frequency oscillations, which may affect the ability to repeatably control the plasma process.

[0005]

[0005] Therefore, there is a need in the art for a novel biasing method that allows for the maintenance of a nearly constant sheath voltage to enable precise control over the shape of the IEDF and the profile of features formed on the surface of the substrate, thereby producing a desired and repeatable monoenergetic IEDF at the surface of the substrate.

[0006]

[0006] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only exemplary embodiments and therefore should not be considered to limit the scope of the present disclosure, as other equally effective embodiments may also be permitted. [Brief explanation of the drawings]

[0007] [Figure 1A] FIG. 1 is a schematic diagram of a feedback loop configured to be attached to a plasma processing chamber, according to one embodiment. [Figure 1B] FIG. 1B is a schematic diagram illustrating an example of the feedback loop shown in FIG. 1A, according to one embodiment. [Figure 1C] FIG. 1B is a schematic diagram illustrating an example of the feedback loop shown in FIG. 1A, according to one embodiment. [Figure 1D] FIG. 1B is a schematic diagram illustrating an example of the feedback loop shown in FIG. 1A, according to one embodiment. [Figure 2] FIG. 1 is a schematic diagram of a voltage divider that may be placed in a feedback loop according to one or more embodiments. [Figure 3] FIG. 1 is a schematic diagram of a low-pass filter that may be placed in a feedback loop according to one or more embodiments. [Figure 4] FIG. 4 illustrates a frequency response curve of the low pass filter shown in FIG. 3 according to one embodiment. [Figures 5A-5D] 1 illustrates an example of a regulated voltage waveform produced by components in a feedback loop according to one or more embodiments. [Figures 6A-6B] 4 illustrates examples of various types of measured voltage waveforms, according to one embodiment. [Figure 7A] 1 illustrates an example series of measured voltage waveforms according to one or more embodiments. [Figure 7B]1 illustrates an example series of measured voltage waveform bursts according to one or more embodiments. [Figure 8A] 1 is a schematic cross-sectional view of a processing chamber configured to perform the methods described herein, according to one embodiment. [Figure 8B] FIG. 8B is a functionally equivalent approximation circuit diagram of a pulsed voltage bias scheme that may be used with the processing chamber shown in FIG. 8A, according to one embodiment. [Figure 9A] 1 illustrates an example of a pulsed voltage waveform established at a bias electrode, according to one embodiment. [Figure 9B] 1 illustrates an example of a pulsed voltage waveform established at a substrate, according to one embodiment. [Figure 9C] 1 illustrates an example of a single-peak IEDF, according to one embodiment. [Figure 10] FIG. 2 is a flow diagram of a method for processing a substrate using a pulsed voltage bias scheme described herein, according to one embodiment. [Figure 11] FIG. 2 is a flow diagram of a method for processing a substrate using a pulsed voltage bias scheme described herein, according to one embodiment.

[0008]

[0025] For ease of understanding, where possible, identical reference numerals have been used to designate identical elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further description. Summary of the Invention

[0009]

[0026] Embodiments of the disclosure provided herein may include a feedback loop for controlling a pulsed voltage waveform with a data acquisition system, the feedback loop including a first input channel including a first conditioning circuit configured to generate a first regulated voltage waveform from a first input voltage waveform, and a high-speed data acquisition module. The high-speed data acquisition module may include a first acquisition channel electrically coupled to the first conditioning circuit of the first input channel and configured to generate a first digitized voltage waveform from the first regulated voltage waveform, and a data acquisition controller configured to determine one or more single-cycle waveform characteristics of the first regulated voltage waveform by analyzing the first digitized voltage waveform. The feedback loop may further include a feedback processor configured to process information about the first regulated voltage waveform processed by the high-speed data acquisition module. In some embodiments, the pulsed voltage waveform is established by a pulsed voltage waveform generator electrically coupled to a bias electrode disposed in a substrate support assembly disposed in a plasma processing chamber.

[0010]

[0027]

[0006] Embodiments of the disclosure provided herein may further include a feedback loop for controlling a pulsed voltage waveform with a data acquisition system, the feedback loop including a first input channel including a first conditioning circuit configured to generate a first regulated voltage waveform from a first input voltage waveform, a second input channel including a second conditioning circuit configured to generate a second regulated voltage waveform from a second input voltage waveform, and a high-speed data acquisition module. The high-speed data acquisition module may include a first acquisition channel electrically coupled to the first conditioning circuit of the first input channel and configured to generate a first digitized voltage waveform from the first regulated voltage waveform, a second acquisition channel electrically coupled to the second conditioning circuit of the second input channel and configured to generate a second digitized voltage waveform from the second regulated voltage waveform, and a data acquisition controller configured to determine one or more single-cycle waveform characteristics of at least one of the first regulated voltage waveform and the second digitized voltage waveform by analyzing at least one of the first digitized voltage waveform and the second digitized voltage waveform. In some embodiments, the pulsed voltage waveform is established by a pulsed voltage waveform generator electrically coupled to a bias electrode disposed in a substrate support assembly disposed in the plasma processing chamber. In some embodiments, the pulsed voltage waveform generator is further electrically coupled to the bias electrode via an electrical conductor using a generator coupling assembly, an input end of a first input channel electrically coupled to an end of the generator coupling assembly, and an input end of a second input channel electrically coupled to one of an output of a current monitor and an ungrounded end of a current sensing resistor, the current monitor being configured to sense a current flowing in the electrical conductor, and the current sensing resistor being disposed in the pulsed voltage waveform generator. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0028] The embodiments of the disclosure provided herein include a closed feedback loop scheme suitable for operation with a pulsed voltage waveform generator to generate a controlled and repeatable pulsed voltage waveform. Accordingly, the embodiments described herein can be used in many different types of plasma-assisted or plasma-enhanced processing chambers used to perform plasma-assisted or plasma-enhanced processing of substrates. While not intending to limit the scope of the disclosure provided herein, in some embodiments, a pulsed voltage bias scheme is used during plasma processing to maintain a nearly constant sheath voltage for up to about 90% of the substrate processing time, resulting in a single (narrow) peak IEDF that can be used to generate IEDFs having any shape. Furthermore, in one or more of the embodiments disclosed herein, the plasma processing method includes a pulsed voltage waveform that further includes multiple cycles (e.g., a series of short positive pulses repeating with a period Ts (e.g., 2.5 microseconds)), where the total period Tp of each pulse is typically on the order of tens of nanoseconds (e.g., 10 to 100 nanoseconds), and each cycle of the multiple cycles corresponds to one or more pulses.

[0012]

[0029] 1A schematically illustrates a feedback loop 100 electrically coupled to one or more electrical components found within a plasma processing system 50. Generally, the feedback loop 100 includes one or more input channels 110 and a high-speed data acquisition module 120. The one or more input channels 110 are electrically coupled to the high-speed data acquisition module 120. In some embodiments, the high-speed data acquisition module 120 is configured to control and maintain a generated pulsed voltage waveform (e.g., a high-voltage nanosecond substrate voltage waveform), thereby controlling the sheath voltage and IEDF at the substrate during plasma processing. Additionally, the high-speed data acquisition module 120 includes one or more acquisition channels 122.

[0013]

[0030] The input ends of one or more input channels 110 are coupled to a connection point 135 within the plasma processing system 50. Thus, an input pulsed voltage waveform 140 received by the one or more input channels 110 and then conditioned can be processed by components within the high-speed data acquisition module 120 and components within the feedback processor 125 so that control parameters can be provided to a pulsed waveform generator (e.g., pulsed voltage waveform generator (PVWG) 150 of FIG. 1B ) within the plasma processing system 50 to control characteristics of a pulsed voltage waveform established at an electrode (e.g., a bias electrode disposed within the substrate support) positioned within the processing chamber of the plasma processing system 50. The one or more input channels 110 receive the input pulsed voltage waveform 140 and generate an output waveform 144 from the input pulsed voltage waveform 140. As described in more detail below, the input pulsed voltage waveform 140 can be processed by the input channel 110 to generate an output waveform 144 including the conditioned waveform. For example, input channel 110 may condition a received input pulsed voltage waveform 140 via a conditioning circuit to generate output waveform 144. Thus, for example, the amplitude and / or shape of output waveform 144 may differ from the amplitude and / or shape of input pulsed voltage waveform 140. Note that the characteristics of the pulsed voltage waveform received by input channel 110 (i.e., input pulsed voltage waveform 140) may have different characteristics depending on the location of connection point 135 relative to inductive, capacitive, or resistive elements formed and / or arranged in one or more circuits coupled to composite load 130 ( FIG. 1B ) of plasma processing system 50. In some embodiments, input channels 110 in feedback loop 100 may each have different input signal attenuation due to different types of components (e.g., voltage dividing components or filtering components) within each input channel. Thus, input channels 110 may be referred to herein as highly attenuated, medium attenuated, or low attenuated, or unattenuated, based on the degree of attenuation or conditioning of the received input pulsed voltage waveform 140 .

[0014]

[0031] FIG. 1B schematically illustrates an example of the feedback loop 100 shown in FIG. 1A. It includes multiple input channels 110, each electrically coupled to a corresponding acquisition channel 122 of the high-speed data acquisition module 120. As shown in FIG. 1B, the input channels 110 may be coupled to connection points coupled to conductive elements located on either side of a generator coupling assembly 133, all of which are used in combination to connect the output of the PVWG 150 to the composite load 130. Generally, the conductive elements and generator coupling assembly 133 used to connect the output of the PVWG 150 to the composite load 130 are often referred to herein as elements in a transmission line 131. Thus, the PVWG 150 is electrically connected to the composite load 130 via the transmission line 131 and the reference line 132. Generally, the term "electrical conductor" or "conductor" as used herein may include the following: (a) a coaxial transmission line, which may include a flexible coaxial cable in series with a rigid coaxial transmission line; (b) an insulated high-voltage corona-resistant hookup wire; (c) a bare wire; (d) a metal rod; (e) an electrical connector; or (f) any combination of the electrical elements of (a)-(e). While FIG. 1B schematically illustrates a configuration in which multiple input channels 110 are coupled to a connection point that is coupled to one of one or more conductive elements used to connect the output of the PVWG 150 to the composite load 130 and / or one or more circuits within the PVWG 150, this configuration is not intended to limit the scope of the disclosure provided herein, as the number of input channels 110 and / or the number of different locations to which various input channels 110 can be connected within the plasma processing system 50 can be increased or decreased as needed to control a desired chamber processing application.

[0015]

[0032] 1B, plasma processing system 50 includes a pulsed voltage waveform generator (PVWG), such as PVWG 150 of processing chamber 800 shown generally in FIGS. 8A and 8B. Additionally, plasma processing system 50 includes a composite load 130. Composite load 130 includes and / or is formed by a pulsed voltage waveform at a bias electrode (e.g., bias electrode 804 in FIG. 8A) during plasma processing. Feedback loop 100 is generally configured to control the pulsed voltage waveform generated by PVWG 150 by adjusting one or more characteristics of the pulsed voltage waveform.

[0016]

[0033] One or more of the input channels 110 may include a conditioning circuit 111, such as, for example, conditioning circuit 1111 in input channel 1101 and conditioning circuit 1112 in input channel 1102. Further, one or more of the input channels 110 are configured to generate a conditioned output waveform 144. In some embodiments, the conditioning circuits 111 may each include a voltage divider (e.g., voltage divider 112 of FIG. 2), a low-pass filter 114 (e.g., the low-pass filter of FIG. 3), both a voltage divider and a low-pass filter 114, or in some cases, no voltage divider or low-pass filter 114, referred to herein as an unattenuated conditioning circuit. In one example, feedback loop 100 includes at least three conditioning circuits 111, one conditioning circuit including a high-ratio voltage divider, another including a medium-ratio voltage divider, and another conditioning circuit including only a filter and therefore no voltage divider. In an embodiment in which the conditioning circuit 111 of the input channel 110 includes a voltage divider and also a low-pass filter, the voltage divider 112 is electrically coupled to the low-pass filter 114. Furthermore, in such an embodiment, the voltage divider generates a divided voltage waveform from the input pulsed voltage waveform 140, and the low-pass filter generates a filtered voltage waveform from the divided voltage waveform. In an embodiment in which the low-pass filter is omitted, the voltage divider generates a divided voltage waveform from the input pulsed voltage waveform 140, and the divided voltage waveform is communicated to the high-speed data acquisition module 120. In such an embodiment, the divided voltage waveform is the conditioned voltage waveform, which is the output waveform 144. In an embodiment in which the voltage divider and the low-pass filter are both omitted from the input channel 110, the input pulsed voltage waveform 140 is also the output waveform 144. In embodiments where the voltage divider is omitted but a low-pass filter is present in the conditioning circuit 111, the low-pass filter generates a filtered voltage waveform from the input pulsed voltage waveform 140, and the filtered waveform is communicated to the high-speed data acquisition module 120.

[0017]

[0034] FIG. 1B shows input channels 1101 to 110 Nwhere N is generally a number greater than 1 (e.g., a number greater than 3), as shown in FIG. 1B. N may each be connected to various points within the plasma processing system 50. For example, the input channel 1101 may be connected to electrical conductors located on either side of the generator coupling assembly 133, including a blocking capacitor (e.g., capacitor C in FIG. 8B ). HVM ) may be included. For example, input channel 1101 may be coupled between composite load 130 and generator linkage assembly 133, or input channel 1101 may be coupled between the output of PVWG 150 and generator linkage assembly 133. In embodiments where input channel 1101 is coupled between the output of PVWG 150 and generator linkage assembly 133, input channel 1101 may receive input pulsed voltage waveform 140 1A and conditioning circuit 1111 generates an output waveform (e.g., a conditioned waveform) 144 1A In one embodiment, the received or measured input pulsed voltage waveform 140 1A represents voltage pulses that include positive and negative voltage levels at various phases of each voltage pulse (i.e., pulses that are above and below the dashed zero volt reference line), as well as an input pulsed voltage waveform 140 1A These include high frequency oscillations within the various phases of the pulses (see, for example, the dashed circle highlighting the region of the pulse), which are then fed to the conditioning circuit 111 1A When adjusted by components such as a voltage divider within the 1A In an embodiment where the input channel 1101 is coupled between the composite load 130 and the generator coupling assembly 133, the input channel 1101 generates an input pulsed voltage waveform 140 1B and conditioning circuit 1111 generates an output waveform (e.g., a conditioned waveform) 144 1B As shown in FIG. 1B, an input pulsed voltage waveform 140 1A The input pulsed voltage waveform 140 is generated by the position of each of its connection points along the transmission line 131 within the plasma processing system 50. 1BAlternatively, in one embodiment, the received or measured input pulsed voltage waveform 140, as shown in FIG. 1B is the input pulse voltage waveform 140 1B (For example, pulse region I 1B ) includes a positive voltage pulse (i.e., the pulse is above the dashed zero volt reference line) that includes high frequency oscillations in the phase of the pulse in 1B When adjusted by components such as a voltage divider and low pass filter within the output waveform 144, the filtered waveform at a reduced voltage level is generated. 1B Form.

[0018]

[0035] 1B , input channel 1102 is connected to or attached to current monitor 134 in PVWG 150. Thus, input channel 1102 receives input pulsed voltage waveform 1402, and conditioning circuit 1112 generates output waveform (conditioned waveform) 1442. In one embodiment, as shown in FIG. 1B , received or measured input pulsed voltage waveform 1402 includes voltage pulses with positive and negative voltage levels in various phases of each voltage pulse, as well as high-frequency oscillations (e.g., see dashed circles highlighting the regions of the pulses) within at least one of the phases of each pulse in input pulsed voltage waveform 1402, which, when conditioned by components such as a voltage divider and low-pass filter, form output waveform 1442 in conditioning circuit 1112, which is a filtered waveform with reduced voltage levels.

[0019]

[0036] 1B , the received or measured input pulsed voltage waveform 1403 includes positive voltage pulses and high-frequency oscillations within at least one of the phases of each pulse in the input pulsed voltage waveform 1403 (see, e.g., the dashed circles), which, when conditioned by components in the conditioning circuit 1113, such as a low-pass filter, form the filtered waveform, output waveform 1443.

[0020]

[0037] In some embodiments, input channels 1104 to 110 N Additional input channels, such as a voltage regulator 111, may be connected to other nodes within the plasma processing system 50 to receive additional information regarding the applied pulsed voltage waveform and / or the state of the plasma process being performed within the plasma processing chamber. N is the corresponding output waveform 144 N The input channel 110 is configured to generate N is the input pulse voltage waveform 140 N and adjusts the signal received by the adjusting circuit 111. N is the output waveform (adjusted waveform) 144 N Therefore, the adjustment circuit 111 N Any of the regulation circuits 111, such as may include any combination of a voltage divider 112 (FIG. 2) and a low-pass filter 114 (FIG. 3), or may not include a voltage divider 112 or a low-pass filter 114.

[0021]

[0038] As shown in FIG. 1B, the input pulsed voltage waveform 140 1A 1403 are different from each other. 1A1443 are also different from each other. Therefore, depending on where the input end of the input channel 110 is connected to the plasma processing system 50, the characteristics of the input pulsed voltage waveform and the output waveform change, and therefore, the selection of the connection location of each input channel can affect the information received by the feedback loop 100, which can affect the ability of the feedback loop 100 to control the pulsed voltage waveform.

[0022] High-Speed ​​Data Acquisition Module

[0039] The high-speed data acquisition module 120 is generally configured to receive an analog voltage waveform (e.g., conditioned waveform 144) and transmit a digitized voltage waveform. The high-speed data acquisition module 120 includes one or more acquisition channels 122 each electrically coupled to a respective conditioning circuit 111 of the first input channel 110. The high-speed data acquisition module 120 is configured to generate a digitized voltage waveform from the received conditioned voltage waveform (e.g., output waveform 144). The data acquisition controller 123 of the high-speed data acquisition module 120 is configured to determine one or more waveform characteristics of the conditioned voltage waveform (e.g., output waveform 144) by analyzing the first digitized voltage waveform. As shown in FIG. 1B, the high-speed data acquisition module 120 includes multiple acquisition channels 1221-1222. N , a data acquisition controller 123, and a memory 124 (e.g., non-volatile memory). Each acquisition channel 122 is electrically coupled to the output of a corresponding one of the input channels 110, such that the acquisition channel 122 receives an output waveform 144 from the corresponding one of the input channels 110. For example, acquisition channel 1221 is electrically coupled to the output of input channel 1101, and receives output waveform 144 depending on the location of the connection point of the input end of input channel 1101. 1A or 144 1BFurthermore, the collection channel 1222 is electrically coupled to the output of the input channel 1102 and receives the output waveform 1442. Additionally or alternatively, the collection channel 1223 is electrically coupled to the output of the input channel 1103 and receives the output waveform 1443. N is input channel 110 N and outputs a waveform 144 N Receive.

[0023]

[0040] In some embodiments, high-speed data collection module 120 is coupled to feedback processor 125 via data communications interface 125A. Feedback processor 125 is configured to generate one or more control parameters using one or more waveform characteristics determined by one or more algorithms executed by a processor within data collection controller 123. The one or more algorithms stored in memory 124 include instructions that, when executed by processor 121 within high-speed data collection module 121, cause the high-speed data collection module to process output waveforms 144 (e.g., one or more regulated voltage waveforms) and determine one or more waveform characteristics of the received output waveforms 144. As described further below, feedback processor 125 includes a memory containing instructions that, when executed by a processor (CPU) within feedback processor 125, cause feedback processor 125 to use the determined one or more waveform characteristics provided by high-speed data collection module 120 to generate one or more control parameters. The instructions executed by the feedback processor may be further configured to cause the feedback processor to send information regarding the generated one or more control parameters to the PVWG 150. The PVWG 150 may further include a memory containing instructions that, when executed by a processor within the PVWG 150, cause the PVWG 150 to establish an adjusted pulsed voltage waveform based on the one or more control parameters generated by the feedback processor 125.

[0024]

[0041] As described above, each acquisition channel 122 processes a corresponding output waveform 144 output by a corresponding input channel 110 to generate a digitized voltage waveform from the output waveform. For example, acquisition channel 1221 processes output waveform 144 1A or 144 1B to generate a digitized voltage waveform. Additionally, acquisition channel 1222 processes output waveform 1442 to generate a digitized voltage waveform, and acquisition channel 1223 processes output waveform 1443 to generate a digitized voltage waveform. Additionally or alternatively, acquisition channel 1222 N is the output waveform 144 N is processed to generate a digitized voltage waveform.

[0025]

[0042] The data acquisition module 120 further includes a data acquisition controller 123. The data acquisition controller 123 is electrically coupled to the output of each acquisition channel 122 and configured to receive the digitized voltage waveform from each acquisition channel 122. Furthermore, an algorithm stored in a memory 124 of the data acquisition controller 123 is adapted to determine one or more waveform characteristics of each conditioned waveform (e.g., output waveform 144) by analyzing each digitized voltage waveform. The analysis may include comparing information received in the digitized voltage waveform with information about the one or more waveform characteristics stored in the memory 124, as described further below.

[0026]

[0043] The data acquisition controller 123 may include one or more of an analog-to-digital converter (ADC) (not shown), a processor 121 (FIG. 1C), a communication interface (not shown), a clock (not shown), and optional drivers (not shown). The processor may be any general-purpose arithmetic processor. Additionally, the processor may be a field programmable gate array (FPGA). The ADC converts the signals in the output waveform 144 from the analog domain to the digital domain, and the output digital signals of the ADC are provided to the processor 121 for processing. The processor 121 of the data acquisition controller 123 determines one or more waveform characteristics of the output waveform by analyzing the output digital signals provided by the ADC.

[0027]

[0044] In various embodiments, data acquisition module 120 further includes memory 124. Memory 124 may be any non-volatile memory. Furthermore, data acquisition controller 123 is electrically coupled to memory 124 and configured to store waveform characteristics in memory 124. In various embodiments, memory 124 includes instructions executable by data acquisition controller 123 that cause data acquisition controller 123 to analyze received output waveforms 144 and / or transmit information corresponding to waveform characteristics determined based on an analysis of received output waveforms 144.

[0028]

[0045] In various embodiments, memory 124 includes one or more of a data logger 124A, a waveform analyzer 124B, and executable instructions 124C. Data collection controller 123 can be configured to store information corresponding to waveform characteristics in data logger 124A of memory 124. For example, data logger 124A can include a database accessible by data collection controller 123 to store information corresponding to waveform characteristics. Waveform analyzer 124B includes instructions executable by data collection controller 123 that, when executed, cause data collection controller 123 to analyze output waveform 144 and determine waveform characteristics. Executable instructions 124C are executable by data collection controller 123 that, when executed, cause data collection controller 123 to transmit waveform characteristics or information corresponding to waveform characteristics to one or more of feedback processor 125, controller 127, controller 128, and controller 191. In one embodiment, the executable instructions 124C, when executed by the data collection controller 123, cause the data collection controller 123 to store waveform characteristics in the data logger 124A and, among other things, analyze the waveform characteristics in relation to one or more thresholds.

[0029]

[0046] The data acquisition controllers 123 are configured to receive and / or analyze in parallel the digitized voltage waveforms from each corresponding acquisition channel 122. Alternatively, the data acquisition controllers 123 are configured to receive and / or analyze in serial the digitized voltage waveforms from each corresponding acquisition channel 122.

[0030]

[0047] As described above, the data collection module 120 may be electrically (wired or wirelessly) coupled to the feedback processor 125. The feedback processor 125 may be any general-purpose computing processor. In some embodiments, the feedback processor 125 is generally one of an external processor connected to the high-speed data collection module 120 via a data communication interface, an internal processor integrated within the high-speed data collection module 120, or a controller for a substrate processing chamber (e.g., a processing chamber controller 126) connected to the high-speed data collection module via a data communication interface. The data collection module 120 may communicate information corresponding to one or more of the received output waveforms 144 to the feedback processor 125. For example, the data collection module 120 may communicate information regarding one or more detected and / or processed waveform characteristics of one or more of the received output waveforms 144 to the feedback processor 125. Furthermore, the feedback processor 125 may be communicatively coupled to the plasma processing system 50. In various embodiments, as described above, feedback processor 125 includes or is coupled to memory, which further includes software algorithms for instructing a processor within feedback processor 125 to perform one or more portions of the methods described herein.

[0031]

[0048] In one or more embodiments, the data acquisition module 120 may be electrically (wired or wirelessly) coupled to a process chamber controller 126 of a process chamber (e.g., process chamber 800 of FIG. 8A ) or a processing system including the process chamber. For example, the data acquisition module 120 sends and receives data to the process chamber controller 126 ( FIG. 1D ). For example, the data acquisition module 120 communicates information regarding one or more waveform characteristics to the process chamber controller 126. Further, the process chamber controller 126 may be communicatively coupled to the plasma processing system 50. In various embodiments, the process chamber controller 126 is omitted. The process chamber controller 126 may separately include a controller CPU (not shown), non-volatile memory (not shown), a graphical user interface (GUI) (not shown), and other useful hardware and software components that may be coded and stored in memory to instruct the CPU. Algorithms stored in the memory of the process chamber controller 126 may include instructions that, when executed by the controller CPU, cause adjustments to various process chamber set points (e.g., a chucking voltage set point on a chucking power supply) based on information regarding one or more waveform characteristics determined by the data acquisition controller 123.

[0032]

[0049] In one or more embodiments, the data collection module 120 is electrically coupled (wired or wirelessly) to a controller 127 that includes a removable memory device. For example, the data collection module 120 sends data to and receives data from the controller 127. For example, the data collection module 120 communicates information regarding one or more waveform characteristics to the removable memory device of the controller 127.

[0033]

[0050] In various embodiments, the data acquisition module 120 is electrically coupled (wired or wirelessly) to an external computing device via a communication interface. The data acquisition module 120 receives and transmits data to and from an external computing device (e.g., a computing device external to the high-speed data acquisition module 120). For example, the data acquisition module 120 communicates (e.g., receives and transmits data to) a controller of a computing device, such as the controller 128 (FIGS. 1B-1D). The data acquisition module 120 can communicate one or more detected and / or processed waveform characteristics to the controller 128. The controller 128 may be, among other things, a personal computer (PC) or a mobile computing device. Additionally, the controller 128 may be communicatively coupled to the data acquisition module 120 and / or the plasma processing system 50 (e.g., via an Ethernet connection). In various embodiments, the controller 128 is omitted.

[0034]

[0051] As explained in more detail below and in the description of FIGS. 5A-5D, determining one or more waveform characteristics generally involves determining the duration of one cycle of the pulse (T cycle ), pulse rise time (T rise ), pulse fall time (T fall ), an offset of the pulse from a reference voltage (e.g., zero volts), an amplitude of the pulse, a pulse width, a direct current (DC) voltage offset, and a phase of the pulsed voltage waveform (e.g., an ion current phase (also referred to herein as an "ion current" waveform characteristic)). Additionally or alternatively, determining one or more waveform characteristics may include determining one or more of the following: a burst of pulses (e.g., T on period, T off This involves determining waveform characteristics of the signal (or signal cycle).

[0035]

[0052] FIG. 1C illustrates a portion of a feedback loop 100A according to one or more embodiments. The feedback loop 100A is configured similarly to the feedback loop 100 of FIG. 1B. For example, the feedback loop 100A includes a high-speed data acquisition module 120 with an acquisition channel 122, a data acquisition controller 123A, and a memory 124. However, compared to the feedback loop 100 of FIG. 1B, the feedback processor 125 may be integrated with the process chamber controller 126. The integrated feedback processor 125, in this case, may include a processor 126B and a memory 126A, which includes a data logger and an algorithm solver (e.g., software instructions for determining control parameters). In the configuration illustrated in FIG. 1C, the feedback loop 100 may not include a separate feedback processor 125, because the functions of the feedback processor 125 are performed by components within the process chamber controller 126.

[0036]

[0053] FIG. 1D illustrates a portion of a feedback loop 100B according to one or more embodiments. Feedback loop 100B is configured similarly to feedback loop 100 of FIG. 1B. For example, feedback loop 100B includes a high-speed data acquisition module 120, which includes an acquisition channel 122 and a memory 124′. However, compared to feedback loop 100 of FIG. 1B, feedback loop 100B does not include a feedback processor 125. For example, in the embodiment of FIG. 1D, data acquisition controller 123B provides the functionality of data acquisition controller 123 of FIG. 1B and feedback processor 125 of FIG. 1B. In this embodiment, data acquisition controller 123B functions to both analyze output waveform 144 to determine waveform characteristics and to determine and communicate control parameters to PVWG 150.

[0037]

[0054] In one or more embodiments, the data acquisition controller 123 is coupled to a monitor 129 within the controller 191 via a digital interface. For example, the data acquisition controller 123 is coupled to the controller 191 and the monitor 129 via a Digital Visual Interface (DVI), a High-Definition Multimedia Interface (HDMI), or a Video Graphics Array (VGA), among others. The data acquisition controller 123 communicates information corresponding to one or more waveform characteristics to the monitor 129, where it is displayed for viewing by a user.

[0038]

[0055] 2 is a schematic diagram of a voltage divider (e.g., voltage divider 112) of adjustment circuit 111 according to one or more embodiments. As shown in FIG. 2, voltage divider 112 may include a first cascade voltage divider 210 and a second cascade voltage divider 212. Voltage divider 112 is electrically coupled to low-pass filter 114 via one or more electrical connections, such as signal line 221 and ground reference line 223. First cascade voltage divider 210 includes resistor R1, resistor R2, capacitor C1, and capacitor C2. Second cascade voltage divider 212 includes resistor R4, resistor R5, capacitor C3, and capacitor C4. The resistance of resistor R1, the resistance of resistor R2, the capacitance of capacitor C1, and the capacitance of capacitor C2 are selected to generate a first voltage division ratio. For example, the first voltage division ratio may range from approximately 1:20 to approximately 1:60. Furthermore, the resistance of resistor R1 may be greater than the resistance of resistor R2, and the capacitance of capacitor C2 may be greater than the capacitance of capacitor C1. For example, the resistance of resistor R1 may be approximately 950 kOhms, and the resistance of resistor R2 may be approximately 20 kOhms. Alternatively, the resistance of resistor R1 may be less than or greater than 950 kOhms, and the resistance of resistor R2 may be less than or greater than 20 kOhms. In addition, the capacitance of capacitor C2 may be approximately 650 pF, and the capacitance of capacitor C1 may be approximately 15 pF. Alternatively, the capacitance of capacitor C2 may be less than or greater than 650 pF, and the capacitance of capacitor C1 may be less than or greater than 15 pF.

[0039]

[0056] The resistance of resistor R4, the resistance of resistor R5, the capacitance of capacitor C3, and the capacitance of capacitor C4 are selected to generate a second voltage divider ratio for second voltage divider cascade 212. In some embodiments, the second voltage divider ratio is greater than the first voltage divider ratio. For example, the second voltage divider ratio may be in a range from approximately 1:80 to approximately 1:120. Furthermore, the resistance of resistor R4 is greater than the resistance of resistor R5, and the capacitance of capacitor C4 is greater than the capacitance of capacitor C1. For example, the resistance of resistor R4 may be approximately 1000 kilohms, and the resistance of resistor R5 may be approximately 10 kilohms. Alternatively, the resistance of resistor R4 may be less than or greater than 1000 kilohms, and the resistance of resistor R5 may be less than or greater than 10 kilohms. Additionally, the capacitance of capacitor C4 may be approximately 1.5 nF and the capacitance of capacitor C3 may be approximately 15 pF. Alternatively, the capacitance of capacitor C4 may be less than or greater than 1.5 nF and the capacitance of capacitor C3 may be less than or greater than 15 pF.

[0040]

[0057] In some embodiments, the first cascade voltage divider 210 is coupled to the second cascade voltage divider 212 via resistor R3. The resistance of resistor R3 may be, for example, approximately 200 kilohms. Alternatively, the resistance of resistor R3 may be greater than or less than approximately 200 kilohms. Resistor R3 can filter out high frequencies from the input pulsed voltage waveform 140. The voltage division ratio of the voltage divider 112 can be changed by changing the values ​​of capacitors C1-C4 and resistors R1, R2, R4, and R5. For example, increasing the difference between R1 and R2 and the difference between C1 and C2, and / or increasing the difference between R4 and R5 and the difference between C3 and C4 increases the voltage division ratio, whereas decreasing the difference between R1 and R2 and the difference between C1 and C2, and / or decreasing the difference between R4 and R5 and the difference between C3 and C4 decreases the voltage division ratio. In some embodiments, the first voltage divider cascade 210 has a voltage division ratio in the range of about 1:10 to about 1:100, and the second voltage divider cascade 212 has a voltage division ratio in the range of about 1:20 to about 1:120.

[0041]

[0058] In an embodiment in which the input channel 110 includes a voltage divider 112 and a low-pass filter 114, the input of the low-pass filter 114 is electrically coupled to the output of the voltage divider 112 such that the low-pass filter 114 receives the divided voltage waveform from the voltage divider 112. Furthermore, the low-pass filter 114 has a frequency response curve including a plateau and a cutoff frequency. For example, the filter response of the low-pass filter 114 has a plateau at a frequency less than a bandwidth (e.g., -3 dB) frequency of approximately 7.3 MHz. The plateau of the low-pass filter 114 is in a range from DC to approximately 7 MHz, and the cutoff frequency is in a range from approximately 5 MHz to approximately 10 MHz. FIG. 4 shows an example of a frequency response curve (e.g., frequency response curve 400) of the low-pass filter 114. As shown, the filter response curve has a plateau at a frequency less than a bandwidth (e.g., -3 dB) frequency of approximately 7.3 MHz. Alternatively, the bandwidth frequency may be greater or less than approximately 7.3 MHz.

[0042]

[0059] FIG. 3 is a schematic diagram of a low-pass filter (e.g., low-pass filter 114) of adjustment circuit 111 according to one or more embodiments. As shown in FIG. 3, low-pass filter 114 includes filter cascade 222 and filter cascade 224. Filter cascade 222 may be a two-stage Chebyshev filter. For example, filter cascade 222 may be a two-stage Chebyshev filter with a stop-band attenuation of approximately 0.1 dB. Alternatively, a two-stage Chebyshev filter with a stop-band attenuation of less than or greater than 0.1 dB may be utilized. Filter cascade 222 includes resistors R6 and R7, capacitors C6 and C5, and operational amplifier 225. The resistances of resistors R6 and R7 may be the same. For example, the resistances of resistors R6 and R7 may be approximately 50 ohms. However, other resistance values ​​may be utilized. Furthermore, in one embodiment, the capacitance of capacitor C6 may be approximately 360 pF and the capacitance of capacitor C5 may be approximately 147 pF. However, other capacitance values ​​may be utilized. Additionally, filter cascade 222 may have a cutoff frequency of approximately 15 MHz. Alternatively, filter cascade 222 may have a cutoff frequency less than or greater than approximately 15 MHz.

[0043]

[0060] The input of the filter cascade 224 is electrically coupled to the output of the filter cascade 222. The filter cascade 224 is an LCL filter cascade. Furthermore, the filter cascade 224 may be a fifth-order Butterworth filter. Additionally, the filter cascade 224 may have a cutoff frequency less than the cutoff frequency of the filter cascade 222. For example, the filter cascade 224 may have a cutoff frequency of approximately 7.3 MHz. Alternatively, the filter cascade 224 may have a cutoff frequency less than or greater than approximately 7.3 MHz. The filter cascade 224 includes resistors R8 and R9, inductors L1, L3, and L3, and capacitors C10 and C11. The resistance of the resistor R8 may be approximately 400 kilohms, although other resistance values ​​may be utilized. Furthermore, the inductance of inductor L1 may be approximately 5.4 uH, the inductance of inductor L2 may be approximately 17.5 uH, and the inductance of inductor L3 may be approximately 5.4 uH. However, other inductance values ​​may be used. Furthermore, the inductance of inductor L2 may be greater than the inductances of inductors L1 and L2. Furthermore, the inductance of inductor L1 may be equal to the inductance of inductor L3. The capacitances of capacitors C10 and C11 may be the same. For example, the capacitance of capacitors C10 and C11 may be approximately 88 pF. However, other capacitance values ​​may be used. Furthermore, the resistance of resistors R8 and R9 may be approximately 400 kOhms. However, other resistance values ​​may be used.

[0044]

[0061] In some embodiments, filter cascade 222 and filter cascade 224 each have a frequency response curve that includes a plateau and a cutoff frequency, the plateau being between 1 MHz and about 7 MHz, and the cutoff frequency being in the range of about 5 MHz to about 10 MHz.

[0045]

[0062] 5A, 5B, 5C, and 5D each show an output waveform (i.e., a regulated waveform) 144.1A , 144 1B , 1442, and 1443. The output waveforms shown in FIGS. 5A, 5B, 5C, and 5D have a period "T" on top of the voltage offset. cycle (e.g., 2.5 microseconds). In one plasma processing example, the short pulses have a period of "T cycle " forms only about 10% of the

[0046]

[0063] As briefly described above, as shown in FIG. 5A, the output waveform 144 1A is analyzed by the acquisition channel 1221 to obtain the pulse duration (T cycle ), pulse rise time (T rise ), pulse fall time (T fall ), and a DC voltage offset of the pulse from a reference voltage (e.g., zero volts). In one embodiment, the conditioning circuit 111 of the input channel 1101 coupled to the bias electrode 804 (FIG. 8A) side of the generator coupling assembly 133 is 1A is the output waveform 144 1A , which is used to form the voltage divider 112. In this configuration, the absence of the low pass filter 114 allows accurate determination of pulse timing characteristics (e.g., period, rise time, fall time, etc.) to be achieved. Furthermore, in some embodiments, the high DC voltage power supply V of the bias electrode 804 (FIG. 8A) and the HVM 816 (FIG. 8B) HVM The chucking force applied to the substrate by using the bias electrode 804 (FIG. 8A) can be determined by measuring the difference between the DC voltage on the bias electrode 804 and the DC voltage on the substrate 803.

[0047]

[0064] Furthermore, as shown in FIG. 5B, the output waveform 144 1Bis analyzed by the acquisition channel 1221 to determine waveform characteristics including the pulse amplitude "Ampl", pulse width "W", and DC voltage offset. The determined pulse width "W" may be equivalent to full width at half maximum. In one embodiment, the input channel 1101 conditioning circuit 111 has the input end of the input channel 1101 coupled to the generator side of the generator coupling assembly 133. 1B is the output waveform 144 1B In this configuration, the sheath voltage (V sh ) (FIG. 10B) and ion energy (Ei) determination can be achieved during plasma processing by predetermining a scaling factor (α), where: TIFF2025143284000002.tif7170. Additionally, in some embodiments, the chucking force applied to the substrate can be determined by measuring the difference between the DC voltage on the bias electrode 804 (FIG. 8A) and the DC voltage on the substrate 803. Additionally, the ion current (I ion ) can be characterized, as will be discussed below.

[0048]

[0065] 5C, the output waveform 1442 can be analyzed by the acquisition channel 1222 to determine waveform characteristics including the ion current offset. In one embodiment, the conditioning circuit 1112 of the input channel 1102, whose input is coupled to the current monitor 134 (FIGS. 1B and 9B), includes a voltage divider 112 and a low pass filter 114, which are used to form the output waveform 1442. In this configuration, determining information about the ion current offset is performed using Equation I ion This can be achieved during plasma processing by using the factor "I" = (ion current offset) / factor. ion " is the ion current and "Factor" is the volts per ampere output characteristic of the current monitor 134.

[0049]

[0066] Additionally or alternatively, the output waveform 1443 (FIG. 5D) can be analyzed by the collection channel 1223 to determine waveform characteristics, including the maximum ion current during plasma processing. In one embodiment, the conditioning circuit 1113 of the input channel 1103, whose input is coupled to the current sense resistor 139 in the PVWG 150, includes only a low pass filter 114 that is used to shape the output waveform 1443. In this configuration, the absence of the voltage divider 112 reduces the ion current (I ion An accurate determination of the magnitude of the maximum ion current "Max" can be achieved by using Equation I ion =(MAx) / R sense This can be achieved during plasma processing by using sense " is R sense is the resistance value.

[0050]

[0067] The feedback processor 125 may receive information regarding one or more of the waveform characteristics from the high-speed data acquisition module 120 and generate corresponding control parameters. The feedback processor 125 communicates the control parameters to the PVWG 150, which adjusts the pulsed voltage waveform established on the composite load 130 based on the received control parameters. For example, the PVWG 150 may increase the amplitude and / or width of the pulsed voltage waveform established on the composite load 130 based on the received control parameters. Adjusting the parameters utilized to generate the pulsed voltage waveform can mitigate undesired changes or process variable drift within the processing chamber during substrate processing. For example, adjusting the parameters utilized to generate the pulsed voltage waveform can mitigate changes to the sheath voltage and ion energy distribution function at the substrate during plasma processing, as will be described in more detail below. The sheath voltage (V sh ) and changes to the ion energy distribution function can occur in response to changes in load, drift in plasma density, changes in chamber wall conditions, changes in substrate temperature, and / or changes in the degree and conditions of chemical dissociation.

[0051]

[0068] 1B , the PVWG 150 establishes a pulsed voltage waveform on the composite load 130 via the generator coupling assembly 133. The PVWG 150 can establish the pulsed voltage waveform based on control parameters derived from waveform characteristics (e.g., amplitude, pulse width, DC offset, and ion current) determined by the data acquisition module 120. In the simplest case, the waveform characteristics determined by the data acquisition module 120 can be provided to a user (e.g., displayed on a monitor of the controller 127), who can then adjust the control parameters used by the PVWG 150 to improve the pulsed waveform characteristics of one or more pulsed waveforms generated by the PVWG 150 based on the determined waveform characteristics. The control parameters may alternatively be received from the feedback processor 125, the controller 128, or the process chamber controller 126. The control parameters may include information used by the PVWG 150 to form a subsequently generated regulated pulse voltage waveform, and may include, but are not limited to, one or more of: a determined one or more waveform characteristics of the first regulated voltage waveform reaching their target values ​​or limits; a maximum DC charging voltage limit reaching; a maximum power limit reaching; a maximum time limit for algorithm convergence reaching; a maximum pulse width limit reaching; and a minimum pulse width limit reaching. The control parameters may be communicated to the PVWG 150 at a predetermined rate. The predetermined rate may be approximately 10 transmissions per second. Alternatively, the predetermined rate may be less than or greater than 10 transmissions per second.

[0052]

[0069] Additionally or alternatively, the process chamber controller 126 can receive one or more waveform characteristics from the high-speed data collection module 120 and then generate corresponding control parameters. The process chamber controller 126 can communicate the control parameters to the PVWG 150. Alternatively, the process chamber controller 126 can communicate the control parameters to the feedback processor 125, which communicates the control parameters to the PVWG 150. The PVWG 150 adjusts the input pulsed voltage waveform 140 output by the PVWG 150 based on the determined control parameters. The PVWG 150 can increase the amplitude and / or width of the pulsed voltage waveform output by the PVWG 150. Furthermore, the process chamber controller 126 can be configured to provide target amplitude and pulse width, as well as values ​​for the control parameters, at least once per process recipe. Furthermore, the high-speed data collection module 120 can communicate one or more of the amplitude, pulse width, and DC offset of the output waveform 144 at a transmission rate. For example, the transmission rate may be approximately 10 transmissions per second, however, transmission rates greater than or less than 10 transmissions per second may be utilized.

[0053]

[0070] Additionally or alternatively, the controller 128 can receive one or more of the amplitude, pulse width, DC offset, and ion current from the high-speed data collection module 120 and then generate corresponding control parameters. Alternatively, the high-speed data collection module 120 can communicate the processed waveform to the controller 128, which can determine one or more control parameters from the waveform. The controller 128 communicates the control parameters to the PVWG 150, which adjusts the pulsed voltage waveform output by the PVWG 150 based on the determined control parameters. Alternatively, the controller 128 communicates the control parameters to the feedback processor 125, which sends the control parameters to the PVWG 150, which adjusts the pulsed voltage waveform output by the PVWG 150 based on the determined control parameters.

[0054]

[0071] 6A and 6B include an example of a portion of one waveform cycle of an input and conditioned (e.g., divided and filtered) voltage waveform originating from signal source 1B (the generator end of the generator coupling assembly) measured using an embodiment of a data acquisition system including conditioning circuitry and a high-speed data acquisition module. The digital information contained in the portion of the waveform recorded over this period can be analyzed by data acquisition controller 123 to determine voltage waveform characteristics such as amplitude (Ampl), full width at half maximum (W), and offset. Specifically, FIG. 6A shows an example of an input pulsed voltage waveform 140. 1B and a portion of one waveform cycle of the divided waveform 610. The divided waveform is the input pulsed voltage waveform 140 1B For example, referring to FIG. 1B, the regulation circuit 111 1B The voltage divider of the input pulsed voltage waveform 140 1B FIG. 6B shows an input pulsed voltage waveform 140 1B and output waveform 144 1B A portion of one waveform cycle of the output waveform 144 is shown. 1Bmay be generated by low-pass filtering the divided waveform 610 (FIG. 6A). In various embodiments, the output waveform 144 1B may be analyzed by the data acquisition controller 123 to determine one or more waveform characteristics.

[0055]

[0072] FIG. 7A shows an input pulsed voltage waveform 140 1B 7A shows multiple cycles of the input voltage waveform 140. More specifically, FIG. 7A includes an example of multiple cycles (pulses) of the input voltage waveform originating from signal source 1B (the generator end of the generator coupling assembly) measured using an embodiment of a data acquisition system including a conditioning circuit and a high-speed data acquisition module. As described with respect to FIG. 1B, the input pulsed voltage waveform 140 1B is input channel 110 1B The digital information contained in the waveform recorded over this period can be analyzed by the data acquisition controller 123 to determine amplitude (AmpI), offset (offset), pulse period (T), and other waveform characteristics. P ), (pulse repetition frequency (f P =1 / T P ) and other voltage waveform characteristics can be determined.

[0056]

[0073] FIG. 7B shows an input pulsed voltage waveform 140 1B 7 shows a plurality of bursts 710 of the input pulsed voltage waveform 140. Each burst 710 has a burst duration that includes an on-time 720 and an off-time 732. 1B The frequency of the input pulsed voltage waveform is based on the on-time 720 and the burst period, and the burst duty cycle is based on the on-time 720 and the burst period. More specifically, Figure 7B includes an example of multiple bursts (each containing multiple waveform cycles) of an input pulsed voltage waveform originating from signal source 1B (the generator end of the generator coupling assembly) measured using an embodiment of a data acquisition system including a conditioning circuit and a high-speed data acquisition module. The digital information contained in the waveform recorded over this period is analyzed by the data acquisition controller to determine the offset, the burst period (TB =T on +T off ), burst frequency (f B =1 / T B ), and the burst duty cycle (Duty=T on / T B ) and other voltage waveform characteristics can be determined.

[0057] Plasma Processing Chamber Example

[0074] FIG. 8A is a schematic cross-sectional view of a processing chamber 800 in which a composite load 130 is formed during plasma processing. According to one embodiment, the processing chamber 800 is configured to implement the biasing scheme proposed herein. In one embodiment, the processing chamber is a plasma processing chamber, such as a reactive ion etching (RIE) plasma chamber. In some other embodiments, the processing chamber is a plasma-enhanced deposition chamber (e.g., a plasma-enhanced chemical vapor deposition (PECVD) chamber or a plasma-enhanced atomic layer deposition (PEALD) chamber). In some other embodiments, the processing chamber is a plasma treatment chamber or a plasma-based ion implantation chamber, such as a plasma doping (PLAD) chamber. Here, the processing chamber includes an inductively coupled plasma source (ICP) electrically coupled to a radio frequency (RF) power source. In some embodiments, the plasma source is a capacitively coupled plasma (CCP) source (e.g., a source electrode positioned in the processing space facing the substrate support and electrically coupled to the RF power source).

[0058]

[0075] The processing chamber 800 features a chamber body 813 including a chamber lid 823, one or more sidewalls 822, and a chamber base 824 that defines a processing space 826. A gas inlet 828 disposed through the chamber lid 823 is used to supply one or more processing gases to the processing space 826 from a processing gas source 819 that is in fluid communication with the gas inlet 828. Here, a plasma generator is configured to ignite and sustain a processing plasma 801 from the processing gases and includes one or more inductive coils 817 disposed proximate the chamber lid 823 outside the processing space 826. The one or more inductive coils 817 are electrically coupled to an RF power source 818 via an RF matching network 830. The plasma generator is used to ignite and sustain the processing plasma 801 using the processing gases and an electromagnetic field generated by the inductive coil 817 and the RF power source 818. The processing space 826 is fluidly connected to one or more dedicated vacuum pumps through a vacuum exhaust 820. The vacuum exhaust 820 maintains the processing space 826 at sub-atmospheric conditions and evacuates process and / or other gases therefrom. A substrate support assembly 836 disposed within the processing space 826 is disposed on a support shaft 838 that sealingly extends through the chamber base 824.

[0059]

[0076] Substrate 803 is loaded into and removed from processing space 826 through an opening (not shown) in one or more sidewalls 822. The opening in one or more sidewalls 822 is sealed with a door or valve (not shown) during plasma processing of substrate 803. Here, substrate 803 is transferred to and from the receiving surface of ESC substrate support 805 using a lift pin system (not shown).

[0060]

[0077] The substrate support assembly 836 includes a support base 807 and an ESC substrate support 805 thermally coupled to and disposed on the support base 807. Typically, the support base 807 is used to regulate the temperature of the ESC substrate support 805 and the substrate 803 disposed on the ESC substrate support 805 during substrate processing. In some embodiments, the support base 807 has one or more cooling channels (not shown) disposed therein, which are fluidly coupled to and in fluid communication with a coolant source (not shown) (e.g., a refrigerant source or a water source having a relatively high electrical resistance). In some embodiments, the ESC substrate support 805 includes a heater (not shown), e.g., a resistive heating element embedded in its dielectric material. Here, the support base 807 is formed of a corrosion-resistant, heat-conducting material, such as a corrosion-resistant metal (e.g., aluminum, an aluminum alloy, or stainless steel), and is coupled to the substrate support by adhesive or mechanical means. Typically, the ESC substrate support 805 is formed from a dielectric material (e.g., a bulk-sintered ceramic material such as a corrosion-resistant metal oxide material or a metal nitride material), such as aluminum oxide (AlO), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (YO), a mixture thereof, or a combination thereof. In embodiments herein, the ESC substrate support 805 further includes a bias electrode 804 embedded in the dielectric material. In one configuration, the bias electrode 804 is a chucking pole used to secure (chuck) the substrate 803 to the support surface of the ESC substrate support 805 and bias the substrate 803 relative to the processing plasma 801 using the pulsed voltage bias scheme described herein. Typically, the bias electrode 804 is formed from one or more conductive components (e.g., one or more metal meshes, foils, plates, or a combination thereof). Here, the bias electrode 804 is electrically coupled to the HVM 816. The HVM 816 supplies a chucking voltage (eg, a static DC voltage) between about −5000V and about 5000V to the bias electrode 804 using an electrical conductor such as a coaxial transmission line 806 (eg, a coaxial cable).

[0061]

[0078] The support base 807 is electrically insulated from the chamber base 824 by an insulating plate 811, and a grounded plate 812 is interposed between the insulating plate 811 and the chamber base 824. In some embodiments, the processing chamber 800 further includes a quartz tube 810 or collar. The quartz tube 810 or collar surrounds the substrate support assembly 836 and prevents the ESC substrate support 805 and / or the support base 807 from contacting corrosive process gases or plasmas, cleaning gases or plasmas, or their by-products. Typically, the quartz tube 810, insulating plate 811, and grounded plate are circumscribed by a liner 808. Here, a plasma screen 809, which is substantially coplanar with the substrate receiving surface of the ESC substrate support 805, prevents plasma from forming in the space between the liner 808 and one or more sidewalls 822.

[0062]

[0079] The bias electrode 804 is separated from the substrate receiving surface of the ESC substrate support 805, and thus the substrate 803, by a layer of dielectric material of the ESC substrate support 805. In this configuration, the bias electrode 804 and the layer of dielectric material form a parallel plate-like structure. The dielectric material may have an effective capacitance of between about 5 nF and about 50 nF. Typically, the layer of dielectric material has a thickness of between about 0.1 mm and about 1 mm (e.g., about 0.3 mm), such as between about 0.1 mm and about 0.5 mm. Here, the bias electrode 804 is electrically coupled to the PVWG 150 using an external conductor, such as a transmission line 806 disposed within the transmission line 131. The PVWG 150 and its components are described in detail above in the body of this disclosure. In some embodiments, the thickness of the dielectric material and layer is determined by the capacitance C of the layer of dielectric material. e may be selected to be between about 5 nF and about 50 nF (eg, between about 7 and about 10 nF).

[0063]

[0080] Generally, a low neutral fill pressure in the processing space 826 of the processing chamber 800 results in poor thermal conduction between surfaces disposed therein, for example, between the dielectric material of the ESC substrate support 805 and the substrate 803 disposed on the substrate receiving surface of the ESC substrate support 805, reducing the effectiveness of the ESC substrate support 805 in heating or cooling the substrate 803. Therefore, in some processes, a thermally conductive inert heat transfer gas, typically helium, is introduced into a space (not shown) between the non-device-side surface of the substrate 803 and the substrate receiving surface of the ESC substrate support 805 to improve heat transfer between these surfaces. The heat transfer gas, supplied by a heat transfer gas source (not shown), flows into the backspace through gas communication passages (not shown). The gas communication passages are disposed through the support base 807 and further through the ESC substrate support 805.

[0064]

[0081] The processing chamber 800 further includes a processing chamber controller 126, which includes a central processing unit (CPU) 833, memory 834, and support circuits 835. The processing chamber controller 126 is used to control the process sequence used to process the substrate 803, including the substrate biasing methods described herein. The CPU 833 is a general-purpose computer processor configured for use in an industrial environment to control the processing chamber and associated sub-processors. The memory 834 described herein may include random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of local or remote digital storage. The support circuits 835 are conventionally coupled to the CPU 833 and include cache, clock circuits, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions (programs) and data may be encoded and stored in the memory 834 to instruct the processor in the CPU 833. The software programs (or computer instructions) readable by the CPU 833 in the processing chamber controller 126 determine which tasks are executable by the components in the processing chamber 800. Preferably, a program readable by the CPU 833 in the process chamber controller 126 includes code that, when executed by the processor (CPU 833), performs tasks related to monitoring and implementing the electrode biasing schemes described herein. The program includes instructions that are used to control various hardware and electrical components within the process chamber 800 to perform various process tasks and various process sequences used to implement the electrode biasing schemes described herein.

[0065]

[0082] The PVWG 150 establishes a pulsed voltage waveform on a load (e.g., composite load 130) through the use of a bias electrode 804. The PVWG 150 includes a nanosecond pulse generator 814 and a current return output stage 815, shown schematically in FIGS. 8A and 8B. The nanosecond pulse generator 814 maintains a predetermined, substantially constant positive voltage across its output (i.e., output to ground) for regularly repeating time intervals of predetermined length by repeatedly opening and closing an internal switch at a predetermined rate. FIG. 8A shows a simplified, functionally equivalent schematic diagram of the nanosecond pulse generator 814. In FIG. 8A, the nanosecond pulse generator 814 is reduced to a minimum set of components that are important for understanding its role in establishing the desired pulsed voltage waveform at the bias electrode 804. These components generally include, among others, an internal voltage source, a high repetition rate switch, and a freewheeling diode. It should be understood that an actual nanosecond pulse generator may include any number of internal components and may be based on a more complex electrical circuit than the circuit of FIG. 8A . Instead, the schematic diagram of FIG. 8A provides only a functionally equivalent view of the nanosecond pulse generator 814 and its electrical circuit components, to the extent necessary to explain the basic principles of operation, their interaction with the plasma in the process space, and their role in establishing a pulsed voltage waveform (e.g., input pulsed voltage waveform 140) at the bias electrode 804. As can be seen from the schematic diagram shown in FIG. 8A , when switch S1 moves from an open (off) position to a closed (on) position, the output of the nanosecond pulse generator is connected to its internal voltage source, which generates a substantially constant output voltage. In one or more embodiments, the purpose of the freewheeling diode, which can be replaced by a different snubber circuit, is to suppress or “snub” any voltage spikes that may result from the opening of switch S1, after which the magnetic energy stored in the inductive element is rapidly released. These inductive elements include (A) a combined inductance L transm and (B) an external electrical conductor such as a transmission line 806 having an inductance L internalThe components of the PVWG 150 include internal electrical conductors connecting to the switch. The nanosecond pulse generator 814 may be used primarily as a charge injector (current source) and not as a constant voltage source. Therefore, even when the switch is in the closed (on) position, the output voltage may vary over time, so strict requirements on output voltage stability are not necessary. Furthermore, in some configurations, the nanosecond pulse generator 814 only passes current in one direction (e.g., the output can charge but not discharge a capacitor), so it is essentially a sourcing, but not a sinking, supply. Additionally, when the switch is in the open (off) position, the voltage V0 at the output of the nanosecond pulse generator is not controlled by an internal voltage source but is instead determined by the interaction of its internal components with other circuit elements.

[0066]

[0083] The current return output stage 815 has one end 815B connected to ground and the other end 815A connected via an internal electrical conductor to the positive output of the nanosecond pulse generator, as well as to an external electrical conductor coupled to one side of the generator coupling assembly 133 (FIG. 1B). The current return output stage 815 may consist of a resistor, a resistor and inductor connected in series, a switch, or a more complex combination of electrical elements (including a parallel capacitor) that allow the flow of positive current toward ground.

[0067]

[0084] Transmission line 131 electrically connects the output of PVWG 150 to a chucking pole (e.g., bias electrode 804). The output of PVWG 150 is end 815A, and the output of nanosecond pulse generator 814 is connected to current return output stage 815 via an inner electrical conductor. The electrical conductor of transmission line 131 connected to the bias electrode side of generator coupling assembly 133 and bias electrode 804 has (a) inductance L rigid in series with a rigid coaxial transmission line having an inductance L flexThe coaxial transmission line 806 may include (a) a flexible coaxial cable having (b) an insulated high voltage corona resistant hookup wire, (c) a bare wire, (d) a metal rod, (e) an electrical connector, or any combination of the electrical elements (a)-(e). Note that the inner electrical conductor may include the same basic elements as the outer electrical conductor.

[0068]

[0085] The bias electrode 804 is typically a metal plate embedded in the electrostatic chuck and separated from the plasma by a thin layer of dielectric material. The chucking pole can be a bias electrode 804 embedded within an electrostatic chuck portion (i.e., the ESC substrate support 805). An external conductor, such as a transmission line 806, and the bias electrode 804 have some combined stray capacitance C to ground. s It has.

[0069]

[0086] FIG. 8B shows a functionally equivalent, simplified electrical circuit 840 of the pulsed voltage bias scheme proposed herein, including the plasma in the process space. These circuits are used to model key aspects of the interaction between a pulsed voltage waveform generator (e.g., PVWG 150) and the process chamber 800; explain the basic principles of operation and the role of the pulsed voltage waveform generator in establishing a pulsed voltage waveform at a bias electrode (e.g., bias electrode 804); explain the accompanying physical phenomena that occur during the various phases of the pulsed voltage waveform; and generally describe the basic principles of operation of the pulsed voltage bias scheme. For clarity, the following definitions are used throughout this disclosure: (1) All potentials are referenced to ground unless otherwise specified. (2) The voltage at any physical point (such as the substrate or bias electrode) is similarly defined as the potential of this physical point relative to ground (zero potential point). (3) The cathode sheath is implied to be an electron-repulsive ion acceleration sheath corresponding to a negative substrate potential relative to the plasma. (4) The sheath voltage (also referred to as the "sheath voltage drop") V sh is defined as the absolute value of the potential difference between the plasma and an adjacent surface (e.g., the surface of the substrate or chamber wall). (5) Substrate potential is the potential at the substrate surface facing the plasma.

[0070]

[0087] First, a dielectric layer within the electrostatic chuck and a treated substrate (e.g., a 0.3-0.8 mm thick doped silicon slab with a capacitance >10 nF) placed on top of it separates the chucking pole (e.g., bias electrode 804) from the plasma, which in the circuit of FIG. 8B is represented by a capacitance C e 8. In other words, the substrate (typically made from a thin layer of semiconductor and / or dielectric material) may be considered to be electrically part of the ESC dielectric layer, and has a chuck capacitance C e (i.e., Item 843), C e is the ESC and the substrate (i.e., C w ) and the combined series capacitance (i.e., C ESC (~dielectric layer capacitance) w is typically very large (>10 nF), or the substrate may be conductive (infinite capacitance), so the series capacitance is primarily the actual C ESC is determined by.

[0071]

[0088] Second, the bias electrode 804, the PVWG 150, and the external electrical conductor (e.g., transmission line 131) connecting the bias electrode 804 with the PVWG 150 have (A) a capacitance C s (B) some combined stray capacitance to ground, represented by a single stray capacitor 842 having a capacitance of (e.g., ∼500 pF), and (C) some inductance, such as inductor L internal , and the inductance L for the external electrical conductor such as the transmission line 806 interconnect and L external (i.e., items 845A and 845B). The current return output stage 815 includes resistor R ros(e.g., ~150 ohms) and inductor L ROS which may optionally also include switch S2.

[0072]

[0089] As shown in FIG. 8B, the PVWG 150 includes a bypass resistor R bypass , and a current sense circuit 821 connected in parallel with the current return output stage 815. The current sense circuit 821 includes a current sense resistor R sense (i.e., item 139), and a switch S3 that can be used to sense the current through the current return output stage 815 during one or more phases of the pulse.

[0073]

[0090] Third, a standard electrical plasma model can be utilized that represents the overall plasma in the process space as three series elements, such as the electron-repellent cathode sheath 844 (sometimes referred to as the "plasma sheath" or simply "sheath") adjacent the substrate. The cathode sheath is represented in FIG. 8B by a conventional three-part circuit element: (a) diode D, which, when open, represents the collapse of the sheath; SH , (b) Current source I representing the ion current flowing through the substrate in the presence of a sheath i (e.g., ∼0.5 to 5 A), (c) a capacitor C representing the sheath for the main period (∼90%) of the bias cycle during which ion acceleration and etching occur, i.e., the ion current phase (e.g., the phase after the short pulse is delivered). SH (e.g., ~100 to 300 pF for high aspect ratio applications).

[0074]

[0091] The bulk plasma 846 is represented in Figure 8B by a single resistor of ∼5 to 10 ohms. The electron-repellent wall sheath formed by the chamber walls is represented in Figure 8B by a three-part circuit element: (a) diode D W , (b) Current source I representing the ion current to the wall iw (e.g., ∼5 to 10 A), and (c) capacitor C W(e.g., ∼5 to 10 nF) and represents the wall sheath primarily during the ESC recharge phase, when there is no electron-repellent cathode sheath and the wall sheath capacitor is being charged by the large current pushed through the ESC by the nanosecond pulse generator. W Since the cathode sheath is much thicker than the wall sheath (due to the high voltage) and the total area of ​​the wall is much larger than the area of ​​the substrate, C W ≫C SH The inner surface of the grounded metal wall is assumed to be coated with a thin layer of dielectric material, which in Figure 8B is represented by a large capacitor C coat (e.g., ~300 to 1000 nF).

[0075]

[0092] In some embodiments, as shown in Figures 8A and 8B, the system includes a high-voltage module (HVM) 816. The HVM 816 is used for chucking, as shown in Figure 8A, to "electrically clamp" the substrate to the substrate receiving surface of the ESC substrate support. Chucking the substrate allows the gap between the substrate receiving surface and the non-device side of the substrate to be filled with helium gas (He), which provides good thermal contact between the two and allows substrate temperature control by regulating the temperature of the ESC substrate support. The combination of the DC chucking voltage generated by the HVM and the pulsed voltage generated by the PVWG 150 at the bias electrode 804 results in an additional voltage offset of the pulsed voltage waveform equal to the DC chucking voltage. A suitably large blocking capacitor C hvm and R hvm2 By selecting resistor R, the HVM816 can have a negligible effect on the operation of the PVWG150. hvm2 shows a resistor placed in a component connecting the HVM 816 to a point in the transmission line 131. hvm The main function of the PVWG150 is to convert the DC power supply hvmThe purpose of this is to protect the HVM from DC voltages generated by the hvm The C is designed to block only the HVM DC voltage but not to load the high frequency output voltage of the pulsed bias generator. hvm A sufficiently large value of C is chosen. hvm (e.g., 40 to 80 nF) to reduce C hvm is, for example, much larger than any other relevant capacitance in the system, so that the voltage drop across this element is larger than the other relevant capacitors (e.g., chuck capacitance C e and sheath capacitance C SH ) is nearly transparent to 400 kHz signals in that the voltage drop across the hvm2 The purpose of this resistor R is to block the high frequency pulsed bias generator voltage and minimize the current it induces in the HVM DC voltage supply. hvm2 must be large enough to effectively minimize the current flowing through it. For example, to make the 400 kHz current from the pulsed bias generator into the HVM negligible, R hvm2 >1 megaohm is typically sufficient. The resulting average induced current of approximately 0.5 to 1 mA is much less than the typical limit of HVM power supplies (approximately 5 mA DC current). C hvm1 and R hvm1 , and R hvm2 together form a current suppression / filtering circuit for the pulsed voltage so that the pulsed voltage does not induce a current through the HVM816.

[0076]

[0093] In some embodiments, the feedback loop 100 is coupled to one or more points within the PVWG 150 or to the PVWG 150 and a blocking capacitor C located within the generator coupling assembly 133. hvmFor example, one or more input channels 110 of the feedback loop 100 may be coupled along an electrical conductor disposed between the PVWG 150 and a blocking capacitor C hvm Furthermore, in some embodiments, one or more of the input channels 110 may be coupled via a connection to one or more points along an electrical conductor disposed between the input channels 110 and the blocking capacitor C hvm and a bias electrode 804 within the processing chamber 800. For example, one or more input channels 110 may be electrically coupled via a connection to one or more points along an electrical conductor disposed between the input channel 110 and a bias electrode 804 within the processing chamber 800. hvm and the bias electrode 804 in the processing chamber 800. Alternatively, in other embodiments, one or more of the input channels 110 may be electrically coupled to one or more points along an electrical conductor disposed between the bias electrode 804 and the blocking capacitor C hvm For example, the first one or more input channels 110 may be coupled to one or more points along the electrical conductors located on either side of the PVWG 150 and the blocking capacitor C hvm and the second one or input channel 110 is electrically coupled to a point along the electrical conductor disposed between hvm and a point along the electrical conductor disposed between the bias electrode 804 within the processing chamber 800.

[0077] Pulse waveform example

[0094] FIG. 9A shows an example of a pulsed voltage waveform 950 established at the bias electrode 804. The pulsed voltage waveform 950 shown in FIG. 9A results in the substrate voltage waveform 951 shown in FIG. 9B, which may enable the sheath voltage to be maintained substantially constant for approximately 90% of the substrate processing time during plasma processing. The pulsed voltage waveforms 950 and 951 shown in FIGS. 9A and 9B are generally based on waveforms that may be generated from the simplified electrical circuit 840 shown in FIG. 8B. The waveforms shown in FIGS. 9A and 9B are intended only to illustrate simplified schematic diagrams of pulsed voltage waveforms that may be used in one of the methods described herein during plasma processing of a substrate. The actual waveforms generated by the PVWG 150 are significantly more complex and may include numerous microscale features (e.g., high-frequency oscillations caused by the presence of inductive elements) that are not shown in FIGS. 9A and 9B. However, examples of some types of microscale features can be seen in FIGS. 6A and 6B and 7A and 7B. However, these small-scale features are not necessary to understand the underlying physical phenomena that determine the general shape of the actual pulsed voltage waveform generated by the pulsed voltage biasing schemes and control methods proposed herein.

[0078]

[0095] 9A, the pulsed voltage waveform 950 includes a series of short positive cycles that repeat with a period T (e.g., 2.5 microseconds) on top of a voltage offset. The waveform within each cycle (repeating period) includes:

[0079]

[0096] (1) A positive voltage jump (i.e., sheath collapse phase 961) to charge the floating capacitor of the system and collapse the cathode sheath. During the sheath collapse phase 961, the sheath capacitor C SH is discharged and the substrate potential is brought to the level of the local plasma potential (as shown in FIG. 9B). The sheath collapse phase 961 begins with the chuck capacitor C being charged by electrons supplied from the plasma during the ESC recharge phase 962. eion current phase 961. Switch S1 (see FIG. 8B) closes and remains in the closed (on) position during phase 961, allowing a nanosecond pulse generator such as PVWG 150 to maintain a substantially constant positive voltage across its output and supply current to the system. The period T1 of phase 961 is much shorter than the period T4 (discussed below) or the overall period T of ion current phase 964, typically on the order of tens of nanoseconds (e.g., 20 to 50 nanoseconds). This is because the plasma current during phase 961 is carried by electrons. That is, the electron cloud moves toward the substrate, gradually sweeping away the ion space charge, eliminating the sheath voltage drop. Due to the very large mass ratio between the two species, the electron velocity is much greater than the ion velocity.

[0080]

[0097] (2) During the ESC recharge phase 962, the chuck capacitor C is charged by rapidly injecting a charge equal to and opposite in polarity to the total charge accumulated on the substrate surface during the ion current phase 964. e (discussed below). As during phase 961, the PVWG 150 maintains a substantially constant positive voltage across its output (switch S1 remains in the "on" position). As with phase 961, the period T2 of phase 962 is much shorter than the period T4 (discussed below) or overall period T of ion current phase 964, typically on the order of tens of nanoseconds (e.g., 30 to 80 nanoseconds). This is because the plasma current during phase 962 is also carried by electrons. That is, in the absence of a cathode sheath, electrons would reach the substrate and build up a surface charge, which would then charge capacitor C. e Charge the battery.

[0081]

[0098] (3) Discharge the floating capacitor of the processing chamber to reform the sheath and reduce the sheath voltage (V SH ) value to set the negative voltage jump (V OUT 8B, switch S1 is opened at the beginning of the sheath formation phase 963, and the inductive element transfers its stored magnetic energy to the chuck capacitor C e and floating capacitor C sThe inductive element discharges rapidly (e.g., within about 10 nanoseconds) to internal The internal components (e.g., inner conductors) of the PVWG 150, as well as the inductance L interconnect and L external , which may include an outer conductor (e.g., transmission line 806) represented by . During the release of the magnetic energy, the corresponding current flows through a flyback diode or a different snubber circuit with a similar function to suppress (or "snubbing") possible voltage spikes. Note that without a flyback diode (or a different component with a similar function to "snubbing" possible voltage spikes), the magnetic energy would have to be released through a resistive current-return output stage, which would result in an unrealistically large negative voltage (e.g., -20 kV, which could damage internal components of the pulsed bias generator 240) across R1 for a few nanoseconds instead of converging to a near-zero value. As the magnetic energy is released, the inductance L interconnect and L external (and L internal ) drops to zero, it reverses direction and flows from the plasma and the floating capacitor through the current-return output stage to ground (the freewheeling diode is reverse biased and blocks current flow through itself), thus causing the floating capacitor C s is discharged, and the sheath capacitor C sh (i.e., re-forming the sheath). The start of sheath formation (C shion current phase 963 (charge of ion current V) can be clearly identified in FIG. 9B as the point at which the substrate potential begins to drop below the local plasma potential. As with phase 961, the duration T3 of phase 963 is much shorter than the duration T4 of ion current phase 964 (discussed below) or the entire period T, typically on the order of 100 to 300 nanoseconds. This is because the plasma current during phase 963 is similarly electron-carried. That is, the electron cloud moves away from the substrate, gradually exposing the ionic space charge, thus forming a sheath and causing a sheath voltage drop. (1) T3 is determined primarily by the stray capacitance and values ​​of the elements (e.g., resistors) comprising the current-return output stage, and (2) the negative voltage jump V OUT and the established sheath voltage V SH is V m (the magnitude of the nanosecond pulse generator output voltage between phases 961 and 962), and the total pulse width, T tot =T rise Note that Tp is determined by T1+T2.

[0082]

[0099] (4) A long ion current phase 964 (approximately 85-90% of cycle period T) with a period T4 during which the PVWG 150 similarly does not maintain a positive voltage across its output (switch S1 remains in the off position) and ion current flows from the plasma to ground through the current-return output stage. The ion current causes a buildup of positive charge on the substrate surface, gradually discharging the sheath and chuck capacitors, slowly reducing the sheath voltage drop and causing the substrate potential to approach zero. This results in a voltage droop ΔV in the substrate voltage waveform 951 shown in FIG. 9B. SH Due to the sheath voltage droop that occurs, the pulsed voltage waveform 950 must transition to the next cycle described above in (1)-(3), during which the PVWG 150 removes the charge accumulated during the ion current phase (or restores the initial ESC charge) and restores the desired sheath voltage V SHre-establishes. Note that surface charge and sheath voltage droop accumulate whenever there is an unbalanced net current (equal to the ion current) from the electron-repulsive cathode sheath and bulk plasma. This is because the ion current from the bulk plasma is not balanced by the electron current from the bulk plasma due to the sheath field, which repels electrons away from the substrate. Thus, surface charge accumulation and voltage droop generation occur even during the sheath formation phase 963, when a non-zero sheath voltage droop is present from the start.

[0083]

[0100] As can be seen from (1) through (4) above, the combined duration of the "electron current" phases 961-963 that make up a single voltage pulse of a pulsed voltage waveform (e.g., pulsed voltage waveform 950) is approximately 200 to 400 nanoseconds, which corresponds to a relatively short duty cycle of approximately 10 to 15%. This short duty cycle characteristic of pulsed voltage waveform 950 is a result of the large ion-to-electron mass ratio that is typical in all plasmas. Therefore, in the pulsed voltage bias scheme described herein, the PVWG 150 actively interacts with the plasma only for a short period of each cycle, thereby allowing the cathode sheath to naturally develop for the remainder of the time. By effectively utilizing fundamental plasma properties, this bias scheme allows for a nearly constant sheath voltage to be maintained for up to 90% of the processing time, resulting in a single-peak IEDF (e.g., IEDF 970 in Figure 9C). Conversely, in conventional biasing schemes, the applied RF voltage modulates the cathode sheath throughout the RF period, thus causing excessive sheath voltage droop throughout the period, resulting in a dual-peak IEDF.

[0084]

[0101] The pulsed voltage bias scheme described herein allows for the maintenance of a particular substrate voltage waveform, such as the substrate voltage waveform 951 shown in FIG. 9B, which can be described as a series of periods of short positive pulses 971 on top of a negative voltage offset 972. During each pulse (with a total period of T5 = T1 + T2 + T3), the substrate potential reaches the local plasma potential and the sheath collapses for a short period. However, for approximately 90% of each cycle (with a cycle period T), the sheath voltage droop remains approximately constant, with the most negative substrate potential V SH (FIG. 9B), and thus determines the average ion energy at the substrate surface. During the sheath collapse phase 961 of the bias cycle, the current from the nanosecond pulse generator (e.g., 814) is proportional to the ratio C SH / C s The parallel-connected processing plasma and floating capacitor C s For the reasons mentioned above, and also C w Since , is generally very large, the voltage droop that builds up across the wall sheath during phase 961 is relatively small. As a result, the plasma potential V near the wall, which is equal to the wall sheath voltage droop plus the small voltage droop expected across the wall dielectric coating, w remains close to zero. Therefore, the local (near the substrate) plasma potential V, which is equal to the plasma potential near the wall plus the voltage droop across the bulk plasma, pl is determined primarily by the latter and increases to a value slightly above zero. Instead, during the ESC recharge phase 962, there is no electron-repellent cathode sheath, and the wall sheath capacitors are charged to substantial voltages (e.g., hundreds of volts) by the large currents pushed through the ESCs by the PVWG 150. Due to the increase in plasma potential near the wall and the presence of an equally large voltage droop across the bulk plasma (caused by the same large currents), the local (near the substrate) plasma potential V pl , and the substrate potential V sub is the established sheath voltage V SHFinally, during sheath formation phase 963, the current through the processing plasma again increases (as in phase 961) to approximately one-third of C SH / C s The voltage drop across the bulk plasma is determined by the ratio of the plasma potential V to the substrate, and is relatively small (and decays quickly), as is the resulting voltage drop across the bulk plasma. Thus, the local plasma potential (near the substrate) remains approximately equal to the plasma potential near the wall, and both relax to values ​​near zero as the end of phase 963 approaches, as the wall sheath is discharged to the chamber wall primarily by ion current. As a result of the disturbance in the local plasma potential during phases 961-963, the established sheath voltage V SH constitutes only ∼75% of the overall negative jump in the substrate voltage waveform 951 at the end of phase 963. SH (almost infinite C w and nearly zero R pl given V (achievable only in m and T tot Define the maximum sheath voltage for the pulsed voltage waveform 950, or V' SH ~V OUT The reason for the latter is that during phase 963, the chuck capacitor loses a small fraction of its initial charge (∝C SH / C e <<1>> is transmitted to the sheath, and thus a nearly constant potential difference is maintained between the electrode and the substrate. SH / V OUT ~0.75~0.8 was actually used, and the measured V OUT From V SH can be estimated.

[0085]

[0102] As described further herein and below, in one or more of the embodiments of the disclosure provided herein, a feedback loop 100 and methods of using the same are provided to detect and adjust the output of the PVWG 150 to achieve a pulsed voltage waveform (e.g., pulsed voltage waveform 950 and / or substrate voltage waveform 951) having desired waveform characteristics. In addition to the pulse waveform characteristics that may be detected and adjusted described above, further pulse waveform characteristics may be detected and adjusted, which may include, for example, the shape or slope of the pulse waveform during one or more of the pulse phases, the period of one or more of the phases (e.g., T1, T2, T3, T4, and T5), and other features of the pulse waveform.

[0086] Example of the method

[0103] 10 is a flow diagram of a method 1000 for processing a pulsed voltage waveform, according to one or more embodiments. In operation 1010, an input pulsed voltage waveform 140 is processed by components found in input channel 110 to form an output waveform 144. In one configuration of input channel 110, the input pulsed voltage waveform is divided using a first voltage division ratio to generate a first divided voltage waveform. For example, if input channel 1101 receives input pulsed voltage waveform 140, 1B and adjusts the input channel 1101. 1B The voltage divider 112 receives the input pulsed voltage waveform and generates a first divided voltage waveform.

[0087]

[0104] In operation 1020, the divided voltage waveform coming from voltage divider 112 is low pass filtered to generate a filtered voltage waveform. In one embodiment, low pass filter 114 of input channel 1101 receives the first divided voltage waveform from voltage divider 112 and generates a filtered voltage waveform, which is then filtered to generate output waveform 144. 1B Operation 1020 may be optional and may be omitted from method 1000. Furthermore, in some embodiments of method 1000, operation 1020 may be performed while operation 1010 is omitted.

[0088]

[0105] After operations 1010 and / or 1020 are performed, and the output waveform 144 1B is generated by each input channel 1101, operation 1030 is performed. In operation 1030, one or more waveform characteristics received from each input channel, such as input channel 1101, and processed by its respective acquisition channel 122 are determined by an algorithm running in data acquisition controller 123. For example, acquisition channel 1221 receives the output waveform from input channel 1101, and the algorithm determines output waveform 144 1B determining one or more waveform characteristics from the

[0089]

[0106] In some embodiments, during operation 1030, the output waveform 144 from each input channel 110 is received by a driver (not shown) each coupled to a corresponding acquisition channel 122. In one example, the output waveform 144 from input channel 1101 is 1B The output waveform 144 received from the input channel 110 is received by a driver of the acquisition channel 1221. The driver is used to convert the output waveform received from the input channel 110 into a differential signal. In this configuration, the differential signal is then received by an ADC (not shown) coupled to or within the acquisition channel 122. The ADC converts the differential signal from the analog domain to the digital domain, and the output digital signal of the ADC is provided to a processor 121 coupled to the acquisition channel 122. The processor of the data collection controller 123 determines one or more waveform characteristics of the output waveform by analyzing the output digital signal provided by the ADC. For example, the processor 121 analyzes the output digital signal to determine one or more of the amplitude, pulse width, and DC offset of pulses in the output waveform 144 received from the input channel 110.

[0090]

[0107] Operation 1030 may further include combining measurements received from corresponding input channels over a period of time. For example, the data acquisition controller 123 may receive "Z" digitized waveforms from the acquisition channel 1221 over a first period of time, where Z is an integer equal to 2 or greater. The first period of time may correspond to "M" cycles of the input pulsed voltage waveform, where M is an integer equal to 1 or greater. The acquisition channel 1221 may combine the Z output waveforms. For example, the acquisition channel 1221 may average data corresponding to the Z output waveforms.

[0091]

[0108] Operation 1030 may further include the data collection controller 123 performing at least one of: 1) sending information regarding the determined one or more waveform characteristics of the adjusted voltage waveform to a controller (e.g., a controller of the feedback processor 125); and 2) sending information regarding the second digitized voltage waveform generated by the collection channel to a second controller (e.g., controller 126, 127, 128, or 191).

[0092]

[0109] In operation 1040, one or more control parameters are generated from one or more waveform characteristics received from one or more input channels 110. For example, data acquisition controller 123 sends information corresponding to the one or more waveform characteristics to feedback processor 125, which generates one or more control parameters from the one or more waveform characteristics. Still referring to the previous example of input channel configuration, in one implementation of operation 1040, after the desired operations 1010 through 1030 have been performed, the processor receives output waveforms from input channels 1101, 1102, and 1103 and sends information corresponding to one or more waveform characteristics derived from the waveforms received and processed by acquisition channels 1221, 1222, and 1223, respectively, to feedback processor 125. Feedback processor 125 may then generate one or more control parameters from the one or more received waveform characteristics. In one embodiment, the one or more control parameters may include instructions to adjust the DC charging voltage, adjust the pulse width, and adjust the amplitude of the pulsed voltage waveform based on a comparison between the received waveform characteristics and target waveform characteristics stored in a memory of feedback processor 125 or a memory coupled to feedback processor 125. The stored target waveform characteristics may be waveform characteristics generated by feedback loop 100 at a prior moment, an average of a series of waveform characteristics generated by feedback loop 100 over a period of time, idealized waveform characteristics (e.g., model-based waveform characteristics) generated by a user and entered into memory, or waveform characteristics generated by other desired means.

[0093]

[0110] Alternatively or additionally, data acquisition controller 123 can communicate information corresponding to one or more waveform characteristics to a separate controller (e.g., controller 127, controller 128, controller 191, and / or process chamber controller 126), which generates one or more control parameters from the one or more waveform characteristics. Similarly, in one embodiment, the one or more control parameters generated by the controller may include instructions to adjust, for example, the pulse width and amplitude of the pulsed voltage waveform based on a comparison of the received waveform characteristics with target waveform characteristics stored in the controller's memory. The stored target waveform characteristics may be waveform characteristics generated by feedback loop 100 at a prior instant in time, an average of a series of waveform characteristics generated by feedback loop 100 over a period of time, idealized waveform characteristics (e.g., model-based waveform characteristics) generated by a user and entered into memory, or waveform characteristics generated by any other desired means.

[0094]

[0111] In operation 1050, feedback processor 125 or a separate controller transmits information corresponding to one or more control parameters to PVWG 150. Additionally, in some embodiments, data acquisition controller 123 can communicate information corresponding to one or more waveform characteristics to controller 128, which generates one or more control parameters based on a comparison of the determined waveform characteristics with information corresponding to one or more target waveform characteristics. Thus, in one embodiment, in operation 1050, controller 128 transmits information corresponding to one or more control parameters to PVWG 150 and / or another controller.

[0095]

[0112] During operation 1060, an adjusted pulsed voltage waveform is provided from PVWG 150 based on the received one or more control parameters. For example, PVWG 150 generates an adjusted pulsed voltage waveform that is provided to bias electrode 804.

[0096]

[0113] In operation 1070, optionally, plasma processing chamber process variables are adjusted, individually or additionally. The plasma processing chamber process variables may include a set point for a chucking power supply. For example, adjusting the set point for a chucking power supply (e.g., HVM816) may include increasing or decreasing the chucking voltage output by the chucking power supply. Adjusting the set point for the chucking power supply will adjust the DC offset of the subsequent pulsed voltage waveform generated by the PVWG 150. The set point for the chucking power supply may be adjusted to be a DC voltage between approximately −5000 V and approximately 5000 V. In some embodiments, method 1000 may omit operation 1060.

[0097]

[0114] In some embodiments of method 1000, the adjusted pulsed voltage waveform is continuously executed until a pulsed voltage waveform having desired pulse waveform characteristics (e.g., target waveform characteristics) is achieved. In some embodiments, operations 1010 through 1050 or operations 1010 through 1060 are executed multiple times until one or more target waveform characteristics of the pulsed voltage waveform within one waveform cycle are reached. For example, controller 128 and / or feedback processor 125 can modify one or more control parameters based on updated waveform characteristics determined by data acquisition controller 123. The updated waveform characteristics are collected by continuously processing the input pulsed voltage waveform collected by one or more of input channels 110. In one example, the pulse width and / or amplitude may be increased until the pulse width and / or amplitude reach corresponding target values ​​stored in a memory of a feedback processor coupled to data acquisition controller 123 or a memory. Furthermore, the adjusted pulsed voltage waveform can be continuously adjusted by modifying one or more control parameters until a maximum limit of the DC offset voltage is reached. For example, one or more control parameters may be varied continuously until a maximum DC offset voltage is reached.

[0098]

[0115] In some embodiments, establishing the adjusted pulsed voltage waveform includes modifying one or more of the control parameters until a maximum time limit for algorithm convergence is reached. For example, feedback processor 125 monitors how long it takes PVWG 150 to generate an adjusted pulsed voltage waveform having one or more target waveform characteristics. If PVWG 150 fails to generate an adjusted pulsed voltage waveform that can achieve the target pulsed voltage waveform characteristics within a certain time limit, feedback processor 125 may instruct PVWG 150 to modify another waveform characteristic. Additionally or alternatively, establishing the adjusted pulsed voltage waveform includes modifying one or more of the control parameters until a predetermined maximum limit for the pulse width of the pulsed voltage waveform is reached. Furthermore, establishing the adjusted pulsed voltage waveform includes modifying one or more of the control parameters until a minimum limit for the pulse width of the pulsed voltage waveform is reached. The pulse width time limits and maximum limits generally comprise predetermined values ​​stored in a memory (e.g., memory 124 or 126A) and derived by a processor (e.g., feedback processor 125 or controller 128) for comparison with one or more pulsed voltage waveforms received by one or more input channels 110.

[0099]

[0116] 11 is a flow diagram illustrating a method 1100 for controlling a pulsed voltage waveform, according to one or more embodiments. In operation 1110, an output waveform 144 is generated by a first input channel 110. For example, input channel 1101 receives an input pulsed voltage waveform 140. 1B and obtain the input pulse voltage waveform 140 1B Output waveform 144 1BInput channel 1101 may include voltage divider 112 and low-pass filter 114, and generating the first output waveform includes generating a divided voltage waveform from the input pulsed voltage waveform with voltage divider 112 and low-pass filtering the divided voltage waveform with low-pass filter 114 to generate a filtered voltage waveform. In another embodiment, input channel 1101 omits low-pass filter 114, and generating the output waveform includes generating a divided voltage waveform from the input pulsed voltage waveform with voltage divider 112.

[0100]

[0117] In operation 1120, a second output waveform is generated by the second input channel 110. For example, the input channel 1102 receives an input pulsed voltage waveform 1402 and generates an output waveform 1442 from the input pulsed voltage waveform 1402. The input channel 1102 may include a voltage divider 112 and a low-pass filter 114, and generating the output waveform 1442 includes generating a divided voltage waveform from the input pulsed voltage waveform with the voltage divider 112 and low-pass filtering the divided voltage waveform with the low-pass filter 114 to generate a filtered voltage waveform.

[0101]

[0118] In operation 1130, a third output waveform is generated by the third input channel 110. For example, in one embodiment, the input channel 1103 receives the input pulsed voltage waveform 1403 and generates the output waveform 1443 from the input pulsed voltage waveform 1403. The input channel 1103 may include a low-pass filter 114, and generating the output waveform 1443 includes generating a filtered voltage waveform formed by low-pass filtering the input pulsed voltage waveform 1403 through the use of the low-pass filter 114.

[0102]

[0119] In operation 1140, one or more waveform characteristics are determined. For example, acquisition channels 1221, 1222, and 1223 receive output waveforms 1441, 1442, and 1443 from input channels 110, 1102, and 1103, respectively, and provide the output waveforms to data acquisition controller 123 to determine one or more waveform characteristics based on various types of voltage waveform information received from output waveforms 1441, 1442, and 1443. In some embodiments, the one or more waveform characteristics determined by acquisition channel 1221 are different from the one or more waveform characteristics determined by acquisition channel 1222, and the one or more waveform characteristics determined by acquisition channel 1223 are different from the one or more waveform characteristics determined by acquisition channel 1221 and acquisition channel 1222. Furthermore, in one embodiment, the data acquisition controller 123 associated with the collection channel 1221 determines the amplitude (Ampl) and pulse width W from the corresponding measured waveform, the data acquisition controller 123 associated with the collection channel 1222 determines the ion current offset from the corresponding measured waveform, and the data acquisition controller 123 associated with the collection channel 1223 determines the maximum ion current from the corresponding received output waveform.

[0103]

[0120] In operation 1150, one or more control parameters are generated from waveform characteristics determined by data acquisition controller 123 based on information received in output waveforms 1441, 1442, and 1443. For example, data acquisition controller 123 sends information corresponding to the one or more waveform characteristics to feedback processor 125 (or a separate controller), which generates one or more control parameters from the one or more determined waveform characteristics. During operation 1150, feedback processor 125 receives the determined one or more waveform characteristics and then generates one or more control parameters based on the one or more received waveform characteristics by using one or more algorithms. In one embodiment, the one or more control parameters may include instructions for adjusting the DC charging voltage, adjusting the pulse width, and adjusting the amplitude of the pulsed voltage waveform based on a comparison of waveform characteristics received from two or more different input channels to target waveform characteristics stored in a memory of feedback processor 125 or a memory coupled to feedback processor 125.

[0104]

[0121] Similar to what was described above for operation 1050 , in operation 1160 , feedback processor 125 sends information corresponding to the generated control parameters to PVWG 150 .

[0105]

[0122] Further, operation 1170 is generally similar to operation 1060, whereby an adjusted pulsed voltage waveform is provided from PVWG 150 based on the received one or more control parameters. For example, PVWG 150 generates an adjusted pulsed voltage waveform that is provided to bias electrode 804. Additionally, in operation 1170, a set point for a chucking power supply is also optionally adjusted.

[0106]

[0123] In some embodiments of method 1100, operations 1110-1170 are performed multiple times until an adjusted pulsed voltage waveform having desired pulse waveform characteristics (e.g., target waveform characteristics) is achieved. In some embodiments, operations 1110-1170 are performed multiple times until one or more target waveform characteristics of the pulsed voltage waveform within one waveform cycle are reached.

[0107]

[0124] While the foregoing is directed to embodiments of the present disclosure, other and additional embodiments of the present disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the claims that follow.

Claims

1. 1. A feedback loop for controlling a pulsed voltage waveform, comprising: a data acquisition system; a first input channel including a first conditioning circuit configured to generate a first regulated voltage waveform from a first input voltage waveform; 1. A high speed data acquisition module, comprising: a first acquisition channel electrically coupled to the first conditioning circuit of the first input channel and configured to generate a first digitized voltage waveform from the first conditioned voltage waveform; a data acquisition controller configured to determine one or more waveform characteristics of the first regulated voltage waveform by analyzing the first digitized voltage waveform; High-speed data acquisition module including It has a feedback loop.

2. The feedback loop of claim 1 , further comprising a feedback processor configured to process information about the first regulated voltage waveform processed by the high-speed data acquisition module.

3. 3. The feedback loop of claim 2, wherein the feedback processor is one of an external processor connected to the high-speed data collection module via a data communication interface, an internal processor integrated within the high-speed data collection module, or a controller for a substrate processing chamber connected to the high-speed data collection module via the data communication interface.

4. 10. The feedback loop of claim 1, wherein the pulsed voltage waveform is established by a pulsed voltage waveform generator electrically coupled to a bias electrode disposed in a substrate support assembly disposed in a plasma processing chamber.

5. 5. The feedback loop of claim 4, wherein the pulsed voltage waveform generator is electrically coupled to the bias electrode via an electrical conductor using a generator coupling assembly, and an input end of the first input channel is electrically coupled to an end of the generator coupling assembly.

6. 10. The feedback loop of claim 1, further comprising: a memory containing instructions that, when executed by the high-speed data collection module, cause the high-speed data collection module to process the first regulated voltage waveform and determine one or more waveform characteristics of the first regulated voltage waveform.

7. 7. The feedback loop of claim 6, further comprising a feedback processor having a memory containing instructions that, when executed by the feedback processor, cause the feedback processor to generate one or more control parameters using the determined one or more waveform characteristics of the first regulated voltage waveform.

8. 8. The feedback loop of claim 7, wherein the instructions executed by the feedback processor are further configured to cause the feedback processor to send information regarding the generated one or more control parameters to a pulsed voltage waveform generator.

9. 9. The feedback loop of claim 8, wherein the pulsed voltage waveform generator further comprises a memory containing instructions that, when executed by the pulsed voltage waveform generator, cause the pulsed voltage waveform generator to establish an adjusted pulsed voltage waveform based on the generated one or more control parameters.

10. the first input voltage waveform is a regulated first input voltage waveform, and the instructions executed by the feedback processor include causing the feedback processor to: the determined one or more waveform characteristics of the first regulated voltage waveform reach their target values ​​or limits; The maximum DC charging voltage limit is reached. Maximum power limit reached, Reaching the maximum time limit for algorithm convergence, The maximum pulse width limit is reached, and Reaching the minimum pulse width limit 10. The feedback loop of claim 9, further configured to generate the one or more control parameters to at least one of:

11. The instructions executed by the high speed data collection module include instructions for the high speed data collection module to: transmitting information regarding the determined one or more waveform characteristics of the first regulated voltage waveform to a first controller; and transmitting information about the first digitized voltage waveform to a second controller; The feedback loop of claim 6 , further configured to cause at least one of:

12. 12. The feedback loop of claim 11, wherein the first controller is a controller for a substrate processing chamber, and the first controller is further configured to adjust a set point for a chucking power supply for the substrate processing chamber based on information regarding the determined one or more waveform characteristics of the first regulated voltage waveform.

13. 2. The feedback loop of claim 1, wherein the first regulation circuit of the first input channel comprises a first voltage divider.

14. 14. The feedback loop of claim 13, wherein the first voltage divider comprises a first voltage divider cascade and a second voltage divider cascade.

15. 15. The feedback loop of claim 14, wherein the first voltage divider cascade has a voltage division ratio in a range from about 1:10 to about 1:100, and the second voltage divider cascade has a voltage division ratio in a range from about 1:20 to about 1:

120.

16. 2. The feedback loop of claim 1, wherein the first conditioning circuit of the first input channel comprises a first low pass filter.

17. 17. The feedback loop of claim 16, wherein the first low pass filter comprises a first filter cascade and a second filter cascade, the first low pass filter having a frequency response curve including a plateau and a cutoff frequency.

18. 18. The feedback loop of claim 17, wherein the plateau is between 1 MHz and about 7 MHz and the cutoff frequency is within a range of about 5 MHz to about 10 MHz.

19. 1. A feedback loop for controlling a pulsed voltage waveform, comprising: a data acquisition system; a first input channel including a first conditioning circuit configured to generate a first regulated voltage waveform from a first input voltage waveform; a second input channel including a second conditioning circuit configured to generate a second regulated voltage waveform from the second input voltage waveform; and 1. A high speed data acquisition module, comprising: a first acquisition channel electrically coupled to the first conditioning circuit of the first input channel and configured to generate a first digitized voltage waveform from the first conditioned voltage waveform; a second acquisition channel electrically coupled to the second conditioning circuit of the second input channel and configured to generate a second digitized voltage waveform from the second conditioned voltage waveform; a data acquisition controller configured to determine one or more waveform characteristics of at least one of the first regulated voltage waveform and the second regulated voltage waveform by analyzing at least one of the first digitized voltage waveform and the second digitized voltage waveform; High-speed data acquisition module with It has a feedback loop.

20. 20. The feedback loop of claim 19, wherein the pulsed voltage waveform is established by a pulsed voltage waveform generator electrically coupled to a bias electrode disposed in a substrate support assembly disposed in a plasma processing chamber.

21. 21. The feedback loop of claim 20, wherein the pulsed voltage waveform generator is electrically coupled to the bias electrode via an electrical conductor using a generator coupling assembly, and an input end of the first input channel is electrically coupled to an end of the generator coupling assembly.

22. 21. The feedback loop of claim 20, wherein the pulsed voltage waveform generator is electrically coupled to the bias electrode via an electrical conductor using a generator coupling assembly, and wherein an input end of the second input channel is electrically coupled to one of an output of a current monitor and an ungrounded end of a current sensing resistor, the current monitor configured to sense current flowing in the electrical conductor, and the current sensing resistor is disposed within the pulsed voltage waveform generator.

23. 20. The feedback loop of claim 19, further comprising a memory containing instructions that, when executed by the high-speed data collection module, cause the high-speed data collection module to process at least one of the first regulated voltage waveform and the second regulated voltage waveform and determine the one or more waveform characteristics of at least one of the first regulated voltage waveform and the second regulated voltage waveform.

24. 24. The feedback loop of claim 23, further comprising a feedback processor comprising a memory containing instructions that, when executed by the feedback processor, cause the feedback processor to generate one or more control parameters using the determined one or more waveform characteristics of at least one of the first regulated voltage waveform and the second regulated voltage waveform.

25. 25. The feedback loop of claim 24, wherein the instructions executed by the feedback processor are further configured to cause the feedback processor to send information regarding the generated one or more control parameters to a pulsed voltage waveform generator.

26. 26. The feedback loop of claim 25, wherein the pulsed voltage waveform generator further comprises a memory containing the instructions that, when executed by the pulsed voltage waveform generator, cause the pulsed voltage waveform generator to establish an adjusted pulsed voltage waveform based on the generated one or more control parameters.

27. the first input voltage waveform and the second input voltage waveform are regulated input voltage waveforms, and the instructions executed by the feedback processor include causing the feedback processor to: the determined one or more waveform characteristics of at least one of the first regulated voltage waveform and the second regulated voltage waveform reach their target values ​​or limits; The maximum DC charging voltage limit is reached. Maximum power limit reached, Reaching the maximum time limit for algorithm convergence, The maximum pulse width limit is reached, and Reaching the minimum pulse width limit 27. The feedback loop of claim 26, further configured to generate the one or more control parameters to at least one of:

28. The instructions executed by the high speed data collection module include instructions for the high speed data collection module to: transmitting information regarding the determined one or more waveform characteristics of at least one of the first regulated voltage waveform and the second regulated voltage waveform to a first controller; and transmitting information regarding at least one of the first digitized voltage waveform and the second digitized voltage waveform to a second controller; 28. The feedback loop of claim 27, further configured to cause at least one of:

29. 30. The feedback loop of claim 28, wherein the first controller is a controller for a substrate processing chamber, and the first controller is further configured to adjust a set point for a chucking power supply for the substrate processing chamber based on the information related to the determined one or more waveform characteristics of at least one of the first regulated voltage waveform and the second regulated voltage waveform.

30. 20. The feedback loop of claim 19, wherein at least one of the following is satisfied: (i) the first adjustment circuit of the first input channel includes at least one of a first voltage divider and a first low-pass filter; (ii) the second conditioning circuit of the second input channel includes at least one of a second voltage divider and a second low-pass filter;

31. the first adjustment circuit of the first input channel comprises a first voltage divider; the second adjustment circuit of the second input channel comprises a second voltage divider; 20. The feedback loop of claim 19, wherein a voltage divider ratio of the first voltage divider is different from a voltage divider ratio of the second voltage divider.

Images