Nitride semiconductor device

Abstract

To provide a nitride semiconductor device capable of reducing fluctuations in a threshold voltage.SOLUTION: A nitride semiconductor device 10 includes: an electron transit layer; an electron supply layer 42 located on the electron transit layer and having a band gap larger than that of the electron transit layer; a source electrode 28 and a drain electrode 30 in contact with an electron supply layer 42, a gate layer 46 including a bottom surface in contact with the electron supply layer 42 and located between a source electrode 28 and the drain electrode 30 and containing an acceptor impurity; and a gate electrode 26 located on the gate layer 46. The gate layer 46 includes a first contact surface 46A1 and a second contact surface 46A2 in contact with the gate electrode 26. The gate layer 46 is configured such that a gate current per unit area flowing through a second contact surface 46A2 is larger than a gate current per unit area flowing through the first contact surface 46A1 when a gate voltage is applied to the gate electrode 26.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Currently, commercialization of high electron mobility transistors (HEMTs) using nitride semiconductors such as gallium nitride (GaN) and aluminum gallium nitride (AlGaN) is progressing. In HEMTs, a two-dimensional electron gas (2DEG) is formed at the heterojunction interface between the electron transport layer (e.g., GaN layer) and the electron supply layer (e.g., AlGaN layer). This 2DEG is used as carriers that travel in the current path (channel). Power transistors using HEMTs are recognized as transistors that have lower on-resistance and are capable of high-speed, high-frequency operation compared to typical silicon (Si) power transistors.

[0003] From a fail-safe perspective, it is desirable for power transistors such as HEMTs to operate normally-off, in which the channel between the drain and source is blocked when no gate voltage is applied. Patent Document 1 discloses an example of a normally-off HEMT that uses a nitride semiconductor. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2020 / 158394

[0005] [overview] In a HEMT using a gate electrode that forms a Schottky junction with a p-type gate layer, the threshold voltage may fluctuate when a voltage is applied to the gate electrode.

[0006] A nitride semiconductor device according to one embodiment of the present disclosure includes an electron transit layer, an electron supply layer located on the electron transit layer and having a bandgap larger than that of the electron transit layer, a source electrode and a drain electrode in contact with the electron supply layer, a gate layer including a bottom surface in contact with the electron supply layer and located between the source electrode and the drain electrode, the gate layer including an acceptor-type impurity, and a gate electrode located on the gate layer. The gate layer includes a first contact surface and a second contact surface in contact with the gate electrode. The gate layer is configured such that, when a gate voltage is applied to the gate electrode, a gate current per unit area flowing through the second contact surface is larger than a gate current per unit area flowing through the first contact surface.

[0007] Other features and aspects will become apparent from the following detailed description, drawings, and claims. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing components of the nitride semiconductor device located below the insulating layer shown in FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view of the nitride semiconductor device taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the nitride semiconductor device taken along line F4-F4 in FIG. [Figure 5] FIG. 5 is a graph schematically showing the impurity concentration profile in the gate layer along the thickness direction. [Figure 6] FIG. 6 is a graph schematically showing the impurity concentration profile in the gate layer along the thickness direction. [Figure 7] FIG. 7 is a graph schematically showing the impurity concentration profile in the gate layer along the thickness direction. [Figure 8]FIG. 8 is a graph schematically showing the impurity concentration profile in the gate layer along the thickness direction. [Figure 9] FIG. 9 is a graph schematically showing the impurity concentration profile in the gate layer along the thickness direction. [Figure 10] FIG. 10 is a graph schematically showing the impurity concentration profile in the gate layer along the thickness direction. [Figure 11] FIG. 11 is a schematic plan view showing a main path region of the drain-source current in the nitride semiconductor device shown in FIG. [Figure 12] FIG. 12 is a schematic plan view of an exemplary nitride semiconductor device according to the second embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view of the nitride semiconductor device taken along line F13-F13 in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view of the nitride semiconductor device taken along line F14-F14 in FIG. [Figure 15] FIG. 15 is a schematic plan view of an exemplary nitride semiconductor device according to the third embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view of the nitride semiconductor device taken along line F16-F16 in FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view of the nitride semiconductor device taken along line F17-F17 in FIG.

[0009] [Detailed explanation] Hereinafter, several embodiments of nitride semiconductor devices of the present disclosure will be described with reference to the accompanying drawings. The same reference numerals refer to the same elements throughout the drawings and detailed description. The drawings may not be to scale, and the relative size, proportions, and depictions of elements in the drawings may be exaggerated for clarity, explanation, and convenience.

[0010] The following detailed description provides a comprehensive understanding of the described methods, devices, and / or systems. Modifications and equivalents of the described methods, devices, and / or systems will be apparent to those skilled in the art. Except for operations that necessarily occur in a particular order, the order of operations is illustrative and may be changed as would be apparent to one skilled in the art. Descriptions of functions and structures well known to those skilled in the art may be omitted. Example embodiments may have different forms and are not limited to the described examples.

[0011] First Embodiment An exemplary nitride semiconductor device 10 according to the first embodiment will be described with reference to Figures 1 to 11. The nitride semiconductor device 10 may be configured as a HEMT using a nitride semiconductor.

[0012] (Schematic structure of nitride semiconductor device) Fig. 1 is a schematic plan view of a nitride semiconductor device 10. As shown in Fig. 1, the nitride semiconductor device 10 may include a gate wiring 12, a source wiring 14, and a drain wiring 16. In the illustrated example, the gate wiring 12, the source wiring 14, and the drain wiring 16 extend in the Y-axis direction and are spaced apart from one another in the X-axis direction.

[0013] 1 and other drawings, the Z-axis direction of the mutually orthogonal X, Y, and Z axes is a direction that intersects (e.g., is perpendicular to) the surface of the semiconductor substrate 36 (see FIG. 3, etc.) As used herein, the term "plan view" refers to a view drawn from a perspective looking down on an object from above along the Z-axis direction, unless explicitly stated otherwise.

[0014] The gate wiring 12, the source wiring 14, and the drain wiring 16 may be made of any metal material, for example, the gate wiring 12, the source wiring 14, and the drain wiring 16 may include at least one of aluminum (Al), copper (Cu), and AlCu.

[0015] The nitride semiconductor device 10 may include an insulating layer 18 located below the gate wiring 12, the source wiring 14, and the drain wiring 16. For example, the insulating layer 18 may include at least one of silicon nitride (SiN), silicon dioxide (SiO), silicon oxynitride (SiON), aluminum oxide (AlO), aluminum nitride (AlN), and aluminum oxynitride (AlON).

[0016] The nitride semiconductor device 10 may include one or more gate vias 20, one or more source vias 22, and one or more drain vias 24 that pass through the insulating layer 18. The one or more gate vias 20 are located below the gate wiring 12 and connected to the gate wiring 12. The one or more source vias 22 are located below the source wiring 14 and connected to the source wiring 14. The one or more drain vias 24 are located below the drain wiring 16 and connected to the drain wiring 16. Each of the vias 20, 22, and 24 may be filled with any metal material. For example, each of the vias 20, 22, and 24 is filled with at least one of tungsten (W), Al, Cu, and AlCu.

[0017] The nitride semiconductor device 10 includes a gate electrode 26, a source electrode 28, and a drain electrode 30. An insulating layer 18 may be located on the gate electrode 26, the source electrode 28, and the drain electrode 30. The gate electrode 26 is connected to a gate wiring 12 located on the insulating layer 18 through one or more gate vias 20 passing through the insulating layer 18. The source electrode 28 is connected to a source wiring 14 located on the insulating layer 18 through one or more source vias 22 passing through the insulating layer 18. The drain electrode 30 is connected to a drain wiring 16 located on the insulating layer 18 through one or more drain vias 24 passing through the insulating layer 18.

[0018] In the illustrated example, the source electrode 28 and the drain electrode 30 extend in the X-axis direction in a plan view. The gate electrode 26 surrounds the source electrode 28 in a plan view. The gate electrode 26 includes two main electrode portions 26A1 and 26A2 extending in the X-axis direction between the source electrode 28 and the drain electrode 30, and a first connection portion 26B1 and a second connection portion 26B2 connecting the two main electrode portions 26A1 and 26A2. The first connection portion 26B1 overlaps the gate wiring 12 in a plan view. The gate wiring 12 is connected to the first connection portion 26B1 of the gate electrode 26 via one or more gate vias 20. The second connection portion 26B2 does not overlap the gate wiring 12 in a plan view and is not directly connected to the gate wiring 12.

[0019] The nitride semiconductor device 10 may include an active region 32 and a non-active region 34 that surrounds the active region 32 in a plan view. The gate electrode 26, the source electrode 28, and the drain electrode 30 are disposed in the active region 32. Details of the active region 32 and the non-active region 34 will be described later.

[0020] 1 is an example, and it should be understood that different layouts may be adopted depending on the desired design of the nitride semiconductor device 10. For example, in the example shown, two drain electrodes 30, a gate electrode 26 disposed between the two drain electrodes 30 in a plan view, and a source electrode 28 surrounded by the gate electrode 26 in a plan view are disposed in the active region 32. However, additional gate electrodes 26, source electrodes 28, and drain electrodes 30 repeatedly arranged in the Y-axis direction may also be disposed in the active region 32.

[0021] Fig. 2 is a schematic plan view showing components of the nitride semiconductor device 10 located below the insulating layer 18 shown in Fig. 1. Fig. 3 is a schematic cross-sectional view of the nitride semiconductor device 10 taken along line F3-F3 in Fig. 2. Fig. 4 is a schematic cross-sectional view of the nitride semiconductor device 10 taken along line F4-F4 in Fig. 2.

[0022] As shown in FIGS. 3 and 4, the nitride semiconductor device 10 may include a semiconductor substrate 36 and a buffer layer 38 located on the semiconductor substrate 36. The semiconductor substrate 36 may be made of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials, and may have a thickness of, for example, 100 μm to 1500 μm.

[0023] The buffer layer 38 may include one or more nitride semiconductor layers. The buffer layer 38 may be made of any material that can reduce warping or cracking of the nitride semiconductor device 10 due to the difference in thermal expansion coefficient between the semiconductor substrate 36 and a layer (e.g., the electron transit layer 40) formed on the buffer layer 38. For example, the buffer layer 38 may include at least one of an AlN layer, an AlGaN layer, and a graded AlGaN layer having a different Al composition. For example, the buffer layer 38 may be made of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0024] In one example, the buffer layer 38 may include a first buffer layer that is an AlN layer formed on the semiconductor substrate 36, and a second buffer layer that is an AlGaN layer formed on the AlN layer. The first buffer layer may be, for example, an AlN layer having a thickness of 100 nm to 300 nm, while the second buffer layer may include multiple AlGaN layers with different compositions, each having a thickness of 100 nm to 300 nm. Note that, in order to reduce leakage current in the buffer layer 38, impurities may be introduced into a portion of the buffer layer 38 to make the buffer layer 38 semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the impurity concentration may be, for example, 4×10 16 cm -3 It can be more than that.

[0025] The nitride semiconductor device 10 includes an electron transit layer 40 and an electron supply layer 42 located on the electron transit layer 40 . The electron transit layer 40 may be located on the buffer layer 38. In this embodiment, the electron transit layer 40 may be a GaN layer. The thickness of the electron transit layer 40 may be, for example, 0.5 μm or more and 2 μm or less. In order to reduce leakage current in the electron transit layer 40, impurities may be introduced into a portion of the electron transit layer 40, thereby making the electron transit layer 40 semi-insulating except for the surface region. In this case, the impurity may be, for example, C. The impurity concentration in the electron transit layer 40 may be, for example, 4×10 16 cm -3 It can be more than that.

[0026] That is, the electron transit layer 40 may include multiple GaN layers with different impurity concentrations, for example, a C-doped GaN layer and a non-doped GaN layer. In this case, the C-doped GaN layer may be in contact with the buffer layer 38. The C-doped GaN layer may have a thickness of 0.3 μm or more and 2 μm or less. The C concentration in the C-doped GaN layer may be 5×10 17 cm -3 Over 9x10 19 cm -3 The non-doped GaN layer may be formed on the C-doped GaN layer and have a thickness of 0.05 μm or more and 0.4 μm or less. The non-doped GaN layer may be in contact with the electron supply layer 42. In one example, the electron transit layer 40 may include a C-doped GaN layer having a thickness of 0.4 μm and a non-doped GaN layer having a thickness of 0.4 μm. The C concentration in the C-doped GaN layer may be approximately 2×10 19 cm -3 It may be.

[0027] The electron supply layer 42 has a larger band gap than the electron transit layer 40. In this embodiment, the electron supply layer 42 may be an AlGaN layer. z Ga 1-zIt is composed of N, where 0.1 < z < 0.4, and more preferably, 0.1 < z < 0.3. The electron supply layer 42 may have a thickness of 5 nm or more and 20 nm or less. In one example, the electron supply layer 42 may have a thickness of 8 nm or more.

[0028] The electron transport layer 40 (for example, a GaN layer) and the electron supply layer 42 (for example, an AlGaN layer) have different lattice constants from each other. Therefore, the electron transport layer 40 and the electron supply layer 42 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 40 and the electron supply layer 42 and the piezo-polarization caused by the crystal strain near the hetero-junction interface, the energy level of the conduction band of the electron transport layer 40 near the hetero-junction interface becomes lower than the Fermi level. As a result, a 2DEG can be generated in the electron transport layer 40 at a position close to the hetero-junction interface between the electron transport layer 40 and the electron supply layer 42 (for example, within a range of about several nm from the interface).

[0029] The above-described non-active region 34 includes an impurity-introduced region 44 into which impurities that reduce or inhibit the generation of 2DEG are introduced. The impurity-introduced region 44 may include at least the electron supply layer 42 and the electron transport layer 40 within the non-active region 34. In the illustrated example, the impurity-introduced region 44 includes the electron supply layer 42 within the non-active region 34, the electron transport layer 40, and a part of the buffer layer 38. The impurities included in the impurity-introduced region 44 include, for example, He, B, N, O, F, and / or Ar. The non-active region 34 may have a higher resistance value than the active region 32.

[0030] As a result, in the active region 32, a 2DEG is generated in the electron transport layer 40, but in the non-active region 34, the generation of 2DEG in the electron transport layer 40 is reduced or inhibited. At least a part of the 2DEG in the electron transport layer 40 within the active region 32 can function as a channel of the nitride semiconductor device 10.

[0031] (Gate layer) The nitride semiconductor device 10 includes a gate layer 46 containing acceptor-type impurities. The gate layer 46 (main electrode portions 26A1, 26A2) is located between the source electrode 28 and the drain electrode 30. The gate layer 46 includes a first contact surface 46A1 and a second contact surface 46A2 in contact with the gate electrode 26. The gate layer 46 also includes a bottom surface 46B in contact with the electron supply layer 42.

[0032] As shown in FIG. 4 , in this embodiment, the gate layer 46 includes a recess 48. The recess 48 is recessed in the Z-axis direction from the first contact surface 46A1. The recess 48 also includes a second contact surface 46A2. Therefore, the thickness T2 of the gate layer 46 between the bottom surface 46B and the second contact surface 46A2 is smaller than the thickness T1 of the gate layer 46 between the bottom surface 46B and the first contact surface 46A1. The gate layer 46 may have a thickness of 50 nm or more and 150 nm or less. In one example, the thickness T1 may be approximately 100 nm, and the thickness T2 may be approximately 80 nm.

[0033] The gate layer 46 may be a GaN layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may include at least one of magnesium (Mg), zinc (Zn), and carbon (C). In one example, the acceptor-type impurities may be Mg. The maximum concentration of the acceptor-type impurities in the gate layer 46 is 7×10 18 cm -3 More than 1×10 20 cm -3 As will be described later, in this embodiment, the impurity concentration in the gate layer 46 may vary in a thickness direction intersecting (e.g., perpendicular to) the bottom surface 46B of the gate layer 46. In the illustrated example, the thickness direction corresponds to the Z-axis direction.

[0034] 2, the gate layer 46 may surround either the source electrode 28 or the drain electrode 30 in a plan view. In the example shown, the gate layer 46 surrounds the source electrode 28 in a plan view. In another example in which the gate layer 46 surrounds the drain electrode 30 in a plan view, the gate electrode 26 located on the gate layer 46 may also surround the drain electrode 30 in a plan view.

[0035] (gate electrode) The gate electrode 26 may be composed of one or more metal layers. For example, the gate electrode 26 may include TiN, TaN, WN, TiSiN, TaSiN, WSi, and / or WSiN. In one example, the gate electrode 26 may be composed of TiN. In another example, the gate electrode 26 may include a Ti layer and a TiN layer disposed on the Ti layer. The gate electrode 26 may form a Schottky junction with the gate layer 46. More specifically, the gate electrode 26 may form a Schottky junction with the first contact surface 46A1 and the second contact surface 46A2. The thickness of the gate electrode 26 may be, for example, 50 nm to 200 nm.

[0036] 3 , the source electrode 28 is in contact with the electron supply layer 42. The source electrode 28 can make ohmic contact with the 2DEG immediately below the electron supply layer 42 in contact with the source electrode 28. The drain electrode 30 is in contact with the electron supply layer 42. The drain electrode 30 can make ohmic contact with the 2DEG immediately below the electron supply layer 42 in contact with the drain electrode 30. The distance between the drain electrode 30 and the gate layer 46 in the Y-axis direction may be greater than the distance between the source electrode 28 and the gate layer 46 in the Y-axis direction.

[0037] The source electrode 28 and the drain electrode 30 may be composed of one or more metal layers (eg, any combination of Ti, TiN, Al, AlSiCu, and / or AlCu layers, etc.).

[0038] When a voltage exceeding the gate threshold voltage is applied to the gate electrode 26, a channel due to the 2DEG is formed in the electron transit layer 40. As a result, a current can flow between the source electrode 28 and the drain electrode 30. On the other hand, when a voltage below the gate threshold voltage is applied to the gate electrode 26 (including when no voltage is applied to the gate electrode 26), the 2DEG is not formed in at least a part of the region of the electron transit layer 40 located below the gate layer 46. This is because the gate layer 46 contains acceptor-type impurities, which raises the energy levels of the electron transit layer 40 and the electron supply layer 42, resulting in depletion of the 2DEG. This allows the nitride semiconductor device 10 to operate normally off.

[0039] (Acceptor-type impurity concentration profile in the gate layer) As described above, the concentration of acceptor-type impurities in the gate layer 46 varies in the thickness direction. FIGS. 5 to 10 are graphs that schematically illustrate the impurity concentration profile in the gate layer 46 along the thickness direction. The vertical axis of each graph represents the concentration of acceptor-type impurities in the gate layer 46. The horizontal axis of each graph represents the position in the thickness direction in the gate layer 46, expressed as the distance from the bottom surface 46B. For example, the impurity concentration when the distance from the bottom surface 46B of the gate layer 46 is equal to 0 corresponds to the impurity concentration in the gate layer 46 at the same position in the thickness direction as the bottom surface 46B. The impurity concentration when the distance from the bottom surface 46B of the gate layer 46 is equal to the thickness T2 of the gate layer 46 between the bottom surface 46B and the second contact surface 46A2 corresponds to the impurity concentration in the gate layer 46 at the same position in the thickness direction as the second contact surface 46A2. When the distance from the bottom surface 46B of the gate layer 46 is equal to the thickness T1 of the gate layer 46 between the bottom surface 46B and the first contact surface 46A1, the impurity concentration corresponds to the impurity concentration in the gate layer 46 at the same position in the thickness direction as the first contact surface 46A1.

[0040] 5, the impurity concentration is approximately constant from the position of distance 0 to the position between distances T2 and T1, and then drops at the position between distances T2 and T1. In this example, the gate layer 46 may include a layer containing acceptor-type impurities and a layer not containing acceptor-type impurities.

[0041] In the example of Fig. 6, the impurity concentration is approximately constant from the position at distance 0 to the position between distances T2 and T1, and then drops at the position between distances T2 and T1. However, the impurity concentration after the drop is higher than in the example of Fig. 5. In this example, the gate layer 46 may include a layer containing acceptor-type impurities at a relatively high concentration and a layer containing acceptor-type impurities at a relatively low concentration.

[0042] In the example of FIG. 7, the impurity concentration is approximately constant from the position at distance 0 to the position between distances T2 and T1, and gradually decreases from the position between distances T2 and T1 toward the position at distance T1.

[0043] In the example of FIG. 8, the impurity concentration gradually increases from a position slightly beyond the distance 0 toward the position of the distance T2, and gradually decreases from the position of the distance T2 toward the position of the distance T1. In the example of FIG. 9, the impurity concentration increases stepwise from a position slightly beyond distance 0 toward a position at distance T2, and then drops at a position between distance T2 and distance T1.

[0044] In the example of Figure 10, the impurity concentration is approximately constant from the position at distance 0 to the position between distance 0 and distance T2, increases at the position between distance 0 and distance T2, and decreases at the position between distance T2 and distance T1.

[0045] In each of the examples shown in FIGS. 5 to 10, the impurity concentration at the distance T2 is higher than the impurity concentration at the distance T1. Therefore, the acceptor-type impurity concentration at the second contact surface 46A2 is higher than the acceptor-type impurity concentration at the first contact surface 46A1. This is because, in each example, the acceptor-type impurity concentration that varies in the thickness direction includes a gradient that decreases toward the first contact surface 46A1. By providing a recess 48 in the gate layer 46 with such a concentration profile, the first contact surface 46A1 and the second contact surface 46A2 can be obtained with different acceptor-type impurity concentrations. The recess 48 can penetrate a portion of the gate layer 46 that contains a relatively low concentration of acceptor-type impurities and expose a portion of the gate layer 46 that contains a relatively high concentration of acceptor-type impurities. In one example, the acceptor-type impurity concentration in the gate layer 46 near the first contact surface 46A1 (e.g., within about 10 nm from the first contact surface 46A1) is about 1×10 19 cm -3 The acceptor-type impurity concentration in the gate layer 46 in the vicinity of the second contact surface 46A2 (for example, within a range of about 10 nm from the second contact surface 46A2) may be about 3×10 19 cm -3 The fact that the concentration of acceptor-type impurities at the second contact surface 46A2 is higher than the concentration of acceptor-type impurities at the first contact surface 46A1 may correspond to the fact that the concentration of acceptor-type impurities in the gate layer 46 near the second contact surface 46A2 is higher than the concentration of acceptor-type impurities in the gate layer 46 near the first contact surface 46A1.

[0046] 8 to 10, the concentration of acceptor-type impurities that changes in the thickness direction may include a first gradient that increases toward the first contact surface 46A1 and a second gradient that decreases toward the first contact surface 46A1. The first gradient that increases toward the first contact surface 46A1 is between the position of distance 0 and the position of distance T2. The second gradient that decreases toward the first contact surface 46A1 is between the position of distance T2 and the position of distance T1. This makes it possible to reduce the amount of impurities contained in the entire gate layer 46 while making the concentration of acceptor-type impurities at the second contact surface 46A2 higher than the concentration of acceptor-type impurities at the first contact surface 46A1.

[0047] The concentration of acceptor-type impurities at the second contact surface 46A2 is higher than the concentration of acceptor-type impurities at the first contact surface 46A1. As the concentration of acceptor-type impurities in the gate layer 46 increases, the width of the depletion layer formed between the gate layer 46 and the gate electrode 26 decreases. Therefore, at the second contact surface 46A2, which has a relatively high concentration of acceptor-type impurities, the Schottky barrier decreases and tunneling current is more likely to occur. Thus, the gate layer 46 is configured such that, when a gate voltage is applied to the gate electrode 26, the gate current per unit area flowing at the second contact surface 46A2 is greater than the gate current per unit area flowing at the first contact surface 46A1.

[0048] (Arrangement of second contact surface) FIG. 11 is a schematic plan view showing a main path region 50 of the drain-source current of the nitride semiconductor device 10 shown in FIG. 2. The main path region 50 of the drain-source current is defined between the source electrode 28 and the drain electrode 30 in a plan view. The second contact surface 46A2 may be located outside the main path region 50 in a plan view. In the illustrated example, the second contact surface 46A2 is arranged to overlap the first connection portion 26B1 of the gate electrode 26 in a plan view. To prevent the gate via 20 from being positioned on a step in the gate electrode 26 caused by the recess 48 in the gate layer 46, the second contact surface 46A2 may be arranged not to overlap the gate via 20 in a plan view.

[0049] The second contact surface 46A2 is surrounded by the first contact surface 46A1 in a plan view. The area of ​​the second contact surface 46A2 may be smaller than the area of ​​the first contact surface 46A1. For example, the area of ​​the first contact surface 46A1 may be 100 times or more the area of ​​the second contact surface 46A2.

[0050] (Functions of nitride semiconductor devices) The following describes the operation of the nitride semiconductor device 10. The nitride semiconductor device 10 includes a gate layer 46 containing acceptor-type impurities and a gate electrode 26 located on the gate layer 46.

[0051] The gate electrode 26 forms a Schottky junction with the gate layer 46. The gate layer 46 is located between the Schottky diode formed by the gate electrode 26 and the gate layer 46 and the pin diode formed by the 2DEG of the gate layer 46, electron supply layer 42, and electron transit layer 40. The barriers of the two diodes allow the potential of the gate layer 46 to float. Therefore, when a voltage is applied between the gate and source or between the gate and drain, the potential of the gate layer 46 can become unstable due to the release or accumulation of holes, resulting in a shift in the threshold voltage. This shift can recover to its original value after a few seconds to a few hours. However, if the threshold voltage shifts negatively during operation, even if the gate is actually in an off state, a small noise signal may erroneously turn the gate on. Furthermore, if the threshold voltage shifts positively, the gate becomes difficult to turn on even when an on voltage is applied to it, resulting in an increased on-resistance and consequently increased power loss.

[0052] In this regard, in the nitride semiconductor device 10 of this embodiment, the gate layer 46 is configured so that the gate current per unit area flowing through the second contact surface 46A2 is larger than the gate current per unit area flowing through the first contact surface 46A1 when a gate voltage is applied to the gate electrode 26. Since the gate current flows more easily through the second contact surface 46A2, the gate layer 46 is less likely to enter a floating state, and even if it does enter a floating state, it quickly becomes the same potential as the gate electrode 26, thereby reducing fluctuations in the threshold voltage.

[0053] The nitride semiconductor device 10 according to this embodiment has the following advantages. (1-1) The gate layer 46 includes a first contact surface 46A1 and a second contact surface 46A2 in contact with the gate electrode 26. The gate layer 46 is configured so that when a gate voltage is applied to the gate electrode 26, the gate current per unit area flowing through the second contact surface 46A2 is larger than the gate current per unit area flowing through the first contact surface 46A1.

[0054] With this configuration, the gate current flows more easily through the second contact surface 46A2, making the gate layer 46 less likely to enter a floating state, and even if it does enter a floating state, it quickly becomes the same potential as the gate electrode 26, thereby reducing fluctuations in the threshold voltage.

[0055] (1-2) The concentration of acceptor-type impurities at the second contact surface 46A2 may be higher than the concentration of acceptor-type impurities at the first contact surface 46A1. This allows the width of the depletion layer formed between the gate layer 46 and the gate electrode 26 to be smaller at the second contact surface 46A2. As a result, it becomes easier to generate a tunnel current at the second contact surface 46A2.

[0056] (1-3) The concentration of the acceptor-type impurities in the gate layer 46 varies in a thickness direction intersecting with the bottom surface 46B of the gate layer 46, and the thickness T2 of the gate layer 46 between the bottom surface 46B and the second contact surface 46A2 may be smaller than the thickness T1 of the gate layer 46 between the bottom surface 46B and the first contact surface 46A1. In the gate layer 46 containing the acceptor-type impurities at a concentration that varies in the thickness direction, by making the thickness T2 smaller than the thickness T1, the concentration of the acceptor-type impurities can be made different between the first contact surface 46A1 and the second contact surface 46A2.

[0057] (1-4) The concentration of the acceptor-type impurities that changes in the thickness direction includes a gradient that decreases toward the first contact surface 46A1. This allows the concentration of the acceptor-type impurities on the second contact surface 46A2 to be higher than the concentration of the acceptor-type impurities on the first contact surface 46A1.

[0058] (1-5) The concentration of the acceptor-type impurities that changes in the thickness direction may include a first gradient that increases toward the first contact surface 46A1 and a second gradient that decreases toward the first contact surface 46A1. This makes it possible to reduce the amount of impurities contained in the entire gate layer 46 while making the concentration of the acceptor-type impurities at the second contact surface 46A2 higher than the concentration of the acceptor-type impurities at the first contact surface 46A1. As a result, it is possible to reduce the on-resistance of the nitride semiconductor device 10 while making it easier for the gate current to flow through the second contact surface 46A2.

[0059] (1-6) The area of ​​the second contact surface 46A2 may be smaller than the area of ​​the first contact surface 46A1, thereby preventing an excessive increase in gate current. (1-7) The area of ​​the first contact surface 46A1 may be 100 times or more the area of ​​the second contact surface 46A2. Since the area of ​​the second contact surface 46A2 can be made sufficiently smaller than the area of ​​the first contact surface 46A1, an excessive increase in gate current can be effectively prevented.

[0060] (1-8) The second contact surface 46A2 may be surrounded by the first contact surface 46A1 in plan view. This allows the depletion layer to expand from the vicinity of the first contact surface 46A1 toward the second contact surface 46A2, thereby preventing an excessive increase in gate leakage current at the second contact surface 46A2.

[0061] (1-9) In a plan view, the second contact surface 46A2 may be located outside the main path region 50 of the drain-source current defined between the source electrode 28 and the drain electrode 30. This allows the second contact surface 46A2 to be separated from the source electrode 28 and the drain electrode 30, thereby preventing an excessive increase in gate leakage current at the second contact surface 46A2.

[0062] (1-10) The gate layer 46 may surround either the source electrode 28 or the drain electrode 30 in plan view. This ensures that the gate layer 46 is present in the current path between the drain and source, thereby reducing the leakage current that flows between the drain and source.

[0063] (1-11) The gate electrode 26 may form a Schottky junction with the first contact surface 46A1 and the second contact surface 46A2. By forming a Schottky junction between the gate layer 46 and the gate electrode 26, it is possible to reduce gate leakage current compared to when an ohmic junction is formed.

[0064] (1-12) The gate electrode 26 may include TiN, TaN, WN, TiSiN, TaSiN, WSi, and / or WSiN. TiN, TaN, WN, TiSiN, TaSiN, WSi, and WSiN are easy to form a Schottky junction with the gate layer 46 (e.g., GaN) and can be processed by dry etching.

[0065] Second Embodiment Next, an exemplary nitride semiconductor device 100 according to a second embodiment will be described with reference to FIGS. 12 to 14. The nitride semiconductor device 100 may be configured as a HEMT using a nitride semiconductor. FIG. 12 is a schematic plan view of the nitride semiconductor device 100. FIG. 13 is a schematic cross-sectional view of the nitride semiconductor device 100 taken along line F13-F13 in FIG. 12. FIG. 14 is a schematic cross-sectional view of the nitride semiconductor device 100 taken along line F14-F14 in FIG. 12. In FIGS. 12 to 14, components similar to those in the first embodiment are denoted by the same reference numerals. Detailed description of components similar to those in the first embodiment will be omitted. The gate wiring 12, source wiring 14, and drain wiring 16 on the insulating layer 18 shown in FIG. 1 can also be applied to the nitride semiconductor device 100. As in FIG. 2, FIG. 12 shows components of the nitride semiconductor device 100 located below the insulating layer 18.

[0066] 12 to 14, the nitride semiconductor device 100 includes a gate layer 102 containing acceptor-type impurities. As shown in FIGS. 12 and 13, the gate layer 102 is located between the source electrode 28 and the drain electrode 30. As shown in FIGS. 12 and 14, the gate layer 102 includes a first contact surface 102A1 and a second contact surface 102A2 in contact with the gate electrode 26. The gate layer 102 also includes a bottom surface 102B in contact with the electron supply layer 42. The gate layer 102 may have a thickness of 50 nm or more and 150 nm or less.

[0067] The gate layer 102 may be a GaN layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may include at least one of Mg, Zn, and C. In one example, the acceptor-type impurity may be Mg.

[0068] As shown in FIG. 14 , in this embodiment, the gate layer 102 includes a base portion 104 and a well portion 106. The well portion 106 extends from the second contact surface 102A2 into the gate layer 102. The second contact surface 102A2 is flush with the first contact surface 102A1. The base portion 104 includes the first contact surface 102A1. The well portion 106 includes the second contact surface 102A2. The base portion 104 includes acceptor-type impurities at a first concentration. The well portion 106 includes acceptor-type impurities at a second concentration higher than the first concentration. In one example, the well portion 106 may be formed by introducing acceptor-type impurities into the gate layer 102 by ion implantation. The first concentration of the base portion 104 is 7×10 18 cm -3 More than 1×10 20 cm -3 The second concentration in the well portion 106 may be at least two times and at most ten times the first concentration.

[0069] The concentration of acceptor-type impurities at the second contact surface 102A2 is higher than the concentration of acceptor-type impurities at the first contact surface 102A1. As the concentration of acceptor-type impurities in the gate layer 102 increases, the width of the depletion layer formed between the gate layer 102 and the gate electrode 26 decreases. Therefore, at the second contact surface 102A2, which has a relatively high concentration of acceptor-type impurities, the Schottky barrier decreases and tunneling current is more likely to occur. Thus, the gate layer 102 is configured such that, when a gate voltage is applied to the gate electrode 26, the gate current per unit area flowing through the second contact surface 102A2 is greater than the gate current per unit area flowing through the first contact surface 102A1. Since the gate current is more likely to flow through the second contact surface 102A2, the gate layer 46 is less likely to enter a floating state. Even if the gate layer 46 enters a floating state, the potential of the gate layer 46 quickly becomes the same as that of the gate electrode 26, thereby reducing fluctuations in the threshold voltage.

[0070] 12, the second contact surface 102A2 is surrounded by the first contact surface 102A1 in a plan view. The area of ​​the second contact surface 102A2 may be smaller than the area of ​​the first contact surface 102A1. For example, the area of ​​the first contact surface 102A1 may be 100 times or more the area of ​​the second contact surface 102A2.

[0071] The nitride semiconductor device 100 according to this embodiment has the following advantages in addition to the advantages (1-1), (1-2), and (1-6) to (1-12) of the first embodiment. (2-1) The second contact surface 102A2 is flush with the first contact surface 102A1. Unlike the first embodiment in which the recess 48 is formed, this configuration does not require an etching step, and therefore does not cause etching damage to the gate layer 102. Furthermore, since the top surface of the gate layer 102 is planarized, it is possible to prevent discontinuities in the gate electrode 26 due to steps on the top surface of the gate layer 102.

[0072] (2-2) The gate layer 102 includes a base portion 104 containing acceptor-type impurities at a first concentration and a well portion 106 containing acceptor-type impurities at a second concentration higher than the first concentration, and the well portion 106 extends from the second contact surface 102A2 into the gate layer 102. This allows the concentration of acceptor-type impurities at the second contact surface 102A2 to be higher than the concentration of acceptor-type impurities at the first contact surface 102A1. Therefore, the gate current can flow more easily through the second contact surface 102A2, thereby reducing fluctuations in the threshold voltage of the nitride semiconductor device 100.

[0073] Third Embodiment Next, an exemplary nitride semiconductor device 200 according to a third embodiment will be described with reference to FIGS. 15 to 17. The nitride semiconductor device 200 may be configured as a HEMT using a nitride semiconductor. FIG. 15 is a schematic plan view of the nitride semiconductor device 200. FIG. 16 is a schematic cross-sectional view of the nitride semiconductor device 200 taken along line F16-F16 in FIG. 15. FIG. 17 is a schematic cross-sectional view of the nitride semiconductor device 200 taken along line F17-F17 in FIG. 15. In FIGS. 15 to 17, components similar to those in the first embodiment are denoted by the same reference numerals. Detailed description of components similar to those in the first embodiment will be omitted. The gate wiring 12, source wiring 14, and drain wiring 16 on the insulating layer 18 shown in FIG. 1 can also be applied to the nitride semiconductor device 200. As in FIG. 2, FIG. 15 shows components of the nitride semiconductor device 200 located below the insulating layer 18.

[0074] 15 to 17, the nitride semiconductor device 200 includes a gate layer 202 containing acceptor-type impurities. As shown in FIGS. 15 and 16, the gate layer 202 is located between the source electrode 28 and the drain electrode 30. As shown in FIGS. 15 and 17, the gate layer 202 includes a first contact surface 202A1 and a second contact surface 202A2 in contact with the gate electrode 26. The gate layer 202 also includes a bottom surface 202B in contact with the electron supply layer 42.

[0075] 17, in this embodiment, the gate layer 202 includes a recess 204. The recess 204 is recessed in the Z-axis direction from the first contact surface 202A1. The recess 204 also includes a second contact surface 202A2. Therefore, a thickness T2 of the gate layer 202 between the bottom surface 202B and the second contact surface 202A2 is smaller than a thickness T1 of the gate layer 202 between the bottom surface 202B and the first contact surface 202A1. The gate layer 202 may have a thickness of 50 nm or more and 150 nm or less. In one example, the thickness T1 may be approximately 100 nm, and the thickness T2 may be approximately 80 nm.

[0076] The gate layer 202 is Al y Ga 1-yA first layer 206 composed of Al x Ga 1-x N, and a second layer 208 composed of Al x Ga 1-x N, where 0 ≦ y < x. In one example, x = 0.1 and y = 0 may be satisfied. The concave portion 204 penetrates the second layer 208 and exposes the first layer 206. Therefore, the first contact surface 202A1 is made of the material of the second layer 208, that is, Al y Ga 1-y N, and the second contact surface 202A2 is made of the material of the first layer 206, that is, Al

[0077] N. In other words, the second layer 208 includes the first contact surface 202A1, and the first layer 206 includes the second contact surface 202A2. As a result, the bandgap of the material constituting the second contact surface 202A2 of the gate layer 202 is smaller than the bandgap of the material constituting the first contact surface 202A1 of the gate layer 202.

[0078] The first layer 206 and / or the second layer 208 may be doped with acceptor-type impurities. The acceptor-type impurities can include at least one of Mg, Zn, and C. In one example, the acceptor-type impurities may be Mg. The maximum concentration of acceptor-type impurities in the gate layer 202 is 7×10 18 cm -3 or more and 1×10 20 cm-3 It can be as follows:

[0079] The first layer 206 may include an acceptor-type impurity at a first concentration, and the second layer 208 may include an acceptor-type impurity at a second concentration that is lower than the first concentration. Note that the second concentration includes the concentration when the acceptor-type impurity is not doped. In one example, the acceptor-type impurity concentration in the first layer 206 is 2×10 19 cm -3 whereas the second layer 208 may not be doped with acceptor-type impurities. Because the first contact surface 202A1 is made of the material of the second layer 208 and the second contact surface 202A2 is made of the material of the first layer 206, the concentration of acceptor-type impurities in the second contact surface 202A2 is higher than the concentration of acceptor-type impurities in the first contact surface 202A1.

[0080] As the concentration of acceptor-type impurities contained in the gate layer 202 increases, the width of the depletion layer formed between the gate layer 202 and the gate electrode 26 decreases. Therefore, a tunnel current is more likely to occur at the second contact surface 202A2, which has a relatively high concentration of acceptor-type impurities. In this way, by making the acceptor-type impurity concentrations different between the first contact surface 202A1 and the second contact surface 202A2 in addition to the band gap, it is possible to make it easier for the gate current to flow through the second contact surface 202A2.

[0081] 15, the second contact surface 202A2 is surrounded by the first contact surface 202A1 in a plan view. The area of ​​the second contact surface 202A2 may be smaller than the area of ​​the first contact surface 202A1. For example, the area of ​​the first contact surface 202A1 may be 100 times or more the area of ​​the second contact surface 202A2.

[0082] The nitride semiconductor device 200 according to this embodiment has the following advantages in addition to the advantages (1-1) and (1-6) to (1-12) of the first embodiment. (3-1) The bandgap of the material forming the second contact surface 202A2 of the gate layer 202 is smaller than the bandgap of the material forming the first contact surface 202A1 of the gate layer 202. Thereby, the Schottky barrier between the gate layer 202 and the gate electrode 26 can be made smaller at the second contact surface 202A2. As a result, the gate current can be made to flow more easily through the second contact surface 202A2. Therefore, the variation in the threshold voltage in the nitride semiconductor device 200 can be reduced.

[0083] (3-2) The first contact surface 202A1 is composed of Al x Ga 1-x N, and the second contact surface 202A2 is composed of Al y Ga 1-y N, and 0 ≦ y < x may hold. By making the Al composition of the AlGaN forming the second contact surface 202A2 relatively small, the bandgap of the second contact surface 202A2 can be made smaller.

[0084] (3-3) The concentration of acceptor-type impurities in the second contact surface 202A2 may be higher than the concentration of acceptor-type impurities in the first contact surface 202A1. By making the acceptor-type impurity concentration different between the first contact surface 202A1 and the second contact surface 202A2 in addition to the bandgap, the gate current can be made to flow more easily through the second contact surface 202A2.

[0085] <Modified Example> Each of the above embodiments can be implemented with the following modifications. · In the example of FIG. 11, the second contact surface 46A2 is provided at two locations outside the main path region 50, but the second contact surface 46A2 may be provided at one location outside the main path region 50, or may be provided at a plurality of three or more locations.

[0086] In the second embodiment, since no recess is formed in the gate layer 102, the second contact surface 102A2 may be disposed so as to overlap the gate via 20 in a plan view. Also, in the first and third embodiments, when the step of the gate electrode 26 caused by the recesses 48, 204 in the gate layers 46, 202 is relatively small, or when the gate via 20 can be appropriately connected to the step of the gate electrode 26, the second contact surface 46A2 may be disposed so as to overlap the gate via 20 in a plan view.

[0087] One or more of the various examples described herein may be combined to the extent that they are not technically inconsistent. In the present disclosure, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."

[0088] As used in this disclosure, terms such as "about," "substantially," and "approximately" indicate a range of values ​​within ±10% of the stated value, unless the context clearly indicates otherwise.

[0089] The term "on" as used in this disclosure can mean both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer can be placed directly on the second layer in contact with the second layer, while in other embodiments, the first layer can be placed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0090] Directional terms such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "front," "rear," "longitudinal," "lateral," "left," "right," "front," and "rear" used in this disclosure depend on the particular orientation of the device being described and illustrated. Various alternative orientations are contemplated in this disclosure, and therefore these directional terms should not be construed narrowly.

[0091] For example, the Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0092] Terms such as "first," "second," and "third" in this disclosure are used merely to distinguish between objects and do not rank the objects. <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0093] (Appendix 1) an electron transit layer (40); an electron supply layer (42) located on the electron transit layer (40) and having a band gap larger than that of the electron transit layer (40); a source electrode (28) and a drain electrode (30) in contact with the electron supply layer (42); a gate layer (46, 102, 202) located between the source electrode (28) and the drain electrode (30), the gate layer (46, 102, 202) including a bottom surface (46B, 102B, 202B) in contact with the electron supply layer (42), the gate layer (46, 102, 202) including acceptor-type impurities; a gate electrode (26) located on the gate layer (46, 102, 202); Equipped with the gate layer (46, 102, 202) includes a first contact surface (46A1, 102A1, 202A1) and a second contact surface (46A2, 102A2, 202A2) in contact with the gate electrode (26); The gate layer (46, 102, 202) is configured so that when a gate voltage is applied to the gate electrode (26), a gate current per unit area flowing through the second contact surface (46A2, 102A2, 202A2) is larger than a gate current per unit area flowing through the first contact surface (46A1, 102A1, 202A1).

[0094] (Appendix 2) 2. The nitride semiconductor device according to claim 1, wherein a concentration of the acceptor-type impurities in the second contact surface (46A2) is higher than a concentration of the acceptor-type impurities in the first contact surface (46A1).

[0095] (Appendix 3) 3. The nitride semiconductor device according to claim 1, wherein a concentration of the acceptor-type impurity in the gate layer (46) varies in a thickness direction intersecting the bottom surface (46B) of the gate layer (46), and a thickness (T2) of the gate layer (46) between the bottom surface (46B) and the second contact surface (46A2) is smaller than a thickness (T1) of the gate layer (46) between the bottom surface (46B) and the first contact surface (46A1).

[0096] (Appendix 4) 4. The nitride semiconductor device according to claim 3, wherein the concentration of the acceptor-type impurities that changes in the thickness direction includes a gradient that decreases toward the first contact surface (46A1).

[0097] (Appendix 5) 4. The nitride semiconductor device according to claim 3, wherein the concentration of the acceptor-type impurities that changes in the thickness direction includes a first gradient that increases toward the first contact surface (46A1) and a second gradient that decreases toward the first contact surface (46A1).

[0098] (Appendix 6) 3. The nitride semiconductor device according to claim 1, wherein the second contact surface (102A2) is flush with the first contact surface (102A1).

[0099] (Appendix 7) The gate layer (102) includes a base portion (104) containing the acceptor-type impurity at a first concentration and a well portion (106) containing the acceptor-type impurity at a second concentration higher than the first concentration, and the well portion (106) extends into the gate layer (102) from the second contact surface (102A2). The nitride semiconductor device according to Supplementary Note 6.

[0100] (Supplementary Note 8) The band gap of the material constituting the second contact surface (202A2) of the gate layer (202) is smaller than the band gap of the material constituting the first contact surface (202A1) of the gate layer (202). The nitride semiconductor device according to Supplementary Note 1.

[0101] (Supplementary Note 9) The thickness (T2) of the gate layer (202) between the bottom surface (202B) and the second contact surface (202A2) is smaller than the thickness (T1) of the gate layer (202) between the bottom surface (202B) and the first contact surface (202A1). The nitride semiconductor device according to Supplementary Note 8.

[0102] (Supplementary Note 10) The first contact surface (202A1) is composed of Al x Ga 1-x N, and the second contact surface (202A2) is composed of Al y Ga 1-y N, where 0 ≦ y < x. The nitride semiconductor device according to Supplementary Note 8 or 9.

[0103] (Supplementary Note 11) The concentration of the acceptor-type impurity on the second contact surface (202A2) is higher than the concentration of the acceptor-type impurity on the first contact surface (202A1). The nitride semiconductor device according to any one of Supplementary Notes 8 to 10.

[0104] (Supplementary Note 12) The area of the second contact surface (46A2, 102A2, 202A2) is smaller than the area of the first contact surface (46A1, 102A1, 202A1). The nitride semiconductor device according to any one of Supplementary Notes 1 to 11.

[0105] (Appendix 13) 13. The nitride semiconductor device according to any one of appendixes 1 to 12, wherein the area of ​​the first contact surface (46A1, 102A1, 202A1) is 100 times or more the area of ​​the second contact surface (46A2, 102A2, 202A2).

[0106] (Appendix 14) 14. The nitride semiconductor device according to any one of claims 1 to 13, wherein the second contact surface (46A2, 102A2, 202A2) is surrounded by the first contact surface (46A1, 102A1, 202A1) in a plan view.

[0107] (Appendix 15) The nitride semiconductor device according to any one of appendixes 1 to 14, wherein the second contact surface (46A2, 102A2, 202A2) is located outside a main path region of a drain-source current defined between the source electrode (28) and the drain electrode (30) in a planar view.

[0108] (Appendix 16) 16. The nitride semiconductor device according to any one of claims 1 to 15, wherein the gate layer (46) surrounds one of the source electrode (28) or the drain electrode (30) in a plan view.

[0109] (Appendix 17) 17. The nitride semiconductor device according to any one of claims 1 to 16, wherein the gate electrode (26) forms a Schottky junction with the first contact surface (46A1, 102A1, 202A1) and the second contact surface (46A2, 102A2, 202A2).

[0110] (Appendix 18) 18. The nitride semiconductor device according to any one of claims 1 to 17, wherein the gate electrode (26) includes TiN, TaN, WN, TiSiN, TaSiN, WSi, and / or WSiN.

[0111] (Appendix 19) an insulating layer (18) located on the gate electrode (26), the source electrode (28), and the drain electrode (30); a gate wiring (12), a source wiring (14), and a drain wiring (16) located on the insulating layer (18); one or more gate vias (20), one or more source vias (22), and one or more drain vias (24) through said insulating layer (18); The nitride semiconductor device according to any one of appendices 1 to 18, further comprising: the gate electrode (26) connected to the gate wiring (12) through the one or more gate vias (20), the source electrode (28) connected to the source wiring (14) through the one or more source vias (22), and the drain electrode (30) connected to the drain wiring (16) through the one or more drain vias (24).

[0112] (Appendix 20) 20. The nitride semiconductor device according to any one of notes 1 to 19, wherein the acceptor-type impurity is Mg.

[0113] (Appendix 21) The nitride semiconductor device according to any one of claims 1 to 7, wherein the electron transit layer (40) is a GaN layer, the electron supply layer (42) is an AlGaN layer, and the gate layer (46) is a GaN layer.

[0114] (Appendix 22) 6. The nitride semiconductor device according to any one of claims 1 to 5, wherein the gate layer (46) includes a recess (48), and the recess (48) includes the second contact surface (46A2).

[0115] (Appendix 23) 12. The nitride semiconductor device according to any one of claims 8 to 11, wherein the gate layer (202) includes a recess (204), and the recess (204) includes the second contact surface (202A2).

[0116] (Appendix 24) The gate layer (202) is Al y Ga 1-y N-composed first layer (206) and Al x Ga 1-x N-composed second layer (208), where 0 ≦ y < x, and the recess (204) penetrates the second layer (208) to expose the first layer (206). The nitride semiconductor device according to supplementary note 24.

[0117] (Supplementary note 25) The first layer (206) contains the acceptor-type impurity at a first concentration, and the second layer (208) contains the acceptor-type impurity at a second concentration lower than the first concentration. The nitride semiconductor device according to supplementary note 24.

[0118] Without departing from the scope of the claims and their equivalents, various modifications can be made in form and detail to the above-described examples. The above examples are for illustrative purposes and not for limitation. The descriptions of the features in each example should be considered applicable to similar features or aspects in other examples. Suitable results can be achieved if consecutive events are performed in a different order and / or if the components within the described system, architecture, device, or circuit are combined in different ways and / or replaced or supplemented by other components or their equivalents. The scope of the present disclosure is defined not by the detailed description but by the claims and their equivalents. All modifications of the claims and their equivalents are included in the present disclosure.

Description of reference numerals

[0119] 10, 100, 200... Nitride semiconductor device 12... Gate wiring 14... Source wiring 16... Drain wiring 18... Insulating layer 20... Gate via 22... Source via 24... Drain via 26... Gate electrode 26A1,26A2…Main electrode part 26B1...First connection part 26B2...Second connection part 28...Source electrode 30...Drain electrode 32…Active region 34...Inactive area 36...Semiconductor substrate 38...Buffer layer 40...Electron transit layer 42…electron supply layer 44...Impurity introduction region 46,102,202...Gate layer 46A1,102A1,202A1…1st contact surface 46A2, 102A2, 202A2…Second contact surface 46B,102B,202B…Bottom surface 48,204...recess 50...Main pathway region 104...base part 106...Well part 206…1st layer 208...Second layer

Claims

1. an electron transit layer; an electron supply layer located on the electron transit layer and having a band gap larger than that of the electron transit layer; a source electrode and a drain electrode in contact with the electron supply layer; a gate layer including a bottom surface in contact with the electron supply layer and positioned between the source electrode and the drain electrode, the gate layer including an acceptor-type impurity; a gate electrode located on the gate layer; Equipped with the gate layer includes a first contact surface and a second contact surface in contact with the gate electrode; the gate layer is configured so that, when a gate voltage is applied to the gate electrode, a gate current per unit area flowing through the second contact surface is larger than a gate current per unit area flowing through the first contact surface.

2. The nitride semiconductor device according to claim 1 , wherein a concentration of said acceptor-type impurities in said second contact surface is higher than a concentration of said acceptor-type impurities in said first contact surface.

3. 3. The nitride semiconductor device according to claim 2, wherein a concentration of the acceptor-type impurity in the gate layer varies in a thickness direction intersecting with the bottom surface of the gate layer, and a thickness of the gate layer between the bottom surface and the second contact surface is smaller than a thickness of the gate layer between the bottom surface and the first contact surface.

4. The nitride semiconductor device according to claim 3 , wherein the concentration of said acceptor-type impurity that varies in said thickness direction includes a gradient that decreases toward said first contact surface.

5. 4. The nitride semiconductor device according to claim 3, wherein the concentration of said acceptor-type impurities that varies in said thickness direction includes a first gradient that increases toward said first contact surface and a second gradient that decreases toward said first contact surface.

6. The nitride semiconductor device according to claim 2 , wherein the second contact surface is flush with the first contact surface.

7. 7. The nitride semiconductor device according to claim 6, wherein the gate layer includes a base portion containing the acceptor-type impurity at a first concentration and a well portion containing the acceptor-type impurity at a second concentration higher than the first concentration, the well portion extending from the second contact surface into the gate layer.

8. The nitride semiconductor device according to claim 1 , wherein a band gap of a material constituting said second contact surface of said gate layer is smaller than a band gap of a material constituting said first contact surface of said gate layer.

9. The nitride semiconductor device according to claim 8 , wherein a thickness of said gate layer between said bottom surface and said second contact surface is smaller than a thickness of said gate layer between said bottom surface and said first contact surface.

10. The first contact surface is Al ｘ Ga １－ｘ N, and the second contact surface is made of Al ｙ Ga １－ｙ 9. The nitride semiconductor device according to claim 8, wherein the nitride semiconductor layer is made up of N, and 0≦y<x.

11. The nitride semiconductor device according to claim 8 , wherein a concentration of said acceptor-type impurities in said second contact surface is higher than a concentration of said acceptor-type impurities in said first contact surface.

12. 12. The nitride semiconductor device according to claim 1, wherein an area of ​​said second contact surface is smaller than an area of ​​said first contact surface.

13. The nitride semiconductor device according to claim 12 , wherein an area of ​​said first contact surface is 100 times or more an area of ​​said second contact surface.

14. 12. The nitride semiconductor device according to claim 1, wherein said second contact surface is surrounded by said first contact surface in a plan view.

15. 12. The nitride semiconductor device according to claim 1, wherein the second contact surface is located outside a main path region of a drain-source current defined between the source electrode and the drain electrode in a plan view.

16. 12. The nitride semiconductor device according to claim 1, wherein said gate layer surrounds one of said source electrode and said drain electrode in a plan view.

17. 12. The nitride semiconductor device according to claim 1, wherein said gate electrode forms a Schottky junction with said first contact surface and said second contact surface.

18. 12. The nitride semiconductor device according to claim 1, wherein the gate electrode comprises TiN, TaN, WN, TiSiN, TaSiN, WSi, and / or WSiN.

19. an insulating layer located on the gate electrode, the source electrode, and the drain electrode; a gate wiring, a source wiring, and a drain wiring located on the insulating layer; one or more gate vias, one or more source vias, and one or more drain vias through the insulating layer; the gate electrode is connected to the gate wiring via the one or more gate vias, the source electrode is connected to the source wiring via the one or more source vias, and the drain electrode is connected to the drain wiring via the one or more drain vias.

20. 12. The nitride semiconductor device according to claim 1, wherein the acceptor-type impurity is Mg.

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