Vector arithmetic processor and arithmetic execution method of vector arithmetic processor

Abstract

To suppress a deterioration in processing performance due to a delay in execution of a subsequent instruction to use a mask register in the case of executing all set instructions to set all mask values of a mask register.SOLUTION: A vector arithmetic processor includes a mask register, an instruction decoder, a dependency resetting part, a scheduler and a vector arithmetic unit. The dependency resetting part resets dependency information showing data dependency with a preceding instruction that respectively corresponds to the mask register and a destination operand of a subsequent instruction to be transferred from the instruction decoder to the scheduler in the case that full set information is set by the instruction decoder that decodes all set instructions in correspondence with the mask register designated by the subsequent instruction. This can suppress a deterioration in processing performance due to a delay in execution of the subsequent instruction.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a vector processor and a method for executing operations on a vector processor. [Background technology]

[0002] In a vector processor capable of performing an operation on each element of vector data, whether or not to store operation result data in a destination register for each element of vector data is determined based on, for example, a mask value stored in a mask register. For example, if the mask value is set, the operation result data is stored in the elements of the destination register, and if the mask value is reset, the data already stored in the elements of the destination register is stored. That is, a merge process is performed to store the operation result data or the data already stored in the destination register in the destination register for each element based on the mask value. Furthermore, in this type of vector processor, execution of a subsequent instruction that has a data dependency with a preceding instruction is delayed until the data dependency is resolved (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-086809 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, when all mask values ​​in the mask register are set, only the operation result data is stored in the destination register. Therefore, merging of the operation result data with the data (merging source) already stored in the destination register is not necessary. However, whether merging of the operation result data with the merging source is necessary cannot be determined until the mask values ​​are read from the mask register.

[0005] A scheduler that controls the issuance of instructions to arithmetic units starts the execution of a subsequent instruction in time with the merging source of the preceding instruction being stored in a register. Also, if a vector processor can execute a set all instruction that sets all mask values ​​in a mask register, the scheduler starts the execution of a subsequent instruction that uses the mask register in time with the setting of all mask values ​​in the mask register. As a result, if the execution of the subsequent instruction is delayed, the processing performance of the vector processor will decrease.

[0006] In one aspect, the present invention aims to prevent a decrease in processing performance due to a delay in the execution of subsequent instructions that use the mask register when a set all instruction that sets all mask values ​​in a mask register is executed. [Means for solving the problem]

[0007] According to one aspect, the vector processor is a vector processor capable of executing vector operations, comprising: a mask register for holding a mask value to be set for each element of a vector when an operation result for each element is stored in a data register; an instruction decoder for decoding an instruction to generate instruction execution information, for setting dependency information included in the instruction execution information when a subsequent instruction having data dependency with a preceding instruction is decoded, and for setting all set information included in the instruction execution information when an all set instruction for setting all the mask values ​​in the mask register is decoded; and a processor for holding the instruction execution information for each instruction and setting the dependency information included in the held instruction execution information. a vector calculator that executes a vector operation for each element based on the instruction execution information output from the scheduler and stores in the data register an operation result for the element corresponding to the mask value in a set state held in the mask register; and a dependency reset unit that resets the dependency information corresponding to the destination operand of the subsequent instruction and the mask register, which are transferred from the instruction decoder to the scheduler, when all the set information is set corresponding to the mask register specified by the subsequent instruction. [Effects of the Invention]

[0008] When a set all instruction that sets all mask values ​​in the mask register is executed, it is possible to prevent a decrease in processing performance due to a delay in the execution of subsequent instructions that use the mask register. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is a block diagram illustrating an example of a vector processor according to one embodiment. [Figure 2] 2 is an explanatory diagram showing an example of merging data in a destination register according to a set value of a mask register when the add instruction shown in FIG. 1 is executed. FIG. [Figure 3]3 is an explanatory diagram showing an example of the operation when the vector operation processor of FIG. 1 and another vector operation processor execute the add instruction shown in FIG. 2; [Figure 4] 1. FIG. 4 is an explanatory diagram showing an example of pipeline operation of another vector operation processor not having the dependency reset unit of FIG. [Figure 5] FIG. 2 is an explanatory diagram showing an example of a pipeline operation of the vector processor of FIG. [Figure 6] FIG. 10 is a block diagram illustrating an example of a vector operation processor according to another embodiment. [Figure 7] FIG. 7 is an explanatory diagram illustrating an example of a register renaming unit in FIG. 6; [Figure 8] FIG. 7 is an explanatory diagram showing an example of a pipeline operation of the vector processor of FIG. 6; [Figure 9] 7 is an explanatory diagram showing an example of the circuit and operation of the dependency reset unit of FIG. 6. FIG. [Figure 10] 10 is an explanatory diagram showing an example of a process of resetting a dependency flag by a dependency reset unit in the D cycle (T2) of the add instruction ADD in FIG. 9; FIG. [Figure 11] 7 is a block diagram showing an example of an information processing system including the vector operation processor shown in FIG. 1 or 6. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following, the same reference numerals as the signal names are used for signal lines through which signals are transmitted. Although not particularly limited, the vector processor described below is a superscalar processor that executes instructions in parallel through pipeline processing. Note that the vector processor described below may also be a scalar processor.

[0011] 1 shows an example of a vector processor according to an embodiment. The vector processor 100 shown in FIG. 1 includes an instruction decoder 101, a dependency reset unit 102, a scheduler 103, a vector calculator 104, and a register file 105.

[0012] The register file 105 has a plurality of registers FPR (FPR0, FPR1, FPR2, FPR3, FPR4, ...) that hold data and a plurality of mask registers PR (PR0, PR1, PR2, ...) that hold mask values. The registers FPR are an example of a data register.

[0013] For example, each register FPR is 256 bits and can hold four elements (i.e., data) of a 64-bit floating-point number included in vector data. In FIG. 1, the four 64-bit elements held in each register FPR are indicated by data D00, D01, D02, D03, etc. Note that, although an example in which floating-point data is calculated using a floating-point register FPR will be described below, fixed-point data may also be calculated using a fixed-point register. In this case, the vector processor 100 has a mask register for fixed-point numbers.

[0014] For example, each mask register PR is 4 bits and can hold four mask values ​​of 1 bit each corresponding to the four elements of the register FPR. A mask value of "0" indicates that the data (merging source) already held in the register FPR (destination register) that stores the operation result data of the subsequent instruction is to be left unchanged without being overwritten with the operation result data. A mask value of "1" indicates that the data already held in the register FPR (destination register) that stores the operation result data of the subsequent instruction is to be overwritten with the operation result data.

[0015] The size of the register FPR is not limited to 256 bits, and the number of elements of the register FPR is not limited to four. The number of elements of the register FPR may be variable, such as four 64-bit elements, eight 32-bit elements, or sixteen 16-bit elements. When the number of elements of the register FPR is variable, the number of elements of the mask register PR is made variable to match the number of elements of the register FPR. Therefore, when the maximum number of elements of the register FPR is 32, the mask register PR is designed to be 32 bits. Of the 32 bits of the mask register PR, the same number of bits as the number of elements of the register FPR are used to hold the mask value.

[0016] The instruction decoder 101 decodes the instructions included in the instruction sequence and outputs the decoded results as instruction execution information to the scheduler 103 via the dependency reset unit 102. As an example, in FIG. 1, it is assumed that a subtraction instruction SUB, a set all instruction ptrue, and an add instruction ADD are sequentially supplied to the instruction decoder 101. Hereinafter, the subtraction instruction SUB, the set all instruction ptrue, and the add instruction ADD will also be referred to as the SUB instruction, the ptrue instruction, and the ADD instruction, respectively.

[0017] In Figure 1, the SUB instruction subtracts the vector data held in register FPR4 element by element from the vector data held in register FPR3, and the subtraction results for each element are stored in register FPR0 ​​(destination register). The ptrue instruction sets each element of mask register PR1 to "1". The ADD instruction adds the vector data held in registers FPR1 and FPR2 element by element, and the addition result is stored in register FPR0 ​​(destination register) according to the mask value of mask register PR1. Because the ptrue instruction sets all mask values ​​of mask register PR1 to "1", all elements of the addition result are stored in register FPR0.

[0018] When the ptrue instruction is not executed, the register FPR0 ​​that stores the subtraction result is the same as the register FPR0 ​​that stores the addition result of the ADD instruction, and the subtraction result or the addition result is selectively held depending on the mask value for each element of the mask register PR1. Therefore, the timing at which the addition result is stored in register FPR0 ​​must be set after the timing at which the subtraction result is stored in register FPR0. The register FPR0, which is shared by the SUB instruction and the ADD instruction, has RAW (Read After Write) data dependency.

[0019] When the instruction decoder 101 decodes the all set instruction ptrue of the mask register PR1, it sets the all set information of the mask register PR1 included in the instruction execution information of the all set instruction ptrue to "1" and outputs the instruction execution information to the dependency reset unit 102. Furthermore, when the instruction decoder 101 detects a data dependency of RAW in the destination register FPR0 ​​when decoding the ADD instruction, it sets the dependency information of the register FPR0 ​​included in the instruction execution information of the ADD instruction to "1". The instruction decoder 101 outputs the instruction execution information in which the dependency information of the register FPR0 ​​has been set to "1" to the dependency reset unit 102.

[0020] 1, all set information is set for the mask register PR1 specified in the subsequent ADD instruction, and dependency information of the destination register FPR0 ​​of the subsequent ADD instruction is set. In this case, the dependency reset unit 102 resets the dependency information of the destination register FPR0 ​​of the subsequent ADD instruction and the dependency information of the mask register PR1 to "0" and outputs them to the scheduler 103.

[0021] Note that if all set information has not been set for the mask register PR specified by the subsequent instruction and the dependency information of the destination register FPR of the subsequent instruction has been set, the dependency reset unit 102 outputs the dependency information to the scheduler 103 without resetting it. In other words, if the all set instruction ptrue is not executed, the dependency reset unit 102 outputs the instruction execution information of the subsequent instruction received from the instruction decoder 101 as is to the scheduler 103. For example, the instruction decoder 101 can decode a mask set instruction that individually sets the mask value of the mask register PR.

[0022] Furthermore, when all set information is set for the mask register PR specified by the subsequent instruction and dependency information of the destination register FPR of the subsequent instruction is not set, the dependency reset unit 102 outputs the instruction execution information of the subsequent instruction received from the instruction decoder 101 as is to the scheduler 103. That is, when the all set instruction ptrue is executed for the mask register PR specified by the subsequent instruction in which dependency information of the destination register FPR is not set, the dependency reset unit 102 outputs the instruction execution information of the subsequent instruction received from the instruction decoder 101 as is to the scheduler 103.

[0023] The scheduler 103 sequentially holds instruction execution information (i.e., vector operation instructions, all set instructions, etc.) received via the dependency reset unit 102. The scheduler 103 sequentially outputs instruction execution information of instructions whose data dependency has been resolved based on the dependency information included in the held instruction execution information to the vector calculator 104 (out of order). Note that the scheduler 103 may be provided corresponding to each of the vector calculator and the mask calculator, which will be described later.

[0024] The vector calculator 104 includes a vector calculator and a mask calculator. When the vector calculator receives instruction execution information of a vector operation instruction (such as a SUB instruction or an ADD instruction) from the scheduler 103, it reads data from the source register FPR, executes the vector operation instruction, and stores the execution result in the destination register FPR.

[0025] When the mask calculator receives instruction execution information of the all set instruction ptrue from the scheduler 103, it sets all mask values ​​of the mask register PR to be set to "1." When the mask calculator receives instruction execution information of the mask set instruction from the scheduler 103, it sets each mask value of the mask register PR to "1" or "0" based on the instruction execution information.

[0026] Figure 2 shows an example of merging data in destination register FPR0 ​​according to the set value of mask register PR1 when executing the add instruction ADD shown in Figure 1. The vector calculator denoted by symbol ADD adds the data stored in source registers FPR1 and FPR2 element by element and outputs the addition result.

[0027] Furthermore, when a mask value of "1" is stored in an element of the mask register PR1, the vector calculator selects the addition result of the corresponding element and stores it in the destination register FPR0. When a mask value of "0" is stored in an element of the mask register PR1, the vector calculator selects the element of the operation result of the corresponding preceding instruction (the subtraction result in this example) and stores it in the destination register FPR0.

[0028] Therefore, when an add instruction is executed by the vector calculator, not only is the data added, but also the mask value stored in the mask register PR1 is read, the calculation result of the preceding instruction is read, and the element to be stored in the destination register FPR0 ​​is selected.

[0029] Fig. 3 shows an example of the operation when the vector operation processor 100 of Fig. 1 and another vector operation processor execute the ADD instruction shown in Fig. 2. Fig. 3 shows an example of an operation execution method of the vector operation processor 100. For ease of explanation, the circuit elements of the other vector operation processor are assigned the same reference numerals as the circuit elements of the vector operation processor 100. The other vector operation processor does not have a dependency reset unit 102.

[0030] The vector processor 100 and other vector processors execute the instruction sequence shown in Fig. 1. Therefore, all set information for setting all mask values ​​in the mask register PR is set to "1" by decoding the ptrue instruction before decoding the ADD instruction.

[0031] In the vector processor 100 and other vector processors, the instruction decoder 101 generates instruction execution information for the ADD instruction based on the decoding of the ADD instruction. As shown in the instruction sequence in Figure 1, the destination register FPR0 ​​of the ADD instruction has a RAW data dependency with the destination register FPR0 ​​of the preceding SUB instruction. Also, the mask register PR1 specified in the ADD instruction has a RAW data dependency with the mask register PR1 specified in the preceding ptrue instruction.

[0032] Therefore, the instruction decoder 101 of the vector processor 100 and the other vector processors sets the dependency information corresponding to the destination operand FPR0 ​​and mask register PR1 of the ADD instruction to "1." The instruction decoder 101 outputs instruction execution information including the set dependency information.

[0033] The dependency reset unit 102 detects, based on all set information of the set state, that all mask values ​​of the mask register PR1 specified by the ADD instruction are set to "1" by the ptrue instruction. Then, the dependency reset unit 102 resets to "0" the dependency information included in the instruction execution information of the ADD instruction and corresponding to the destination operand FPR0 ​​of the ADD instruction and the mask register PR1. The dependency reset unit 102 outputs the instruction execution information including the reset dependency information to the scheduler 103.

[0034] The scheduler 103 of the vector processor 100, which has received the instruction execution information of the ADD instruction, determines that there is no data dependency with the preceding instruction because the dependency information is "0", and immediately issues the ADD instruction to the vector calculator 104. That is, the scheduler 103 can issue the ADD instruction to the vector calculator 104 without reading the operation result from the register FPR0 ​​before the operation result from the SUB instruction is stored in the register FPR0. Furthermore, the scheduler 103 can issue the ADD instruction to the vector calculator 104 before all mask values ​​in the mask register PR1 are set to "1" by the ptrue instruction.

[0035] The vector calculator 104 of the vector processor 100 reads data from the source registers FPR1 and FPR2, adds them, and stores the calculation result in the destination register FPR0 ​​based on the instruction execution information from the scheduler 103. Then, the execution of the ADD instruction shown in FIG. 2 is completed.

[0036] When all mask values ​​in the mask register PR1 are set to "1" by the ptrue instruction, the execution result of the ADD instruction is stored in all elements of the destination register FPR0. This makes it possible to omit reading data from the register FPR0 ​​(merging source) that holds the operation result of the SUB instruction and reading the mask value from the mask register PR1 described in Figure 2.

[0037] Furthermore, the process of bypassing the operation result of the SUB instruction to the destination register FPR0 ​​of the ADD instruction without storing it in the register FPR0 ​​can also be omitted. By omitting the read operation of the register FPR0 ​​and the mask register PR1 and the bypassing of the operation result of the SUB instruction, the power consumption of the vector processor 100 can be reduced.

[0038] On the other hand, since other vector operation processors do not have a dependency reset unit 102, the dependency information set to "1" contained in the instruction execution information generated by the instruction decoder 101 is output to the scheduler 103 without being reset.

[0039] The scheduler 103 of the other vector processor holds the instruction execution information of the ADD instruction received from the instruction decoder 101. The scheduler 103 determines that there is a data dependency of RAW between the destination register FPR0 ​​of the preceding SUB instruction and the ADD instruction, based on the dependency information of the set state corresponding to the destination operand FPR0 ​​of the ADD instruction. The scheduler 103 also determines that there is a data dependency of RAW between the destination register PR1 specified by the preceding ptrue instruction and the ADD instruction, based on the dependency information of the set state corresponding to the mask register PR1 specified by the ADD instruction.

[0040] Therefore, after the data dependency of the register FPR0 ​​between the ADD instruction and the SUB instruction and the data dependency of the mask register PR1 between the ADD instruction and the ptrue instruction are resolved, the scheduler 103 issues the ADD instruction to the vector operation unit 104. Therefore, in other vector operation processors, execution of the ADD instruction is delayed until the data dependency between the ADD instruction and the SUB instruction and the data dependency between the ADD instruction and the ptrue instruction are resolved.

[0041] As a result, the other vector operation processors have lower instruction execution efficiency and lower processing performance compared to the vector operation processor 100. In other words, the vector operation processor 100 can suppress the decrease in instruction execution efficiency and the decrease in processing performance compared to other vector operation processors.

[0042] Fig. 4 shows an example of pipeline operation of another vector processor that does not have the dependency reset unit 102 of Fig. 1. In Fig. 4, the other vector processor executes the instruction sequence (SUB instruction, ptrue instruction, ADD instruction) shown in Fig. 1. The other vector processor divides instructions into multiple cycles by flip-flops and executes the instructions by pipeline processing.

[0043] For example, the pipeline cycles include a decode cycle D, a decode transfer cycle DT, a priority cycle P, a priority transfer cycle PT, a buffer cycle B (B1, B2, etc.), an execution cycle X (X1, X2, etc.), and store cycles FPR and PR. Hereinafter, the pipeline cycles will also be referred to as the D cycle, DT cycle, P cycle, PT cycle, B cycle, X cycle, FPR cycle, and PR cycle.

[0044] In the D cycle, the instruction is decoded by the instruction decoder 101. In the DT cycle, the instruction execution information generated by the decoding by the instruction decoder 101 is transferred to the scheduler 103 via the dependency reset unit 102. In the P cycle, the instruction to be issued from the scheduler 103 to the vector calculator 104 is determined, and the instruction execution information of the determined instruction is issued from the scheduler 103 to the vector calculator 104.

[0045] In the PT cycle, instruction execution information is transferred from the scheduler 103 to the vector arithmetic unit 104. In the B1 and B2 cycles, data (source operands) used in the arithmetic unit are read from the register FPR. In the X1 and X2 cycles, an operation is executed by the vector arithmetic unit 104. In the FPR cycle, the operation result by the vector arithmetic unit 104 is stored in the register FPR. In the PR cycle, the operation result by the mask arithmetic unit included in the vector arithmetic unit 104 is stored in the mask register PR.

[0046] In the instruction sequence shown in Figure 1, all mask values ​​in mask register PR1 are set to "1" by the ptrue instruction, so only the operation result of the ADD instruction is stored in destination register FPR0. However, in terms of the circuit, as shown in Figure 2, only the operation result of the ADD instruction is selected element by element according to the mask value held in mask register PR1 and stored in destination register FPR0. For this reason, scheduler 103 issues the ADD instruction to vector calculator 104 so that the B1 cycle of the ADD instruction is executed after the FPR cycle of the SUB instruction.

[0047] The ADD instruction reads the mask value of the mask register PR1 and selects data to be stored in the destination register FPR0. Therefore, the scheduler 103 issues the ADD instruction to the vector calculator 104 so that the B1 cycle of the ADD instruction is executed after the PR cycle of the ptrue instruction.

[0048] In the first operational example, even if the store cycle FPR for storing the result of the SUB instruction in register FPR0 ​​is completed before the P cycle of the ADD instruction, the data dependency of the ADD instruction is not resolved until the store cycle PR for the ptrue instruction for setting a mask value in mask register PR1. Therefore, after receiving the ADD instruction in the DT cycle, the scheduler 103 cannot execute the P cycle for issuing the ADD instruction. As a result, a wait time of, for example, five cycles occurs between the DT cycle and the P cycle, degrading processing performance.

[0049] In Operation Example 2, even if the store cycle PR of the ptrue instruction that sets a mask value in the mask register PR1 is completed before the P cycle of the ADD instruction, the data dependency of the ADD instruction is not resolved until the store cycle FPR that stores the operation result of the SUB instruction in the register FPR0. Therefore, as in Operation Example 1, for example, after the scheduler 103 receives the ADD instruction in the DT cycle, a waiting time of five cycles occurs until the P cycle in which the ADD instruction is issued, resulting in a decrease in processing performance.

[0050] 5 shows an example of pipeline operation of the vector processor 100 of FIG. 1. In FIG. 5, the vector processor 100 executes the instruction sequence (SUB instruction, ptrue instruction, ADD instruction) shown in FIG. 1. The vector processor 100 divides instructions into multiple cycles by flip-flops and executes the instructions by pipeline processing. Each cycle of the pipeline is the same as that of FIG. 4.

[0051] When the instruction decoder 101 decodes the ptrue instruction in cycle D, it is clear that all mask values ​​in the mask register PR1 are set to "1." When executing an ADD instruction that uses the mask register PR1 in which all mask values ​​are "1," the vector calculator 104 does not need to read the mask values ​​from the mask register PR1. Also, the vector calculator 104 does not need to read data from the destination register FPR0 ​​of the SUB instruction, which has data dependency.

[0052] 3, the dependency reset unit 102 resets the dependency information in the set state included in the instruction execution information of the ADD instruction to "0" based on all the set information from the instruction decoder 101, and outputs it together with other instruction execution information to the scheduler 103. For example, the dependency reset unit 102 resets the dependency information corresponding to the destination operand FPR0 ​​and the mask register PR1 of the ADD instruction.

[0053] As a result, the scheduler 103 determines that there is no data dependency between the ADD instruction and the SUB instruction or ptrue instruction, executes the P cycle following the DT cycle in which the ADD instruction is received, and issues the ADD instruction to the vector calculator 104. As a result, in Fig. 5, it is possible to suppress the occurrence of the wait time between the DT cycle and the P cycle shown in Fig. 4, and to suppress a decrease in processing performance.

[0054] 1 to 5, when the mask register PR used by a subsequent instruction is set by the ptrue instruction, the subsequent instruction can be executed without waiting for the execution of a preceding instruction having data dependency. Furthermore, the subsequent instruction can be executed without reading the mask value from the mask register PR. As a result, compared to other vector processors, it is possible to suppress a decrease in instruction execution efficiency and a decrease in processing performance.

[0055] Furthermore, when the mask register PR specified by the subsequent instruction is set by the ptrue instruction, it is possible to omit reading the data from the destination register FPR of the preceding instruction having data dependency and the mask value from the mask register PR1. Because it is possible to omit the read operation of the register FPR and the read operation of the mask register PR1, it is possible to reduce the power consumption of the vector operation processor 100.

[0056] Figure 6 shows an example of a vector operation processor according to another embodiment. Detailed descriptions of elements and functions similar to those described in Figures 1 to 5 may be omitted. The vector operation processor 110 shown in Figure 6 includes an instruction fetch address generator 10, a branch prediction mechanism 12, a primary instruction cache 14, a secondary cache 16, an instruction buffer 18, an instruction decoder 20, a register renaming unit 22, and a dependency reset unit 24.

[0057] The vector processor 110 also has a reservation station RS, a commit control unit 36, and a program counter 38. Hereinafter, the commit control unit 36 ​​is also referred to as a CSE (Commit Stack Entry) 36. The reservation station RS has an RSA (Reservation Station for Address generation) 26, an RSE (Reservation Station for Execution) 28, an RSF (Reservation Station for Floating point) 30, an RSP (Reservation Station for Predicate) 32, and an RSBR (Reservation Station for Branch) 34.

[0058] Hereinafter, when there is no need to distinguish between the RSA 26, RSE 28, RSF 30, RSP 32, and RSBR 34, they will also be referred to as the reservation station RS. The RSF 30 is an example of a scheduler that holds instruction execution information for each instruction and sequentially outputs instruction execution information for instructions whose data dependency has been resolved based on the dependency information included in the held instruction execution information.

[0059] Furthermore, the vector calculation processor 110 has an operand address generator 40, a first-level data cache 42, a fixed-point calculation unit 44, a floating-point calculation unit 46, a mask calculation unit 48, a fixed-point register 50, a floating-point register 52, and a mask register 54. Note that the configuration of the vector calculation processor 110 is not limited to the example shown in Fig. 6. The following describes the case where the vector calculation processor 110 executes a vector calculation.

[0060] The instruction fetch address generator 10 generates a fetch address of the next instruction based on the value of the program counter 38, the prediction result by the branch prediction mechanism 12, or the address included in the instruction refetch request from the RSBR 34. The instruction fetch address generator 10 outputs the generated fetch address of the next instruction to the primary instruction cache 14, and fetches the instruction from the primary instruction cache 14.

[0061] The branch prediction mechanism 12 predicts whether or not a branch due to a conditional branch instruction will be taken, based on the address generated by the instruction fetch address generator 10. If the branch prediction mechanism 12 predicts a branch (taken), it outputs a branch destination address (target address) to the instruction fetch address generator 10.

[0062] The primary instruction cache 14 retrieves an instruction from an area indicated by an address from the instruction fetch address generator 10, and outputs the retrieved instruction to the instruction buffer 18. The instructions held in the primary instruction cache 14 include an arithmetic instruction that performs an operation using the fixed-point arithmetic unit 44 or the floating-point arithmetic unit 46, an instruction that updates the mask register 54, a memory access instruction, or a branch instruction. If the primary instruction cache 14 does not hold an instruction for the area indicated by the address specified in the instruction, it outputs an access request to the secondary cache 16 and retrieves the instruction from the secondary cache 16.

[0063] The secondary cache 16 retrieves an instruction from the area indicated by the address included in the access request and outputs the retrieved instruction to the primary instruction cache 14. If the secondary cache 16 does not hold an instruction from the area indicated by the address included in the access request, it outputs an access request to the main memory 120 and retrieves the instruction from the main memory 120. For example, the main memory 120 is included in a semiconductor chip separate from the semiconductor chip including the vector calculation processor 110. Note that the secondary cache 16 may hold not only instructions but also data.

[0064] The instruction buffer 18 holds, for example, a plurality of instructions output from the primary instruction cache 14 in parallel, and outputs the held instructions in parallel to the instruction decoder 20. The instruction decoder 20 has, for example, a plurality of decode slots that decode, in parallel, a plurality of instructions output from the instruction buffer 18. Each decode slot determines a reservation station RS (RSA26, RSE28, RSF30, RSP32, or RSBR34) corresponding to the fixed-point arithmetic unit 44, floating-point arithmetic unit 46, mask arithmetic unit 48, etc. that executes each instruction. Each decode slot adds information indicating the reservation station RS to which the instruction is to be output, etc., to the instruction execution information and outputs the information to the register renaming unit 22.

[0065] The instruction decoder 20 also assigns instruction identifiers to instructions according to the order of the instructions written in the program to be executed by the vector operation processor 110, and outputs the assigned instruction identifiers together with the decoded instructions (decoded results) to the CSE 36. The instruction buffer 18 and the instruction decoder 20 process multiple instructions in parallel (in order) without changing the order of the instructions written in the program.

[0066] The register renaming unit 22 has a renaming map that converts logical register numbers specified by instruction operands into physical register numbers, and a free list that indicates available physical registers, corresponding to the fixed-point registers 50, the floating-point registers 52, and the mask register 54. By converting the logical register numbers specified by instruction operands into physical register numbers, out-of-order execution by the reservation station RS becomes possible.

[0067] The register renaming unit 22 adds a physical register number to the instruction execution information and outputs the instruction execution information to the reservation station RS via the dependency reset unit 24. The instruction execution information output from the instruction decoder 20 includes information indicating to which RSA 26, RSE 28, RSF 30, RSP 32, or RSBR 34 the instruction execution information should be output. An example of the register renaming unit 22 is shown in FIG. 7.

[0068] 6, the vector processor 110 employs a physical register map method that converts logical register numbers into physical register numbers using the register renaming unit 22. However, even if the update buffer method is employed, it is possible to realize the same operations as those in FIGS. 7 to 10, and it is possible to suppress a decrease in processing performance when the set all instruction ptrue, which will be described later, is executed.

[0069] The register renaming unit 22 is included in the register management facility RGMF. The register management facility RGMF generates a read signal (reg_f shown in FIG. 9) that instructs reading of data (merging source) already stored in the destination register based on the instruction execution information from the instruction decoder 20. The register management facility RGMF also generates a read signal (reg_p shown in FIG. 9) that instructs reading of a mask value from the mask register 54 based on the instruction execution information from the instruction decoder 20.

[0070] For example, if the instruction decoded by the instruction decoder 20 is a memory access instruction (load instruction or store instruction), the instruction is output to the RSA 26 via the dependency reset unit 24. If the instruction decoded by the instruction decoder 20 is a fixed-point number arithmetic instruction, the instruction is output to the RSE 28 via the dependency reset unit 24. If the instruction decoded by the instruction decoder 20 is a floating-point number arithmetic instruction, the instruction is output to the RSF 30 via the dependency reset unit 24. If the instruction decoded by the instruction decoder 20 is an access instruction (load instruction or store instruction) for the mask register 54, the instruction is output to the RSP 32 via the dependency reset unit 24. If the instruction decoded by the instruction decoder 20 is a branch instruction, the instruction is output to the RSBR 34 via the dependency reset unit 24.

[0071] The dependency reset unit 24 transfers instruction execution information such as the addition instruction ADD, subtraction instruction SUB, or multiplication instruction MUL received from the register renaming unit 22 to the reservation station RS. For example, suppose that the all-set instruction ptrue is executed on the mask register 54 used in the subsequent instruction, and there is a RAW data dependency in the destination register between the subsequent instruction and the preceding instruction. In this case, the dependency reset unit 24 resets, for example, the dependency information for the destination register and transfers it to the reservation station RS. For example, the preceding instruction is the SUB instruction in the instruction sequence shown in FIG. 1, and the subsequent instruction is the ADD instruction shown in FIG. 1. An example of the circuit configuration of the dependency reset unit 24 is shown in FIG. 9.

[0072] The RSA 26 holds memory access instructions received sequentially from the instruction decoder 20 and outputs the held memory access instructions to the operand address generator 40 in the order in which they can be executed (out of order). The operand address generator 40 generates an address based on the memory access instruction received from the RSA 26 and outputs the generated address to the primary data cache 42. Note that although the vector calculation processor 110 in FIG. 6 has multiple operand address generators 40, the number of operand address generators 40 may be one.

[0073] For example, when a load instruction is executed, the primary data cache 42 retrieves data held in an area indicated by an address from the operand address generator 40. The primary data cache 42 outputs the retrieved data to the fixed-point register 50, the floating-point register 52, or the mask register 54. Similar to the primary instruction cache 14, if the primary data cache 42 does not hold data in the area indicated by the address, it outputs an access request to the secondary cache 16 and retrieves the data from the secondary cache 16.

[0074] The RSE 28 holds fixed-point arithmetic instructions received sequentially from the instruction decoder 20 and outputs the held arithmetic instructions to the fixed-point arithmetic unit 44 in executable order (out of order). The RSF 30 holds floating-point arithmetic instructions received sequentially from the instruction decoder 20 and outputs the held arithmetic instructions to the floating-point arithmetic unit 46 in executable order (out of order). The RSP 32 holds access instructions for the mask register 54 received sequentially from the instruction decoder 20 and outputs the held access instructions to the mask arithmetic unit 48 in executable order (out of order).

[0075] The RSBR 34 holds branch instructions received sequentially from the instruction decoder 20 until it determines whether the branch is taken or not and outputs a completion report. The RSBR 34 performs completion processing of the branch instructions in order, notifies the CSE 36 of a completion signal, and causes the CSE 36 to commit the branch instruction. If the RSBR 34 determines that the branch prediction is incorrect, it outputs an instruction refetch request to the instruction fetch address generator 10 and the branch prediction mechanism 12.

[0076] The CSE 36 has a queue that stores instructions received via the register renaming unit 22 in the order written in the program, and a completion processing unit that performs completion processing of the instructions. The completion processing unit performs completion processing of the instructions in order in the order written in the program, based on the completion reports of the instructions executed in each reservation station RS and queue information. In the completion processing, the completion processing unit commits (terminates) the instruction corresponding to the completion report from among the instructions stored in the queue of the CSE 36 waiting for the completion report, and updates the resources.

[0077] Based on an instruction from the CSE 36, the program counter 38 updates the memory address indicating the storage location of the instruction, and outputs the updated memory address to the instruction fetch address generator 10 as the program counter PC.

[0078] The fixed-point arithmetic unit 44 obtains fixed-point data to be used for the operation from the fixed-point register 50 and stores the operation result in the fixed-point register 50. The vector operation processor 110 may have multiple fixed-point arithmetic units 44 in order to execute, in parallel, fixed-point operation instructions decoded in parallel by the instruction decoder 20.

[0079] The floating-point arithmetic unit 46 obtains floating-point number data to be used in the operation from the floating-point register 52 and stores the operation result in the floating-point register 52. The floating-point arithmetic unit 46 may include an arithmetic unit that executes multiply-accumulate operations, integer operations, logical operations, etc. The vector operation processor 110 may also have multiple floating-point arithmetic units 46 in order to execute floating-point number operation instructions decoded in parallel by the instruction decoder 20 in parallel.

[0080] The mask calculator 48 obtains a mask value from the mask register 54 and stores the mask value updated by calculation in the mask register 54. When the mask calculator 48 receives instruction execution information of the all-set instruction ptrue from the RSP 32, it sets all mask values ​​in the mask register 54 to "1." The vector calculation processor 110 may have multiple mask calculators 48.

[0081] The fixed-point register 50 has a plurality of entries that hold data used in the calculations executed by the fixed-point arithmetic unit 44 and the results of the calculations executed by the fixed-point arithmetic unit 44. Hereinafter, the plurality of entries of the fixed-point register 50 will also be referred to as the fixed-point register 50.

[0082] The floating-point register 52 has a plurality of entries that hold data used in the calculations executed by the floating-point arithmetic unit 46 and the results of the calculations executed by the floating-point arithmetic unit 46. Hereinafter, the plurality of entries of the floating-point register 52 will also be referred to as the floating-point register 52.

[0083] The mask register 54 has a plurality of entries in which a mask value of "0" or "1" is stored for each element of a vector. Hereinafter, the plurality of entries of the mask register 54 will also be referred to as a mask register PR.

[0084] 7 to 10 below will explain an example of executing a floating-point data operation instruction using the floating-point operation unit 46, floating-point register 52, floating-point mask operation unit 48, and floating-point mask register 54. FIGS. 7 to 10 show an example of an operation execution method of the vector operation processor 110. Note that FIGS. 7 to 10 can also be applied to the execution of a fixed-point data operation instruction. When executing a fixed-point data operation instruction, the fixed-point operation unit 44, fixed-point register 50, fixed-point mask operation unit 48, and fixed-point mask register 54 are used.

[0085] 7 shows an example of the register renaming unit 22 of FIG. 6. The register renaming unit 22 has a renaming map RNMAP(FPR) and a free list FRLIST(FPR) for floating-point registers FPR. The register renaming unit 22 also has a renaming map RNMAP(PR) and a free list FRLIST(PR) for mask registers PR. Although not shown, the register renaming unit 22 may have a renaming map and free list for fixed-point registers, and a renaming map and free list corresponding to the fixed-point mask register 54.

[0086] The renaming map RNMAP (FPR) has 32 entries that can store physical register numbers PRN and dependency flags RI (Read Interlock) that are set to "1" when there is a RAW data dependency. The 32 entries correspond to the logical register numbers LRN of the 32 logical registers that can be specified by operands of floating-point instructions. The renaming map RNMAP (FPR) is an example of a first renaming map. The 32 entries are an example of a first entry, and the dependency flag RI is an example of dependency information.

[0087] The free list FRLIST(FPR) has 96 entries that store the physical register numbers PRN of free floating-point registers FPR that are not stored in the renaming map RNMAP(FPR). This allows the physical register numbers PRN indicating all 128 floating-point registers FPR to be stored in either the renaming map RNMAP(FPR) or the free list FRLIST(FPR). The instruction decoder 20 can recognize the physical register number PRN of the floating-point register FPR that corresponds to the logical register number LRN specified in the operand of the subsequent instruction by accessing the renaming map RNMAP(FPR) using the logical register number LRN.

[0088] The register renaming unit 22 sequentially retrieves physical register numbers PRN from the free list FRLIST(FPR) in the D cycle of the pipeline that executes an instruction that includes a floating-point register FPR as an operand. The register renaming unit 22 stores the physical register numbers PRN retrieved from the free list FRLIST(FPR) in the renaming map RNMAP(FPR).

[0089] The old physical register numbers PRN held in the renaming map RNMAP(FPR) before the new physical register numbers PRN are stored in the entry in the free list FRLIST(FPR) from which the new physical register numbers PRN were extracted. This makes it possible to make 128 physical floating-point registers FPR available for use by 32 logical register numbers LRN that can be specified by instruction operands.

[0090] The renaming map RNMAP(PR) has 16 entries that can store physical register numbers PRN, dependency flags RI, and all active flags ALLACT that are set to "1" when the set all instruction ptrue is executed. The 16 entries correspond to the logical register numbers LRN of the 16 mask registers PR that can be specified by the operand of an instruction that updates the mask value. The renaming map RNMAP(PR) is an example of a second renaming map. The 16 entries are an example of second entries.

[0091] The free list FRLIST(PR) has 48 entries that store the physical register numbers PRN of free mask registers PR that are not stored in the renaming map RNMAP(PR). This allows the physical register numbers PRN indicating all 64 mask registers PR to be stored in either the renaming map RNMAP(PR) or the free list FRLIST(PR).

[0092] The register renaming unit 22 sequentially retrieves physical register numbers PRN from the free list FRLIST(PR) in the D cycle of the pipeline that executes an instruction that includes a mask register PR as an operand. The register renaming unit 22 stores the physical register numbers PRN retrieved from the free list FRLIST(PR) in the renaming map RNMAP(PR).

[0093] The old physical register number PRN held in the renaming map RNMAP(PR) before the new physical register number PRN is stored is stored in the entry in the free list FRLIST(PR) from which the new physical register number PRN was extracted. This makes it possible to make 64 physical mask registers PR available for use by 16 logical register numbers LRN that can be specified by instruction operands.

[0094] Thus, in the D cycle of the pipeline, the instruction decoder 20 decodes the instruction, and the register renaming unit 22 converts the logical register number LRN into the physical register number PRN. The instruction decoder 20 reads out information to be used in the decoded instruction from the information held in the renaming maps RNMAP(FPR) and RNMAP(PR) in the D cycle. The information read by the instruction decoder 20 becomes available in the DT cycle.

[0095] Figure 8 shows an example of pipeline operation of the vector operation processor 110 of Figure 6. For example, the instruction sequence executed by the vector operation processor 110 is the same as the instruction sequence shown in Figure 1. The pipeline operation shown in Figure 8 shows operation focusing on instruction execution information input / output to / from the renaming maps RNMAP(PR) and RNMAP(FPR) by the ptrue instruction and the ADD instruction. A detailed description of operations similar to those in Figure 5 will be omitted.

[0096] In the D cycle of the ptrue instruction, the register renaming unit 22 stores the physical register number PRN, the dependency flag RI, and the all active flag ALLACT in the renaming map RNMAP(PR) in correspondence with the operand (logical register number LRN) of the ptrue instruction. The dependency flag RI and the all active flag ALLACT held in the renaming map RNMAP(PR) are output to the dependency reset unit 24 in correspondence with the physical register number PRN.

[0097] Next, in the DT cycle of the ptrue instruction, the instruction execution information held in the renaming map RNMAP(PR) is transferred to the RSP 32 together with the instruction execution information of the ptrue instruction generated by the instruction decoder 20. Although not shown in the figure, the information held in the renaming map RNMAP(PR) and the information generated by the register management facility RGMF are transferred to the RSP 32 via the dependency reset unit 24.

[0098] In the D cycle of the ADD instruction, the register renaming unit 22 stores the physical register number PRN in the renaming map RNMAP(FPR) corresponding to each operand (logical register number LRN) of the ADD instruction. The register renaming unit 22 also updates the dependency flag RI of the entry in the renaming map RNMAP(FPR) that stores the physical register number PRN.

[0099] The dependency flag RI held in the renaming map RNMAP(FPR) is associated with the physical register number PRN and output to the dependency reset unit 24. Note that in the D cycle of the ADD instruction, it is known from the all active flag ALLACT output from the renaming map RNMAP(PR) that a ptrue instruction will be issued to the mask register PR1 specified in the ADD instruction.

[0100] Next, in the P cycle of the ptrue instruction, the RSP 32 determines to issue the ptrue instruction and issues the ptrue instruction to the mask calculator 48. Then, the mask calculator 48 executes the ptrue instruction.

[0101] In the DT cycle of the ADD instruction, the instruction execution information of the ADD instruction is transferred to the RSP 32. A part of the instruction execution information transferred to the RSF 30 is transferred to the RSF 30 via the dependency reset unit 24.

[0102] For example, the dependency flag RI and all active flag ALLACT held in the renaming maps RNMAP(FPR) and RNMAP(PR) are transferred to the RSF 30 via the dependency reset unit 24. Also, information indicating the merging source generated by the register management facility RGMF is transferred to the RSF 30 via the dependency reset unit 24. As a result, as will be described with reference to FIG. 9, instruction execution information in a set state indicating data dependency between the destination register FPR0 ​​specified by the SUB instruction and the mask register PR1 specified by the ptrue instruction, which are the merging sources of the ADD instruction, is reset.

[0103] Next, in the P cycle of the ADD instruction, the RSF 30 determines to issue the ADD instruction and issues the ADD instruction to the floating-point arithmetic unit 46. The P cycle of the ADD instruction is executed in the cycle following the DT cycle of the ADD instruction. The ADD instruction is then executed by the floating-point arithmetic unit 46.

[0104] Fig. 9 shows an example of the circuit and operation of the dependency reset unit 24 of Fig. 6. Fig. 9 shows the logic circuit of the dependency reset unit 24 used when an ADD instruction included in the instruction sequence is executed, and the states of signals input to and output from the dependency reset unit 24.

[0105] The instruction sequence shown in Figure 9 is the same as the instruction sequence shown in Figure 1. In the ADD instruction, the mask register PR1 is an example of a first source operand, and the floating-point register FPR0 ​​is an example of a destination operand. The renaming map RNMAP(PR) corresponding to the mask register 54 is updated in the D cycle (time T1) of the ptrue instruction.

[0106] For example, the dependency reset unit 24 has 11 AND circuits AND1 to AND11. The floating-point registers FPR1, FPR2, and FPR0 ​​and the mask register PR1, which are source operands for which the presence or absence of data dependency is determined in the ADD instruction, are assigned register numbers R1, R2, R3, and R4 used in the pipeline, respectively.

[0107] 9 shows the state of the renaming map RNMAP(PR) when the instruction decoder 20 updates the renaming map RNMAP(PR) after decoding the ptrue instruction at time T1. For example, decoding the ptrue instruction sets the dependency flag RI and all active flag ALLACT of the entry in the mask register PR1 of the renaming map RNMAP(PR) to "1." Hereinafter, the dependency flag RI of the mask register PR1 assigned to register number R4 will also be referred to as the dependency flag R4_RI.

[0108] 9 shows the state of the renaming map RNMAP(FPR) when the instruction decoder 20 updates the renaming map RNMAP(FPR) after decoding the ADD instruction at time T2. For example, decoding the ADD instruction sets the dependency flag RI included in the entry for floating-point register FPR0 ​​in the renaming map RNMAP(FPR) to "1." Also, decoding the ADD instruction updates the dependency flags RI included in the entries for floating-point registers FPR1 and FPR2 in the renaming map RNMAP(FPR) to "0" and "1," respectively. Hereinafter, the dependency flags RI of floating-point registers FPR0, FPR1, and FPR2 assigned to register numbers R3, R1, and R2, respectively, will also be referred to as dependency flags R3_RI, R1_RI, and R2_RI, respectively.

[0109] In the dependency reset unit 24, the circles shown at one input of the AND circuits AND1, AND2, AND4, AND5, AND7, AND8, AND10, and AND11 that receive a signal including the logic of the all active flag ALLACT indicate that the logic is inverted.

[0110] The all active flag ALLACT is input to one input of the AND circuits AND3, AND6, and AND9, and one of the merging source signals R3_m_s, R1_m_s, and R2_m_s is input to the other input. The merging source signals R3_m_s, R1_m_s, and R2_m_s are set to "1" by the instruction decoder 20 when the corresponding floating-point register FPR0, FPR1, or FPR2 is a merging source (destination register). The merging source signals R3_m_s, R1_m_s, and R2_m_s are reset to "0" by the instruction decoder 20 when the corresponding floating-point register FPR0, FPR1, or FPR2 is not a merging source.

[0111] In the example shown in FIG. 9, since the floating-point register FPR0 ​​is the merging source, the merging source signal R3_m_s is set to "1", and the other merging source signals R1_m_s and R2_m_s are reset to "0". Therefore, the AND circuit AND3 outputs "1", and the AND circuits AND6 and AND9 output "0". The instruction decoder 20 can determine whether the merging source is R1, R2, or R3.

[0112] The read signals R4_reg_p, R3_reg_f, R1_reg_f, and R2_reg_f are generated by the register management facility RGMF. The read signal R4_reg_p is an example of a second read signal, and the read signal R3_reg_f is an example of a first read signal. The read signals R1_reg_f and R2_reg_f are examples of a third read signal.

[0113] The read signal R4_reg_p is set to "1" when a mask value is read from the corresponding mask register PR1, and is reset to "0" when no mask value is read from the corresponding mask register PR1. The read signals R3_reg_f, R1_reg_f, and R2_reg_f are set to "1" when data is read from the corresponding floating-point register (source operand), and are reset to "0" when no data is read from the corresponding floating-point register (source operand).

[0114] In the example shown in Figure 9, the read signal R4_reg_p is set to "1" because it is specified by the ptrue instruction and corresponds to the mask register PR1 (merging source) used in the ADD instruction. The read signal R3_reg_f is set to "1" because it corresponds to the merging source in which the operation result of the SUB instruction is stored. The read signals R1_reg_f and R2_reg_f correspond to the source operands of the ADD instruction and are set to "1".

[0115] The AND circuit AND1 inverts the "1" of the all active flag ALLACT, resets the "1" of the dependency flag R4_RI to "0", and outputs it to RSF30. The AND circuit AND1 is an example of a first reset circuit that resets the dependency flag R4_RI held in the entry of the renaming map RNMAP(PR) in which all set information is set, and transfers it to RSF30.

[0116] The AND circuit AND2 inverts the "1" of the all active flag ALLACT, resets the "1" of the read signal R4_reg_p to "0", and outputs it to RSF 30. The AND circuit AND2 is an example of a third reset circuit that resets the read signal R4_reg_p and transfers it to RSF 30 when the source operand indicates the mask register specified by the ptrue instruction.

[0117] The AND circuit AND4 inverts the "1" from the AND circuit AND3, resets the "1" of the dependency flag R3_RI to "0", and outputs it to RSF 30. The AND circuit AND4 is an example of a first reset circuit that resets the dependency information R3_RI held in an entry of the renaming map RNMAP(FPR) corresponding to the destination operand FPR0 ​​specified in the subsequent instruction ADD that uses the mask register PR1 specified in the ptrue instruction as a source operand, and transfers it to RSF 30.

[0118] The AND circuit AND5 inverts the "1" from the AND circuit AND3, resets the "1" of the read signal R3_reg_f to "0", and outputs it to RSF 30. The AND circuit AND5 is an example of a second reset circuit that resets the read signal R3_reg_f and transfers it to RSF 30 when the source operand of the ADD instruction indicates the mask register PR1 specified by the ptrue instruction.

[0119] The AND circuit AND7 inverts the "0" from the AND circuit AND6 and outputs the "0" of the dependency flag R1_RI as is to the RSF 30. The AND circuit AND8 inverts the "0" from the AND circuit AND6 and outputs the "1" of the read signal R1_reg_f as is to the RSF 30.

[0120] The AND circuit AND10 inverts the "0" from the AND circuit AND9 and outputs the "1" of the dependency flag R2_RI as is to the RSF 30. The AND circuit AND11 inverts the "0" from the AND circuit AND9 and outputs the "1" of the read signal R2_reg_f as is to the RSF 30.

[0121] The AND circuits AND6, AND7, AND9, and AND10 are examples of a first suppression circuit that suppresses the resetting of the dependency flags R1_RI and R2_RI stored in the renaming map RNMAP(FPR) corresponding to operands of the floating-point register FPR specified in a subsequent instruction that are not merging sources, and transfers them to RSF30.

[0122] The AND circuits AND6, AND8, AND9, and AND11 are examples of a second suppression circuit that suppresses the resetting of read signals R1_reg_f and R2_reg_f, which instruct the reading of data from operands that are not merging sources, excluding the mask register PR specified in the subsequent instruction, and transfers them to RSF30.

[0123] The dependency flag R2_RI is set to "1" to explain the operation of the AND circuit AND11. In reality, when the RSF 30 can issue the ADD instruction to the floating-point arithmetic unit 46 at time T4, the dependency flag R2_RI is reset to "0."

[0124] As described above, when the ADD instruction is executed, the dependency reset unit 24 resets the dependency flags R4_RI, R3_RI and the read signals R4_reg_p, R3_reg_f corresponding to the merging sources and outputs them to the RSF 30. This allows the RSF 30 to issue the ADD instruction to the floating-point arithmetic unit 46 before the operation result of the SUB instruction is stored in the register FPR0, similar to the operation of the vector operation processor 100 shown in FIG.

[0125] Furthermore, the RSF 30 can issue an ADD instruction to the floating-point arithmetic unit 46 before all mask values ​​in the mask register PR1 are set to "1" by the ptrue instruction. As a result, it is possible to prevent delays in the execution of the addition process after the ADD instruction is decoded, and it is possible to prevent a decrease in processing performance.

[0126] Furthermore, when the ADD instruction is executed, it is possible to omit reading data from the floating-point register FPR0 ​​that holds the calculation result of the SUB instruction and reading the mask value from the mask register PR1. By omitting the read operation from the register FPR0 ​​and the read operation from the mask register PR1, it is possible to reduce the power consumption of the vector operation processor 110.

[0127] Fig. 10 shows an example of a process in which the dependency reset unit 24 resets the dependency flag RI in the D cycle (T2) of the add instruction ADD in Fig. 9. For simplicity of the diagram, the number of parallel instructions is set to "1", but the number of parallel instructions may be increased using a superscalar processor technique.

[0128] The renaming map RNMAP(PR) shown at time T2 shows the state set by an instruction that updates the mask register 54 decoded before time T1. In the renaming map RNMAP(PR), the physical register number PRN, the dependency flag RI, and the all active flag ALLACT shown in the entry for the mask register PR1 are set to "1" by the decoding of the ptrue instruction at time T1.

[0129] The renaming map RNMAP(FPR) shown at time T2, like the renaming map RNMAP(PR), shows the state set by the instructions decoded before time T1. For example, in the renaming map RNMAP(FPR), the dependency flags RI of the floating-point registers FPR0, FPR1, and FPR2 are updated to "1", "0", and "1".

[0130] At time T2, the instruction decoder 20 decodes the ADD instruction. The instruction decoder 20 reads the physical register number PRN, the dependency flag RI, and the all active flag ALLACT stored in the entry (PR1) of the renaming map RNMAP (PR) corresponding to the source operand (PR1) of the ADD instruction.

[0131] Furthermore, the instruction decoder 20 reads out the physical register numbers PRN and the dependency flags RI stored in the entries (FPR0-FPR2) of the renaming map RNMAP (FPR) corresponding to the merging source (FPR0) and source operands (FPR1, FPR2) of the ADD instruction. Note that, as described in FIG. 9, the dependency flag RI (R2_RI in FIG. 9) of the register number R2 corresponding to the floating-point register FPR2 may actually be reset to "0."

[0132] Although not shown, the instruction decoder 20 sets the read signals R1_reg_f, R2_reg_f, R3_reg_f, and R4_reg_p shown in Fig. 9 to "1." Then, the instruction decoder 20 outputs the information read from the renaming maps RNMAP(PR) and RNMAP(FPR) and the read signals R1_reg_f, R2_reg_f, R3_reg_f, and R4_reg_p to the dependency reset unit 24.

[0133] The dependency reset unit 24 converts the logical values ​​of the instruction execution information held in the renaming maps RNMAP(PR) and RNMAP(FPR) received from the instruction decoder 20. As shown in Fig. 9, the dependency reset unit 24 resets the dependency flags R4_RI and R3_RI in the set state to "0" and resets the read signals R3_reg_f and R4_reg_p in the set state to "0". The instruction execution information converted by the dependency reset unit 24 is output to the RSF 30 at time T3.

[0134] At time T3, the register renaming unit 22 refers to the free list FRLIST(FPR) in FIG. 7 and changes the physical register number PRN of the floating-point register FPR0 ​​used in the ADD instruction to "32". This determines the entry of the floating-point register 52 that stores the calculation result of the ADD instruction. The operations from time T4 onwards are similar to those of the scheduler 103, vector operator 104, mask register PR and data register FPR of the vector processor 100 in FIG. 3.

[0135] For example, based on the dependency flag RI, the RSF 30 determines that there is no data dependency between the ADD instruction and the preceding SUB instruction, and between the ADD instruction and the ptrue instruction. As a result, the RSF 30 can execute the P cycle of the ADD instruction at time T4 and issue the ADD instruction to the floating-point arithmetic unit 46. Furthermore, because the read signals R3_reg_f and R4_reg_p are reset to "0," it is possible to omit read accesses to the floating-point register FPR0 ​​and the mask register PR1, thereby reducing power consumption.

[0136] As described above, the embodiments shown in Figures 6 to 10 can also achieve the same effects as the embodiments shown in Figures 1 to 5. For example, when the mask register PR used in a subsequent instruction is set by the ptrue instruction, the subsequent instruction can be executed without waiting for the execution of a preceding instruction having data dependency. Also, the subsequent instruction can be executed without reading the mask value from the mask register PR. As a result, it is possible to prevent a decrease in the efficiency of instruction execution of the vector calculation processor 110, and to prevent a decrease in processing performance.

[0137] Furthermore, when the mask register PR specified by the subsequent instruction is set by the ptrue instruction, it is possible to omit reading the data from the destination register FPR of the preceding instruction having data dependency and the mask value from the mask register PR1. Because it is possible to omit the read operation of the register FPR and the read operation of the mask register PR1, it is possible to reduce the power consumption of the vector operation processor 110.

[0138] Furthermore, in this embodiment, the AND circuits AND3, AND6, and AND9 of the dependency reset unit 24 generate a logical product of the all active flag ALLACT and each of the merging source signals R3_m_s, R1_m_s, and R2_m_s. This allows only the dependency flag RI corresponding to the floating-point register FPR that is a merging source to be reset. This also prevents changes in the logic of the dependency flag RI corresponding to the floating-point register FPR that is not a margin source. Furthermore, it also prevents changes in the logic of the read signals such as R1_reg_f corresponding to the floating-point register FPR that is not a margin source. As a result, malfunctions of the vector processor 110 caused by the dependency reset unit 24 can be prevented.

[0139] Fig. 11 shows an example of an information processing system including the vector operation processor shown in Fig. 1 or 6. For example, the information processing system shown in Fig. 1 is a server 200 or the like. The server 200 has a plurality of vector operation processors 210, a plurality of main memories 220, and an interconnect control unit 230. The vector operation processor 210 corresponds to the vector operation processor 100 in Fig. 1 or the vector operation processor 110 in Fig. 6. The main memory 220 corresponds to the main memory 120 in Fig. 6.

[0140] For example, each vector operation processor 210 is a processor such as a CPU (Central Processing Unit), and is connected to an interconnect control unit 230. Each main memory 220 is connected to a corresponding vector operation processor 210. The interconnect control unit 230 is connected to an external device such as a hard disk drive or a communication device, and performs input / output control for the external device.

[0141] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims encompass the features and advantages of the above-described embodiments without departing from the spirit and scope of the claims. Furthermore, any improvements and modifications will be readily apparent to those skilled in the art. Therefore, it is not intended that the scope of the inventive embodiments be limited to the above-described embodiments, and appropriate improvements and equivalents within the scope of the disclosed embodiments may be utilized. [Explanation of symbols]

[0142] 10 Instruction Fetch Address Generator 12 Branch Prediction Mechanism 14 Primary instruction cache 16 Secondary cache 18 Instruction Buffer 20 Instruction Decoder 22 Register Renaming Section 24 Dependency Reset Unit 36 Commit control section 38 Program Counter 40 Operand Address Generator 42 Level 1 Data Cache 44 Fixed-point arithmetic unit 46 Floating-point arithmetic unit 48 Mask Calculator 50 fixed-point registers 52 floating-point registers 54 Mask Register 100 Vector Calculation Processors 101 Instruction Decoder 102 Dependency Reset Unit 103 Scheduler 104 Vector Operator 105 Register File 110 Vector Calculation Processor 120 main memory 200 servers 210 Vector Calculation Processor 220 main memory 230 Interconnect Control Section ADD Addition instruction AND1-AND11 AND circuit DT Decode Transfer Cycle FPR Floating Point Register FRLIST Free List LRN Logical Register Number MUL multiplication instruction P Priority Cycle PR Mask register PRN Physical Register Number PT Priority Transfer Cycle ptrue full set of commands R1-R4 register number R1_m_s, R2_m_s, R3_m_s Margining source signals R1_reg_f, R2_reg_f, R3_reg_f read signals R4_reg_p read signal R1_RI, R2_RI, R3_RI, R4_RI, RI dependent flag R2 register number RGMF Register Management Facility RNMAP Renaming Map RS, RSA, RSF, RSP Reservation Station SUB Subtraction instruction X run cycle

Claims

1. A vector operation processor capable of executing vector operations, a mask register for storing a mask value set for each element of a vector when the operation result for each element is stored in a data register; an instruction decoder that decodes an instruction to generate instruction execution information, and when a subsequent instruction having data dependency with a preceding instruction is decoded, sets dependency information included in the instruction execution information, and when a full set instruction that sets all the mask values ​​of the mask register is decoded, sets all the set information included in the instruction execution information; a scheduler that stores the instruction execution information for each of the instructions and sequentially outputs the instruction execution information of the instructions whose data dependency has been resolved based on the dependency information included in the stored instruction execution information; a vector calculator that executes a vector operation for each of the elements based on the instruction execution information output from the scheduler, and stores in the data register a result of the operation on the element corresponding to the mask value in a set state held in the mask register; a dependency reset unit that resets the dependency information corresponding to the destination operand of the subsequent instruction and the mask register, which are transferred from the instruction decoder to the scheduler, when all the set information is set corresponding to the mask register specified by the subsequent instruction; A vector operation processor having:

2. a first renaming map having a plurality of first entries corresponding to logical register numbers of the data registers that can be specified by the instruction, each of the plurality of first entries being capable of holding a physical register number of the data register and the dependency information; a second renaming map having a plurality of second entries corresponding to logical register numbers of the mask register that can be specified by the instruction, each of the plurality of second entries being capable of holding a physical register number of the mask register, the dependency information, and the full set information; The dependency reset unit has a first reset circuit that resets the dependency information held in the first entry corresponding to the destination operand designated in the subsequent instruction that uses the mask register designated in the all-set instruction as a first source operand, and the dependency information held in the second entry in which the all-set information is set, and transfers the reset information to the scheduler. The vector operation processor according to claim 1 .

3. the instruction decoder sets a first read signal instructing reading of data from a merging source corresponding to the destination operand of the subsequent instruction when decoding the subsequent instruction; The dependency reset unit has a second reset circuit that resets the first read signal and transfers it to the scheduler when the first source operand indicates the mask register specified by the set all instruction. The vector operation processor according to claim 2 .

4. the instruction decoder sets a second read signal instructing reading of the mask value from the first source operand when decoding the subsequent instruction; The dependency reset unit has a third reset circuit that resets the second read signal and transfers it to the scheduler when the first source operand indicates the mask register specified by the set all instruction.

4. The vector operation processor according to claim 2 or 3.

5. The dependency reset unit includes a first suppression circuit that suppresses resetting of the dependency information held in the first renaming map corresponding to source operands other than the first source operand specified by the subsequent instruction and transfers the dependency information to the scheduler when the first source operand indicates the mask register specified by the all-set instruction.

4. The vector operation processor according to claim 2 or 3.

6. the instruction decoder sets a third read signal instructing reading of data from the data register indicated by a source operand other than the first source operand when decoding the subsequent instruction; The dependency reset unit has a second inhibition circuit that inhibits resetting of the third read signal and transfers it to the scheduler when the first source operand indicates the mask register specified by the set all instruction.

4. The vector operation processor according to claim 2 or 3.

7. 1. A method for executing a vector operation processor that includes a mask register for storing a mask value set for each element of a vector when storing an operation result for each element of the vector in a data register, and that can execute vector operations, comprising: an instruction decoder of the vector operation processor decodes an instruction to generate instruction execution information, and when a subsequent instruction having data dependency with a preceding instruction is decoded, sets dependency information included in the instruction execution information, and when a full set instruction that sets all the mask values ​​of the mask register is decoded, sets all the set information included in the instruction execution information; a scheduler included in the vector processor holds the instruction execution information for each of the instructions, and sequentially outputs the instruction execution information of the instructions whose data dependency has been resolved based on the dependency information included in the held instruction execution information; a vector calculator included in the vector operation processor executes a vector operation for each of the elements based on the instruction execution information output from the scheduler, and stores in the data register a calculation result for the element corresponding to the mask value in a set state held in the mask register; A dependency reset unit included in the vector operation processor resets the dependency information corresponding to the destination operand of the subsequent instruction and the mask register, which are transferred from the instruction decoder to the scheduler, when all the set information is set corresponding to the mask register specified by the subsequent instruction. A method for performing operations on a vector processor.

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