Data corruption detection for an electronic device

Abstract

To provide an apparatus, a method and a program for realizing data corruption detection for an electronic device.SOLUTION: A method of detecting data corruption generates a first signature based on a first plurality of sets of signals communicated by a bus. Here, a first plurality of sets of signals are communicated by the bus in a first set of transactions. The method also generates a second signature based on a second plurality of sets of signals communicated by the bus. A second plurality of sets of signals are communicated by the bus in a second set of transactions. The method further compares the first signature and the second signature to determine whether a data corruption error has occurred.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates generally to the field of computing systems, and more particularly to data corruption detection for electronic devices. [Background technology]

[0002] Electronic device debugging generally focuses on identifying and resolving problems in the functionality of a component (e.g., an integrated circuit). Debugging can encompass design verification, simulation, and testing to find and improve problematic components. In some cases, engineers can use software-based debugging environments to monitor signals, inspect internal states, and trace the root cause of problems in the logic of an electronic device. [Brief explanation of the drawings]

[0003] [Figure 1] 1 illustrates a system with a data corruption detector and comparison logic for detecting data corruption at two different points on a bus, according to certain embodiments.

[0004] [Figure 2] 1 illustrates a system with a data corruption detector and comparison logic for detecting data corruption at a single point on a bus, according to certain embodiments.

[0005] [Figure 3] 1 illustrates a system with a data corruption detector for verifying first in first out (FIFO) correction operations, according to certain embodiments.

[0006] [Figure 4] 1 illustrates a data corruption detector in accordance with certain embodiments.

[0007] [Figure 5]1 illustrates a flow for generating a signature based on a bus transaction, according to certain embodiments.

[0008] [Figure 6] 1 illustrates a flow for detecting data corruption, according to certain embodiments.

[0009] [Figure 7] 1 illustrates a computing system in accordance with certain embodiments.

[0010] [Figure 8] 1 illustrates an exemplary electronic device that may include a microelectronic assembly, according to certain embodiments.

[0011] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION OF THE INVENTION

[0012] Over the years, the complexity of electronic devices has increased dramatically. As an example, today's flagship semiconductor processor products have transistor counts well over 10 billion. The complexity of electronic devices makes debugging errors within the devices an overwhelming task.

[0013] Data signals (e.g., containing data, address, or control information) may travel on communication buses between various logic blocks of an electronic device. Data corruption refers to any error in the data, address, control information (e.g., transaction ID), or other information transmitted on the bus. Errors may occur during the writing, reading, transmission, or processing of information. Errors may occur due to any of a variety of reasons, such as logic bugs, timing issues, unintended configurations, or circuit marginalities. Data corruption errors are difficult to debug because detection may be chronologically or physically distant from the source of the corruption.

[0014] 1 illustrates a system 100 having a data corruption detector 108 (e.g., 108A, 108B) and comparison logic 110 for detecting data corruption at two different locations 114, 116 of a bus 112, according to a particular embodiment. The data corruption detector 108 may enable a cost-effective solution for detecting data corruption in silicon debug. The system 100 generates and compares signatures based on a history of events (also referred to herein as transactions) on the bus at preselected locations to identify the location and time of data corruption.

[0015] In various embodiments, in addition to the signature generator, the data corruption detector 108 may also include an event counter that tracks the number of events used by the signature generator to generate the signature (e.g., the number of events on which the signature is based). The event counter may be useful to ensure that signatures being compared are based on the same number of events (and so the event counter may be used to detect instances of packet loss).

[0016] The comparison of the signatures and / or event counters may be performed at any suitable time, such as when the electronic device 101 is hung (e.g., not progressing as expected), when the electronic device 101 is halted (e.g., intentionally stopped, e.g., by freezing one or more clock signals), in response to a selected event (e.g., the electronic device 101 or a portion thereof entering a low power state, the detection of an error, an on-demand request to perform a comparison issued by debug software or other logic, etc.), or at regular or irregular intervals. Signatures may be compared at different locations on the bus (point-to-point comparison) or at the same location but on different runs (single-point comparison) (e.g., in a pass-versus-fail scenario). When an error due to a signature and / or event counter mismatch is detected, the error may be hooked to trigger a debug mechanism to enable the error to be further debugged. For example, detecting an error may trigger the collection of a predefined list of registers that can help triage and analyze the reason for the error; stopping the system and / or gating one or more clocks (e.g., by a micro-breakpoint controller) to allow dumping of array values ​​or shifting of flip-flop data using a scan mechanism; communicating the error to a debug fabric (e.g., Intel VISA) to send the error to a debug pin, stopping the system, or taking a trace; or sending a machine check exception.

[0017] Various embodiments of the present disclosure may provide one or more technical advantages, such as a simple and fast method for isolating, detecting, and debugging data corruption; a continuous health check to detect corruption during system (e.g., system on chip (SOC)) activity; detection of packet loss and / or transaction anomalies (thus providing advantages over per-transaction error detection mechanisms such as parity checks, cyclic redundancy checks, or error correction codes); error detection in bus fields including data, address, and / or control signals (e.g., source ID, destination ID, transaction ID, communication credit information, or other fields carried in a separate signal from the data or address); a higher detection rate compared to other correction mechanisms (e.g., while parity has a 50% error detection rate, various embodiments may enable a higher detection rate, e.g., greater than 90% or even greater than 95%).

[0018] Electronic device 101 includes logic block 102, which provides signals to logic block 104 for communication over first bus segment 112A of bus 112. Logic block 104 may provide signals to logic block 106 for communication over second bus segment 112B of bus 112. Logic block 102 may include any suitable circuitry for generating and / or providing signals to be communicated over bus 112. A set of signals (e.g., a signal set may refer to a group of signals on the bus at a particular moment in time) may be communicated over the bus in coordination with a clock signal. For example, a first set of signals may be communicated in a first transaction during a first cycle of the clock, a second set of signals may be communicated in a second transaction during a second cycle of the clock, and so on. In some embodiments, a cycle of the clock may refer to the period from one edge of the clock to a corresponding edge of the clock. For example, a cycle of the clock may refer to the period from a rising edge of the clock to the next rising edge of the clock or from a falling edge of the clock to the next falling edge of the clock. In another example, a cycle of a clock may refer to the period from the rising edge of the clock to the falling edge of the clock and / or from the falling edge of the clock to the rising edge of the clock (e.g., where a new transaction is sent each time the clock toggles).

[0019] At a first location 114 of the bus 112, various signal lines 118 of the bus are routed to the data corruption detector 108A. In various embodiments, the signal lines 118 may be a subset of the signal lines of the bus 112 or may be all of the signal lines of the bus 112. For example, the signal lines may include one or more data lines, one or more address lines, or one or more control lines (e.g., communicating a source ID, a destination ID, a transaction ID, communication credit information, or other suitable control information).

[0020] Logic block 104 may include any suitable circuitry for storing and / or manipulating signals on bus 112. For example, logic block 104 may include routing circuitry, arbitration circuitry, buffer circuitry, memory circuitry, or other suitable circuitry. For bus signals communicated on bus segment 112A and used to generate a signature by data corruption detector 108A, the same bus signals must be communicated on bus segment 112B (and in the same order if the signature generated by data corruption detector 108A depends on the order of the signals). Therefore, any changes made by logic block 104 to signals that will be used to generate signatures by data corruption detectors 108A and 108B must be inverted by logic block 104 so that the same values ​​of these signals are provided to the data corruption detectors. For example, if logic block 104 compressed and / or encrypted signals, logic block 104 may decompress and / or decrypt the signals. As another example, if logic block 104 performed protocol conversion on signals, it may also convert the signals back to the original protocol. As yet another example, if logic block 104 packetizes a signal, it may also depacketize the signal. In some cases, logic block 104 does not change the value and / or format of the signal (e.g., logic block 104 may simply store the signal in a first-in-first-out (FIFO) memory structure, etc.).

[0021] Data corruption detector 108A may receive input signals from location 114 of bus 112 via signal lines 118 and may generate signature 122 based thereon. For each valid set of input signals on signal lines 118, detector 108A updates a signature and an event counter (more information about what a valid set of input signals for a detector may consist of is provided later in connection with FIG. 4). In a similar manner, data corruption detector 108B may receive input signals from location 116 of bus 112 via signal lines 120 and may generate signature 124 based thereon. For each valid set of input signals on signal lines 120, detector 108B updates a signature and an event counter.

[0022] Data corruption detector 108 may include any suitable circuitry for generating signatures, such as an accumulator, a multiple input shift register (MISR), a linear feedback shift register (LFSR), other signature mechanisms, or a combination thereof. The signature generated by any of these signature generators is based on the entire history of a valid set of input signals. Accordingly, system 100 checks the integrity of the input signal sets so that signatures do not match if one set of signals is missed by one detector but not the other. Similarly, if the values ​​of the input signals in the input signal set provided to detector 108A differ from the corresponding input signals in the corresponding input signal set provided to detector 108B, the signatures will differ. In various embodiments (e.g., when a MISR or LFSR is used), the signature may also depend on the order of the set of input signals, while in other embodiments (e.g., when an accumulator is used), the signature does not depend on the order of the signal set (so that the signal set may be communicated in a different order on bus segment 112A than on bus segment 112B and still result in the same signature value for signatures 122 and 124).

[0023] At a point when the signature values ​​and / or event counter values ​​are expected to be the same (e.g., after the bus is quiesced to allow all transactions on bus segment 112A to propagate to location 116), signatures 122 and 124 and / or their respective event counter values ​​are compared by comparison logic 110 to determine whether they are equal (e.g., whether the value of each bit in the signature or event counter value matches the value of the corresponding bit in the signature or event counter value). If they are not equal, it is known that an error has occurred between location 114 and location 116. In some embodiments, the debugger then proceeds to perform low-level debugging on the focus area (e.g., logic block 104).

[0024] In the illustrated embodiment, memory 126A (e.g., registers or other memory elements) may be used to store signature 122 and / or associated event counters, while memory 126B may be used to store signature 124 and / or associated event counters. In some cases, a single memory including one or more registers or other memory elements may be used to store signatures and / or event counters from any number of data corruption detectors 108. In various embodiments, the memory used to store the signatures and / or event counters may be part of the data corruption detector 108 (e.g., integrated with or coupled to the signature generator and / or event counter of the detector 108). In other embodiments, the signatures (or event counters) may be compared in real time, such that they do not need to be read from a register or other memory prior to comparison, but rather the signatures (or event counters) may be provided directly to comparison logic by the signature generator.

[0025] The comparison logic includes any suitable logic for comparing the signature and / or event counter values ​​and determining whether they match. In this embodiment, the comparison logic 110 is shown as separate from and coupled to the electronic device (e.g., the comparison logic 110 may reside on a system running a debugger or some other computing system external to the electronic device 101), although in other embodiments, the comparison logic 110 may be included in the electronic device 101 itself. The comparison logic 110 may read the signature and / or event counter from memory at any suitable time and perform the comparison.

[0026] In various embodiments, there may be any number of data corruption detectors 108 coupled to various locations on one or more buses of an electronic device, and comparison logic 110 may be coupled to any number of these data corruption detectors 108 (or separate instances of comparison logic 110 may be coupled to a subset of these data corruption detectors).

[0027] During debugging, it is often desirable to compare data between different points to determine whether a transaction was corrupted between the two points. This can be done between two interfaces (e.g., a sender and a receiver) on the same interconnect fabric or within a sensitive area, such as a clock or power domain crossing. To perform a point-to-point comparison, electronic device 101 (or a portion thereof) can pause at a desired point to allow any pending transactions to complete. Therefore, the same number of transactions (e.g., as indicated by an event counter) and the same data and / or other information (e.g., as indicated by a signature) are expected to be transferred between these two points. A mismatch between the signatures indicates that data corruption occurred somewhere between the two points. For example, if logic block 104 is a FIFO, the signature of data corruption detector 108A on the write side of the FIFO should equal the signature of data corruption detector 108B on the read side at any point in time, once the FIFO is emptied and no additional transactions enter the FIFO.

[0028] In various embodiments, the signature comparison may be extended beyond point-to-point comparison to other configurations, for example, the detector configuration may be one-to-many, many-to-one, or many-to-many.

[0029] In a one-to-many configuration, a single location on a bus is connected to a first data corruption detector (i.e., multiple signal lines from locations on the bus are provided as inputs to the data corruption detector in a manner similar to that shown in FIG. 1), while signal lines from multiple locations on one or more buses (e.g., from the same and / or different buses) are connected to a second data corruption detector (and the signature generated by the second detector may be based on a valid set of signals aggregated from multiple points). Such a configuration may be useful when aggregated transactions sent through multiple locations are expected to be the same set of transactions as transactions sent through a single location. For example, such a configuration may be used to test a demultiplexer, with a first data corruption detector coupled to the input of the demultiplexer and a second data corruption detector coupled to each output of the demultiplexer.

[0030] In a many-to-one configuration, signal lines from multiple locations on one or more buses are connected to a first data corruption detector (and the signature generated by the first detector may be based on a set of valid signals aggregated from the multiple locations), while a single location on the bus is connected to a second data corruption detector. Such a configuration may be useful when transactions sent through a single location are expected to be the same set of transactions as the aggregated transactions sent through the multiple locations. For example, such a configuration may exist to test a multiplexer, with a first data corruption detector coupled to each input of the multiplexer and a second data corruption detector coupled to the output of the multiplexer. In another example, multiple components (e.g., intelligence processing units, vision processing units, microcontrollers, etc.) may access memory through a memory controller. Signal lines coupled to various components may be coupled to a first data corruption detector, and signal lines coupled to the memory controller may be coupled to a second data corruption detector.

[0031] In a many-to-many configuration, a first plurality of locations of one or more buses are connected to a first data corruption detector (and the signature generated by the first detector may be based on a set of valid signals aggregated from the first plurality of locations), and a second plurality of locations of one or more buses (the same or different buses) are connected to a second data corruption detector (and the signature generated by the second detector may be based on a set of valid signals aggregated from the second plurality of locations). Such a configuration may be useful when aggregated transactions sent through the first plurality of locations are expected to be the same transaction set as aggregated transactions sent through the second plurality of locations.

[0032] FIG. 2 illustrates a system 200 including a data corruption detector 208 and comparison logic 210 for detecting data corruption at a single location on a bus 212, according to certain embodiments. The system 200 may, for example, enable signature comparison of transactions between pass and fail scenarios. For example, there are some instances in pass and fail scenarios where the electronic device 201 may be stopped (e.g., by stopping a finite state machine or firmware) at a critical point in the flow. In such cases, a signature comparison may be performed for one or more data corruption detectors in the pass and fail states. Thus, a debugger may follow transactions even when they change between protocols. One exemplary use case includes checking firmware downloads. For example, a first download of firmware may result in the generation of a first signature based on signals on the bus communicating the firmware, and a second download of firmware may result in the generation of a different signature (thus indicating either that the firmware has been changed or that some other error has occurred).

[0033] The various components of system 200 may have any suitable characteristics of corresponding components described elsewhere herein. In system 200, bus 212 couples logic block 202 to logic block 204. Data corruption detector 208 is coupled to a single location 214 on bus 212. Multiple signal lines 216 from bus 212 are routed to data corruption detector 208. During a first window, multiple sets of signals are communicated across the bus and via signal lines 216 to data corruption detector 208. As each set of signals is received, data corruption detector 208 may update the signature based on the current signature value and the values ​​of the signals in the set. When the first window closes, the signature output by data corruption detector 208 may be stored in memory 218 (e.g., a register or other suitable memory element). In various embodiments, memory 218 may be included within electronic device 201, and / or comparison logic 210 may include memory. In some embodiments, comparison logic 210 may access memory to retrieve one or more signatures stored therein. At some point, a second window may begin, in which another set of signals is communicated across the bus via signal line 216 to data corruption detector 208. Again, as each set of signals is received during the second window, data corruption detector 208 may update the signature based on the current signature value and the values ​​of the signals in the set. When the second window closes, the signature output by data corruption detector 208 may optionally be stored in memory. Comparison logic 210 compares the signature from the first window with the signature from the second window. In some embodiments, comparison logic 210 may also compare the event counter from the first window against the event counter from the second window. If the signature values ​​match, it may be assumed that no data corruption error is present.

[0034] 3 illustrates a system 300 including a data corruption detector 304 (304A, 304B) that verifies the corrective operation of a FIFO 302, according to a particular embodiment. The data corruption detector may have any suitable characteristics of the other data corruption detectors described herein. The bus segment between the FIFO 302 and logic (not shown) that provides write data to the FIFO 302 includes signal lines for data (data_in) and control (clk_write, wr, and full) signals. Similarly, the bus segment between the FIFO 302 and logic (not shown) that receives read data from the FIFO 302 includes signal lines for data (data_out) and control (clk_read, rd, and empty) signals.

[0035] A write signal (wr), a clock for the write signal (clk_write), and input data (data_in) are provided to data corruption detector 304A via respective signal lines. Detector 304A may generate a signature based on the input data. In this case, detector 304A may determine each valid set of input data signals based on the clk_write and wr signals (e.g., if the wr signal is asserted and the clk_write signal has a rising edge, detector 304A may assume that a new valid set of data exists). Detector 304A may then update the signature (accum_out[15:0]) and increment its event counter (event_counter[11:0]) based on the current signature value and the value of the data_in signal. Thus, detector 304A may update its signature and event counter each time FIFO 302 is written to.

[0036] In the illustrated embodiment, data corruption detector 304A may utilize an accumulator to generate the signature, so that when the signature is generated, the data_in value (or a value based on the data_in value, such as a compressed version of the data_in value) is added to the current value of the signature output by detector 304A (accum_out[15:0]).

[0037] Similarly, a read signal (rd), a clock for the read signal (clk_read), and output data (data_out) are provided to data corruption detector 304B. Detector 304B may generate a signature based on the output data. In this instance, detector 304B may determine each valid set of data based on the clk_read and rd signals (e.g., if the rd signal is asserted and the clk_read signal has a rising edge, detector 304B may assume that a new valid set of data exists). Detector 304B may then update the signature (Accum_out[15:0]) and increment its event counter (Event_counter[11.0]) based on the current signature value and the value of the data_out signal. Thus, detector 304B may update its signature and increment its event counter each time a read is performed from FIFO 302. Although particular bus sizes are shown for the outputs of data corruption detectors 304A and 304B, in various embodiments, these buses may be of any suitable size.

[0038] In this embodiment, whenever the FIFO is empty, the signatures and event counters generated by detectors 304A and 304B are expected to be equal. If a mismatch is detected in either of them, a data corruption error has occurred somewhere in FIFO 302.

[0039] FIG. 4 illustrates a data corruption detector 402 according to a particular embodiment. Detector 402 may have any suitable characteristics of any of the data corruption detectors described herein. In this embodiment, detector 402 includes a control block 404, a signature generator 406, an event counter 408, and comparison logic 410. Control block 404 receives various signals, including input signals (carried on any suitable number of signal lines) and control signals, such as some or all of a clock (clk) signal, a valid signal, a reset signal, an enable signal, a trigger signal, a clear signal, and a freeze signal (in other embodiments, additional control signals may be present, or some of the depicted control signals may be omitted). The input signals may include any suitable signals used as the basis for signature generation (e.g., these are signals that are checked for errors). For example, the input signals may include any one or more of data, address, credit, parity bits, read / write control, header, or other suitable signals. Some of these signals (e.g., input signal, enable, and / or clk) may be transmitted on a bus coupled to logic of the system being tested for data corruption errors (e.g., logic block 104, logic block 202, FIFO 302, etc.). Other signals (e.g., control signals such as enable, reset, enable, trigger, clear, freeze) may be provided from control logic (e.g., a debugger or other software and / or hardware) or may be derived from signals on the bus. For example, one or more of these control signals may come from a register that can be written to by a debugger or through other suitable means.

[0040] In some embodiments, each new set of signals received by detector 402 is used to generate an updated signature. However, in other embodiments, the set of signals transmitted on the bus may be filtered, and only a specific set of signals on the bus (e.g., a valid set of signals) may be used to generate an updated signature. In various embodiments, data corruption detector 402 may determine, in a suitable manner, whether a specific set of signals should be included in signature generation. In one embodiment, a valid signal may indicate whether a specific set of signals being received by detector 402 (e.g., from the bus) should be used to generate an updated signature. If the valid signal is not asserted, signature generator 406 and event counter 408 may ignore the signal set. If the valid signal is asserted, signature generator 406 may use the signal set to update the signature (signature_value), and event counter 408 may increment the event counter (event_value) in response to edges (e.g., rising and / or falling edges) of the clk signal.

[0041] Any suitable filtering of the signal set may be performed internally to the control block 404 and / or externally to the control block 404 (e.g., by a debugger or other logic). If the filter is performed internally to the control block 404, in one example, the control may have an internally generated valid signal (e.g., generated by combining an external valid signal and a result indicating whether the filter matches). In some embodiments, the data corruption detector 402 receives a filtering field and a value to match against the input signal (and may also receive mask bits indicating which signals to ignore).

[0042] As an example of filtering, only signal sets for a particular command type (e.g., one or more of write, read, erase, etc.) may be considered for signature generation. As another example, only signal sets within a particular address range may be considered for signature generation. As another example, for a bus that carries memory commands and various notifications, only signal sets for the memory commands may be considered for signature generation. As another example, only signal sets for a particular data type may be considered for signature generation. As yet another example, a filter may be applied for one or more source IDs, one or more destination IDs, header values, or particular bit combinations (e.g., in particular signals in the input signal).

[0043] The reset signal may perform a general reset of the logic within the control block 404 , the signature generator 406 , and / or the event counter 408 .

[0044] The enable signal may disable logic within the control block 404, signature generator 406, and / or event counter 408 without completely resetting the logic. This may be used to provide power savings when the detector 402 is not in use. In some embodiments, the enable signal may be gated with the clk signal (so that the clk signal does not propagate within the detector 402 unless the enable signal is asserted). If a valid transaction is received when the enable is asserted, the transaction may be used to update the signature and event counter.

[0045] The trigger signal provides an indication to start or stop signature generation and event counting. The trigger signal may be based on an event occurring in the wider system (e.g., the trigger signal may be controlled by a register or other external logic that can dynamically start or stop accumulation).

[0046] The clear signal may clear the signature value and the event counter value (eg, by resetting the values ​​to their initial values).

[0047] The freeze signal may freeze signature updates and event counter updates (eg, even if a valid signal set is received, signature and event counters will not be updated when the freeze signal is asserted).

[0048] The control block 404 may receive any suitable signals from the bus and / or other sources and control the inputs provided to the signature generator 406 and the event counter 408. If a signal set received from the bus is used to update a signature, the control block 404 may pass the signal set (or a derivative thereof) along with associated control signals (e.g., a clock signal and / or a valid_event signal) to the signature generator 406. In some embodiments, the control block 404 may compress the signal set received from the bus (including one or more data signals, one or more address signals, and / or one or more other signals) and provide the compressed signal set (compressed_signal) to the signature generator 406, which may update the signature_value based on the compressed_signal and the current signature_value. Compression may be performed in any suitable manner. In one embodiment, an XOR tree is used to compress the signal set (e.g., to 16 bits or other number of bits).

[0049] The control block 404 may provide the signature generator 406 with a compressed version of the incoming signal set (compressed_signal_set as shown), an uncompressed signal set, or some other variation of the signal set. In some embodiments, the control block 404 may also send a clock signal to the signature generator 406 to control when the signature is updated (e.g., the signature may be updated on the rising and / or falling edge of the clock signal). In some embodiments, the clock signal may be the same as the clk signal or other suitable clock signal input to the control block 404. In various embodiments, the control block 404 may also send a qualified enable signal. For example, a qualified enable signal may be a combination of two or more of the signals received by the control block. By way of example only, a qualified enable signal may be a combination of valid, enable, trigger, and freeze (such that the qualified enable signal is asserted when valid, enable, and trigger are asserted and freeze is not asserted). A qualifying enable signal (when asserted) may indicate to signature generator 406 that the compressed_signal_set (or uncompressed signal set) is used to update the signature on the rising and / or falling edges of the clock signal. In other embodiments, any other suitable method for notifying signature generator 406 that a signal set is used to update the signature is contemplated herein. The valid_event signal indicates to the data corruption detector that new data has arrived in the input signal and passed filtering (if any).

[0050] Signature generator 406 may output a signature_value (which may be of any suitable size), and event counter 408 may output an event_value (which may also be of any suitable size). In some embodiments, comparison logic 410 may compare the signature_value and / or event_counter against one or more predetermined signature values ​​or event counter values ​​and assert a signature_match or event_count_match signal if a match is found. These signals may be used to trigger any suitable system action, such as stopping a portion of the system, clock gating, starting tracing, or other suitable action.

[0051] In some embodiments, to synchronize and stop the data corruption detectors at different times, a signal (dedicated for that purpose) may be provided to the data corruption detector that serves as an indication of whether to sample or not. The signal may be set by the sending block according to the filtering results, for example, or by a control register. This signal may propagate as part of a bus, along with other bus signals, to the data corruption detector, such that the data corruption detector samples or ignores the input signal based on the value of this signal.

[0052] In various embodiments, the data corruption detector may be used in conjunction with a software debugger. For example, one or more of the control signals sent to the detector may be provided by the debugger (e.g., the debugger may control when the detector is enabled, which filtered transactions are considered, etc.). As another example, the debugger may read (e.g., from memory such as a register) the signature value, the event value, and / or an indication of whether the values ​​match (e.g., if a comparison is performed by circuitry of the computing system that includes the detector). As another example, if a mismatch is detected, the debugger may take various actions in response to detecting the mismatch.

[0053] In other embodiments, the data corruption detector may be used independently of a software debugger (e.g., by using logic external to the computing system to write to control registers and / or read from registers containing signature values, event values, and / or comparison results).

[0054] Various embodiments may be used by manufacturers or other entities to debug systems under development, but use cases are not limited to this. For example, in some embodiments, the detector may be utilized by end users to perform inductive safety, error reporting, or other operations. By way of example only, if a signature mismatch is detected at one or more critical points in a computing system, the computing system may be shut down (e.g., automatically triggered by the detection of the mismatch) or other remedial action may be taken.

[0055] 5 illustrates a flow 500 for generating a signature based on a bus transaction, according to certain embodiments. Any operations in the flow may be performed by any one or more components described herein, such as an electronic device, a computing system coupled to an electronic device, a debugger, or other suitable logic.

[0056] At 502, filtering criteria are set up. The filtering criteria define which transactions are considered in signature generation and event counting for one or more particular data corruption detectors. Setting up filtering criteria may include, for example, writing to one or more registers of the electronic device with settings that define the filtering and / or otherwise configuring the filtering logic of the electronic device.

[0057] Signature generation is enabled at 504. For example, a data corruption detector may be powered up, configured, and / or instructed to begin generating a signature.

[0058] At 506, a transaction is communicated over the bus. At 508, a determination is made as to whether the transaction meets previously set up filtering criteria. If the transaction does not meet the filtering criteria, the signature and event counters of the data corruption detector coupled to the bus are not updated and flow moves to 514. If the transaction meets the filtering criteria, flow moves to 510 where a signature is updated based at least in part on the values ​​of the signals in the transaction. An event counter associated with the signature is updated at 512.

[0059] At 514, a determination is made as to whether the transaction being analyzed is complete. If not, flow moves to 506, where an additional transaction is communicated over the bus and, if it meets the filtering criteria, the transaction is used to update the signature and event counters. If the transaction is complete, the signature and event counters are provided for comparison at 516. For example, the signature and event counters may be provided for comparison with signature and event counters from a different data corruption detector, or from signature and event counters updated by the same data corruption detector in response to a separate set of transactions.

[0060] 6 illustrates a flow 600 for detecting data corruption, according to certain embodiments. At 602, a first signature is generated based on a first set of signals communicated by a bus, where the first set of signals is communicated by the bus in a first set of transactions. At 604, a second signature is generated based on a second set of signals communicated by the bus, where the second set of signals is communicated by the bus in a second set of transactions. At 606, the first signature and the second signature are compared to determine whether a data corruption error has occurred.

[0061] In various embodiments, the flows described herein (e.g., in FIG. 5, FIG. 6, or elsewhere) may include additional operations, omit any of the described operations, perform any of the operations in parallel with one or more other operations, or repeat operations. For example, signatures may be generated in parallel to compare two or more points.

[0062] 7 illustrates a computing system 700 according to certain embodiments. Any suitable components of system 700 may be used to perform any of the functions described above. For example, all or a portion of system 700 may be included in an electronic device (e.g., 101, 201). As another example, any number of data corruption detectors may be included within system 700 or its components. As yet another example, a debugger may run on system 700 and interact with a data corruption detector of the electronic device (which may also include any of the components of system 700).

[0063] System 700 may include a computing device 701 including a central processing unit (CPU) 702 coupled to an external input / output (I / O) controller 704, a storage device 706, and a system memory 707. While various components are illustrated, computing system 700 may include additional components or multiple components of the ones illustrated.

[0064] During operation, data may be transferred between storage device 706 or system memory 707 and CPU 702. In various embodiments, certain data operations involving storage device 706 or system memory 707 (e.g., erase, program, and read operations) may be managed by an operating system or other software application executed by processor 708.

[0065] CPU 702 includes a processor 708, such as a microprocessor, embedded processor, digital signal processor (DSP), network processor, handheld processor, application processor, co-processor, system on a chip (SOC), or other device that executes code (i.e., software instructions). In the embodiment shown, processor 708 includes two processing elements (cores 714A and 714B in the embodiment shown), which may include asymmetric processing elements or symmetric processing elements. However, a processor may include any number of processing elements, which may be symmetric or asymmetric.

[0066] In one embodiment, a processing element refers to hardware or logic that supports a software thread. Examples of hardware processing elements include a thread unit, thread slot, thread, processing unit, context, context unit, logical processor, hardware thread, core, and / or any other element capable of maintaining processor state, such as execution state or architectural state. In other words, in one embodiment, a processing element refers to any hardware that can be associated with code, such as a software thread, an operating system, an application, or independently other code. A physical processor (or processor socket) typically refers to an integrated circuit that potentially contains any number of other processing elements, such as cores or hardware threads.

[0067] A core 714 may refer to logic located on an integrated circuit capable of maintaining independent architectural state. Each independently maintained architectural state is associated with at least some dedicated execution resources. A hardware thread may refer to any logic located on an integrated circuit capable of maintaining independent architectural state. The independently maintained architectural state shares access to the execution resources. As will be appreciated, the nomenclature boundaries between hardware threads and cores overlap when certain resources are shared and other resources are dedicated to architectural state. However, often cores and hardware threads are viewed by the operating system as individual logical processors, and the operating system can schedule operations on each logical processor independently.

[0068] In various embodiments, a processing element may also include one or more arithmetic logic units (ALUs), floating point units (FPUs), caches, instruction pipelines, interrupt handling hardware, registers, or other hardware that facilitates the operation of the processing element.

[0069] The I / O controller 710 is an integrated I / O controller. The I / O controller 710 may include logic for communicating data between the CPU 702 and an I / O device, which may refer to any suitable device capable of transferring data to and / or receiving data from an electronic system, such as the CPU 702. For example, the I / O device may include an audio / video (A / V) device controller, such as a graphics accelerator or audio controller; a data storage device controller, such as a flash memory device, magnetic storage disk, or optical storage disk controller; a wireless transceiver; a network processor; a network interface controller; or a controller for another input device, such as a monitor, printer, mouse, keyboard, or scanner; or other suitable device. In particular embodiments, the I / O device may include a storage device 706, which may be coupled to the CPU 702 through the I / O controller 710.

[0070] I / O devices may communicate with I / O controller 710 of CPU 702 using any suitable signaling protocol, such as Peripheral Component Interconnect (PCI), PCI Express (PCIe), Universal Serial Bus (USB), Serial Attached SCSI (SAS), Serial ATA (SATA), Fibre Channel (FC), IEEE 802.3, IEEE 802.11, or other current or future signaling protocols. In particular embodiments, I / O controller 710 and the underlying I / O devices may communicate data and commands according to a logic device interface specification such as Non-Volatile Memory Express (NVMe) (e.g., as described by one or more of the specifications available at www.nvmexpress.org / specifications / ) or Advanced Host Controller Interface (AHCI) (e.g., as described by one or more AHCI specifications such as Serial ATA AHCI: Specification, Rev. 1.3.1 available at http: / / www.intel.com / content / www / us / en / io / serial-ata / serial-ata-ahci-spec-rev1-3-1.html). In various embodiments, the I / O devices coupled to the I / O controller may be located off-chip (i.e., not on the same chip as CPU 702) or may be integrated on the same chip as CPU 702.

[0071] The CPU memory controller 712 is an integrated memory controller. In various embodiments, the CPU memory controller 712 may include any one or more features of the I / O controller 710. The CPU memory controller may include logic to control the flow of data to and from one or more system memories 707. The CPU memory controller 712 may include logic operable to read from, write to, or request other operations from the system memories 707. In various embodiments, the CPU memory controller 712 may receive write requests from the cores 714 and / or the I / O controller 710 and provide the data specified in these requests to the system memory 707 for storage therein. The CPU memory controller 712 may also read data from the system memory 707 and provide the read data to the I / O controller 710 or the cores 714. In operation, the CPU memory controller 712 may issue commands including one or more addresses of the system memory 707 to read data from or write data to memory, or to perform other operations. In some embodiments, CPU memory controller 712 may be implemented on the same chip as CPU 702, while in other embodiments, CPU memory controller 712 may be implemented on a different chip than CPU 702. I / O controller 710 may perform similar operations in connection with one or more storage devices 706.

[0072] CPU 702 may also be coupled to one or more other I / O devices through an external I / O controller 704. In particular embodiments, external I / O controller 704 may couple storage device 706 to CPU 702. External I / O controller 704 may include logic for managing the flow of data between one or more CPUs 702 and the I / O devices. In particular embodiments, external I / O controller 704 is located on a motherboard along with CPU 702. External I / O controller 704 may exchange information with components of CPU 702 using point-to-point or other interfaces.

[0073] System memory 707 may store any suitable data, such as data used by processor 708 to provide functionality of computer system 700. For example, data associated with programs being executed or files accessed by cores 714 may be stored in system memory 707. Thus, system memory 707 may include system memory that stores data and / or sequences of instructions executed or otherwise used by cores 714. In various embodiments, system memory 707 may store persistent data (e.g., user files or instruction sequences) that remain stored even after power to system memory 707 is removed. System memory 707 may be dedicated to a particular CPU 702 or may be shared with other devices in computer system 700 (e.g., one or more other processors or other devices).

[0074] In various embodiments, system memory 707 may include memory, including any number of memory arrays, memory device controllers, and other support logic (not shown). The memory arrays (or other memory described herein, such as memory used to store signatures and / or event counter values) may include non-volatile memory and / or volatile memory. Non-volatile memory is a storage medium that does not require power to maintain the state of data stored by the medium. Non-limiting examples of non-volatile memory may include any one or combination of: solid-state memory (e.g., planar or 3D NAND flash memory or NOR flash memory), 3D cross-point memory, memory devices using chalcogenide phase change materials (e.g., chalcogenide glass), byte-addressable non-volatile memory devices, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory (e.g., ferroelectric polymer memory), ferroelectric transistor random access memory (Fe-TRAM) ovonic memory, nanowire memory, electrically erasable programmable read-only memory (EEPROM), various other types of non-volatile random access memory (RAM), and magnetic storage memory. In some embodiments, 3D cross-point memory may include a transistorless stackable cross-point architecture in which memory cells are located at the intersections of word lines and bit lines and are individually addressable, and bit storage is based on changes in bulk resistance. Volatile memory is a storage medium that requires power to maintain the state of data stored by the medium.Examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random-access memory (SRAM). One particular type of DRAM that may be used in a memory array is synchronous dynamic random-access memory (SDRAM). In some embodiments, any portion of memory 707 that is volatile memory may conform to JEDEC standards, including, but not limited to, Double Data Rate (DDR) standards, such as DDR3, 4, and 5, or Low Power DDR4 (LPDDR4), as well as emerging standards.

[0075] Storage device 706 may store any suitable data, such as data used by processor 708 to provide functionality of computer system 700. For example, data associated with programs executed or files accessed by cores 714A and 714B may be stored in storage device 706. Thus, in some embodiments, storage device 706 may store data and / or sequences of instructions executed or otherwise used by cores 714A and 714B. In various embodiments, storage device 706 may store persistent data (e.g., user files or software application code) that remains stored even after power to storage device 706 is removed. Storage device 706 may be dedicated to CPU 702 or may be shared with other devices in computer system 700 (e.g., another CPU or other devices).

[0076] In various embodiments, storage device 706 includes a storage device controller and one or more memory modules. In various embodiments, the memory modules of storage device 706 include one or more NAND flash memory arrays, one or more hard disk drives, or other suitable memory storage devices. Storage device 706 may comprise any suitable type of memory and, in various embodiments, is not limited to a particular speed, technology, or form factor of memory. For example, storage device 706 may be a disk drive (e.g., a solid-state drive), a flash drive, memory integrated into the computing device (e.g., memory integrated on a circuit board of the computing device), a memory module that may be inserted into a memory socket (e.g., a dual in-line memory module), or other type of storage device. Computer system 700 may also include multiple different types of storage devices. Storage device 706 may include any suitable interface for communicating with CPU memory controller 712 or I / O controller 710 using any suitable communication protocol, such as a DDR-based protocol, PCI, PCIe, USB, SAS, SATA, FC, System Management Bus (SMBus), or other suitable protocol. Storage device 706 may also include a communication interface for communicating with CPU memory controller 712 or I / O controller 710 according to any suitable logic device interface specification, such as NVMe, AHCI, or other suitable specification. In particular embodiments, storage device 706 may include multiple communication interfaces, each communicating with CPU memory controller 712 and / or I / O controller 710 using a separate protocol.

[0077] In some embodiments, all or some of the elements of system 700 are on (or coupled to) the same circuit board (e.g., motherboard). In various embodiments, any suitable division between the elements may exist. For example, the elements illustrated in CPU 702 may be located on a single die (i.e., on-chip), or either the package or chip of the elements of CPU 702 may be located off-chip or off-package. Similarly, the elements illustrated in storage device 706 may be located on a single chip or on multiple chips. In various embodiments, storage device 706 and a computing device (e.g., CPU 702) may be located on the same circuit board or device, while in other embodiments, storage device 706 and a computing device may be located on different circuit boards or devices.

[0078] The components of system 700 may be coupled together in any suitable manner. For example, a bus may couple any of the components together. The bus may include any known interconnect, such as a multi-drop bus, a mesh interconnect, a ring interconnect, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g., cache coherent) bus, a layered protocol architecture, a differential bus, and a Gunning Transceiver Logic (GTL) bus. In various embodiments, an integrated I / O subsystem includes point-to-point multiplexing logic between various components of system 700, such as cores 714, one or more CPU memory controllers 712, an I / O controller 710, integrated I / O devices, direct memory access (DMA) logic (not shown), etc. In various embodiments, the components of computer system 700 may be coupled together through one or more networks including any number of intervening network nodes, such as routers, switches, or other computing devices. For example, a computing device (e.g., CPU 702) and a storage device 706 may be communicatively coupled through a network.

[0079] Although not shown, system 700 may use a battery and / or a power outlet connector and associated system for receiving power, a display for outputting data provided by CPU 702, or a network interface that allows CPU 702 to communicate over a network. In various embodiments, the battery, power outlet connector, display, and / or network interface may be communicatively coupled to CPU 702. Other power sources, such as renewable energy (e.g., solar power or motion-based power), may also be used.

[0080] 8 is a block diagram of an exemplary electronic device 800 according to certain embodiments of the present disclosure. Any suitable components of device 800 may be used to perform any of the functions described above. For example, any number of data corruption detectors may be included within device 800 or its components.

[0081] 8 as being included in electronic device 800, any one or more of these components may be omitted or duplicated as suitable for an application. In some embodiments, some or all of the components included in electronic device 800 may be mounted on one or more motherboards, main boards, or system boards. In some embodiments, one or more of these components are fabricated on a single system-on-chip (SoC) die.

[0082] 8, electronic device 800 may include interface circuitry for coupling to one or more components. For example, electronic device 800 may not include display device 806, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 806 may be coupled. In another set of examples, electronic device 800 may not include audio input device 824 or audio output device 808, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which audio input device 824 or audio output device 808 may be coupled.

[0083] Electronic device 800 may include one or more processor units 802 (e.g., one or more processor units). As used herein, the terms “processor unit,” “processing unit,” or “processor” may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptoprocessors (dedicated processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. As such, the processor unit may be referred to as an XPU (or xPU).

[0084] The electronic device 800 may include memory 804, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-volatile memory, solid-state memory, and / or a hard drive). In some embodiments, the memory 804 may include memory located on the same integrated circuit die as the processor unit 802. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0085] In some embodiments, electronic device 800 may include one or more processor units 802 that are heterogeneous or asymmetric with respect to other processor units 802 in electronic device 800. There may be a wide variety of differences between processing units 802 in a system in terms of a spectrum of metrics of merit, including architectural, microarchitectural, thermal, power consumption characteristics, etc. These differences may themselves effectively manifest as asymmetries and heterogeneities between processor units 802 in electronic device 800.

[0086] In some embodiments, electronic device 800 may include a communications component 812 (e.g., one or more communications components). For example, communications component 812 may manage wireless communications for the transfer of data to and from electronic device 800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data through the use of modulated electromagnetic radiation over a non-solid medium. The term "wireless" does not imply that the associated device does not include any wires, although in some embodiments this may not be the case.

[0087] The communications component 812 may implement any of several wireless standards or protocols, including, but not limited to, Institute for Electrical and Electronic Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), the IEEE 802.16 standard (e.g., the IEEE 802.16-2005 amendment), and the Long-Term Evolution (LTE) project with any amendments, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks. The acronym stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed IEEE 802.16 standard compliance and interoperability testing. The communications component 812 may operate in accordance with a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communications component 812 may operate in accordance with an Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communications component 812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond.In other embodiments, communication component 812 may operate according to other wireless protocols. Electronic device 800 may include an antenna 822 to facilitate wireless communications and / or receive other wireless communications (e.g., amplitude modulation (AM) or frequency modulation (FM) radio transmissions).

[0088] In some embodiments, the communications component 812 may manage wired communications, such as electrical, optical, or any other suitable communications protocol (e.g., the IEEE 802.3 Ethernet standard). As noted above, the communications component 812 may include multiple communications components. For example, a first communications component 812 may be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communications component 812 may be dedicated to longer-range wireless communications, such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communications component 812 may be dedicated to wireless communications, and the second communications component 812 may be dedicated to wired communications.

[0089] Electronic device 800 may include battery / power circuitry 814. Battery / power circuitry 814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of electronic device 800 to an energy source (e.g., AC line power) separate from electronic device 800.

[0090] Electronic device 800 may include a display device 806 (or corresponding interface circuitry as discussed above), which may include one or more embedded or wired or wirelessly connected external visual indicators, such as, for example, a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0091] The electronic device 800 may include an audio output device 808 (or corresponding interface circuitry as discussed above), which may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, headset, or earphones.

[0092] The electronic device 800 may include an audio input device 824 (or corresponding interface circuitry as discussed above). The audio input device 824 may include any embedded, wired, or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a musical instrument digital interface (MIDI) output). The electronic device 800 may include a Global Navigation Satellite System (GNSS) device 818 (or corresponding interface circuitry as discussed above), such as a Global Positioning System (GPS) device. The GNSS device 818 may communicate with a satellite-based system and determine the geographic location of the electronic device 800 based on information received from one or more GNSS satellites, as known in the art.

[0093] The electronic device 800 may include other output devices 810 (or corresponding interface circuitry as discussed above). Examples of other output devices 810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0094] The electronic device 800 may include other input devices 820 (or corresponding interface circuitry as discussed above). Examples of other input devices 820 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, a proximity sensor, a microphone, a barcode reader, a Quick Response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmogram) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0095] Electronic device 800 may have any desired form factor, for example, a handheld or mobile electronic device (e.g., a mobile phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable gaming console, etc.), a desktop electronic device, a server, a rack-level computing solution (e.g., a blade, tray, or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, a smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electronic device, or an embedded computing system (e.g., a computing system that is part of a vehicle, a smart home appliance, a home appliance or device, or manufacturing equipment). In some embodiments, electronic device 800 may be any other electronic device that processes data. In some embodiments, electronic device 800 may include multiple discrete physical components. Given the range of devices that electronic device 800 may be in various embodiments, in some embodiments electronic device 800 may be referred to as a computing device or a computing system.

[0096] A design may go through various stages, from creation to simulation to manufacturing. Data representing the design may represent the design in multiple ways. First, the hardware may be represented using a hardware description language (HDL) or another functional description language, useful in simulation. In addition, a circuit-level model using logic and / or transistor gates may be generated at some stages of the design process. Furthermore, most designs, at some stage, reach a level of data representing the physical placement of various devices in the hardware model. When conventional semiconductor manufacturing techniques are used, the data representing the hardware model may be data specifying the presence or absence of various features on different mask layers of a mask used to fabricate the integrated circuit. In some implementations, such data may be stored in a database file format, such as Graphic Data System II (GDS II), Open Artwork System Interchange Standard (OASIS), or a similar format.

[0097] In some implementations, software-based hardware models and HDL and other functional description language objects may include register transfer language (RTL) files, among other examples. Such objects may be machine-parseable, allowing design tools to accept HDL objects (or models), parse the HDL objects for attributes of the described hardware, and determine a physical circuit and / or on-chip layout from the objects. The output of the design tools can be used to manufacture physical devices. For example, design tools can determine the configuration of various hardware and / or firmware elements from the HDL objects, such as bus widths, registers (including sizes and types), memory blocks, physical link paths, and fabric topology, among other attributes that will be implemented to realize the system modeled in the HDL objects. Design tools may include tools for determining the topology and fabric configuration of systems-on-chips (SoCs) and other hardware devices. In some instances, HDL objects can be used as the basis for developing models and design files that can be used by manufacturing equipment to produce the described hardware. Indeed, the HDL objects themselves can be provided as input to manufacturing system software to yield the described hardware.

[0098] In any representation of the design, the data can be stored in any form of machine-readable medium. Memory, or magnetic or optical storage such as a disk, may be a machine-readable medium that stores such information transmitted via light or radio waves modulated or otherwise generated to transmit the information. When an electrical carrier wave indicating or carrying the code or design is transmitted, a new copy is made to the extent that copying, buffering, or retransmission of the electrical signal is performed. Thus, a communications provider or network provider may store, at least temporarily, items such as information encoded in a carrier wave on a tangible, machine-readable medium, embodying the techniques of embodiments of the present disclosure.

[0099] In various embodiments, a medium storing a representation of a design may be provided to a manufacturing system (e.g., a semiconductor manufacturing system capable of manufacturing integrated circuits and / or related components). The design representation may instruct the system to manufacture a device capable of performing any combination of the functions described above. For example, the design representation may instruct the system regarding which components to manufacture, how the components should be coupled together, where the components are to be placed on the device, and / or other suitable specifications for the device to be manufactured.

[0100] As used herein, a module refers to circuitry and any combination of hardware, software, and / or firmware. As an example, a module includes hardware such as a microcontroller associated with non-transitory media that stores code adapted to be executed by the microcontroller. Thus, in one embodiment, reference to a module refers to hardware specifically configured to recognize and / or execute code held on the non-transitory media. Furthermore, in another embodiment, the use of a module refers to non-transitory media containing code specifically adapted to be executed by a microcontroller to perform a plurality of predetermined operations. As can be inferred, in yet another embodiment, the term module (in this example) may refer to a combination of a microcontroller and non-transitory media. In many cases, the boundaries of multiple modules shown as separate typically vary and potentially overlap. For example, a first and second module may share hardware, software, firmware, or a combination thereof, but potentially maintain some independent hardware, software, or firmware. In one embodiment, the use of the term logic includes hardware, e.g., transistors, registers, or other hardware, e.g., programmable logic devices.

[0101] Logic may be used to implement any of the described flows or functions of the various components described herein. "Logic" may refer to hardware, firmware, software, and / or combinations of each for performing one or more functions. In various embodiments, logic may include a microprocessor or other processing element operable to execute software instructions, discrete logic such as an application specific integrated circuit (ASIC), a programmed logic device such as a field programmable gate array (FPGA), a storage device containing instructions, a combination of logic devices (e.g., as found on a printed circuit board), or other suitable hardware and / or software. Logic may include one or more gates or other circuit components. In some embodiments, logic may be embodied entirely in software. Software may be embodied as a software package, code, instructions, instruction sets, and / or data recorded on a non-transitory computer-readable storage medium. Firmware may be embodied as hard-coded (e.g., non-volatile) code, instructions, instruction sets, and / or data in a storage device.

[0102] The use of the phrases "to" or "configured to" refers, in one embodiment, to arranging, combining, manufacturing, selling, importing, and / or designing a device, hardware, logic, or element to perform a specified or determined task. In this example, a non-operational device or its elements is still "configured to" perform a specified task if it is designed, coupled, and / or interconnected to perform the specified task. As a purely illustrative example, a logic gate may provide a 0 or a 1 during operation. However, a logic gate "configured to" provide an enable signal to a clock does not include all potential logic gates that can provide a 1 or a 0. Instead, the logic gate is coupled in some manner such that a 1 or 0 output enables the clock during operation. It should be noted that the use of the term "configured to" does not require operation, but instead focuses on the potential state of a device, hardware, and / or element, in which the device, hardware, and / or element is designed to perform a particular task when the device, hardware, and / or element is operating.

[0103] Additionally, the use of the phrase "capable of / to" or "operable to" refers, in one embodiment, to some device, logic, hardware, and / or element that is designed to enable that device, logic, hardware, and / or element to be used in a specified manner. Note, as above, that the use of "to," "capable of," or "operable to," in one embodiment, refers to the underlying state of a device, logic, hardware, and / or element, where the device, logic, hardware, and / or element is not operating but is designed to enable a device to be used in a specified manner.

[0104] As used herein, a value includes any known representation of a number, state, logical state, or binary logical state. Often, the use of logic levels, logic values, or logical values, also referred to as 1 and 0, simply represents a binary logic state. For example, 1 refers to a high logic level and 0 refers to a low logic level. In one embodiment, a storage cell, such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values ​​in computer systems are used. For example, the decimal number 10 may also be represented as the binary value 1010 or the letter A in hexadecimal. Thus, a value includes any representation of information that can be held in a computer system.

[0105] Furthermore, a state may be represented by a value or portion of a value. As an example, a first value, such as a logical one, may represent a default or initial state, while a second value, such as a logical zero, may represent a non-default state. Additionally, in one embodiment, the terms reset and set refer to default and updated values ​​or states, respectively. For example, a default value may optionally include a high logical value, i.e., reset, and an updated value may optionally include a low logical value, i.e., set. It should be noted that any combination of multiple values ​​may be utilized to represent any number of states.

[0106] The above-described method, hardware, software, firmware, or code embodiments may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium that is executable by a processing element. A non-transitory machine-accessible / readable medium includes any mechanism that provides (i.e., stores and / or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, a non-transitory machine-accessible medium includes random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM), ROM, magnetic or optical storage media, flash storage devices, electrical storage devices, optical storage devices, acoustic storage devices, other forms of storage devices for retaining information received from a transitory (propagated) signal (e.g., carrier wave, infrared signal, digital signal), and the like, which are distinct from non-transitory media that may receive information therefrom.

[0107] The instructions used to program logic to implement embodiments of the present disclosure may be stored in memory in the system, such as DRAM, cache, flash memory, or other storage. Additionally, the instructions may be distributed over a network or by other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including, but not limited to, floppy diskettes, optical disks, compact disks, read-only memories (CD-ROMs), and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or tangible machine-readable storage used to transmit information over the Internet via electrical, optical, acoustic, or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, computer-readable media includes any type of tangible, machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (eg, a computer).

[0108] Example 1 includes an apparatus comprising: a bus that communicates a plurality of sets of signals in a plurality of transactions; a first circuit that generates a first signature based on the plurality of sets of signals communicated by the bus, wherein the first circuit updates the signature based on a current value of a signature and a valid incoming signal set; and a second circuit that provides the first signature for comparison with a second signature.

[0109] Example 2 includes the subject matter of example 1, wherein the first signature depends on an order of the plurality of signal sets.

[0110] Example 3 includes the subject matter of any of Examples 1 and 2, wherein the first signature does not depend on the order of the plurality of signal sets.

[0111] Example 4 includes the subject matter of any of Examples 1-3, further including a third circuit that generates a first counter value indicative of the number of signal sets used to generate the first signature, and a fourth circuit that provides the first counter value for comparison with a second counter value indicative of the number of signal sets used to generate the second signature.

[0112] Example 5 includes the subject matter of any of Examples 1-4, wherein the first circuit further generates a second signature based on a second plurality of sets of signals communicated by the bus.

[0113] Example 6 includes the subject matter of any of Examples 1-5, further including a third circuit that generates a second signature based on a second plurality of sets of signals communicated by the bus.

[0114] Example 7 includes the subject matter of any of Examples 1-6, wherein the plurality of signal sets comprises signals communicating one or more of: at least one or more data bits, at least one address bit, or at least one control bit.

[0115] Example 8 includes the subject matter of any of Examples 1-7, further including a third circuit that compresses at least some of the signals of the plurality of signal sets to generate a plurality of compressed signal sets, and the first signature is based on the plurality of compressed signal sets.

[0116] Example 9 includes the subject matter of any of Examples 1 to 8, wherein the third circuit comprises an XOR tree.

[0117] Example 10 includes the subject matter of any of Examples 1-9, wherein the first circuit comprises one or more of an accumulator, a multiple-input shift register, or a linear feedback shift register to generate the first signature.

[0118] Example 11 includes the subject matter of any one of Examples 1 to 10, and further includes a processor having the bus.

[0119] Example 12 includes the subject matter of any of Examples 1-10, further including one or more of a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor.

[0120] Example 13 includes a method comprising: generating a first signature based on a first plurality of sets of signals communicated over a bus during a first set of transactions; generating a second signature based on a second plurality of sets of signals communicated over the bus during a second set of transactions; and comparing the first signature and the second signature to determine whether a data corruption error has occurred.

[0121] Example 14 includes the subject matter of example 13, further including incrementing an event counter associated with the first signature each time the first signature is updated based on a set of signals.

[0122] Example 15 includes the subject matter of any of examples 13 and 14, further including reporting the data corruption error via a debugger interface.

[0123] Example 16 includes the subject matter of any of Examples 13-15, further including compressing the first plurality of signal sets to generate a plurality of compressed signal sets, and the first signature is based on the plurality of compressed signal sets.

[0124] Example 17 includes the subject matter of any of Examples 13-16, wherein the first signature depends on the order of the plurality of signal sets.

[0125] Example 18 includes the subject matter of any of Examples 13-17, wherein the first signature does not depend on the order of the plurality of signal sets.

[0126] Example 19 includes the subject matter of any of Examples 13-18, further including generating a first counter value indicative of a number of signal sets used to generate the first signature, and providing the first counter value for comparison with a second counter value indicative of a number of signal sets used to generate the second signature.

[0127] Example 20 includes the subject matter of any of Examples 13-19, wherein the first plurality of sets of signals includes signals communicating one or more of at least one data bit, at least one address bit, or at least one control bit.

[0128] Example 21 includes the subject matter of any of Examples 13-20, wherein the signature generation is performed by an accumulator, a multiple-input shift register, or a linear feedback shift register.

[0129] Example 22 includes at least one machine-readable storage medium having stored thereon instructions that, when executed by a machine, cause the machine to: generate a first signature based on a first plurality of sets of signals communicated by a bus, where the first plurality of sets of signals are communicated by the bus at different clock cycles; generate a second signature based on a second plurality of sets of signals communicated by the bus, where the second plurality of sets of signals are communicated by the bus at different clock cycles; and provide the first signature and the second signature for comparison to determine whether a data corruption error has occurred.

[0130] Example 23 includes the subject matter of example 22, wherein the instructions, when executed, further cause the machine to filter transactions on the bus used to generate the first signature.

[0131] Example 24 includes the subject matter of any of Examples 22-23, wherein the instructions, when executed, further cause the machine to perform a comparison of the first signature and the second signature.

[0132] Example 25 includes the subject matter of any of Examples 22-24, wherein the instructions, when executed, further cause the machine to read the first signature and the second signature from at least one memory of the machine.

[0133] Example 26 includes the subject matter of any of Examples 22-25, wherein the instructions, when executed, further cause the machine to increment an event counter associated with the first signature each time the first signature is updated based on a set of signals.

[0134] Example 27 includes the subject matter of any of Examples 22-26, wherein the instructions, when executed, further cause the machine to report the data corruption error via a debugger interface.

[0135] Example 28 includes the subject matter of any of Examples 22-27, wherein the instructions, when executed, further cause the machine to compress the first plurality of signal sets to generate a plurality of compressed signal sets, and the first signature is based on the plurality of compressed signal sets.

[0136] Example 29 includes the subject matter of any of Examples 22-28, wherein the first signature depends on the order of the first plurality of signal sets.

[0137] Example 30 includes the subject matter of any of Examples 22-29, wherein the first signature does not depend on the order of the first plurality of signal sets.

[0138] Example 31 includes the subject matter of any of Examples 22-30, wherein the instructions, when executed, further cause the machine to generate a first counter value indicating the number of signal sets used to generate the first signature and provide the first counter value for comparison with a second counter value indicating the number of signal sets used to generate the second signature.

[0139] Example 32 includes the subject matter of any of Examples 22-31, wherein the first plurality of sets of signals includes signals communicating one or more of at least one data bit, at least one address bit, or at least one control bit.

[0140] Example 33 includes the subject matter of any of Examples 22-32, wherein the signature generation is performed by an accumulator, a multiple-input shift register, or a linear feedback shift register.

[0141] Example 34 includes a system comprising: means for generating a first signature based on a first plurality of sets of signals communicated over a bus during a first set of transactions; means for generating a second signature based on a second plurality of sets of signals communicated over the bus during a second set of transactions; and means for comparing the first signature and the second signature to determine whether a data corruption error has occurred.

[0142] Example 35 includes the subject matter of example 34, further including means for incrementing an event counter associated with the first signature each time the first signature is updated based on a set of signals.

[0143] Example 36 includes the subject matter of any of Examples 34 and 35, further including means for reporting the data corruption error via a debugger interface.

[0144] Example 37 includes the subject matter of any of Examples 34-36, further including means for compressing the first plurality of signal sets to generate a plurality of compressed signal sets, and the first signature is based on the plurality of compressed signal sets.

[0145] Example 38 includes the subject matter of any of Examples 34-37, wherein the first signature depends on the order of the plurality of signal sets.

[0146] Example 39 includes the subject matter of any of Examples 34-38, wherein the first signature does not depend on the order of the plurality of signal sets.

[0147] Example 40 includes the subject matter of any of Examples 34 to 39, further including means for generating a first counter value indicative of the number of signal sets used to generate the first signature, and means for providing the first counter value for comparison with a second counter value indicative of the number of signal sets used to generate the second signature.

[0148] Example 41 includes the subject matter of any of Examples 34-40, wherein the first plurality of sets of signals includes signals communicating one or more of at least one data bit, at least one address bit, or at least one control bit.

[0149] Example 42 includes the subject matter of any of Examples 34-41, wherein the signature generation is performed by an accumulator, a multiple-input shift register, or a linear feedback shift register.

[0150] Throughout this specification, a reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0151] In the foregoing specification, the detailed description has been given with reference to certain exemplary embodiments. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings should be considered in an illustrative, rather than a restrictive, sense. Furthermore, the above use of the terms embodiment and other descriptions does not necessarily refer to the same embodiment or the same example, but may refer to multiple different, separate, and potentially identical, embodiments. Other possible items [Item 1] a bus that communicates multiple sets of signals in multiple transactions; a first circuit for generating a first signature based on the plurality of sets of signals communicated by the bus, wherein the first circuit updates the signature based on a current value of the signature and a valid set of incoming signals; and a second circuit for providing the first signature for comparison with a second signature; An apparatus comprising: [Item 2] Item 10. The apparatus of item 1, wherein the first signature is dependent on the order of the plurality of signal sets. [Item 3] Item 10. The apparatus of item 1, wherein the first signature is independent of the order of the plurality of signal sets. [Item 4] Item 10. The apparatus of claim 1, further comprising: a third circuit that generates a first counter value indicative of the number of signal sets used to generate the first signature; and a fourth circuit that provides the first counter value for comparison with a second counter value indicative of the number of signal sets used to generate the second signature. [Item 5] Item 10. The apparatus of item 1, wherein the first circuit further generates a second signature based on a second plurality of sets of signals communicated by the bus. [Item 6] Item 10. The apparatus of item 1, further comprising a third circuit that generates a second signature based on a second plurality of sets of signals communicated by the bus. [Item 7] Item 10. The apparatus of item 1, wherein the plurality of sets of signals comprises signals communicating one or more of: at least one or more data bits, at least one address bit, or at least one control bit. [Item 8] Item 10. The apparatus of item 1, further comprising a third circuit that compresses at least some of the signals of the plurality of signal sets to generate a plurality of compressed signal sets, wherein the first signature is based on the plurality of compressed signal sets. [Item 9] Item 10. The apparatus of item 8, wherein the third circuit comprises an XOR tree. [Item 10] Item 10. The apparatus of item 1, wherein the first circuit includes one or more of an accumulator, a multiple-input shift register, or a linear feedback shift register to generate the first signature. [Item 11] Item 10. The apparatus of item 1, further comprising a processor having the bus. [Item 12] Item 12. The device of item 11, further comprising one or more of a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor. [Item 13] generating a first signature based on a first plurality of sets of signals communicated over the bus in a first set of transactions; generating a second signature based on a second plurality of sets of signals communicated over the bus during a second set of transactions; and comparing the first signature and the second signature to determine if a data corruption error occurred. A method comprising: [Item 14] Item 14. The method of item 13, further comprising incrementing an event counter associated with the first signature each time the first signature is updated based on a set of signals. [Item 15] Item 14. The method of item 13, further comprising reporting the data corruption error via a debugger interface. [Item 16] Item 14. The method of item 13, further comprising compressing the first plurality of signal sets to generate a plurality of compressed signal sets, wherein the first signature is based on the plurality of compressed signal sets. [Item 17] At least one machine-readable storage medium having stored thereon instructions that, when executed by a machine, cause the machine to: generating a first signature based on a first plurality of sets of signals communicated by a bus, wherein the first plurality of sets of signals are communicated by the bus at different clock cycles; generating a second signature based on a second plurality of sets of signals communicated by the bus, wherein the second plurality of sets of signals are communicated by the bus at different clock cycles; and providing the first signature and the second signature for comparison to determine whether a data corruption error has occurred; At least one machine-readable storage medium. [Item 18] Item 18. The at least one machine-readable storage medium of item 17, wherein the instructions, when executed, further cause the machine to filter transactions on the bus used to generate the first signature. [Item 19] Item 18. The at least one machine-readable storage medium of item 17, wherein the instructions, when executed, further cause the machine to perform a comparison of the first signature and the second signature. [Item 20] 20. The at least one machine-readable storage medium of claim 17, wherein the instructions, when executed, further cause the machine to read the first signature and the second signature from at least one memory of the machine.

Claims

1. a bus for communicating multiple sets of signals in multiple transactions; a first circuit for generating a first signature based on the plurality of sets of signals communicated by the bus, wherein the first circuit updates the signature based on a current value of the signature and a valid set of incoming signals; and a second circuit for providing the first signature for comparison with a second signature; An apparatus comprising:

2. The apparatus of claim 1 , wherein the first signature is dependent on an order of the plurality of sets of signals.

3. The apparatus of claim 1 , wherein the first signature is independent of the order of the plurality of signal sets.

4. 4. The apparatus of claim 1, further comprising: a third circuit for generating a first counter value indicative of the number of signal sets used to generate the first signature; and a fourth circuit for providing the first counter value for comparison with a second counter value indicative of the number of signal sets used to generate the second signature.

5. The apparatus of any one of claims 1 to 3, wherein the first circuitry further generates a second signature based on a second plurality of sets of signals communicated by the bus.

6. The apparatus of any one of claims 1 to 3, further comprising a third circuit for generating a second signature based on a second plurality of sets of signals communicated by the bus.

7. 4. The apparatus of claim 1, wherein the plurality of sets of signals comprises signals communicating one or more of: at least one or more data bits, at least one address bit, or at least one control bit.

8. 4. The apparatus of claim 1, further comprising a third circuit for compressing at least some of the signals of the plurality of signal sets to generate a plurality of compressed signal sets, wherein the first signature is based on the plurality of compressed signal sets.

9. 9. The apparatus of claim 8, wherein the third circuit comprises an XOR tree.

10. 4. The apparatus of claim 1, wherein the first circuit comprises one or more of an accumulator, a multiple-input shift register, or a linear feedback shift register for generating the first signature.

11. The apparatus of any one of claims 1 to 3, further comprising a processor having the bus.

12. 12. The device of claim 11, further comprising one or more of a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor.

13. generating a first signature based on a first plurality of sets of signals communicated over the bus in a first set of transactions; generating a second signature based on a second set of signals communicated over the bus during a second set of transactions; and comparing the first signature and the second signature to determine if a data corruption error occurred. A method comprising:

14. 14. The method of claim 13, further comprising incrementing an event counter associated with the first signature each time the first signature is updated based on a set of signals.

15. 15. The method of claim 13 or 14, further comprising reporting the data corruption error via a debugger interface.

16. 15. The method of claim 13 or 14, further comprising compressing the first plurality of signal sets to generate a plurality of compressed signal sets, wherein the first signature is based on the plurality of compressed signal sets.

17. 15. The method of claim 13 or 14, wherein the first signature depends on the order of the first plurality of signal sets.

18. To the machine: generating a first signature based on a first plurality of sets of signals communicated over a bus, wherein the first plurality of sets of signals are communicated over the bus at different clock cycles; generating a second signature based on a second plurality of sets of signals communicated by the bus, wherein the second plurality of sets of signals are communicated by the bus at different clock cycles; providing a first signature and a second signature for comparison to determine if a data corruption error has occurred; A computer program for executing

19. 20. The computer program product of claim 18, further causing the machine to perform the steps of filtering transactions on the bus used to generate the first signature.

20. 20. The computer program product of claim 18 or 19, further causing the machine to perform a comparison of the first signature and the second signature.

21. 20. The computer program product of claim 18 or 19, further causing the machine to perform the step of reading the first signature and the second signature from at least one memory of the machine.

22. 20. A machine-readable storage medium storing a computer program according to claim 18 or 19.

23. a bus for communicating multiple sets of signals in multiple transactions; a first means for generating a first signature based on the plurality of sets of signals communicated by the bus, wherein the first means updates the signature based on a current value of the signature and a valid incoming set of signals; and second means for providing the first signature for comparison with a second signature; A system comprising:

24. 24. The system of claim 23, wherein the first signature is dependent on an order of the plurality of signal sets.

25. 24. The system of claim 23, wherein the first signature is independent of the order of the plurality of signal sets.

26. 26. The system of claim 23, further comprising: third means for generating a first counter value indicative of the number of signal sets used to generate the first signature; and fourth means for providing the first counter value for comparison with a second counter value indicative of the number of signal sets used to generate the second signature.

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