AD conversion circuit, photoelectric converter, imaging device, and mobile unit

Abstract

This technology provides advantages in reducing the circuit size of continuous-time ΔΣ type AD conversion circuits. [Solution] An AD conversion circuit that converts an analog signal applied to an input terminal into a digital signal, comprising: a continuous-time ΔΣ type AD converter including an integration circuit for integrating a difference signal; and a switching circuit that switches the supply of an analog signal to the input terminal to the continuous-time ΔΣ type AD converter during a first period, and during a second period following the first period, a voltage signal corresponding to the voltage output from the integration circuit at the end of the first period to be supplied to the continuous-time ΔΣ type AD converter, wherein the continuous-time ΔΣ type AD converter is configured to allow gain adjustment of the analog signal input to the continuous-time ΔΣ type AD converter.

Description

Technical Field

[0001] The present invention relates to an AD conversion circuit, a photoelectric conversion device, an imaging device, and a moving body.

Background Art

[0002] An analog-to-digital converter (ADC) that converts an analog signal of pixel output in a solid-state imaging device into a digital signal is known. Also, a ΔΣ type ADC is known as an ADC. In Non-Patent Document 1, a two-stage continuous-time ΔΣ type ADC is disclosed as a technique for speeding up a second-order continuous-time ΔΣ type ADC. In this two-stage continuous-time ΔΣ type ADC, an ADC that performs AD conversion corresponding to a higher-order bit string and an ADC that performs AD conversion corresponding to a lower-order bit string with the residual voltage of the ADC corresponding to the higher-order bit as an input are connected in cascade.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Non-Patent Documents

[0004]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] A two-stage continuous-time ΔΣ ADC is a useful technology for achieving high-speed A / D conversion while reducing the drive load on the pixel output. On the other hand, because it requires an ADC that performs A / D conversion corresponding to the higher bit sequence and another ADC that performs A / D conversion corresponding to the lower bit sequence, the circuit implementation area becomes large.

[0006] The present invention aims to provide a technology that is advantageous for reducing the circuit size of a continuous-time ΔΣ type AD conversion circuit. [Means for solving the problem]

[0007] In view of the above issues, an AD conversion circuit according to an embodiment of the present invention is an AD conversion circuit that converts an analog signal applied to an input terminal into a digital signal, comprising: a continuous-time ΔΣ type AD converter including an integration circuit for integrating a difference signal; and a switching circuit that, in a first period, supplies the analog signal supplied to the input terminal to the continuous-time ΔΣ type AD converter, and in a second period following the first period, supplies the continuous-time ΔΣ type AD converter with a voltage signal corresponding to the voltage output from the integration circuit at the end of the first period, wherein the continuous-time ΔΣ type AD converter is configured to allow gain adjustment of the analog signal input to the continuous-time ΔΣ type AD converter. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a technology that is advantageous for reducing the circuit size of a continuous-time ΔΣ type AD conversion circuit. [Brief explanation of the drawing]

[0009] [Figure 1] This figure shows an example of the configuration of the AD conversion circuit of this embodiment. [Figure 2] This figure shows an example of the configuration of the AD conversion circuit of this embodiment. [Figure 3] This figure shows an example of the configuration of the AD conversion circuit of this embodiment. [Figure 4] Figure 3 shows the operating timing of the AD conversion circuit. [Figure 5]A diagram showing a configuration example of the gain control circuit of the AD conversion circuit in FIG. 3. [Figure 6] A diagram showing a configuration example of the two-stage continuous-time ΔΣ ADC in the AD conversion circuit of FIG. 3. [Figure 7] A diagram showing another example of the integrator of the two-stage continuous-time ΔΣ ADC in FIG. 6. [Figure 8] A diagram showing a configuration example of the two-stage continuous-time ΔΣ ADC in the AD conversion circuit of FIG. 3. [Figure 9] A diagram showing a configuration example of the AD conversion circuit of this embodiment. [Figure 10] A diagram showing the operation timing of the AD conversion circuit in FIG. 9. [Figure 11] A diagram showing a configuration example of the gain control circuit of the AD conversion circuit in FIG. 9. [Figure 12] A diagram showing a configuration example of the variable amplification circuit and the buffer circuit having a voltage holding function of the AD conversion circuit in FIG. 9. [Figure 13] A diagram showing another example of the variable amplification circuit in FIG. 12. [Figure 14] A diagram showing a configuration example of the AD conversion circuit of this embodiment. [Figure 15] A diagram showing a configuration example of the variable amplification circuit of the AD conversion circuit in FIG. 14. [Figure 16] A diagram showing a configuration example of the gain control circuit of the AD conversion circuit in FIG. 14. [Figure 17] A diagram showing a configuration example of the AD conversion circuit of this embodiment. [Figure 18] A diagram showing the operation timing of the AD conversion circuit in FIG. 17. [Figure 19] A diagram showing another example of the variable amplification circuit in FIG. 15. [Figure 20] A diagram showing another example of the variable amplification circuit in FIG. 15. [Figure 21] A diagram showing a configuration example of the photoelectric conversion device including the AD conversion circuit of this embodiment. [Figure 22] A diagram showing a configuration example of the photoelectric conversion system including the AD conversion circuit of this embodiment. [Figure 23] A diagram showing a configuration example of the moving body including the AD conversion circuit of this embodiment. [Modes for carrying out the invention]

[0010] The embodiments will be described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the invention as defined in the claims. While the embodiments describe multiple features, not all of these features are essential to the invention, and the features may be combined in any way. Furthermore, in the attached drawings, identical or similar configurations are given the same reference numerals, and redundant descriptions are omitted.

[0011] The AD conversion circuit according to an embodiment of the present disclosure will be described with reference to Figures 1 to 20. Figure 1 shows the configuration of the AD conversion circuit 1 of the first embodiment of the present disclosure. The AD conversion circuit 1 is configured as a two-stage continuous-time ΔΣ type AD conversion circuit. The AD conversion circuit 1 converts the analog signal supplied to the input terminal IN into a digital signal and outputs it from the output terminal OUT. The AD conversion circuit 1 may include a continuous-time ΔΣ type AD converter 910 and a switching circuit 930. The AD conversion circuit 1 may also include a residual voltage holding circuit 920, a digital demodulation circuit 940, and a reconstruction circuit 950. The continuous-time ΔΣ type AD converter 910 may include an integration circuit that integrates the difference signal. The switching circuit 930 supplies the analog signal supplied to the input terminal IN to the continuous-time ΔΣ type AD converter 910 during the first period. Furthermore, in the second period following the first period, the switching circuit 30 supplies a voltage signal to the continuous-time ΔΣ type AD converter 910 corresponding to the voltage output from the integrating circuit of the continuous-time ΔΣ type AD converter 910 at the end of the first period. The first period is a period in which A / D conversion is performed to generate the upper bit sequence of a digital signal corresponding to the analog signal applied to the input terminal IN. The second period is a period in which A / D conversion is performed to generate the lower bit sequence of a digital signal corresponding to the analog signal applied to the input terminal IN. The upper bit sequence may consist of multiple bits. The lower bit sequence may also consist of multiple bits.

[0012] The residual voltage holding circuit 920 holds (samples) a voltage signal corresponding to the residual voltage output from the continuous-time ΔΣ type AD converter 910 at the end of the first period, and provides that voltage signal to the switching circuit 930 during the second period. The residual voltage holding circuit 920 can be controlled, for example, by a holding circuit reset signal and a sample signal.

[0013] During the first period, the continuous-time ΔΣ AD converter 910 performs A / D conversion corresponding to the upper bit sequence, and at the end of the first period, the voltage signal corresponding to the residual voltage held by the residual voltage holding circuit 920 is supplied to the continuous-time ΔΣ AD converter 910 by the switching circuit 930. Subsequently, during the second period, the continuous-time ΔΣ AD converter 910 performs A / D conversion corresponding to the lower bit sequence. The time-series ΔΣ modulated signal (upper bit sequence) output from the continuous-time ΔΣ AD converter 910 during the first period is demodulated into a multi-bit digital signal by the digital demodulation circuit 940. Similarly, the time-series ΔΣ modulated signal (lower bit sequence) output from the continuous-time ΔΣ AD converter 910 during the second period is demodulated into a multi-bit digital signal by the digital demodulation circuit 940. The reconstruction circuit 950 generates an output digital signal based on the digital signal of the upper bit sequence and the digital signal of the lower bit sequence demodulated by the digital demodulation circuit 940. The internal signals of the continuous-time ΔΣ AD converter 910 and the digital demodulation circuit 940 are reset according to the reset signal before the start of the first period and before the start of the second period. With this configuration, by using one continuous-time ΔΣ AD converter 910 and a residual voltage holding circuit 920, the AD conversion circuit 1 can be realized as a two-stage continuous-time ΔΣ AD conversion circuit. In other words, the circuit size of the continuous-time ΔΣ AD conversion circuit is reduced.

[0014] Figure 2 shows a modified version of the AD conversion circuit 1 shown in Figure 1. In the AD conversion circuit 1 shown in Figure 2, the residual voltage holding circuit 920 shown in Figure 1 is replaced with a buffer circuit 970 that has a residual voltage holding function. In Figure 2, the digital demodulation circuit 940 and the reconstruction circuit 950, which are located after the continuous-time ΔΣ type AD converter 910, are omitted from the description.

[0015] The buffer circuit 970, which has a residual voltage holding function, can be controlled, for example, by a holding circuit reset signal and a sample signal. The buffer circuit 970 buffers the output of the switching circuit 930 and supplies it to the continuous-time ΔΣ type AD converter 910. During the first period, while the continuous-time ΔΣ type AD converter 910 performs A / D conversion corresponding to the higher bit sequence, the buffer circuit 970 buffers the analog input signal selected by the switching circuit 930 and supplies it to the continuous-time ΔΣ type AD converter 910. After performing A / D conversion corresponding to the higher bit sequence, the buffer circuit 970 samples and holds the residual voltage output from the continuous-time ΔΣ type AD converter 910 during or after the A / D conversion corresponding to the higher bits. Subsequently, the held residual voltage signal is input to the continuous-time ΔΣ type AD converter 910 via the switching circuit 930 and the buffer circuit 970 with a residual voltage holding function, and A / D conversion corresponding to the lower bit sequence is performed.

[0016] In a continuous-time ΔΣ AD converter 910, a voltage-to-current conversion circuit composed of resistive elements is generally used as the input to the integrator. Therefore, a DC current corresponding to the voltage of the input analog signal flows through the voltage-to-current conversion circuit. For example, when a source follower circuit is used as the circuit that supplies the analog signal to the continuous-time ΔΣ AD converter 910, a DC current corresponding to the analog signal voltage flows in addition to the bias current of the source follower circuit. Therefore, a gain deviation occurs in the source follower circuit, and the linearity of the input analog signal may deteriorate. As shown in the configuration in Figure 2, by adding a buffer circuit 970 to the input path of the analog signal, the DC current flowing in the source follower circuit according to the voltage value of the input analog signal is suppressed. This makes it possible to improve the deterioration of the linearity of the input analog signal. In addition, by sharing the residual voltage retention circuit and the buffer circuit amplifier, it becomes possible to improve linearity without increasing the number of circuit components or power.

[0017] Incidentally, in the readout circuit of an imaging device using a ΔΣ type AD converter, there is a need to reduce the noise of the analog signal output from pixels in low light conditions and achieve high image quality without increasing the oversampling rate of the AD converter. As a technology to achieve this, Patent Document 1 describes a solid-state image sensor equipped with a variable gain amplifier circuit that allows gain adjustment according to the input amplitude in the preceding stage of the ΔΣ type AD converter. The amplification effect of the analog signal using the variable gain amplifier circuit suppresses the noise of the subsequent ΔΣ type AD converter, thereby reducing noise. However, adding an amplifier circuit as shown in Patent Document 1 may increase the power consumption of the readout circuit.

[0018] Figure 3 is a block diagram showing an example configuration of the AD conversion circuit 1 of this embodiment. The AD conversion circuit 1 is configured as a two-stage continuous-time ΔΣ type AD conversion circuit, similar to the configurations shown in Figures 1 and 2. The AD conversion circuit 1 converts the analog signal applied to the input terminal IN into a digital signal and outputs it from the output terminal OUT. The AD conversion circuit 1 may include a continuous-time ΔΣ type AD converter 10 with a gain adjustment function, a switching circuit 30, and a gain control circuit 50 as a control circuit for controlling the gain adjustment function of the continuous-time ΔΣ type AD converter 10. The AD conversion circuit 1 may also include a buffer circuit 20. Furthermore, the AD conversion circuit 1 may include a digital demodulation circuit 940 and a reconstruction circuit 950 after the continuous-time ΔΣ type AD converter 10, but these are omitted from Figure 3. The configuration of the buffer circuit 20 and the switching circuit 30 may be the same as that of the buffer circuit 970 and the switching circuit 930 described above.

[0019] The switching circuit 30 controls the switching between the input analog signal and the output signal of the buffer circuit 20, which has a voltage holding function. The buffer circuit 20 receives the analog signal selected by the switching circuit 30, and the buffer circuit 20 outputs the buffered signal to the continuous-time ΔΣ type AD converter 10. The continuous-time ΔΣ type AD converter 10 performs A / D conversion on the buffered signal using a set gain controlled by the gain control circuit 50, corresponding to the higher bits. The switching control of the switching circuit 30 can be controlled by a switching signal.

[0020] During or after the A / D conversion corresponding to the higher bit sequence, the buffer circuit 20, which has a voltage holding function, samples and holds the residual voltage output from the continuous-time ΔΣ type AD converter 10. The buffer circuit 20 may be controlled by a holding circuit reset signal and a sample signal. After the A / D conversion corresponding to the higher bit sequence, the residual voltage held by the buffer circuit 20 with the voltage holding function is selected by the switching circuit 30, and the buffered signal is supplied to the continuous-time ΔΣ type AD converter 10. Subsequently, the continuous-time ΔΣ type AD converter 10 performs A / D conversion corresponding to the lower bit sequence according to the set gain supplied by the gain control circuit 50.

[0021] The time-series ΔΣ modulated signals output during the A / D conversion period corresponding to the upper and lower bit sequences are demodulated into multi-bit digital signals by the digital demodulation circuit 940. The multi-bit demodulated signals are input to the reconstruction circuit 950 after the conversion of the upper and lower bit sequences to obtain a digital output signal. The internal signals of the continuous-time ΔΣ AD converter 10 and the holding voltage of the buffer circuit 20 can be reset using a reset signal before the start of the A / D conversion corresponding to the upper and lower bit sequences, respectively.

[0022] In the AD conversion circuit 1 shown in Figure 3, the gain adjustment of the input analog signal is performed in the continuous-time ΔΣ type AD converter 10. In other words, the continuous-time ΔΣ type AD converter 10 is configured to allow gain adjustment of the analog signal input to it. By adjusting the gain according to the signal amplitude of the input analog signal, the quantization error of the continuous-time ΔΣ type AD converter 10 for the analog signal output from pixels in low light conditions can be reduced. For example, if the set gain controlled by the gain control circuit 50 is G, and the quantization noise of the continuous-time ΔΣ type AD converter 10 is V qn_ADC In this case, assuming that an analog signal appropriately adjusted to match the maximum value of the input signal range in the continuous-time ΔΣ type AD converter 10 is input, the input-referred noise V n_in This can be found using equation (1).

[0023]

number

[0024] The configuration shown in Figure 3 eliminates the need for the variable gain amplifier circuit required in Patent Document 1. Therefore, it is possible to reduce the circuit size of the continuous-time ΔΣ type AD conversion circuit 1 while further reducing power consumption.

[0025] Figure 4 shows the operating timing of the continuous-time ΔΣ type AD converter 10 with the gain adjustment function shown in Figure 2. As an example of the operation of the two-stage continuous-time ΔΣ type AD converter 10, the processing flow in which the reconstruction circuit 950 outputs the final ADC result (0) will be explained.

[0026] Between time t1 and time t2, the reset signal becomes high, and the continuous-time ΔΣ AD converter 10 with gain adjustment function and the digital demodulation circuit 940 are reset. Simultaneously, the hold circuit reset signal becomes high, and the buffer circuit 20 with voltage hold function is reset. At time t1, the switching signal becomes low, and the buffered analog signal is supplied from the input terminal IN to the continuous-time ΔΣ AD converter 10 with gain adjustment function via the buffer circuit 20. At time t2, from the moment the reset signal becomes low, the continuous-time ΔΣ AD converter 10 starts A / D conversion corresponding to the upper bit sequence, and the buffer circuit 20 with voltage hold function starts sampling the residual voltage. Furthermore, the digital demodulation circuit 940 starts demodulation processing of the upper bit sequence. At time t3, after the completion of A / D conversion corresponding to the upper bit sequence, the buffer circuit 20 with voltage hold function starts holding the residual voltage of the continuous-time ΔΣ AD converter 10 with gain adjustment function. Simultaneously, the reconstruction circuit 950 acquires a multi-bit demodulated signal corresponding to the higher bit sequence. Also, at time t3, the switching signal becomes high level, and the residual voltage after buffering is supplied to the continuous-time ΔΣ type AD converter 10, which has a gain adjustment function.

[0027] Next, during the period from time t3 to time t4, the reset signal becomes high again, and the continuous-time ΔΣ AD converter 10 with gain adjustment function and the digital demodulation circuit 940 are reset. At time t4, from the moment the reset signal becomes low, the continuous-time ΔΣ AD converter 10 with gain adjustment function starts A / D conversion corresponding to the lower bit sequence, and the digital demodulation circuit 940 starts demodulation processing of the lower bit sequence.

[0028] At time t5, after the completion of the A / D conversion corresponding to the lower bit sequence, the reconstruction circuit 950 acquires a multi-bit demodulated signal corresponding to the lower bit sequence. Subsequently, the reconstruction circuit 950 performs reconstruction processing using the multi-bit demodulated signal corresponding to the upper bit sequence and the multi-bit demodulated signal corresponding to the lower bit sequence. As a result, the final A / D conversion result corresponding to the digital output signal is output.

[0029] The continuous-time ΔΣ type AD converter 10, which has a gain adjustment function, performs ΔΣ A / D conversion on an input signal whose gain has been adjusted according to the set gain supplied by the gain control circuit 50 when the switching signal is at a low level. When the switching signal is at a high level, the continuous-time ΔΣ type AD converter 10 performs ΔΣ A / D conversion on an input signal whose gain has been adjusted with a set gain of 1. In other words, the continuous-time ΔΣ type AD converter 10 does not perform gain adjustment when the switching signal is at a high level.

[0030] During the period in which A / D conversion is performed corresponding to the higher bit sequence, the analog signal input to the continuous-time ΔΣ type AD converter 10 may be gain-adjusted. However, during the period in which A / D conversion is performed corresponding to the lower bit sequence, the analog signal input to the continuous-time ΔΣ type AD converter 10 does not need to be gain-adjusted (gain adjustment of 1x). For example, the set gain may be 2x, 4x, 8x, 16x, etc., and the analog signal input to the continuous-time ΔΣ type AD converter 10 may be amplified. The set gain set by the gain control circuit 50 may be, for example, around 1 to 8x. However, it is not limited to this, and the set gain set by the gain control circuit 50 may be 0.5x or less, such as 1x.

[0031] The AD conversion circuit 1 performs A / D conversion on any input analog signal by repeatedly performing the above A / D conversion. Here, it is assumed that the input analog signal during the A / D conversion period corresponding to the aforementioned higher bit sequence is constant.

[0032] Figure 5 shows an example configuration of the gain control circuit 50. The gain control circuit 50 may include a multiplexer 520. The multiplexer 520 is controlled by a switching signal to select between a gain adjustment signal and a gain of 1, and its output is input as the set gain to a continuous-time ΔΣ type AD converter 10 which has a gain adjustment function. The continuous-time ΔΣ type AD converter 10 performs gain adjustment on the analog signal supplied according to the set gain.

[0033] Figure 6 shows an example configuration of a continuous-time ΔΣ type AD converter 10 having a gain adjustment function. The continuous-time ΔΣ type AD converter 10 may be, for example, a second-order continuous-time ΔΣ type AD converter. The continuous-time ΔΣ type AD converter 10 includes, as an integrating circuit, a first integrator 110 and a second integrator 120 connected to the output of the first integrator 110. The continuous-time ΔΣ type AD converter 10 also includes a comparator 130 that compares the output of the second integrator 120 with a reference signal and a DA converter 140 connected to the output of the comparator 130. The first integrator 110 includes a variable resistor 113 connected to the output of the switching circuit 30, an amplification circuit 116 connected to the output of the variable resistor 113, and a resistor 112 placed between the node between the variable resistor 113 and the amplification circuit 116 and the output of the DA converter 140. The amplification circuit 116 includes an amplifier 111, a capacitor 114, and a switch 115 connected in parallel with each other.

[0034] The output of the DA converter 140 is input to the first integrator 110 and the second integrator. The output of the second integrator 120 is output as the residual voltage of the continuous-time ΔΣ type AD converter 10, which has a gain adjustment function.

[0035] In the continuous-time ΔΣ AD converter 10 shown in Figure 6, the first integrator 110 and the second integrator 120 are reset when the reset signal is high level. For example, the first integrator 110 is reset by shorting the capacitor 114 with the switch 115. When the reset signal is low level, the first integrator 110 integrates the difference voltage between the input analog signal and the output of the DA converter 140. The variable resistor 113 is adjusted by the set gain supplied from the gain control circuit 50. Therefore, the ratio of resistor 112 and variable resistor 113 is calculated for the input analog signal.

[0036] Furthermore, the second integrator 120 integrates the difference voltage between the output voltage of the first integrator 110 and the output of the DA converter 140. The comparator 130 compares the difference voltage between the output voltage of the second integrator 120 and a reference voltage (e.g., ground voltage) using a clock signal (not shown). The DA converter 140 outputs an analog voltage corresponding to the output signal of the comparator 130. The DA converter 140 may be configured to output an analog voltage corresponding to the input signal according to a 1-bit transfer function shown in equation (2), for example.

[0037]

number

[0038] In the configuration shown in Figure 6, the continuous-time ΔΣ AD converter 10 is configured to allow gain adjustment of the analog signal input to the continuous-time ΔΣ AD converter 10 by providing a variable resistor 113 in the first integrator 110. The gain control circuit 50 is a control circuit that controls the amount of gain adjustment by controlling the resistance value of the variable resistor 113. In the configuration shown in Figure 6, the second integrator 120 may have the same configuration as the first integrator 110. In that case, the variable resistor 113 provided in the second integrator 120 may have a constant resistance value. In other words, the second integrator 120 may have a configuration in which the variable resistor 113 of the first integrator 110 is a normal resistor.

[0039] In the configuration shown in Figure 6, the AD conversion circuit 1 is configured as a second-order continuous-time ΔΣ type AD conversion circuit. Also, in the example in Figure 6, the AD conversion circuit 1 has a 1-bit configuration for both the comparator 130 and the DA converter 140. However, the comparator 130 and DA converter 140 may be configured with multiple bits, and the resistors of the first integrator 110 and the second integrator 120 (corresponding to resistor 112) may be increased according to the resolution of the comparator 130 and DA converter 140, and connected in parallel. By configuring the comparator 130 and DA converter 140 with multiple bits, the A / D conversion speed of the continuous-time ΔΣ type AD converter 10 can be increased. Furthermore, by adding one or more integrators between the second integrator 120 and the comparator 130, a third-order or higher continuous-time ΔΣ type AD converter may be configured. By increasing the number of integrators, the A / D conversion speed of the continuous-time ΔΣ type AD converter 10 can be increased.

[0040] Figure 7 shows a Gm-C type integrator 310 as another example of an integrator configuration in the continuous-time ΔΣ type AD converter 10. The integrator 310 may include switches 1401 and 1402, a capacitor 1403, a transconductor 1404, and an inverter 1405. Switch 1401 is controlled by a reset signal, and switch 1402 is controlled by the reset signal inverted by the inverter 1405. When the reset signal is high level, the capacitor 1403 is reset. When the reset signal is low level, integration is performed by the difference current between the current generated by the transconductor 1404 in response to the input signal and the output signal current of the DA converter 190, and the capacitor 1403. When the Gm-C type integrator 310 is used as the first integrator 110, the output of the DA converter 140 is connected to the output of the transconductor 1404. In this configuration, power consumption can be reduced while achieving the same functionality as an integrator composed of resistors, capacitors, and amplifiers. Furthermore, by making capacitor 1403 a variable capacitor, the Gm-C type integrator 310 can be applied to the first integrator 110. In other words, the first integrator 110 may be a Gm-C type integrator including a transconductor and a variable capacitor. In that case, the gain control circuit 50 is a control circuit that controls the amount of gain adjustment by controlling the capacitance value of capacitor 1403, which is a variable capacitor.

[0041] Figure 8 shows another configuration example of a continuous-time ΔΣ type AD converter 10 with a gain adjustment function. The continuous-time ΔΣ type AD converter 10 shown in Figure 8 has a feedforward path. More specifically, the continuous-time ΔΣ type AD converter 10 may include a first integrator 110, a second integrator 120, a four-input comparator 150, and a DA converter 140. The first integrator 110 may have a configuration similar to that shown in Figure 6, for example. In the continuous-time ΔΣ type AD converter 10 shown in Figure 8, the comparator 150 compares the output of the first integrator 110, the output of the second integrator 120, and the analog signal supplied to the first integrator 110 with a reference signal. Thus, the continuous-time ΔΣ type AD converter 10 has a feedforward mechanism. The continuous-time ΔΣ type AD converter 10 with a feedforward path is realized by connecting the analog signal input to the first integrator 110 to the comparator 150. In this configuration, it is possible to suppress the output signal amplitudes of the first integrator 110 and the second integrator 120, respectively. By suppressing the influence of the nonlinearity of the amplifier 111 in the first integrator and the amplifier in the second integrator, the nonlinear distortion characteristics of the continuous-time ΔΣ type AD converter 10 can be improved.

[0042] Figure 9 shows a modified version of the AD conversion circuit 1 shown in Figure 3. In addition to the configuration shown in Figure 3, the AD conversion circuit 1 shown in Figure 9 further includes a variable amplification circuit 40 between the input terminal IN and the switching circuit 30. The continuous-time ΔΣ type AD converter 10 may include a digital demodulation circuit 940 and a reconstruction circuit 950 after the continuous-time ΔΣ type AD converter 910, but these are omitted from Figure 9.

[0043] The variable amplifier circuit 40 amplifies the analog signal supplied to it and outputs the amplified analog signal. The switching circuit 30 switches between the analog signal amplified by the variable amplifier circuit 40 and the output signal of the buffer circuit 20, which has a voltage holding function, and supplies them to the buffer circuit 20. The buffer circuit 20 is supplied with the analog signal selected by the switching circuit 30, and the buffered signal is supplied to the continuous-time ΔΣ type AD converter 10.

[0044] The continuous-time ΔΣ type A / D converter 10 performs A / D conversion on the signal, which is amplified by the variable amplifier circuit 40 and buffered by the buffer circuit 20, according to the set gain of the gain control circuit 50, for the signal corresponding to the upper bit sequence. The switching control of the switching circuit 30 can be performed by a switching signal. During or after the A / D conversion corresponding to the upper bit sequence, the buffer circuit 20, which has a voltage holding function, samples and holds the residual voltage output from the continuous-time ΔΣ type A / D converter 10. The buffer circuit 20, which has a voltage holding function, can be controlled by a holding circuit reset signal and a sample signal. After the A / D conversion corresponding to the upper bit sequence is performed, the residual voltage held by the buffer circuit 20 is selected by the switching circuit 30, and the buffered signal is supplied to the continuous-time ΔΣ type A / D converter 10 after passing through the buffer circuit 20. Subsequently, the continuous-time ΔΣ type A / D converter 10 performs A / D conversion corresponding to the lower bit sequence according to the set gain of the gain control circuit 50. The time-series ΔΣ modulated signals output during the A / D conversion period corresponding to the upper and lower bit sequences are demodulated into multi-bit digital signals by the digital demodulation circuit 940. These multi-bit demodulated signals are then supplied to the reconstruction circuit 950 after the conversion of the upper and lower bit sequences to obtain the digital output signal. The variable amplifier circuit 40 is reset internally by an auto-zero signal. Furthermore, the internal signals of the continuous-time ΔΣ AD converter 10 and the holding voltage of the buffer circuit 20 with voltage holding function are reset using a reset signal before the start of the A / D conversion corresponding to the upper and lower bit sequences, respectively.

[0045] In the configuration shown in Figure 9, the gain adjustment function of the analog signal input to the AD conversion circuit 1 can be distributed between the variable amplifier circuit 40 and the continuous-time ΔΣ type AD converter 10. Even in a configuration where gain adjustment is distributed, the quantization error of the continuous-time ΔΣ type AD converter 10 for the pixel output analog signal in low light conditions can be reduced by performing gain adjustment according to the input signal amplitude. In addition, the configuration shown in Figure 9 can also suppress noise of the continuous-time ΔΣ type AD converter 10 other than quantization noise. For example, if the set gain of the variable amplifier circuit 40 is G1, the set gain of the two-stage continuous-time ΔΣ type AD converter 10 with a gain adjustment function is G2, and the circuit noise voltage at a set gain of 1 for part of the variable amplifier circuit 40 and the continuous-time ΔΣ type AD converter 10 is V n_ADC The quantization noise of the continuous-time ΔΣ type AD converter 10 is V qn_ADC In this case, assuming that an analog signal appropriately adjusted to match the maximum value of the input signal range in the continuous-time ΔΣ type AD converter 10 is input, the input-referred noise V n_in This can be found using equation (3).

[0046]

number

[0047] By distributing the gain settings of the analog signals output from pixels, etc., the maximum gain setting value of the variable amplifier circuit 40 can be reduced. Therefore, compared to a configuration in which gain adjustment is performed with a single variable amplifier circuit 40 or a continuous-time ΔΣ type AD converter 10 with a gain adjustment function, power consumption can be reduced. Furthermore, some circuit noise can be reduced. For example, the set gain in the variable amplifier circuit 40 set by the gain control circuit 50 may be 2x, 4x, 8x, 16x, etc., similar to the continuous-time ΔΣ type AD converter 10. The set gain may be, for example, around 1 to 8x. However, it is not limited to this, and the set gain set in the variable amplifier circuit 40 by the gain control circuit 50 may be 0.5x or less, or 1x or less. The gain set in the variable amplifier circuit 40 may be set high when imaging under dark conditions and low when imaging under bright conditions.

[0048] Figure 10 shows the operating timing diagram of the AD conversion circuit 1, which includes the continuous-time ΔΣ type AD converter 10 and the variable amplifier circuit 40, both of which have the gain adjustment function shown in Figure 9. The basic operation of the continuous-time ΔΣ type AD converter 10 is the same as described above.

[0049] Between time t3 and time t5, the auto-zero signal becomes high, and the variable amplifier circuit 40 performs auto-zero operation. From the time the auto-zero signal becomes low until the next auto-zero signal becomes high, the variable amplifier circuit 40 amplifies the signal according to the first set gain supplied by the gain control circuit 50. The time when the auto-zero signal becomes low can be determined by considering the period during which the output voltage of the variable amplifier circuit 40 completes the desired amplification operation before the continuous-time ΔΣ type AD converter 10, which has a gain adjustment function, starts A / D conversion corresponding to the higher bit sequence.

[0050] The continuous-time ΔΣ type AD converter 10, which has a gain adjustment function, performs A / D conversion on an input signal whose gain has been adjusted according to a second set gain supplied from the gain control circuit 50 when the switching signal is at a low level, and performs A / D conversion on an input signal whose gain has been adjusted with a set gain of 1 when the switching signal is at a high level. The continuous-time ΔΣ type AD converter 10 performs A / D conversion on an analog input signal with any gain adjustment by repeating the above A / D conversion flow. Here, it is assumed that the input analog signal during the A / D conversion period corresponding to the above-mentioned upper bit sequence is constant.

[0051] Figure 11 shows an example configuration of a gain control circuit 50 corresponding to the AD conversion circuit 1 shown in Figure 9. The gain control circuit 50 may include a gain separation circuit 510 and a multiplexer 520. One output of the gain separation circuit 510 is supplied to the variable amplifier circuit 40 as a first set gain, and the other output is supplied to the multiplexer 520. The multiplexer 520 is controlled by a switching signal to select between the output of the gain separation circuit 510 and a gain of 1, and the output of the multiplexer 520 is supplied to the continuous-time ΔΣ type AD converter 10, which has a gain adjustment function, as a second set gain.

[0052] Figure 12 shows an example configuration of a variable amplifier circuit 40 and a buffer circuit 20 with a voltage holding function. The variable amplifier circuit 40 includes a capacitor 420 and an amplifier 410, a switch 440, and a variable capacitor 430 connected to the output of the capacitor 420 and arranged in parallel with each other. When the auto-zero signal is high level, the input and output of the amplifier 410 are short-circuited and the variable capacitor 430 is reset. During auto-zero operation, the difference between the analog input signal and the voltage when the input and output of the amplifier 410 are short-circuited is sampled by the capacitor 420. When the auto-zero signal is low level, the variable amplifier circuit 40 performs amplification operation on the difference voltage between the analog input signal in auto-zero operation and the analog input signal in amplification operation. The amplification factor is determined by the ratio of the capacitor 420 to the variable capacitor 430, under the condition that the finite DC gain of the amplifier circuit >> 1. The variable capacitor 430 is controlled according to a first set gain supplied from the gain control circuit 50.

[0053] The buffer circuit 20, which has a voltage holding function, may include an amplifier 210 and a voltage holding circuit 220. The amplifier 210 is a voltage follower circuit in which one input and output are connected. Under the condition that the finite DC gain of the amplifier circuit >> 1, it drives the input signal without attenuation. The voltage holding circuit 220 resets the holding voltage when the holding circuit reset signal is high level. It samples the residual voltage during the period when the holding circuit reset signal is low level and the sample signal is high level. When the sample signal is low level, the voltage holding circuit 220 holds the sampled residual voltage and outputs it.

[0054] Figure 13 shows another configuration example of the variable amplifier circuit 40. The variable amplifier circuit 40 includes a capacitor 420, an amplifier 450 connected to the output of the capacitor 420 and arranged in parallel with each other, a switch 440, and a variable capacitor 430. The variable amplifier circuit 40 also includes a switch 470 arranged between the output of the variable capacitor 430 and the output of the amplifier 450, a switch 460 arranged between the output of the variable capacitor 430 and a reference signal (internal reference voltage), and an inverter 408. The amplifier 450 constitutes a single-ended amplifier. When the auto-zero signal is high level, the input and output of the amplifier 450 are short-circuited, and the variable capacitor 430 is reset by the voltage when it is short-circuited and the reference signal. During auto-zero operation, the difference between the analog input signal and the voltage when the input and output of the amplifier 450 are short-circuited is sampled in the capacitor 420. When the auto-zero signal is low level, the variable amplifier circuit 40 performs amplification operation on the difference voltage between the analog input signal in auto-zero operation and the analog input signal in amplification operation. The amplification factor is determined by the ratio of capacitance 420 to variable capacitance 430, under the condition that the finite DC gain of the amplification circuit >> 1. In this case, the output voltage after amplification by amplifier 450 will oscillate around the reference signal. Here, variable capacitance 430 is controlled according to the first set gain supplied from gain control circuit 50, similar to the configuration shown in Figure 12. The variable amplification circuit 40 shown in Figure 13 can reduce power consumption compared to the configuration shown in Figure 12 by utilizing a single-ended amplifier.

[0055] Figure 14 shows the configuration of the AD conversion circuit 1 of the second embodiment of this disclosure. Compared to the configuration shown in Figure 9, a variable amplifier circuit 60 for internal signals is added. It amplifies the analog signal input to the switching circuit 30 from the input terminal IN. In this embodiment, the continuous-time ΔΣ type AD converter 10 may be an AD converter having a feedforward path as shown in Figure 8.

[0056] The variable amplifier circuit 40 adjusts the gain of the input analog signal according to the gain setting supplied by the gain control circuit 50, and outputs, for example, an amplified analog signal. The switching circuit 30 controls the switching between the analog signal whose gain has been adjusted by the variable amplifier circuit 40 and the output signal of the buffer circuit 20, which has a voltage holding function. The buffer circuit 20 is supplied with the analog signal selected by the switching circuit 30 and outputs the buffered analog signal. The variable amplifier circuit 60 for the internal signal adjusts the gain of the analog signal whose gain has been adjusted by the variable amplifier circuit 40 according to the gain setting supplied by the gain control circuit 50, and outputs the internal signal whose gain has been adjusted. The continuous-time ΔΣ type AD converter 10, which has a feedforward path with a gain adjustment function, performs A / D conversion on the signal buffered by the buffer circuit 20, according to the internal signal whose gain has been adjusted by the variable amplifier circuit 60 and the gain setting supplied by the gain control circuit 50, corresponding to the upper bit sequence and the lower bit sequence. The switching control of the switching circuit 30 is performed by a switching signal. As shown in Figure 14, by adding a variable amplifier circuit 60 for the internal signal, continuous-time ΔΣ A / D conversion can be performed while considering the gain adjustment of the feedforward path. By using a feedforward configuration as the continuous-time ΔΣ AD converter 10, the nonlinear distortion characteristics can be improved regardless of the set gain of the variable amplifier circuit 40.

[0057] Figure 15 shows an example configuration of a variable amplifier circuit 60 for internal signals. The variable amplifier circuit 60 includes a variable resistor 166 and amplifiers 161 and 165 connected in parallel to the output of the variable resistor 166. The variable resistor 166 is connected to one input of amplifier 161, and a reference signal is connected to the other input. The resistance value of the variable resistor 166 is switched according to a second set gain supplied from the gain control circuit 50. The voltage output from the variable amplifier circuit 60 is obtained by multiplying the difference between the analog signal input to the variable amplifier circuit 60 and the reference signal by the ratio of the resistances of the variable resistor 166 and the resistor 165.

[0058] In a continuous-time ΔΣ AD converter 10 with a feedforward path, as shown in Figure 8, the output of the first integrator 110, the output of the second integrator 120, and the analog signal supplied to the first integrator 110 are compared with a reference signal. A variable amplifier circuit 60 for internal signals is located in the path for supplying the analog signal supplied to the first integrator 110 to a comparator 150. Therefore, the comparator 150 compares the output of the first integrator 110, the output of the second integrator 120, and the output of the variable amplifier circuit 60 with the reference signal. The variable amplifier circuit 60 may, for example, amplify the analog signal input to the comparator 150 shown in Figure 8 during the period when the analog signal input to the continuous-time ΔΣ AD converter 10 is gain-adjusted. Alternatively, for example, the variable amplifier circuit 60 may not amplify the analog signal during the period when the analog signal input to the continuous-time ΔΣ AD converter 10 is not gain-adjusted (the period of 1x gain). Alternatively, the gain adjustment of the variable amplifier circuit 60 may be performed by using a variable resistor connected between the input and output of amplifier 161 and a fixed resistor connected between amplifier 161 and the input of the variable amplifier circuit 60.

[0059] Figure 16 shows an example configuration of a gain control circuit 50 corresponding to the AD conversion circuit 1 shown in Figure 14. The gain control circuit 50 may include a gain separation circuit 510 and a multiplexer 520. One output of the gain separation circuit 510 is supplied to the variable amplifier circuit 40 as the first set gain, and the other output is input to the multiplexer 520 and also supplied to the variable amplifier circuit 60 for internal signals as the third set gain. The multiplexer 520 is controlled by a switching signal to select between the output of the gain separation circuit and a gain of 1. The second set gain, which is the output of the multiplexer 520, is supplied to a continuous-time ΔΣ type AD converter 10 which has a gain adjustment function and a feedforward path.

[0060] Figure 17 shows another configuration example of a continuous-time ΔΣ type AD converter 10 that has a gain adjustment function and a feedforward path. The configuration shown in Figure 17 has a separate switching circuit 160 in addition to the switching circuit 30, compared to the configuration shown in Figure 8. The switching circuit 160 switches between the output of the variable amplifier circuit 60 for amplifying the analog signal input to the switching circuit 30 from the input terminal IN and the analog signal input to the first integrator 110, and supplies them to the comparator 150. The other configurations may be the same as those in the configuration of Figure 8 described above, so similar configurations will not be explained here.

[0061] Figure 18 is a timing diagram showing an example of operation of an AD conversion circuit 1 equipped with a continuous-time ΔΣ type AD converter 10 as shown in Figure 17. The variable amplifier circuit 60 for internal signals performs auto-zero operation using a second auto-zero signal. The time when the second auto-zero signal becomes high is simultaneous with the auto-zero signal. On the other hand, the time when the second auto-zero signal becomes low is set to be later than the time when the reset signal becomes low, and earlier than the time when the auto-zero signal becomes low. In other words, the auto-zero period of the variable amplifier circuit 60 is set to be shorter than the auto-zero period of the variable amplifier circuit 40, and the variable amplifier circuit 60 amplifies the analog signal according to the third set gain supplied from the gain control circuit 50 after the auto-zero operation of the variable amplifier circuit 40. The amplified analog signal is used in the comparison operation of the 4-input comparator 150 during the period when A / D conversion corresponding to the higher bit sequence is performed. In other words, the comparator 150 compares the output of the first integrator 110, the output of the second integrator 120, and the output of the switching circuit 160 with a reference signal. In that case, the switching circuit 160 can supply the output of the variable amplifier circuit 60 to the comparator 150 during the period when the analog signal input to the continuous-time ΔΣ type AD converter 10 is gain-adjusted. On the other hand, the switching circuit 160 can supply the analog signal input to the first integrator 110 to the comparator 150 during the period when the analog signal input to the continuous-time ΔΣ type AD converter 10 is not gain-adjusted.

[0062] Figure 19 shows another configuration example of the variable amplifier circuit 60 for internal signals. The variable amplifier circuit 60 may include a capacitor 162 and an amplifier 161, a switch 164, and a variable capacitor 163 connected in parallel to the output of the capacitor 162. In the variable amplifier circuit 60 shown in Figure 19, the input and output of the amplifier 161 are shorted and reset when the second auto-zero signal is high level. During auto-zero operation, the difference between the output signal of the variable amplifier circuit 40 and the voltage when the input and output of the amplifier 161 are shorted is sampled by the capacitor 162. When the second auto-zero signal is low level, the variable amplifier circuit 60 performs amplification operation on the difference voltage between the analog signal input during auto-zero operation and the analog signal input during amplification operation. The amplification factor is determined by the ratio of the capacitor 162 to the variable capacitor 163, given that the finite DC gain of the amplifier circuit >> 1. The variable capacitor 163 is controlled according to a third set gain supplied by the gain control circuit 50.

[0063] In the circuit configuration shown in Figure 15 above, where gain adjustment is performed by the resistance ratio, a DC current continuously flows through the input resistor regardless of the circuit's operating state. On the other hand, in the circuit configuration shown in Figure 19, almost no DC current flows to the capacitor 162 after the desired amplification operation is completed. Therefore, in this circuit, in addition to improving the nonlinearity distortion characteristics of the continuous-time ΔΣ type AD converter 10 shown in Figure 14, the variable amplifier circuit 60 for the internal signal consumes less power compared to the circuit configuration shown in Figure 15.

[0064] Figure 20 shows yet another configuration example of the variable amplifier circuit 60 for internal signals. The variable amplifier circuit 60 shown in Figure 20 may include a transconductor 604 and a variable capacitor 603 connected to the output node of the transconductor 604. The variable amplifier circuit 60 may also include switches 601, 602, AND gates 605, 606, and an inverter 607. Switch 602 is connected between the variable capacitor 603 and the transconductor 604. Switch 601 is connected in parallel with the variable capacitor 603. One end of the variable capacitor 603 is connected to a reference signal. The AND gate 606 is supplied with a second auto-zero signal and a reset signal, and the output of the AND gate 606 is used as a control signal for switch 601. The AND gate 605 is supplied with a second auto-zero signal and a reset signal via inverter 607, and the output of the AND gate 605 is used as a control signal for switch 602. The capacitance value of the variable capacitor 603 is controlled according to the third set gain supplied by the gain control circuit 50.

[0065] The variable amplifier circuit 60 shown in Figure 20 resets the variable capacitor 603 when the second auto-zero signal is high and the reset signal is high. When the second auto-zero signal is high and the reset signal is low, a current corresponding to the voltage difference between the input signal and the reference signal flows from the transconductor 604 to the variable capacitor 603, thereby accumulating charge. Charge accumulation occurs during the period when the second auto-zero signal is high, and the voltage corresponding to the accumulated charge becomes the output signal. The voltage of the output signal can be adjusted by the value of the variable capacitor.

[0066] The following describes application examples of the AD conversion circuit 1 described above. Figure 21 shows the configuration of a photoelectric converter PEC using the AD conversion circuit 1 of this disclosure. The photoelectric converter PEC can be configured as a solid-state imaging device that captures and outputs an image. Alternatively, the photoelectric converter PEC can be configured as a device that captures an image and outputs a signal obtained from the captured image.

[0067] The photoelectric converter PEC may include, for example, a pixel array (an array composed of multiple photoelectric conversion units) 600, a vertical drive circuit 630, a readout circuit (current source, AD conversion circuit) 610, a control circuit 650, and a signal processing circuit 620. The readout circuit 610 may include multiple current sources connected to multiple vertical lines 640, and an AD conversion circuit that performs AD conversion on signals output from the pixels of a selected row to the multiple vertical lines 640. Each AD conversion circuit in the readout circuit 610 may be the two-stage continuous-time ΔΣ type AD conversion circuit (AD conversion circuit 1) described above. This makes it possible to miniaturize the readout circuit 610.

[0068] The photoelectric converter PEC may be configured to read a reset level and an optical signal level generated by photoelectric conversion from each pixel of the pixel array 600 using a readout circuit 610. The readout circuit 610 may be configured to output a digital signal of the reset level and a digital signal of the optical signal level. The signal processing circuit 620 may be configured to perform CDS processing on the digital signal of the reset level and the digital signal of the optical signal level, and to output the CDS-processed signal. The pixel array 600, vertical drive circuit 630, readout circuit 610, control circuit 650, and signal processing circuit 620 may be configured on a single substrate, distributed across multiple substrates and then stacked, or divided into multiple chips. The photoelectric converter PEC may be a CMOS image sensor. Furthermore, the photoelectric converter PEC may be a front-illuminated sensor or a back-illuminated sensor.

[0069] The following describes an example of a photoelectric conversion system using a photoelectric converter (PEC). Figure 22 is a block diagram showing the configuration of a photoelectric conversion system 1200 according to one embodiment. The photoelectric conversion system 1200 of this embodiment includes a photoelectric converter 1215. Here, the photoelectric converter 1215 can be fitted with the above-described photoelectric converter (PEC). The photoelectric conversion system 1200 can be used, for example, as an imaging system. Specific examples of imaging systems include digital still cameras, digital camcorders, and surveillance cameras. Figure 22 shows an example of a digital still camera (imaging device) as the photoelectric conversion system 1200.

[0070] The photoelectric conversion system 1200 shown in Figure 22 includes a photoelectric converter 1215, a lens 1213 that forms an optical image of the subject onto the photoelectric converter 1215, an aperture 1214 for varying the amount of light passing through the lens 1213, and a barrier 1212 for protecting the lens 1213. The lens 1213 and aperture 1214 form an optical system that focuses light onto the photoelectric converter 1215. A photoelectric conversion system used for imaging purposes is also called an imaging system.

[0071] The photoelectric conversion system 1200 has a signal processing unit 1216 that processes the output signal output from the photoelectric conversion device 1215. The signal processing unit 1216 performs signal processing operations that perform various corrections and compressions on the input signal as needed before outputting it. The photoelectric conversion system 1200 further has a buffer memory unit 1206 for temporarily storing image data, and an external interface unit (external I / F unit) 1209 for communicating with an external computer or the like. Furthermore, the photoelectric conversion system 1200 has a recording medium 1211 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1210 for recording or reading from the recording medium 1211. The recording medium 1211 may be built into the photoelectric conversion system 1200 or it may be detachable. In addition, communication from the recording medium control I / F unit 1210 to the recording medium 1211 and communication from the external I / F unit 1209 may be performed wirelessly.

[0072] Furthermore, the photoelectric conversion system 1200 includes an overall control and calculation unit 1208 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1217 that outputs various timing signals to the photoelectric conversion device 1215 and the signal processing unit 1216. Here, the timing signals and the like may be input from an external source, and the photoelectric conversion system 1200 only needs to include at least the photoelectric conversion device 1215 and the signal processing unit 1216 that processes the output signals output from the photoelectric conversion device 1215. The timing generation unit 1217 may be mounted on the photoelectric conversion device. The overall control and calculation unit 1208 and the timing generation unit 1217 may be configured to perform some or all of the control functions of the photoelectric conversion device 1215.

[0073] The photoelectric converter 1215 outputs an image signal to the signal processing unit 1216. The signal processing unit 1216 performs predetermined signal processing on the image signal output from the photoelectric converter 1215 and outputs image data. The signal processing unit 1216 also generates an image using the image signal. The signal processing unit 1216 may also perform distance measurement calculations on the signal output from the photoelectric converter 1215. The signal processing unit 1216 and the timing generation unit 1217 may be mounted on the photoelectric converter. In other words, the signal processing unit 1216 and the timing generation unit 1217 may be provided on the substrate on which the pixels are arranged, or they may be provided on a separate substrate. By configuring an imaging system using the photoelectric converters of each embodiment described above, an imaging system capable of acquiring higher quality images can be realized.

[0074] Other embodiments of the photoelectric conversion system or mobile device will be described with reference to Figure 23. Figure 23 is a schematic diagram showing an example of the configuration of the photoelectric conversion system or mobile device according to this embodiment. In this embodiment, an example of an in-vehicle camera is shown as the photoelectric conversion system.

[0075] Figure 23 shows an example of a vehicle system and a photoelectric conversion system mounted thereon for imaging. The photoelectric conversion system 1301 includes a photoelectric converter 1302, an image preprocessing unit 1315, an integrated circuit 1303, and an optical system 1314. The optical system 1314 forms an optical image of the subject on the photoelectric converter 1302. The photoelectric converter 1302 converts the optical image of the subject formed by the optical system 1314 into an electrical signal. The photoelectric converter 1302 may be the photoelectric converter described above. The image preprocessing unit 1315 performs predetermined signal processing on the signal output from the photoelectric converter 1302. The functions of the image preprocessing unit 1315 may be incorporated into the photoelectric converter 1302. The photoelectric conversion system 1301 is provided with at least two sets of optical systems 1314, photoelectric conversion devices 1302, and image preprocessing units 1315, and the output from each set of image preprocessing units 1315 is input to the integrated circuit 1303.

[0076] The integrated circuit 1303 is an integrated circuit for imaging system applications and includes an image processing unit 1304 with memory 1305, an optical distance measuring unit 1306, a distance measurement calculation unit 1307, an object recognition unit 1308, and an anomaly detection unit 1309. The image processing unit 1304 performs image processing such as development and defect correction on the output signal of the image preprocessing unit 1315. The memory 1305 stores the primary storage of the captured image and the location of defects in the captured pixels. The optical distance measuring unit 1306 focuses on the subject and measures the distance. The distance measurement calculation unit 1307 calculates distance measurement information from multiple image data acquired by multiple photoelectric converters 1302. The object recognition unit 1308 recognizes subjects such as cars, roads, signs, and people. When the anomaly detection unit 1309 detects an anomaly in the photoelectric converter 1302, it alerts the main control unit 1313 to the anomaly.

[0077] The integrated circuit 1303 may be implemented by specially designed hardware, by a software module, or by a combination of these. It may also be implemented by an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit), or by a combination of these.

[0078] The main control unit 1313 oversees and controls the operation of the photoelectric conversion system 1301, the vehicle sensor 1310, the control unit 1320, and other components. Alternatively, the system may not have a main control unit 1313, and the photoelectric conversion system 1301, the vehicle sensor 1310, and the control unit 1320 may each have their own communication interfaces, sending and receiving control signals via a communication network (e.g., CAN standard).

[0079] The integrated circuit 1303 has the function of receiving control signals from the main control unit 1313 or transmitting control signals and set values ​​to the photoelectric converter 1302 via its own control unit.

[0080] The photoelectric conversion system 1301 is connected to the vehicle sensor 1310 and can detect the vehicle's driving conditions, such as vehicle speed, yaw rate, and steering angle, as well as the external environment and the state of other vehicles and obstacles. The vehicle sensor 1310 also serves as a distance information acquisition means for acquiring distance information to objects. Furthermore, the photoelectric conversion system 1301 is connected to the driver assistance control unit 1311, which performs various driving assistance functions such as automatic steering, automatic cruising, and collision avoidance. In particular, regarding the collision judgment function, it determines whether a collision with another vehicle or obstacle has occurred and estimates a collision based on the detection results of the photoelectric conversion system 1301 and the vehicle sensor 1310. This enables avoidance control when a collision is estimated and activation of safety devices in the event of a collision.

[0081] Furthermore, the photoelectric conversion system 1301 is also connected to a warning device 1312 that issues a warning to the driver based on the judgment result of the collision judgment unit. For example, if the collision judgment unit determines that there is a high probability of collision, the main control unit 1313 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 1312 warns the user by sounding an alarm, displaying warning information on a display screen such as the car navigation system or instrument panel, or vibrating the seat belt or steering wheel.

[0082] This disclosure includes the following AD conversion circuits, photoelectric converters, imaging devices, and mobile bodies.

[0083] (Item 1) An AD conversion circuit that converts an analog signal applied to an input terminal into a digital signal, A continuous-time ΔΣ type AD converter including an integrating circuit for integrating the difference signal, A switching circuit that, in a first period, supplies an analog signal to the input terminal to the continuous-time ΔΣ type AD converter, and in a second period following the first period, switches the supply of a voltage signal corresponding to the voltage output from the integrating circuit at the end of the first period to the continuous-time ΔΣ type AD converter, The system includes a holding circuit that holds the voltage signal corresponding to the voltage output from the integrating circuit at the end of the first period, and provides the voltage signal to the continuous-time ΔΣ type AD converter via the switching circuit during the second period, The continuous-time ΔΣ type AD converter is an AD conversion circuit characterized in that the analog signal input to the continuous-time ΔΣ type AD converter is configured to allow gain adjustment.

[0084] (Item 2) The AD conversion circuit according to item 1, characterized in that the analog signal input to the continuous-time ΔΣ type AD converter during the first period is gain-adjusted.

[0085] (Item 3) The AD conversion circuit according to item 1 or 2, characterized in that the analog signal input to the continuous-time ΔΣ type AD converter during the first period is amplified.

[0086] (Item 4) The AD conversion circuit according to any one of items 1 to 3, characterized in that, during the second period, the analog signal input to the continuous-time ΔΣ type AD converter is not gain-adjusted.

[0087] (Item 5) The AD conversion circuit according to any one of items 1 to 4, further comprising a buffer circuit that buffers the output of the switching circuit and supplies it to the continuous-time ΔΣ type AD converter.

[0088] (Item 6) The integrating circuit includes a first integrator and a second integrator connected to the output of the first integrator, The continuous-time ΔΣ type AD converter further includes a comparator that compares the output of the second integrator with a reference signal, and a DA converter connected to the output of the comparator. The AD conversion circuit according to any one of items 1 to 5, characterized in that the first integrator includes a variable resistor connected to the output of the switching circuit, an amplification circuit connected to the output of the variable resistor, and a resistor disposed between the node between the variable resistor and the amplification circuit and the output of the DA converter.

[0089] (Item 7) The AD conversion circuit according to item 6, further comprising a control circuit including a multiplexer for controlling the resistance value of the variable resistor.

[0090] (Item 8) The integrating circuit includes a first integrator and a second integrator connected to the output of the first integrator, The continuous-time ΔΣ type AD converter further includes a comparator that compares the output of the second integrator with a reference signal, and a DA converter connected to the output of the comparator. The AD conversion circuit according to any one of items 1 to 5, characterized in that the first integrator is a Gm-C type integrator including a transconductor and a variable capacitor, and the output of the DA converter is connected to the output of the transconductor.

[0091] (Item 9) The AD conversion circuit according to item 8, further comprising a control circuit including a multiplexer for controlling the capacitance value of the variable capacitance.

[0092] (Item 10) The AD conversion circuit according to any one of items 6 to 9, characterized in that the comparator compares the output of the first integrator, the output of the second integrator, and the analog signal supplied to the first integrator with the reference signal.

[0093] (Item 11) The circuit includes a first variable amplifier circuit for amplifying the analog signal input to the switching circuit from the input terminal, The AD conversion circuit according to any one of items 6 to 9, characterized in that the comparator compares the output of the first integrator, the output of the second integrator, and the output of the first variable amplifier circuit with the reference signal.

[0094] (Item 12) The AD conversion circuit according to item 11, characterized in that the first variable amplifier circuit amplifies the analog signal input to the switching circuit during the period in which the analog signal input to the continuous-time ΔΣ type AD converter is gain-adjusted.

[0095] (Item 13) The AD conversion circuit according to item 12, characterized in that the first variable amplifier circuit includes a variable resistor and an amplifier and a resistor connected to the output of the variable resistor and arranged in parallel with each other.

[0096] (Item 14) A first variable amplifier circuit for amplifying the analog signal input to the switching circuit from the input terminal, The system further comprises a switching circuit separate from the switching circuit that switches the output of the first variable amplifier circuit and the analog signal input to the first integrator and supplies them to the comparator, The AD conversion circuit according to any one of items 6 to 9, characterized in that the comparator compares the output of the first integrator, the output of the second integrator, and the output of the other switching circuit with the reference signal.

[0097] (Item 15) The AD conversion circuit according to item 14, characterized in that the other switching circuit supplies the output of the first variable amplifier circuit to the comparator during the period in which the analog signal input to the continuous-time ΔΣ type AD converter is gain-adjusted, and supplies the analog signal input to the first integrator to the comparator during the period in which the analog signal input to the continuous-time ΔΣ type AD converter is not gain-adjusted.

[0098] (Item 16) The AD conversion circuit according to item 14 or 15, characterized in that the first variable amplification circuit includes a capacitor and an amplifier and a variable capacitor connected to the output of the capacitor and arranged in parallel with each other.

[0099] (Item 17) The AD conversion circuit according to item 14 or 15, characterized in that the first variable amplifier circuit includes a transconductor and a variable resistor connected to the output node of the transconductor.

[0100] (Item 18) An AD conversion circuit according to any one of items 1 to 17, further comprising a second variable amplification circuit between the input terminal and the switching circuit.

[0101] (Item 19) The AD conversion circuit according to item 18, characterized in that the second variable amplification circuit includes a capacitor and an amplifier and a variable capacitor connected to the output of the capacitor and arranged in parallel with each other.

[0102] (Item 20) The AD conversion circuit according to item 19, characterized in that the amplifier constitutes a single-ended amplifier.

[0103] (Item 21) Photoelectric conversion unit, An AD conversion circuit according to any one of items 1 to 20, configured to convert the analog signal output by the aforementioned photoelectric conversion unit into a digital signal, A photoelectric conversion device characterized by comprising the following features.

[0104] (Item 22) The photoelectric converter described in item 21, A signal processing unit that processes the signal output from the photoelectric converter, An imaging device characterized by comprising:

[0105] (Item 23) A mobile body characterized by being equipped with the imaging device described in item 22.

[0106] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of Symbols]

[0107] 1: AD conversion circuit, 10: Continuous-time ΔΣ type AD converter, 30: Switching circuit, IN: Input terminal

Claims

1. An AD conversion circuit that converts an analog signal applied to an input terminal into a digital signal, A continuous-time ΔΣ type AD converter including an integrating circuit for integrating the difference signal, A switching circuit that, during the first period, supplies an analog signal to the input terminal to the continuous-time ΔΣ type AD converter, and during the second period following the first period, switches the supply of a voltage signal corresponding to the voltage output from the integration circuit at the end of the first period to the continuous-time ΔΣ type AD converter, The system includes a holding circuit that holds the voltage signal corresponding to the voltage output from the integrating circuit at the end of the first period, and provides the voltage signal to the continuous-time ΔΣ type AD converter via the switching circuit during the second period, The continuous-time ΔΣ type AD converter is characterized in that the analog signal input to the continuous-time ΔΣ type AD converter is configured to allow gain adjustment.

2. The AD conversion circuit according to claim 1, characterized in that the analog signal input to the continuous-time ΔΣ type AD converter during the first period is gain-adjusted.

3. The AD conversion circuit according to claim 1, characterized in that the analog signal input to the continuous-time ΔΣ type AD converter during the first period is amplified.

4. The AD conversion circuit according to claim 1, characterized in that, during the second period, the analog signal input to the continuous-time ΔΣ type AD converter is not gain-adjusted.

5. The AD conversion circuit according to claim 1, further comprising a buffer circuit that buffers the output of the switching circuit and supplies it to the continuous-time ΔΣ type AD converter.

6. The integrating circuit includes a first integrator and a second integrator connected to the output of the first integrator. The continuous-time ΔΣ type AD converter further includes a comparator that compares the output of the second integrator with a reference signal, and a DA converter connected to the output of the comparator. The AD conversion circuit according to claim 1, characterized in that the first integrator includes a variable resistor connected to the output of the switching circuit, an amplification circuit connected to the output of the variable resistor, and a resistor disposed between the node between the variable resistor and the amplification circuit and the output of the DA converter.

7. The AD conversion circuit according to claim 6, further comprising a control circuit including a multiplexer for controlling the resistance value of the variable resistor.

8. The integrating circuit includes a first integrator and a second integrator connected to the output of the first integrator. The continuous-time ΔΣ type AD converter further includes a comparator that compares the output of the second integrator with a reference signal, and a DA converter connected to the output of the comparator. The AD conversion circuit according to claim 1, characterized in that the first integrator is a Gm-C type integrator including a transconductor and a variable capacitor, and the output of the DA converter is connected to the output of the transconductor.

9. The AD conversion circuit according to claim 8, further comprising a control circuit including a multiplexer for controlling the capacitance value of the variable capacitance.

10. The AD conversion circuit according to claim 6, characterized in that the comparator compares the output of the first integrator, the output of the second integrator, and the analog signal supplied to the first integrator with the reference signal.

11. The circuit includes a first variable amplifier circuit for amplifying the analog signal input to the switching circuit from the input terminal, The AD conversion circuit according to claim 6, characterized in that the comparator compares the output of the first integrator, the output of the second integrator, and the output of the first variable amplifier circuit with the reference signal.

12. The AD conversion circuit according to claim 11, characterized in that the first variable amplification circuit amplifies the analog signal input to the switching circuit during the period in which the analog signal input to the continuous-time ΔΣ type AD converter is gain-adjusted.

13. The AD conversion circuit according to claim 12, characterized in that the first variable amplifier circuit includes a variable resistor and an amplifier and a resistor connected to the output of the variable resistor and arranged in parallel with each other.

14. A first variable amplifier circuit for amplifying the analog signal input to the switching circuit from the input terminal, The system further comprises a switching circuit separate from the switching circuit that switches the output of the first variable amplifier circuit and the analog signal input to the first integrator and supplies them to the comparator, The AD conversion circuit according to claim 6, characterized in that the comparator compares the output of the first integrator, the output of the second integrator, and the output of the other switching circuit with the reference signal.

15. The AD conversion circuit according to claim 14, characterized in that the other switching circuit supplies the output of the first variable amplifier circuit to the comparator during the period in which the analog signal input to the continuous-time ΔΣ type AD converter is gain-adjusted, and supplies the analog signal input to the first integrator to the comparator during the period in which the analog signal input to the continuous-time ΔΣ type AD converter is not gain-adjusted.

16. The AD conversion circuit according to claim 14, characterized in that the first variable amplification circuit includes a capacitor and an amplifier and a variable capacitor connected to the output of the capacitor and arranged in parallel with each other.

17. The AD conversion circuit according to claim 14, characterized in that the first variable amplifier circuit includes a transconductor and a variable resistor connected to the output node of the transconductor.

18. The AD conversion circuit according to claim 1, further comprising a second variable amplification circuit between the input terminal and the switching circuit.

19. The AD conversion circuit according to claim 18, characterized in that the second variable amplification circuit includes a capacitor and an amplifier and a variable capacitor connected to the output of the capacitor and arranged in parallel with each other.

20. The AD conversion circuit according to claim 19, characterized in that the amplifier constitutes a single-ended amplifier.

21. Photoelectric conversion unit, An AD conversion circuit according to any one of claims 1 to 20, configured to convert an analog signal output by the photoelectric conversion unit into a digital signal, A photoelectric conversion device characterized by comprising the following features.

22. The photoelectric conversion device according to claim 21, A signal processing unit that processes the signal output from the photoelectric converter, An imaging device characterized by comprising:

23. A mobile body characterized by comprising the imaging device described in claim 22.

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