Electronic components

Abstract

We provide highly reliable ceramic electronic components. [Solution] The electronic component (capacitor) 1 has a functional part 7 and a cover 9. The functional part has a first surface facing the first side in the first direction D3. The cover overlaps the first surface. The cover also has two or more insulating layers 11A to 11C, one or more dummy electrodes 13, and a base electrode 15. The two or more insulating layers and one or more dummy electrodes overlap alternately in the first direction. The base electrode overlaps the outermost insulating layer from the first side. The area of ​​the cover that overlaps with the base electrode or dummy electrode in a planar perspective view from the first direction is referred to as the first range. When the total area of ​​voids per unit area in a cross section along the first direction is referred to as the void ratio, in the first range, the void area ratio of the outermost insulating layer is 0.300% or less, and the void ratio of the innermost insulating layer is smaller than the void ratio of the outermost insulating layer.

Description

[Technical Field]

[0001] This disclosure relates to electronic components such as multilayer ceramic capacitors. [Background technology]

[0002] Multilayer ceramic capacitors are known in which ceramic layers and internal electrodes are alternately stacked (for example, Patent Document 1 below). In Patent Document 1, a laminate in which ceramic layers and auxiliary electrodes are alternately stacked is superimposed on the upper and lower surfaces of a laminate consisting of ceramic layers and internal electrodes. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2014-212298 [Overview of the project]

[0004] An electronic component according to one aspect of the present disclosure comprises a functional portion and a cover portion. The functional portion has a first surface facing a first side in a first direction. The cover portion overlaps the first surface. The cover portion also comprises two or more insulating layers, one or more dummy electrodes, and a base electrode. The base electrode is exposed on the first side surface of the cover portion. The one or more dummy electrodes are exposed on the first side surface of the cover portion facing a second direction intersecting the first direction. The two or more insulating layers and the one or more dummy electrodes overlap alternately in the first direction. The base electrode overlaps the outermost insulating layer from the first side. The portion of the cover portion that overlaps with the base electrode or dummy electrode in a planar perspective view from the first direction is referred to as the first range.

[0005] In one example, when the number of voids per unit area of ​​the insulating layer in a cross-section along the first direction is referred to as the void density, in the first range, the void density of the innermost insulating layer is smaller than the void density of the outermost insulating layer.

[0006] In one example, when the total area of ​​voids per unit area of ​​the insulating layer in a cross-section along the first direction is referred to as the void area ratio, in the first range, the void area ratio of the outermost insulating layer is 0.300% or less, and the void area ratio of the innermost insulating layer is smaller than the void area ratio of the outermost insulating layer. [Brief explanation of the drawing]

[0007] [Figure 1] A perspective view showing a capacitor according to the first embodiment. [Figure 2] A schematic exploded perspective view of the capacitor shown in Figure 1. [Figure 3] Cross-sectional view along line III-III in Figure 1. [Figure 4] Enlarged view of region IV in Figure 3. [Figure 5] A perspective view showing a capacitor according to the second embodiment. [Figure 6] A cross-sectional view showing a capacitor according to the third embodiment. [Modes for carrying out the invention]

[0008] The embodiments relating to this disclosure will be described below with reference to the drawings. The figures used in the following description are schematic. Therefore, for example, the dimensional ratios on the drawings do not necessarily match those of reality. Also, the dimensional ratios may not match between drawings. Certain shapes and / or dimensions may be exaggerated, or details may be omitted. However, the above does not negate the fact that the actual shape and / or dimensions may be as shown in the drawings, or that the characteristics of the shape and / or dimensions may be extracted from the drawings.

[0009] Regarding the aspects described relatively later, basically, only the differences from the aspects described relatively earlier will be described. For matters not specifically mentioned, they may be the same as the aspects described earlier or inferred from the aspects described earlier. For components corresponding to each other among different aspects, for the sake of convenience, even if there are differences, the same reference numerals may be used.

[0010] In the description of the embodiments, the term of shape may include the case without dimensions and the case with dimensions. As long as there is no contradiction or the like, it may be interpreted either way. When referring to a rectangle (or rectangular shape) or a cuboid (or cuboid shape), the corners may be chamfered. Also, relatively small concave or convex portions (intentional ones, not errors) may be formed. The same applies to other shapes. When it is said that a predetermined layer has a certain thickness, there may be a change in thickness due to manufacturing errors (as long as a certain thickness is intended).

[0011] The determination of whether various dimensions are included in the ranges (absolute values such as μm or relative values with respect to other dimensions) exemplified in the description of the embodiments may be made reasonably. For example, the dimensions of specific portions may be disregarded. More specifically, for example, in the determination of whether the thickness falls within a predetermined range, the chamfered portions may be ignored. Also, for example, in a layer where a certain thickness is intended, when the thickness of the end portion is significantly different (for example, significantly thinner) from the thickness of most other portions (for example, 60% or more or 80% or more of the area), the thickness of the end portion may be disregarded. Also, when there are fluctuations in the thickness in most of the predetermined layer where the above-mentioned certain thickness is intended, for example, the average value may be referred to. Of course, if both the minimum value and the maximum value of the thickness are within the numerical range, there is no need to specifically specify and refer to the average value.

[0012] Regarding materials (such as conductive materials or insulating materials), the main component may be a component that occupies, for example, 60 mass% or more or 80 mass% or more.

[0013] (Summary of the Embodiment) FIG. 1 is a perspective view showing a capacitor 1 (an example of an electronic component) according to the first embodiment. For convenience, a rectangular coordinate system D1D2D3 is attached to FIG. 1 and other figures described later. The capacitor 1 may be used with either side being the upper or lower side. However, in the description of the embodiment, for convenience, the +D3 side is assumed to be the upper side, and terms such as the upper surface and the lower surface may be used.

[0014] The capacitor 1 is, for example, a multilayer ceramic capacitor. The capacitor 1 has a substantially rectangular parallelepiped main body 3 and four external electrodes 5 located at the four corners of the main body 3 in plan view (viewed in the D3 direction). The external electrode 5 contributes to the electrical connection between the capacitor 1 and other electronic components (e.g., a circuit board not shown).

[0015] FIG. 3 is a cross-sectional view taken along line III-III of FIG. 1. Note that FIG. 3 shows a D1D3 cross-section that cuts the external electrode 5 on the +D2 side. However, the D1D3 cross-section that cuts the external electrode 5 on the -D2 side, the D2D3 cross-section that cuts the external electrode 5 on the -D1 side, and the D2D3 cross-section that cuts the external electrode 5 on the +D1 side are basically the same. In the description of the embodiment, for convenience, without particular notice, the positional relationship between components may be described using the terms D1, D2, and D3 on the premise of the cross-section illustrated in FIG. 3.

[0016] The main body 3 has, for example, a functional part 7 and two covers 9 (an example of a cover part) that overlap the upper and lower surfaces of the functional part 7, respectively. The functional part 7 is a part (at least a part thereof) that directly performs the function of an electronic component (here, a capacitor). The cover 9 contributes to, for example, protecting the functional part 7 and / or improving the strength of the capacitor 1.

[0017] Focusing on the region R4 in FIG. 3. The cover 9 has two or more (three in the illustrated example) insulator layers 11 (11A to 11C) and one or more (from another perspective, the number of insulator layers 11 - 1) dummy electrodes 13 (13A and 13B) that are alternately laminated in the D3 direction. The cover 9 also has a base electrode 15 that overlaps the upper surface of the outermost insulator layer 11C.

[0018] In this context, the outermost layer refers to the layer furthest from the functional part 7 in the stacking direction among the multiple insulating layers 11 of each cover 9. The innermost layer, described later, refers to the layer closest to the functional part 7 in the stacking direction among the multiple insulating layers 11 of each cover 9.

[0019] Here, we are focusing on region R4 on the +D1 and +D3 sides, but the same applies to other regions corresponding to region R4. In the description of the embodiment, for convenience, without further explanation, we may use the terms "upper surface" and "lower surface" and refer to the positive and negative signs of each axis (D1, D2, and D3) using region R4 as an example.

[0020] The insulating layer 11 contributes, for example, to the insulation of the functional part 7. The dummy electrode 13 and the base electrode 15 contribute, for example, to deposit the metal that will become the external electrode 5 by a plating method, and / or to improve the adhesion force of the external electrode 5 to the main body 3. In Figure 3, for convenience, the boundary line between the insulating layers 11 is shown in the area where they directly overlap (the area where the dummy electrode 13 is not placed). Such a boundary line does not actually need to be observable (the same applies to the dielectric layer 17, which will be described later).

[0021] Figure 4 is an enlarged view of region R4. However, for convenience, the hatching of the insulating layer 11 has been omitted. Also, there are differences in the details of the configuration between Figure 3 and Figure 4. This difference may be interpreted as either Figure 3 being more schematic than Figure 4, or Figure 4 illustrating a strictly different configuration from Figure 3. Furthermore, in Figure 4, the boundary lines in the areas where the insulating layers 11 (and dielectric layers 17) directly overlap, as shown for convenience in Figure 3, are not shown.

[0022] The insulating layer 11 contains multiple voids 21. The number of voids 21 per unit area in a cross-section as shown in the figure (a cross-section along the D3 direction) shall be referred to as the "void density." The total area of ​​voids 21 per unit area in the above cross-section shall be referred to as the "void occupancy ratio." The area in the spread of the cover 9 where the base electrode 15 or dummy electrode overlaps shall be referred to as the first range A1. In this case, in the first range A1, the void density and / or void occupancy ratio of the innermost insulating layer 11A is smaller than the void density and / or void occupancy ratio of the outermost insulating layer 11C.

[0023] Therefore, for example, the likelihood of cracks caused by voids 21 occurring in the insulating layer 11A, which is relatively close to the functional part 7, is reduced. The characteristics of the functional part 7 are stabilized by the reduction of cracks near the functional part 7. On the other hand, in the outermost insulating layer 11C, there are relatively many recesses on the upper surface formed by the same principle as the formation of voids 21, so the adhesion strength of the base electrode 15 is improved by the anchoring effect, and delamination is reduced. Therefore, it is easier to balance the reliability of characteristics and the reliability of structural strength.

[0024] It should be noted that the effects described above do not necessarily have to be achieved. Furthermore, technical ideas different from those described above may be extracted from this disclosure. In this case, for example, the above-mentioned relationship between void density and / or void occupied area ratio does not have to be met, and two or more insulating layers 11 and one or more dummy electrodes 13 do not have to be provided in the first range A1.

[0025] The above is an overview of the embodiment. Specifically, the embodiment will be described in the following order. 1. First Embodiment (Figures 1-4) 1.1. Overall Structure 1.2. Functional Section 1.3. Cover (excluding voids) 1.3.1. Entire Cover 1.3.2. Insulator Layer 1.3.3. Dummy electrodes and base electrodes 1.4.External electrode 2. Void 2.1. General Voids 2.2. Void Density and Void Occupancy Ratio 2.3. Others 3. Capacitor manufacturing method 4. Other Embodiments 4.1. Second Embodiment (Figure 5) 4.2. Third Embodiment (Figure 6) 4.3. Embodiments not shown 5. Summary of Embodiments

[0026] (1. First Embodiment) (1.1. Overall Structure) The capacitor 1 shown in Figure 1 is configured as, for example, a surface-mount chip component. Specifically, for example, the capacitor 1 is positioned with its -D3 side or +D3 side facing a circuit board (not shown). The capacitor is then mounted on the circuit board by joining the four pads of the circuit board and the four external electrodes 5 with a conductive bonding material (e.g., solder) (not shown).

[0027] The configuration (internal structure and external shape) of capacitor 1 is, for example, generally symmetrical with respect to a plane of symmetry (not shown) that is parallel to the D1D2 plane and passes through the center of capacitor 1 in the thickness direction (D3 direction). Furthermore, the configuration of capacitor 1 is, for example, 180° rotationally symmetrical when viewed in the D3 direction. Of course, capacitor 1 does not necessarily have to have such symmetries.

[0028] The shape of the main body 3 is, for example, generally a thin rectangular parallelepiped. This rectangular parallelepiped may be a square (as shown in the illustration) or a rectangle (excluding squares; the same applies hereinafter) when viewed from above. In the description of the embodiment, for convenience, the description may assume a square shape unless otherwise specified.

[0029] Although not specifically shown in the illustrations, the main body 3 may have chamfered edges. This chamfering may be relatively large. For example, a curved or flat chamfered surface may extend across the entire side surface of the cover 9, as well as over a portion of the functional part 7 on the cover 9 side. Such a chamfered surface may be obtained, for example, by barrel polishing of the main body 3.

[0030] The specific dimensions of the main body 3 (or capacitor 1) are arbitrary. An example of dimensions when capacitor 1 is relatively small is given below. In the main body 3 (or capacitor 1), the lengths in the D1 and D2 directions may be between 0.3 mm and 2.0 mm, respectively. The thickness in the D3 direction may be between 0.030 mm and 1.0 mm. Note that the examples of dimensions for each component described later are also for the case where capacitor 1 is relatively small. Therefore, larger (or smaller) dimensions than those exemplified may be used.

[0031] Multiple components of the same type (e.g., 5, 9, 11, 13, 15, 17, and 19) may be provided with the same (or corresponding) shape, size, material, and position, etc., unless otherwise specified and unless contradictions arise. Therefore, unless otherwise specified and unless contradictions arise, the description of one component may be considered common to multiple components of the same type.

[0032] A single layered (film-like) component (e.g., 5, 11, 13, 15, 17, and 19, etc.) may be composed entirely of one material. However, a single layered component may be composed of layers made of different materials stacked on top of each other. Furthermore, a single layered component composed entirely of one material may, when considering the manufacturing process, be composed of a single layer, or it may be composed of multiple layers made of the same material stacked on top of each other.

[0033] (1.2. Functional Section) The shape of the functional part 7 shown in Figure 3 is, for example, generally a thin rectangular parallelepiped. Its planar shape is basically the same as that of the main body part 3. The specific thickness of the functional part 7 is arbitrary. For example, the thickness of the functional part 7 may be 30% or more, 40% or more, or 50% or more of the thickness of the main body part 3, and may also be 90% or less, 80% or less, 70% or less, or 60% or less. The above lower and upper limits may be combined in any way. The thickness of the main body part 3 is, for example, the thickness from the upper surface of the upper base electrode 15 to the lower surface of the lower base electrode 15. The thickness of the functional part 7 is, for example, the thickness from the uppermost internal electrode 19 (described later) to the lowermost internal electrode 19.

[0034] The functional unit 7 has multiple dielectric layers 17 and multiple internal electrodes 19 that are alternately stacked. This enables it to function as a capacitor.

[0035] The dielectric layer 17 is basically a layered structure with a constant thickness (at least between the internal electrodes 19). The shape and dimensions of the dielectric layer 17 in plan view are basically the same as those of the functional part 7 in plan view. The thickness of the dielectric layer 17 may be set appropriately according to the characteristics required of the capacitor 1. As an example of a relatively thin thickness, the thickness between adjacent internal electrodes 19 in the D3 direction may be 0.1 μm or more or 0.5 μm or more, and may also be 3.0 μm or less, 2.0 μm or less, or 1.0 μm or less. The above lower and upper limits may be combined in any way. The number of layers of dielectric layer 17 (internal electrodes 19) is arbitrary. For example, it may be 10 to 30 layers. The material of the dielectric layer is, for example, ceramics, and the specific type is also arbitrary.

[0036] The internal electrode 19 is layered and has a certain thickness. The thickness of the internal electrode 19 is arbitrary; for example, it may be thinner than, the same as, or thicker than the thickness of the region between the internal electrodes 19 in the dielectric layer 17. As an example of a relatively thin thickness, the thickness of the internal electrode 19 may be 0.3 μm or more or 0.5 μm or more, or it may be 3.0 μm or less, 2.0 μm or less, or 1.0 μm or less. The above lower and upper limits may be combined in any way. The material of the internal electrode 19 (e.g., the main component) is, for example, a metal. The specific type of metal is arbitrary; for example, all or the main component of the metal may be a base metal (e.g., Ni and / or Cu). The material of the internal electrode 19 may also include ceramics (co-material).

[0037] Figure 2 is an exploded perspective view of capacitor 1. Figure 2 is a schematic representation for understanding the planar shape and relative positions of internal electrodes 19, etc. Therefore, in Figure 2, various layers are shown in fewer numbers compared to Figure 3.

[0038] The internal electrode 19, for example, in a plan view, has a rectangular (square in the illustrated example) electrode body 19a and a pair of lead electrodes 19b extending from a pair of opposing corners of the electrode body 19a. The electrode body 19a is located inside the outer edge of the dielectric layer 17 and is not exposed from the side of the functional part 7. The pair of lead electrodes 19b reach the outer edge of the dielectric layer 17 and are connected to a pair of external electrodes 5 located at a pair of opposing corners of the main body 3. In the D3 direction, adjacent internal electrodes 19 are connected to different pairs of external electrodes 5. The dimensions of each part are arbitrary.

[0039] (1.3. Cover (excluding voids)) (1.3.1. Entire cover) The cover 9 shown in Figure 3 is, for example, a layered structure with a shape and dimensions that overlap the functional part 7 without excess or deficiency. The thickness of the cover 9 is approximately constant in both the area where the base electrode 15 is placed (first range A1) and the area where it is not placed. The thickness in the area where the base electrode 15 is placed is, for example, thicker than the thickness in the area where it is not placed. This is because the conductive paste that will become the dummy electrode 13 and the base electrode 15 is placed on a ceramic green sheet of a constant thickness. However, the thickness of the cover 9 may be made approximately constant throughout, for example, by making the thickness of the ceramic green sheet not constant or by employing other manufacturing methods.

[0040] The thickness range of the cover 9 exemplified below may apply to the thickness in the area where the base electrode 15 is placed, the thickness in the area where it is not placed, or the overall thickness (average value) of the cover 9. The thickness in the area where the base electrode 15 is placed can be defined as the thickness from the inner surface (bottom surface, top surface of the functional part 7) of the innermost insulating layer 11A to the top surface of the base electrode 15, when focusing on area R4. In cases where the internal electrode 19 overlaps most of the area of ​​the base electrode 15, as in the illustrated example, the thickness in the area where the base electrode 15 is placed may refer to the thickness of the area overlapping with the internal electrode 19. Similarly, the thickness of the functional part 7 may refer to the thickness in the area where the internal electrode 19 is placed.

[0041] The ratio of the thickness of the cover 9 to the thickness of the main body 3 may be roughly the inverse of the ratio of the thickness of the functional part 7 to the thickness of the main body 3 (as described above). For example, in an embodiment in which covers 9 are provided on both sides in the D3 direction, the thickness of one cover 9 may be, for example, 5% or more, 10% or more, 15% or more, or 20% or more relative to the thickness of the main body 3, or it may be 35% or less, 30% or less, or 25% or less. The above lower and upper limits may be combined in any way.

[0042] Furthermore, the thickness of one cover 9 may be 1 / 18 or more, 1 / 8 or more, 3 / 14 or more, 1 / 5 or more, or 1 / 3 or more of the thickness of the functional part 7, or 7 / 6 or less, 3 / 4 or less, 1 / 3 or less, or 1 / 2 or less. The above lower and upper limits may be combined in any way.

[0043] Furthermore, the thickness of one cover 9 may be, for example, 5 μm or more, 10 μm or more, or 15 μm or more, and may also be 50 μm or less, 30 μm or less, 25 μm or less, 20 μm or less, 15 μm or less, or 10 μm or less. The above lower and upper limits may be combined in any way so as not to cause any contradiction.

[0044] (1.3.2. Insulating layer) The insulating layer 11 is layered and has a generally constant thickness, except for variations in thickness due to differences such as whether or not it overlaps with the conductive layers (13, 15, and 19). The planar shape of the insulating layer 11 is, for example, basically the same as the planar shape of the dielectric layer 17.

[0045] The number of insulating layers 11 (or, from another perspective, the number of dummy electrodes 13 in one first range A1) is arbitrary. When extracting a technical idea in which the void density and / or void area ratio between the outermost and innermost layers satisfy a predetermined relationship, as described in the overview of the embodiment, the number of insulating layers 11 is 2 or more (the number of dummy electrodes 13 is 1 or more). In Figures 3 and 4, 3 is shown as an example for the number of insulating layers 11. Unlike the illustrated example, the number of insulating layers 11 may be 2 or 4 or more. When extracting a technical idea different from the above (for example, the relationship between the void density and / or void area ratio in the second range A2 to the fourth range A4 described later), the number of insulating layers 11 may be 1.

[0046] The thickness of the insulating layer 11 (for example, the thickness in the first range A1; the same applies hereafter in this paragraph and the next paragraph) is arbitrary. For example, the thickness of the insulating layer 11 may be thicker than the thickness of the dielectric layer 17 (between the internal electrodes 19) (as shown in the illustration), the same as, or thinner than the thickness of the dielectric layer 17. Also, for example, the thicknesses of multiple insulating layers 11 may be the same as or different from each other.

[0047] Furthermore, for example, the thickness of the insulating layer 11 may be 2 times or more, 3 times or more, or 5 times or more the thickness of the dielectric layer 17 (between the internal electrodes 19), or it may be 20 times or less, 10 times or less, or 5 times or less. The above lower and upper limits may be combined in any way. Furthermore, for example, the thickness of the insulating layer 11 may be 1.0 μm or more or 2.0 μm or more, or it may be 10.0 μm or less or 5.0 μm or less. The above lower and upper limits may be combined in any way.

[0048] The material of the insulating layer 11 is arbitrary. For example, the material of the insulating layer 11 may be the same as or different from the material of the dielectric layer 17. Multiple insulating layers 11 may be the same as or different from each other. The material of the insulating layer 11 may be a ceramic or a material other than a ceramic (e.g., resin). Examples of ceramics (all or the main component thereof) include barium titanate (BaTiO3), titanium dioxide (TiO2), strontium titanate (SrTiO3), calcium titanate (CaTiO3), and calcium zirconate (CaZrO3).

[0049] (1.3.3. Dummy electrodes and base electrodes) The dummy electrode 13 and the base electrode 15 may have the same configuration, except that their positions in the D3 direction are different. Therefore, for convenience, in this section, the explanation of the dummy electrode 13 may be given, and the explanation of the base electrode 15 may be omitted. Unless otherwise specified, and as long as it does not cause a contradiction, the term "dummy electrode 13" may be replaced with the term "base electrode 15".

[0050] The dummy electrodes 13 are, for example, layered and have a basically constant thickness. Each dummy electrode 13 is exposed on, for example, the side (more specifically, two side) of the main body 3. The exposed portion of each dummy electrode 13 is fixed to one external electrode 5. Each base electrode 15 constitutes a part of the upper or lower surface of the main body 3. Each base electrode 15 is fixed to one external electrode 5.

[0051] In a plan view, the position, shape, and dimensions of the dummy electrode 13 are arbitrary. In the examples of Figures 2 and 3, the position, shape, and dimensions of the dummy electrode 13 are such that, in a plan view, they roughly overlap with the external electrode 5 without excess or deficiency (however, the external electrode 5 is slightly wider). The dummy electrode 13 is located at the four corners of the rectangular (square in the illustrated example) insulating layer 11 and has a rectangular shape (square in the illustrated example) with four sides parallel to the four sides of the insulating layer 11.

[0052] The length of each dummy electrode 13 in the D1 direction (for example, the maximum length if it is not constant in the D2 direction; the same applies hereafter to the dummy electrode 13 and the insulating layer 11) may be, for example, 1 / 10 or more, 2 / 10 or more, or 4 / 10 or less, or 3 / 10 or less, of the length of the insulating layer 11 in the D1 direction. The above lower and upper limits may be combined in any way. Also, for example, the length of each dummy electrode 13 in the D1 direction may be 50 μm or more, 100 μm or more, or 150 μm or more, or 500 μm or less, 300 μm or less, or 200 μm or less. The above lower and upper limits may be combined in any way. Although examples of lengths in the D1 direction have been given, these lengths may also be applied to the lengths in the D2 direction.

[0053] Furthermore, the area of ​​each dummy electrode 13 may be 1 / 100 or more, or 4 / 100 or more, of the area of ​​the insulating layer 11, or 16 / 10 or less, or 9 / 10 or less. The above lower and upper limits may be combined in any way. Furthermore, the total area of ​​all dummy electrodes 13 may be 4 / 100 or more, or 16 / 100 or more, of the area of ​​the insulating layer 11, or 64 / 100 or less, or 36 / 100 or less. The above lower and upper limits may be combined in any way.

[0054] The thickness of the dummy electrode 13 may be, for example, thicker than the thickness of the internal electrode 19 (as shown in the illustration), the same as, or thinner than, the thickness of the internal electrode 19. Also, for example, the thicknesses of one or more dummy electrodes 13 and the base electrode 15 may be the same as, or different from, the thickness of each other. In Figure 3, an example is shown in which multiple dummy electrodes 13 and base electrodes 15 have the same thickness. In Figure 4, an example is shown in which the thickness of the base electrode 15 is thicker than the thickness of the dummy electrode 13. Furthermore, the thickness of the dummy electrode 13 may be thinner than, the same as, or thicker than the thickness of the insulating layer 11 (for example, the thickness in the first range A1).

[0055] Furthermore, for example, the thickness of the dummy electrode 13 (excluding the base electrode 15) may be 1 or more, 1.5 or more, or 2 or more times the thickness of the internal electrode 19, or it may be 10 or less, 5 or less, or 2 or less. The above lower and upper limits may be combined in any way so as not to cause any contradiction. Furthermore, for example, the thickness of the dummy electrode 13 (excluding the base electrode 15) may be 0.3 μm or more, 0.5 μm or more, 1.0 μm or more, or 2.0 μm or more, or it may be 10.0 μm or less, 5.0 μm or less, 3.0 μm or less, or 2.0 μm or less. The above lower and upper limits may be combined in any way so as not to cause any contradiction.

[0056] Furthermore, for example, the thickness of the base electrode 15 may be 1 or more, 2 or more, 3 or more, or 5 or more times the thickness of the internal electrode 19 and / or the dummy electrode 13, or it may be 20 or less, 10 or less, or 5 or less. The above lower and upper limits may be combined in any way so as not to cause any contradiction. Furthermore, for example, the thickness of the base electrode 15 may be 1.0 μm or more, 2.0 μm or more, 3.0 μm or more, or 5.0 μm or more, or it may be 20.0 μm or less, 10.0 μm or less, or 5.0 μm or less. The above lower and upper limits may be combined in any way so as not to cause any contradiction.

[0057] The material of the dummy electrode 13 is arbitrary. For example, the material of the dummy electrode 13 may be the same as or different from the material of the internal electrode 19. In any case, the description of the material of the internal electrode 19 may be applied to the material of the dummy electrode 13.

[0058] As previously described, the dummy electrode 13 and the base electrode 15 are located in different positions in the D3 direction. Specifically, in region R4, the base electrode 15 is located on the opposite side of the functional part 7 from all the dummy electrodes 13. From another perspective, unlike the dummy electrodes 13, the base electrode 15 constitutes a part of the upper surface of the cover 9. Furthermore, the upper surface of the base electrode 15 is not covered by an insulator (insulator layer 11 or other insulator). Consequently, most of the upper surface of the base electrode 15 (for example, 60% or more, 80% or more, or 100%) is a connection area with other conductors (external electrodes 5).

[0059] (1.4.External electrode) The external electrode 5 is, for example, layered with a basically constant thickness. As shown in Figure 1, the external electrode 5 covers four surfaces (top, bottom, and two sides) of the main body 3, for example, at the corners in a plan view of the main body 3. This allows one external electrode 5 to be connected to one lead electrode 19b on two sides of the main body 3, and also allows surface mounting on either the top or bottom surface of the capacitor 1. The shape and dimensions of the portions of the external electrode 5 on each surface are arbitrary. The planar shape of the portion of the external electrode 5 located on the top or bottom surface of the main body 3 is, for example, rectangular (square in the illustrated example). The planar shape and dimensions of the portion of the external electrode 5 located on the side surface of the main body 3 are, for example, rectangular with the same lateral length as the portion located on the top or bottom surface.

[0060] The thickness of the external electrode 5 is arbitrary. For example, the thickness of the external electrode 5 may be greater than the thickness of the internal electrode 19, dummy electrode 13, and base electrode 15. For example, the thickness of the external electrode 5 may be 1.2 times or more, 2 times or more, or 3 times or more, or 10 times or less, 5 times or less, or 3 times or less, than the thickness of the base electrode 15. The above lower and upper limits may be combined in any way. Also, for example, the thickness of the external electrode 5 may be 3 μm or more, 5 μm or more, or 10 μm or more, or 30 μm or less, 20 μm or less, or 10 μm or less. The above lower and upper limits may be combined in any way so as not to cause any contradictions.

[0061] The material of the external electrode 5 is, for example, a metal. The specific type of metal is arbitrary; for example, all or the main component may be a base metal (e.g., Ni and / or Cu). The external electrode 5 may also be constructed by laminating different materials as needed. For example, the external electrode 5 may be constructed by laminating Cu, Ni, and Sn from the side of the base electrode 15. The material of the external electrode 5 may be the same as or different from the material (e.g., main component) of the internal electrode 19, dummy electrode 13, and / or base electrode 15.

[0062] (2. Void) (2.1. General Voids) In the following, the explanations regarding voids 21, void density, and void area ratio basically pertain to the first range A1. Even if it is not explicitly stated that the explanations are for voids 21, void density, and void area ratio in the first range A1, they may be considered as explanations for the first range A1 unless contradictions arise. Furthermore, the explanations for the first range A1 may be applied to voids 21, void density, and void area ratio in ranges other than the first range A1 (areas where the base electrode 15 is not placed) or to the entire range including the first range A1, unless contradictions arise.

[0063] The various configurations relating to voids 21 in the first range A1 described below (for example, the relative relationship of void densities between insulating layers 11) may be established in each of the first range A1, for example, all of them (eight in the example of Figures 1 to 3). However, they may be established in only 60% or 80% or more of the total number of first range A1s, or in any one or more first range A1s. Furthermore, the configuration relating to voids 21 in the D1D3 cross section described below may be established in the D2D3 cross section in addition to, or instead of, the D1D3 cross section.

[0064] The void 21 shown in Figure 4 is a space where no material exists. The void 21 is usually sealed and does not lead to the outside of the capacitor 1. A gas may be present in the void 21. The type of gas is arbitrary. The pressure of the gas inside the void 21 is also arbitrary; for example, it may be lower than atmospheric pressure at room temperature.

[0065] Voids 21 are formed, for example, when the insulating layer 11 is made of ceramics, by the fact that gaps between particles are not completely eliminated during the firing process. Also, when the insulating layer 11 is made of other insulating materials (e.g., resin), voids 21 are formed, for example, by the entrainment of gas during the flow process or by the contraction of the insulating material during the cooling process. In the description of the embodiments, unless otherwise specified, an example in which the insulating layer 11 is made of ceramics may be used.

[0066] The shape of the void 21 is not particularly limited. For example, in a cross-section as shown in Figure 4, the shape of the void 21 may be a block shape such as a circle or an ellipse, or it may be linear or crack-shaped. For example, in a cross-section as shown in Figure 4, the value obtained by dividing the longer of any two mutually orthogonal lengths by the shorter of the two lengths, and the maximum value in each void 21, is referred to as the aspect ratio. In this case, in each insulating layer 11 (either the whole or the portion located in the first range A1) having at least one void 21, the number of voids 21 with an aspect ratio of 3.0 or less may be 80% or more, 90% or more, 95% or more, or 100% of the total number of voids 21.

[0067] The dimensions of the voids 21 are not particularly limited. For example, the length of each void 21 in the D3 direction is less than the thickness of the insulating layer 11 to which the void 21 belongs (the average thickness of the entire layer, the average thickness in the first range A1, or the thickness at the location of the void 21). For example, the former is 2 / 3, 1 / 2, or 1 / 3 of the latter. In each insulating layer 11 (either the whole or the portion located in the first range A1) having at least one void 21, the number of voids 21 whose length in the D3 direction is less than the thickness of the insulating layer 11 (or any of the above-mentioned lengths) may be 95% or more, or 100%, of the total number of voids 21.

[0068] The insulating layer 11 is basically formed in such a way that there are fewer voids 21. In this case, the shape of the multiple voids 21 is likely to be in the form of a lump, and the shape and dimensions of the multiple voids 21 are likely to be similar to each other. Figure 4 schematically shows the voids 21 in such a case.

[0069] (2.2. Void density and void occupancy ratio) As described above, when the shapes and dimensions of multiple voids 21 are similar to each other, the void density and the void area ratio are correlated. Therefore, the explanation of void density may be applied by substituting the term void density with the void area ratio, as long as no contradictions arise. In the description of the embodiments, for convenience, only the void density may be mentioned, and the void area ratio may not be mentioned.

[0070] In the following explanation, for convenience, the symbols of each part may be treated as representing the void density (or void area ratio) of that part. For example, as described in the overview of the embodiment, if the void density of the insulating layer 11A is smaller than the void density of the insulating layer 11C in the first range A1, this may be expressed as 11A < 11C. Also, for example, the ratio of the former to the latter may be expressed as 11A / 11C.

[0071] Void density is a parameter in a predetermined cross-section (the D1D3 cross-section in Figure 4). Figure 4 shows the extent of the first range A1 (the area where the base electrode 15 or dummy electrode overlaps with the area overlapping in the D3 direction) in the direction along the predetermined cross-section (D1 direction). However, the first range A1 also has extent in the direction perpendicular to the predetermined cross-section (the D2 direction in Figure 4). When a predetermined condition regarding void density (e.g., 11A < 11C) is met in the first range A1, this condition is met in a predetermined proportion or more of a predetermined number of cross-sections that equally divide the first range A1 in the D2 direction. The predetermined number may be, for example, 3 or more, 5 or more, 10 or more, or 20 or more. The predetermined proportion may be, for example, 60% or more, 80% or more, or 90% or more. While the first range A1 is used as an example, the same applies to other ranges described later. If it is difficult to observe the predetermined number of cross-sections of a single sample, the predetermined number of cross-sections may be observed in multiple samples intended to have the same configuration. Also, if it is difficult to observe the predetermined number of cross-sections of the first range A1, cross-sections of other ranges other than the first range A1 that are intended to have the same configuration may be observed.

[0072] The definitions of void density and void area ratio have already been described. For clarification, void density is obtained by dividing the number of voids 21 in a specified target region by the cross-sectional area of ​​that region in each cross-section. For example, when referring to the void density in insulating layer 11A, it refers to the value obtained by dividing the number of voids 21 in insulating layer 11A by the cross-sectional area of ​​insulating layer 11A. When referring to the void density in two or more insulating layers 11 (the whole), it refers to the value obtained by dividing the number of voids 21 in the two or more insulating layers 11 by the cross-sectional area of ​​the two or more insulating layers 11 (the sum of the cross-sectional areas of the two or more insulating layers 11). As can be understood from this example, the void density of two or more insulating layers 11 is not simply the sum of the void densities of each insulating layer 11 divided by the number of insulating layers 11. Similarly, the void area ratio is obtained by dividing the total area of ​​voids 21 in the target region by the cross-sectional area of ​​the target region.

[0073] When determining the void density and void occupancy ratio, the void 21 is, for example, 0.008 μm. 2 The above may be used. This size corresponds, for example, to the size of a void 21 visible in a 1500x magnification image of a cross-section like the one in Figure 4, captured by an SEM (Scanning Electron Microscope). In other words, by targeting voids 21 with an area greater than or equal to the above, it becomes easier to count the number of voids 21 or to calculate the area of ​​the voids 21 using image processing with an SEM or other device. Note that, for example, linear voids 21 that are too thin to determine their area (e.g., width less than the resolution) may be excluded from the calculation of void density and void area ratio.

[0074] For determining the void density and void area ratio, for example, a JSM-IT500HR manufactured by JEOL Ltd. may be used. Then, an image may be acquired under the conditions of magnification: 1500x, acceleration voltage: 15kV, and irradiation current: 70 (unitless). Based on the image, the number of voids 21 in the target area may be visually determined. Alternatively, the area to be measured (target area or voids 21) may be specified based on the visual inspection of the above image, and the area of ​​the above range may be obtained by image processing.

[0075] Furthermore, in determining the void density and void area ratio, it is generally acceptable to focus on voids 21 that are closed in the observed cross-section. This is because the upper or lower surface of the insulating layer 11 is not always smooth, and it may be difficult to distinguish between recesses on the upper or lower surface and voids 21. However, cavities that can be clearly identified as voids 21 based on their shape and dimensions may be considered when determining the void density and void area ratio. Examples of such cavities include generally closed cavities and / or cavities that are clearly larger than the recesses.

[0076] As described in the overview of the embodiment, in the first range A1, the void density is 11A < 11C. When the number of insulating layers 11 is three or more, the void density in the insulating layer 11 located between insulating layer 11A and insulating layer 11C (one insulating layer 11B in the illustrated example) is arbitrary. For example, the void density in insulating layer 11B (if there are two or more insulating layers 11B, the total or individual void density thereafter; the same applies hereinafter unless there is a contradiction) may be less than, the same as, or greater than the void density of insulating layer 11A (or insulating layer 11C).

[0077] In the example in Figure 4, the void density increases with increasing density in the outer insulator layer 11 within the first range A1. That is, 11A < 11B < 11C. If 11A < 11B < 11C as in the illustrated example, and unlike the illustrated example, there are two or more insulator layers 11B, the relative magnitudes of the void densities between the insulator layers 11B are arbitrary. For example, the void density may be higher in the outer insulator layers 11B, or they may be roughly the same.

[0078] The void density in the cover 9 (or, from another perspective, the entire set of insulating layers 11) may vary in the D1 direction (and / or D2 direction; the same applies hereinafter) instead of, or in addition to, the D3 direction. The D1 direction can be defined as the direction to which one side of the cover 9 (the +D1 side in Figure 4) faces. The D1 direction can also be defined as the direction in which the base electrode 15 extends (and further, the direction in which it is exposed from the +D1 side). The change in void density in the D1 direction may, for example, be smaller towards the -D1 side (inside), or conversely, larger towards the inside.

[0079] As shown in Figure 4, the change in void density in the D1 direction may be understood by the relative magnitudes of void densities between the second range A2 to the fourth range A4, which are defined by dividing the first range A1 into three equal parts in the D1 direction. The second range A2 can be said to be the range on the +D1 side (the side where the base electrode 15 is exposed) of the three ranges. The third range A3 can be said to be the central range of the three ranges. The fourth range A4 can be said to be the range on the opposite side from the +D1 side of the three ranges, and in the illustrated example, it can be said to be the range on the central side of the cover 9.

[0080] In the example of FIG. 4, in the plurality of insulator layers 11 (11A to 11C), the void density is such that A4 < A3 and A2 < A3. In this case, the void density in the second range A2 may be smaller, the same, or larger than the void density in the fourth range A4. Note that, unlike the above description, only one of A4 < A3 and A2 < A3 may hold. Also, A4 (and / or A2) = A3, or A4 (and / or A2) > A3 may be acceptable.

[0081] In the above description, regarding the void density in the first range A1 and the entire plurality of insulator layers 11, the change in the void density in the D1 direction was described. However, for example, instead of or in addition to the entire plurality of insulator layers 11, the above change may hold for each of the plurality (all) of the insulator layers 11, or may hold only for each of any one or more of the insulator layers 11.

[0082] In the magnitude relationships exemplified above, the degree of difference (such as difference and ratio) between the two is arbitrary. For example, regarding the void density in the first range A1, when 11A < 11C holds, 11A / 11C may be 9 / 10 or less, 4 / 5 or less, 3 / 4 or less, 1 / 2 or less, or 1 / 3 or less. The lower limit of 11A / 11C is not particularly limited (it may be 0). Also, for example, 11C - 11A is 2 0.005 pieces / μm or more, 2 0.010 pieces / μm or more, 2 0.020 pieces / μm or more, 2 0.050 pieces / μm or more 2 or 0.100 pieces / μm or more may be acceptable. The upper limit of 11C - 11A is not particularly limited.

[0083] Also, for example, regarding the void density in the first range A1, in an embodiment where 11A < 11B < 11C holds, 11B / 11C may be 19 / 20 or less, 9 / 10 or less, 7 / 8 or less, 3 / 4 or less, or 2 / 3 or less. The lower limit of 11B / 11C (only the value in the case of 11A < 11B < 11C) may be any value greater than 0. Also, for example, 11A / 11B may be 18 / 19 or less, 8 / 9 or less, 6 / 7 or less, 2 / 3 or less, or 1 / 2 or less. The lower limit of 11A / 11B is not particularly limited (it may be 0). Also, for example, 11C - 11B and / or 11B - 11A is 0.002 voids / μm 2 or more, 0.005 voids / μm 2 or more, or 0.010 voids / μm 2 or more, 0.025 voids / μm 2 or more, or 0.050 voids / μm 2 or more. The upper limit of 11C - 11B and 11B - 11A is not particularly limited.

[0084] Also, for example, regarding the void density in the first range A1 and the entire plurality of insulator layers 11 (or each insulator layer 11), in an embodiment where A2 < A3 holds, A2 / A3 may be 9 / 10 or less, 4 / 5 or less, 3 / 4 or less, or 1 / 2 or less. The lower limit of A2 / A3 is not particularly limited (it may be 0). Also, for example, A3 - A2 is 0.005 voids / μm 2 or more, 0.010 voids / μm 2 or more, or 0.020 voids / μm 2 or more, 0.050 voids / μm 2 or more, or 0.100 voids / μm 2 or more. The upper limit of A3 - A2 is not particularly limited. In the description of this paragraph and the next paragraph, A2 may be replaced by A4.

[0085] The above explanation of the example of void density ratios (e.g., 11A / 11C) may be applied to the ratio of void area ratios. Furthermore, the difference in void area ratios may be, for example, as follows: When 11A < 11C holds true, 11C - 11A (void area ratio) may be, for example, 0.005% or more, 0.010% or more, 0.020% or more, or 0.050% or more. When 11A < 11B < 11C holds true, 11C - 11B and / or 11B - 11A (void area ratio) may be 0.002% or more, 0.005% or more, 0.010% or more, or 0.020% or more. A3 - A2 (void area ratio) may be 0.005% or more, 0.010% or more, 0.020% or more, or 0.050% or more. In all cases, there is no particular upper limit.

[0086] The absolute value of the void density when various conditions are met is arbitrary. For example, the void density of the first range A1 and the innermost insulating layer 11A (and / or insulating layer 11B) is 0.000 voids / μm 2 More than 0.005 pieces / μm 2 More than 0.010 pieces / μm 2 Above or above, or 0.050 particles / μm 2 The above is sufficient, and also 0.200 particles / μm 2 Below, 0.100 pieces / μm 2 Less than or 0.050 pieces / μm 2 The following may be applied. The above lower and upper limits may be combined in any way so as not to create any contradictions.

[0087] Furthermore, for example, the void density of the first range A1 and the outermost insulating layer 11C (and / or insulating layer 11B) is 0.020 voids / μm 2 More than 0.050 pieces / μm 2 More than or equal to 0.100 particles / μm 2 The above is sufficient, and also 0.500 particles / μm 2 Below, 0.300 pieces / μm 2 Below, 0.200 pieces / μm 2 Less than or 0.100 pieces / μm 2 The following may be applied. The above lower and upper limits may be combined in any way so as not to create any contradictions.

[0088] Furthermore, for example, the void occupancy ratio of the first range A1 and the insulating layer 11A (and / or insulating layer 11B) may be 0.005% or more, 0.010% or more, or 0.020% or more, or 0.100% or less, 0.080% or more, or 0.060% or less. The above lower and upper limits may be any combination of any two values.

[0089] Furthermore, for example, the void occupancy ratio of the first range A1 and the insulating layer 11C (and / or insulating layer 11B) may be 0.050% or more, 0.080% or more, or 0.100% or more, or 0.300% or less, 0.200% or less, or 0.150% or less. The above lower and upper limits may be any combination of any two values.

[0090] The above examples of lower and / or upper limits for void density and / or void occupancy ratio of the insulating layer 11A may also apply to the second range A2 and / or the fourth range A4. The above examples of lower and / or upper limits for void density and / or void occupancy ratio of the insulating layer 11C may also apply to the third range A3.

[0091] (2.3. Others) Although not shown in Figure 4, voids may also exist in areas other than the insulating layer 11. That is, voids may also exist in the dielectric layer 17, internal electrode 19, dummy electrode 13, base electrode 15 and / or external electrode 5. In this case, for example, the average equivalent diameter of the voids in the dielectric layer 17 may be smaller than that of the voids 21 in the insulating layer 11 (but it does not have to be). Also, for example, the average equivalent diameter of the voids in the internal electrode 19, dummy electrode 13, base electrode 15 and external electrode 5 may be larger than that of the voids 21 in the insulating layer 11 (but it does not have to be). The void density and void area ratio are also arbitrary.

[0092] (3. Capacitor manufacturing method) The manufacturing method for capacitor 1 can be varied. For example, the general procedure may be the same as a known procedure. An example is shown below.

[0093] First, ceramic green sheets are fabricated to form the dielectric layer 17 and the insulating layer 11. Next, conductive paste is applied (for example, printed) to the ceramic green sheets to form the internal electrodes 19, dummy electrodes 13, or base electrodes 15. Then, the ceramic green sheets are laminated to form the main body 3. The lamination of the functional part 7 and the lamination of the cover 9 for the laminate may be performed together or separately.

[0094] Up to the point of fabricating the laminate described above, the process is carried out using a base substrate that is large enough to produce multiple main body parts 3. After fabricating the laminate, the base substrate containing the laminate is pieced into pieces (for example, cut) that roughly correspond to the size of the main body parts 3. Next, the laminate having the size of the main body parts 3 is fired. After that, a metal film is formed on the main body parts 3 to form the external electrodes 5.

[0095] Degreasing may be performed before firing. Firing may be carried out, for example, in a reducing atmosphere. Re-oxidation heat treatment may be performed after firing. Polishing (e.g., barrel polishing) of the main body 3 may be performed before and / or after firing. During polishing, for example, the edges of the main body 3 may be chamfered, or the sides of the main body 3 may be polished.

[0096] The method for adjusting the void density is arbitrary. For example, in the process of stacking the ceramic green sheets described above to form a laminate, the laminate is pressed when the ceramic green sheet that will become the outermost insulating layer 11C is not stacked on top. Then, the ceramic green sheet that will become the outermost insulating layer 11C is stacked on top of the laminate, and the pressing is performed again. Since the number of presses for the insulating layer 11C is less than the number of presses for the other insulating layers 11, voids 21 are more easily formed.

[0097] Further, for example, the ratio of the solid content (e.g., ceramic powder) in the ceramic green sheet that becomes the insulator layer 11C is made smaller than that of other ceramic green sheets. As a result, the insulator layer 11C is more likely to form voids 21 than the other insulator layers 11. Note that the green sheet of the insulating layer may be a single layer or a plurality of layers.

[0098] In the above, the method of increasing the void density of the insulator layer 11C (the method of realizing 11A < 11C) has been described. It is clear that the above can also be applied to realize 11A < 11B < 11C and A2 (and / or A4) < A3, etc. For example, when realizing A2 < A3 and A4 < A3, when pressing the portion where the base electrode 15 and the dummy electrode 13 are present, pressure may be applied to both ends sides rather than the central part side of these electrodes. Further, a difference in void density may be realized by a method other than the above. For example, a difference in void density may be realized by appropriately setting the temperature conditions during firing.

[0099] The external electrode 5 may be formed by various methods. For example, metal may be deposited on the surface of the base electrode 15, the exposed portion from the side surface of the main body portion 3 of the dummy electrode 13, and the exposed portion from the side surface of the main body portion 3 of the internal electrode 19 by electroless plating and / or electrolytic plating. Further, for example, a thin film formation method such as a dip method, a printing method, CVD (Chemical Vapor Deposition), or PVD (Physical Vapor Deposition) may be adopted. As understood from the above, the base electrode 15, the dummy electrode 13, and the internal electrode 19 may or may not contribute to the deposition of metal.

[0100] (4. Other Embodiments) (4.1. Second Embodiment) FIG. 5 is a perspective view of the capacitor 201 according to the second embodiment. FIG. 3 according to the first embodiment may be referred to as a view showing the D1D3 cross section of the capacitor 201. The same applies to FIG. 4.

[0101] Generally speaking, capacitor 201 differs from capacitor 1, which is a four-terminal type, in that it is a two-terminal type. In such capacitor 201, the void density and void area ratio described with reference to Figures 3 and 4 may also be set.

[0102] The specific shape and dimensions of each part of capacitor 201 may differ from those of capacitor 1, depending on whether it is a two-terminal type. Specifically, they are as follows:

[0103] The shape of the main body 203 (or capacitor 201) is, for example, roughly rectangular. This rectangular parallelepiped may have a height (length in the D3 direction) equal to or smaller than its width (length in the D2 direction) (as shown in the illustration). The length of the rectangular parallelepiped (in the D1 direction) is, for example, greater than its width. The dimensions of the main body 203 are arbitrary. Specific examples of the dimensions of the main body 3 in the first embodiment may be applied to the dimensions of the main body 203. The external electrodes 5 are generally layered, covering the longitudinal end of the main body 203 across five faces of the rectangular parallelepiped.

[0104] The planar shape of the internal electrode 19 is, for example, roughly a rectangle with four sides parallel to the four sides of the rectangular main body 203 (dielectric layer 17). Of the four sides of the internal electrode 19, two long sides and one short side are located inside (not exposed) the side surface of the main body 203, for example. The remaining short side is exposed from the +D1 side or -D1 side of the main body 203. The region of the internal electrode 19 that overlaps with other internal electrodes 19 in a planar view is the electrode body 19a. The portion extending from the electrode body 19a to the external electrode 5 is the lead-out electrode 19b.

[0105] Between two adjacent insulating layers 11 in the D3 direction, for example, two dummy electrodes 13 are provided at both ends in the longitudinal direction of the main body 203. The planar shape of the dummy electrodes 13 is, for example, rectangular, extending across the entire width (length in the D2 direction) of the main body 203, and is exposed from the +D1 side or -D1 side of the main body 203, as well as from the +D2 side and the -D2 side. The above description of the planar configuration of the dummy electrodes 13 may be used to describe the planar shape of the base electrode 15 that overlaps the uppermost insulating layer 11C.

[0106] In the capacitor 1 of the first embodiment, the D1D3 cross-section and the D2D3 cross-section are basically the same. Consequently, in the explanation relating to void density, the D1 direction and the D2 direction are basically reversible. On the other hand, in the capacitor 201 of the second embodiment, the D1D3 cross-section and the D1D2 cross-section are different.

[0107] In an embodiment such as capacitor 201, the cross-section used to measure the void density in the first range A1 may be either a D1D3 cross-section or a D2D3 cross-section. Theoretically, increasing the number of cross-sections used for measurement will bring the values ​​at multiple D1D3 cross-sections closer to the values ​​at multiple D2D3 cross-sections. However, one of the cross-sections may be selected from various viewpoints.

[0108] The second range A2 to the fourth range A4 will have different positions and shapes depending on whether the first range A1 is divided into three equal parts in the D1 direction or the D2 direction. Either the D1 direction or the D2 direction may be selected. If the D1 direction is selected, the fourth range A4 can be said to be the range located on the central side of the capacitor 201, similar to the first embodiment, relative to the second range A2 and the third range A3. On the other hand, if the D2 direction is selected, the fourth range A4 can be said to be the range adjacent to the side of the capacitor 201, similar to the second range A2.

[0109] (4.2. Third Embodiment) Figure 6 is a cross-sectional view of the capacitor 401 according to the third embodiment. This cross-sectional view corresponds to Figure 3 of the first embodiment. For convenience, in the following description, the top cover 9 may be used as an example without further explanation. The capacitor 401 may be a four-terminal type as in the first embodiment, or a two-terminal type as in the second embodiment.

[0110] In short, the capacitor 401 has a configuration similar to the capacitor 101 of the first embodiment, where the base electrode 15 is embedded in the outermost insulating layer 11C. In Figure 6, the upper surface of the base electrode 15 is approximately flush with the upper surface of the outermost insulating layer 11. However, the upper surface of the base electrode 15 may be located above (or below) the upper surface of the outermost insulating layer 11.

[0111] Such arrangement of the base electrode 15 can be realized, for example, by making the following modifications to the manufacturing method described above. Two layers of ceramic green sheets are prepared to form one of the outermost insulating layers 11C. A conductive paste, which will be the base electrode 15, is placed on the outer layer side (upper surface) of the inner layer side (lower) ceramic green sheet. A hole is formed in the outer layer side (upper) ceramic green sheet where the base electrode 15 will be located.

[0112] Furthermore, whether two or more ceramic green sheets used in the manufacturing process constitute a single insulating layer 11 after completion can be determined by the presence or absence of a dummy electrode 13 interposed between them. For example, even if the insulating layer 111C is made from two ceramic green sheets as described above, if there is no dummy electrode 13 interposed between them, the insulating layer 11C can be considered as a single insulating layer.

[0113] Furthermore, in the above manufacturing method, the conductive paste that forms the base electrode 15 is placed on the upper surface of the inner layer ceramic green sheet, but after completion, the base electrode 15 remains on top of the outermost insulating layer 11C. Also, the base electrode 15 remains on top of the outermost insulating layer 11C from the +D3 side.

[0114] When the above manufacturing method is adopted, the outer ceramic green sheet may, due to manufacturing tolerances or intentionally, cover the edges of the base electrode 15. In this case as well, since the two ceramic green sheets are not separated by the dummy electrode 13, the insulating layer 11C can be considered as a single insulating layer. Furthermore, the base electrode 15 (more precisely, the portion of it not covered by the outer ceramic green sheet) remains on top of the outermost insulating layer 11C, and the base electrode 15 remains on top of the outermost insulating layer 11C from the +D3 side.

[0115] From another perspective, in the example in Figure 6, the outermost insulating layer 11C is relatively deeply recessed in the region where the base electrode 15 is located. Even in this case, the base electrode 15 still overlaps the upper surface of the outermost insulating layer 11C, and the base electrode 15 still overlaps the outermost insulating layer 11 from the +D3 side.

[0116] The explanations above that the insulating layer 11C may be made of two or more ceramic green sheets, and that relatively large recesses may be formed in the insulating layer 11C, may also be applied to other insulating layers 11. Although it has been stated that the boundaries of multiple insulating layers 11 may be defined by dummy electrodes 13, in areas where dummy electrodes 13 are not placed in a planar view, the boundaries of multiple insulating layers 11 may be ambiguous.

[0117] Figure 4 illustrates a configuration in which the base electrode 15 is slightly embedded in the insulating layer 11C. In this example, it is assumed that the base electrode 15 (conductive paste) placed on the upper surface of the outermost ceramic green sheet is pressed into the ceramic green sheet. In both the examples in Figure 4 and Figure 6, the amount of embedding of the base electrode 15 in the insulating layer 11 is arbitrary. Furthermore, regardless of the amount of embedding, the embedding method is also arbitrary.

[0118] (4.3. Embodiments not shown) Although not specifically illustrated, other embodiments will be described.

[0119] The cover 9 may be provided on only one of the upper or lower surfaces of the functional unit 7. The capacitor 1 may be distributed from one factory to another without the external electrodes 5 attached (i.e., the main body 3).

[0120] The capacitor may have an outer resin covering the entire structure as illustrated in Figure 1 or Figure 5, and lead wires connected to the external electrodes 5 and extending from the outer resin. In another view, the capacitor may be a through-hole mounting type rather than a surface-mount type. In such an embodiment, one external electrode 5 may cover only one side. Also, the number of terminals (external electrodes 5) of the capacitor is not limited to two or four, but may be three or five or more.

[0121] The two types of internal electrodes 19, each connected to a different external electrode 5, may be stacked alternately in pairs rather than one at a time. In this case, for example, the thickness of the dielectric layer 17 between two opposing internal electrodes 19 connected to the same external electrode 5 may be thinner than the thickness of the dielectric layer 17 between two opposing internal electrodes 19 connected to different external electrodes 5. As can be seen from this, the multiple dielectric layers 17 do not have to have the same shape and size.

[0122] Furthermore, the two types of internal electrodes 19 connected to different external electrodes 5 do not necessarily have to face each other. For example, a circuit in which two parallel plate capacitors are connected in series may be formed by providing two types of internal electrodes 19 connected to different external electrodes 5 on the same layer, and providing an internal electrode 19 facing the two types of internal electrodes 19. Alternatively, a circuit in which three or more parallel plate capacitors are connected in series may be formed.

[0123] In the example shown in Figure 5, the rectangular internal electrode 19 is sandwiched between dielectric layers 17 that extend on both sides (outward) in the D2 direction than the two long sides of the internal electrode 19 parallel to the D1 direction. As a result, the two long sides are not exposed from the -D2 side and +D2 side of the main body 203. However, the configuration that prevents the long sides from being exposed may also be achieved by stacking other dielectric layers on the -D2 side and +D2 side of the laminate composed of the dielectric layer 17 and the insulating layer 11. From another viewpoint, the main body 203 does not need to be a laminated structure in its entirety.

[0124] Electronic components are not limited to capacitors. For example, electronic components may be multilayer electronic components other than capacitors, or non-multilayer electronic components. Examples of multilayer electronic components include multilayer inductors, multilayer varistors, multilayer ferrite beads, multilayer thermistors, and multilayer filters. Non-multilayer electronic components are diverse, but an example is an integrated circuit (IC).

[0125] A multilayer electronic component has a functional part (7) in which insulators (e.g., dielectric layers 17) and conductors (e.g., internal electrodes 19) are alternately stacked. In such a configuration, a cover 9 having two or more insulating layers 11 can be formed, for example, as an extension of the process of forming the functional part. Therefore, even if the configuration of the cover 9 according to the embodiment is adopted, the likelihood of the manufacturing process becoming complicated is reduced.

[0126] A multilayer ceramic filter may, for example, have an LC circuit. As can be seen from this example, a multilayer electronic component may implement two or more functions (capacitor and inductor). The parts that implement different functions may be different parts in a planar view and / or different parts in a side view.

[0127] (5. Summary of the Embodiments) In the following, the configuration of the electronic component according to the embodiment is extracted, and the effects of the extracted configuration are illustrated. However, the effects illustrated below do not necessarily have to be achieved. Also, for convenience, the reference numerals of the first embodiment are used below. However, the matters described below are also the same for other embodiments unless they cause inconsistencies. Also, to reiterate, unless they cause inconsistencies, the term "void density" may be replaced with the term "void occupied area ratio" (or the term "void density and void occupied area ratio").

[0128] Capacitor 1 (an example of an electronic component) has a functional part 7 and a cover 9 (an example of a cover). The functional part 7 has an upper surface (an example of a first surface) facing the +D3 side (an example of a first side) in the D3 direction (an example of a first direction). The cover 9 overlaps the upper surface of the functional part 7. The cover 9 also has two or more (three in the example of Figure 4) insulating layers 11 and one or more dummy electrodes 13 (two in the example of Figure 4) that overlap alternately in the D3 direction, and an underlay electrode 15 that overlaps the +D3 side surface (upper surface) of the outermost insulating layer 11C.

[0129] The area of ​​the cover 9 where the base electrode 15 is located shall be referred to as the first range A1. The number of voids 21 per unit area in a cross-section along the D3 direction shall be referred to as the void density. In this case, in the first range A1, the void density of the innermost insulating layer 11A is smaller than the void density of the outermost insulating layer 11C.

[0130] And / or, when the total area of ​​voids 21 per unit area in a cross-section along the D3 direction is referred to as the void area ratio, in the first range A1, the void area ratio of the innermost insulating layer 11A is smaller than the void area ratio of the outermost insulating layer 11C.

[0131] Therefore, as described in the overview of the embodiment, for example, it is possible to reduce cracks in the insulating layer 11A that is relatively close to the functional part 7, while improving the peel strength between the outermost insulating layer 11C and the underlying electrode 15. More specifically, reducing the void density in the insulating layer 11A contributes to reducing the number of voids 21 that can become crack initiation points, for example. Reducing the void-occupied area ratio in the insulating layer 11A contributes to reducing the stress concentrated around the voids 21, for example. However, as previously mentioned, in reality, void density and void-occupied area ratio are often correlated.

[0132] The number of insulating layers 11 may be three or more. In the first range A1, the void density of one or more insulating layers 11B (not each of them individually, but the whole) located between the outermost insulating layer 11C and the innermost insulating layer 11A may be less than the void density of the outermost insulating layer 11C, and greater than the void density of the innermost insulating layer 11A (with respect to void density, 11A < 11B < 11C).

[0133] In this case, for example, the probability of a sudden change in void density from insulating layer 11A to insulating layer 11C is reduced. As a result, for example, the mechanical properties of adjacent insulating layers 11 in the D3 direction become similar, and it is expected that the stress between them will be reduced.

[0134] In the first range A1, the void density of the innermost insulating layer 11A may be 3 / 4 or less of the void density of the outermost insulating layer 11C.

[0135] In this case, for example, the difference in void density between the insulating layers 11A and 11C is relatively large, and consequently, the effects described above are more likely to occur.

[0136] The cover 9 may have a side facing the D1 direction (an example of a second direction) that intersects the D3 direction (for example, the side facing +D1 as shown in Figure 4). The base electrode 15 may extend in the D1 direction to the above-mentioned side facing +D1. Assuming that the first range A1 is divided into three equal parts in the D1 direction, the second range A2 on the +D1 side, the third range A3 in the center, and the fourth range A4 on the -D1 side are defined. In this case, in two or more (all) insulating layers 11 (not individually, but as a whole), the void density of the fourth range A4 and the second range A2 may be smaller than the void density of the third range A3.

[0137] In this case, for example, the second range A2 and the fourth range A4 are located at the ends of the base electrode 15, making them susceptible to moisture intrusion. However, by reducing the number of voids 21 at these ends, moisture intrusion can be reduced, thereby improving reliability. Furthermore, the likelihood of cracks occurring at a location relatively close to the end of the external electrode 5 on the -D1 side (the fourth range A4 side relative to the third range A2) can be reduced. Multilayer ceramic capacitors often develop cracks at the end of the external electrode on the -D1 side. By improving reliability at such ends, the reliability of the capacitor 1 can be effectively improved.

[0138] The thickness of the cover 9 in the first range A1 may be 25 μm or less.

[0139] In this case, for example, the thickness of the cover 9 is relatively thin, and consequently, cracks in the insulating layer 11A have a relatively large impact on the electrical and / or mechanical reliability of the capacitor 1. Therefore, the effect of reducing the void density of the insulating layer 11A is effectively realized.

[0140] The thickness of the cover 9 in the first range A1 may be 1 / 5 or more of the thickness of the functional part 7.

[0141] In this case, for example, since the thickness of the cover 9 accounts for a relatively large proportion of the thickness of the capacitor 1, the mechanical reliability of the cover 9 has a relatively large influence on the mechanical and / or electrical reliability of the capacitor 1. Therefore, the effect of reducing the void density of the insulating layer 11A is effectively realized.

[0142] Capacitor 1 may further have external electrodes 5. The external electrodes 5 may span the top surface and side surface of cover 9 along the D3 direction, as well as the side surface of functional part 7 along the D3 direction. Functional part 7 may have a plurality of dielectric layers 17 (an example of an insulator layer) and a plurality of internal electrodes 19 (an example of a conductor) that are alternately overlapping in the D1 direction. The external electrodes 5 may be joined to at least a portion of the internal electrodes 19 on the side surface of functional part 7, to dummy electrodes 13 on the side surface of cover 9, and further joined to base electrodes 15 on the top surface of cover 9.

[0143] In this case, for example, as described above, the cover 9 according to the embodiment can be realized as an extension of the process of forming the laminated functional part 7. Also, for example, the internal electrode 19 and the external electrode 5 can be directly connected on the side surface of the main body 3 without using the base electrode 15 to reduce electrical resistance. On the other hand, since the external electrode 5 is fixed to the upper surface of the main body 3 via the base electrode 15, the fixing strength is improved. And the effect of having a relatively high void density in the insulating layer 11C is effective in improving this fixing strength.

[0144] In the embodiments described above, capacitors 1 and 201 are examples of electronic components. The D3 direction is an example of a first direction. The +D3 side is an example of a first side. The upper surface of the functional part 7 is an example of a first surface. The D1 direction is an example of a second direction. The +D3 side of the cover 9 is an example of a first side. The dielectric layer 17 is an example of a non-conducting layer. The internal electrode 19 is an example of a conductor. The technology described herein is not limited to the embodiments described above and may be implemented in various forms. For example, the embodiments described above may be combined as appropriate.

[0145] The following concepts may be extracted from this disclosure: An electronic component comprises a functional portion and a cover portion. The functional portion has a first surface facing a first side in a first direction. The cover portion overlaps the first surface. The cover portion also has one or more insulating layers overlapping the first surface, and a base electrode overlapping the first side surface of the outermost insulating layer, and has a first side surface facing a second direction intersecting the first direction. The base electrode extends in the second direction to the first side surface. Assuming that the first range is divided into three equal parts in the second direction, a second range on the side of the first side surface, a third range in the center, and a fourth range opposite to the first side surface are defined. In the one or more insulating layers, the void density in the second range and / or the fourth range is smaller than the void density in the third range. [Explanation of symbols]

[0146] 1...Capacitor (electronic component), 7...Functional part, 9...Cover (cover part), 11...Insulating layer, 13...Dummy electrode, 15...Base electrode, 21...Void.

Claims

1. A functional part having a first surface facing the first side in the first direction, The cover portion overlapping the first surface, It has, The aforementioned cover portion is Two or more insulating layers and one or more dummy electrodes that are alternately overlapping in the first direction, The outermost insulating layer has an underlay electrode that overlaps it from the first side, The aforementioned base electrode is exposed on the first side surface of the cover portion, The one or more dummy electrodes are exposed on the first side surface of the cover portion facing the second direction intersecting the first direction, Of the cover portion, the area that overlaps with the base electrode or dummy electrode in a planar perspective view from the first direction is referred to as the first range, and the total area of ​​voids per unit area in a cross-section along the first direction is referred to as the void occupancy area ratio. In the first range, The void area ratio of the outermost insulating layer is 0.300% or less, and The void area ratio of the innermost insulating layer is smaller than the void area ratio of the outermost insulating layer. Electronic components.

2. The number of insulating layers is three or more. In the first range, the void area ratio of one or more insulating layers located between the outermost insulating layer and the innermost insulating layer is smaller than the void area ratio of the outermost insulating layer and larger than the void area ratio of the innermost insulating layer. The electronic component according to claim 1.

3. In the first range, the void area ratio of the innermost insulating layer is 3 / 4 or less of the void area ratio of the outermost insulating layer. The electronic component according to claim 1.

4. Assuming that the first range is divided into three equal parts in the second direction, and defining the second range on the first side, the third range in the center, and the fourth range on the opposite side from the first side, in the two or more insulating layers, the void area ratio of the fourth range and the second range is smaller than the void area ratio of the third range. The electronic component according to claim 1.

5. In the cover portion, the void area ratio of the innermost insulating layer in the first range is smaller than the void area ratio of the insulating layer outside the first range. The electronic component according to claim 1.

6. The average equivalent diameter of the voids in the aforementioned substrate electrode is greater than the average equivalent diameter of the voids in the aforementioned insulating layer. The electronic component according to claim 1.

7. The innermost insulating layer in the cover portion is located between the dummy electrode that is closest to the functional portion among the one or more dummy electrodes and the functional portion. The electronic component according to claim 1.

8. The aforementioned base electrode is embedded in the outermost insulating layer. The electronic component according to claim 1.

9. The thickness of the base electrode is between 2 and 20 times the thickness of each of the one or more dummy electrodes. The electronic component according to claim 1.

10. It has an external electrode that contacts the base electrode from the first side and contacts the one or more dummy electrodes from the side that the first side faces. The electronic component according to claim 1.

11. The external electrode is formed by plating. The electronic component according to claim 10.

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