Substrates and printed circuit boards containing nanotwinned metal layers

Abstract

The present invention provides a substrate and printed circuit board containing a nano-twin metal layer that can easily accommodate fine pitches such as microbumps and offer superior reliability. [Solution] The present invention relates to a substrate comprising a substrate, a seed layer disposed on the substrate, and a nanotwin metal layer disposed on the seed layer, wherein the seed layer comprises a randomly oriented crystal structure, a crystal structure preferentially oriented on the (200) plane and / or a crystal structure preferentially oriented on the (220) plane, and a printed circuit board formed using the same.

Description

Technical Field

[0001] The present invention relates to a substrate including a nanobimodal metal layer and a printed circuit board formed using such a substrate including a nanobimodal metal layer.

Background Art

[0002] Recently, with the emergence of high-performance products such as artificial intelligence chips and substrates for servers, more input / output terminals for realizing high performance have been required, and as a result, miniaturization of fine pitches has been required. For example, miniaturization of fine pitches of microbumps formed in the mounting area of semiconductor chips on package substrates may be required. In addition, with the increase in power, high-temperature operation reliability is required before and after mounting semiconductor chips.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the various objects of the present invention is to provide a substrate and a printed circuit board including a nanobimodal metal layer that can easily cope with miniaturization of fine pitches such as microbumps and can provide more excellent reliability.

Means for Solving the Problems

[0004] One of the various solutions proposed in the present invention is to form a nanobimodal metal, for example, nanobimodal copper, based on a seed layer including a crystal structure that is not preferentially oriented on the (111) plane, and apply the formed metal layer to a wiring layer or the like of a printed circuit board.

[0005] For example, a substrate including a nanobimodal metal layer according to an example can include a substrate, a seed layer disposed on the substrate, and a nanobimodal metal layer disposed on the seed layer. At this time, the seed layer can include a randomly oriented crystal structure, a crystal structure preferentially oriented on the (200) plane, and / or a crystal structure preferentially oriented on the (220) plane.

[0006] For example, a printed circuit board according to one example may include an insulating layer and a wiring layer disposed on the insulating layer, the wiring layer may include a seed layer and a metal layer disposed on the seed layer, in which case the seed layer may include electrolytic copper foil, rolled copper foil, electrolytic copper layer, electroless copper layer, electrolytic nickel layer and / or electroless nickel layer, and the metal layer may include nanotwinned copper. [Effects of the Invention]

[0007] One of the various effects of the present invention is the ability to provide a substrate and printed circuit board containing a nanotwin metal layer that can easily accommodate fine pitching such as microbumps and provide superior reliability. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram illustrating an example of an electronic equipment system. [Figure 2] This is a perspective view showing a schematic example of an electronic device. [Figure 3] This is a schematic cross-sectional view showing an example of a substrate containing a nanotwinned metal layer. [Figure 4] This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 5] A schematic cross-sectional image of nanotwinned copper is shown. [Figure 6] A schematic cross-sectional image of nanotwinned copper is shown. [Figure 7] A schematic cross-sectional image of nanotwinned copper is shown. [Modes for carrying out the invention]

[0009] The present invention will be described below with reference to the attached drawings. In the drawings, the shape and size of the elements may be exaggerated or reduced for clearer explanation.

[0010] Figure 1 is a block diagram illustrating an example of an electronic equipment system.

[0011] Referring to the drawing, the electronic device 1000 houses the main board 1010. The main board 1010 is physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040, etc. These are also connected to other electronic components, which will be described later, to form various signal lines 1090.

[0012] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). It is also true that these chip-related components 1020 may be combined with each other. The chip-related components 1020 may also be in the form of a package containing the aforementioned chips and electronic components.

[0013] The network-related component 1030 includes, but is not limited to, any other wireless and wired protocols specified in Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth®, 3G, 4G, 5G, and subsequent versions. It also includes any other numerous wireless or wired standards and protocols. Of course, the network-related component 1030 may be combined with the chip-related component 1020.

[0014] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (Electromagnetic Interference) filters, MLCCs (Multi-Layer Ceramic Capacitors), etc. However, they are not limited to these, and may also include passive elements in chip component form used for a variety of other applications. Of course, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0015] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the main board 1010, or not. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, a battery 1080, etc. However, it is not limited to these, and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. Of course, other electronic components used for various purposes may also be included depending on the type of electronic device 1000.

[0016] The electronic device 1000 may be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smartwatch, automobile, server, etc. However, it is not limited to these, and of course it may be any other electronic device that processes data.

[0017] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0018] Referring to the drawings, the electronic device could be, for example, a smartphone 1100. Inside the smartphone 1100 is a motherboard 1110, to which various components 1120 are physically and / or electrically connected. Other components, such as a camera module 1130 and / or a speaker 1140, may or may not be physically and / or electrically connected to the motherboard 1110. Some of the components 1120 may be the aforementioned chip-related components, for example, a component package 1121, but are not limited to this. The component package 1121 may be in the form of a printed circuit board on which electronic components, including active and / or passive components, are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board with the active and / or passive components incorporated. On the other hand, the electronic device is not necessarily limited to a smartphone 1100, and as mentioned above, it may be other electronic devices.

[0019] FIG. 3 is a cross-sectional view schematically showing an example of a substrate including a nanobimodal metal layer.

[0020] Referring to the drawings, a substrate 100 including a nanobimodal metal layer according to an example can include a substrate 110, a seed layer 121 disposed on the substrate 110, and a nanobimodal metal layer 122 disposed on the seed layer 121. The substrate 100 can include an organic insulating layer including an organic material such as epoxy or polyimide, but is not limited thereto, and may include an inorganic insulating layer including an inorganic material such as silicon (Si) as necessary. The seed layer 121 can include copper including a crystal structure that is not preferentially oriented in the (111) plane. For example, the seed layer 121 can include a randomly oriented crystal structure, a crystal structure preferentially oriented in the (200) plane, and / or a crystal structure preferentially oriented in the (220) plane. The seed layer 121 including such a crystal structure can include, for example, an electrolytic copper foil, a rolled copper foil, an electrolytic copper layer, an electroless copper layer, an electrolytic nickel layer, and / or an electroless nickel layer. The nanobimodal metal layer 122 can include a nanobimodal metal, for example, nanobimodal copper. The nanobimodal copper can include a plurality of columnar grains, and at least a part of the plurality of columnar grains can include nanobimodes. A transition layer 123 can be disposed in a boundary region between the seed layer 121 and the nanobimodal metal layer 122. The transition layer 123 can include a part of the seed layer 121 and a part of an initial growth layer of the nanobimodal metal layer 122. The transition layer 123 can be formed with a thickness within 20% of the thickness of the nanobimodal metal layer 122, but is not limited thereto.

[0021] On the other hand, a randomly oriented crystal structure can refer to a state in a polycrystalline metal or thin film structure where the crystal grains are not aligned in a specific direction but are randomly distributed in all directions. This can occur when, in a metallic structure, each crystal grain is arranged independently of the others and no preferential orientation appears. For example, a preferential orientation may not appear on a particular surface, and the directions of all crystal grains may be distributed independently. This can be measured using methods such as X-ray diffraction (XRD), pole figure, SAED (Selected Area Electron Diffraction), and EBSD (Electron Backscatter Diffraction). For example, in XRD data, the peak intensity of each diffracted surface may roughly match or be similar to the relative intensity ratio in an ideal polycrystalline sample. To quantitatively evaluate this, a texture coefficient can be calculated, and the texture coefficient of all surfaces may be approximately close to 1. Alternatively, the intensity may be uniformly distributed in the pole figure. Alternatively, in electron diffraction (SAED or EBSD), the orientation can be distributed in various directions, and a particular direction may not be dominant.

[0022] Also, a crystal structure with a preferred orientation on the (200) plane can mean that the (200) plane, which is a specific crystal plane in a polycrystalline metal or thin film structure, is preferred or mainly aligned compared to other planes. This can occur when, in a metal crystal structure, the lattice plane represented by the Miller index (200) grows or is oriented preferentially due to specific process conditions, energy states, or interactions with the substrate. This can be measured using X-ray diffraction (XRD), pole figure, SAED (Selected Area Electron Diffraction), EBSD (Electron Backscatter Diffraction), etc. For example, in X-ray diffraction (XRD) data, the preferred orientation of the (200) plane can be confirmed through the relative prominence of the (200) peak intensity compared to other peaks. A texture coefficient can be calculated to quantitatively evaluate this. If the texture coefficient of the (200) plane is relatively large compared to other planes, for example, if it is 1.5 or more, it can be determined that the (200) plane has a preferred orientation. Alternatively, in the pole figure, the diffraction radius and intensity of the (200) plane can be analyzed to confirm the orientation. Alternatively, in electron diffraction (SAED or EBSD), the fraction and orientation distribution of crystal grains having the (200) plane direction can be analyzed to confirm the preferred orientation.

[0023] Furthermore, a crystal structure with preferred orientation of the (220) plane can mean that in a polycrystalline metal or thin film structure, the (220) plane, a specific crystal plane, is preferred or primarily aligned to other planes. This can occur in a metallic crystal structure when a lattice plane represented by the Miller index (220) preferentially grows or is oriented due to specific process conditions, energy states, or interactions with the substrate. This can be measured using methods such as X-ray diffraction (XRD), pole figures, SAED (Selected Area Electron Diffraction), and EBSD (Electron Backscatter Diffraction). For example, in X-ray diffraction (XRD) data, the preferred orientation of the (220) plane can be confirmed by the relatively prominent intensity of the (220) peak compared to other peaks. To quantitatively evaluate this, a texture coefficient can be calculated, and if the texture coefficient of the (220) plane is relatively large compared to other planes, for example, 1.5 or higher, it can be determined that the (220) plane has preferred orientation. Alternatively, the orientation can be confirmed by analyzing the diffraction radius and intensity of the (220) plane in the pole figure. Or, the preferred orientation can be confirmed by analyzing the fraction and orientation distribution of crystal grains having the (220) plane direction in electron diffraction (SAED or EBSD).

[0024] Thus, the substrate 100 containing the nanotwin metal layer, as an example, may include a seed layer 121 that can be used in printed circuit boards, package substrates, etc., and such a seed layer 121 may include a crystal structure that is not preferentially oriented to the (111) plane, as described above. For example, when the crystal orientation state of the seed layer 121 is measured and analyzed using SAED (Selected Area Electron Diffraction), the (111) and other (hkl) planes may all show ring patterns of similar intensity, in which case it may not appear that the (111) plane is predominantly oriented. On the other hand, if the (111) plane is strongly oriented, the (111) plane may appear as a partial ring or point form, and the other (hkl) planes may show a relatively low intensity partial ring form, etc. Thus, when the seed layer 121 contains a crystal structure that is not preferentially oriented to the (111) plane, the

[0111] direction of at least one columnar crystal grain containing nanotwinned nanotwinned copper in the nanotwinned metal layer 122 can be tilted with respect to the growth direction GD at an angle θ of more than 0 degrees and less than or equal to 25 degrees. When such a nanotwinned metal layer 122 is applied to fine-pitch wiring, rewiring, pads, microbumps, etc., in package substrates, it is possible to suppress the generation and growth of Kirkendall voids, etc., during processes such as thermal compression bonding, thereby improving reliability. For example, such a nanotwinned copper structure has many triple points where twin boundaries and grain boundaries intersect, which may hinder the movement of vacancies, thereby suppressing the generation and growth of Kirkendall voids, etc.

[0025] On the other hand, the nanotwin metal layer 122 can have (111) plane nanotwin copper accounting for 80% or more but less than 100% in cross-section, and 90% or more but less than 100% on the surface. Furthermore, the nanotwin metal layer 122 can have a thickness of approximately 1 μm to 10 μm, or approximately 1 μm to 5 μm, and the size of at least one columnar crystal grain containing nanotwin copper can also be approximately 1 μm to 10 μm, or approximately 1 μm to 5 μm. However, it is not necessarily limited to these dimensions.

[0026] Figure 4 is a schematic cross-sectional view showing an example of a printed circuit board.

[0027] Referring to the drawings, the printed circuit board 200 in one example can be a multilayer substrate structure including a plurality of insulating layers 211, 212, 213, 241, 242, a plurality of wiring layers 221, 222, 223, 224, 250, and a plurality of via layers 231, 232, 233. For example, the printed circuit board 200 in one example may be a package substrate, but is not limited thereto. One or more of the wiring layers 221, 222, 223, 224, 250 may include the seed layer 121, the nanotwin metal layer 122, and the transition layer 123, respectively, as described in the substrate 100 containing the nanotwin metal layer in one example described above. For example, one or more of the multiple wiring layers 221, 222, 223, 224, 250 may each include a seed layer containing one or more of the following: electrolytic copper foil, rolled copper foil, electrolytic copper layer, electroless copper layer, electrolytic nickel layer, and electroless nickel layer, and a metal layer disposed on the seed layer containing nanotwinned copper. Furthermore, each of these may further include a transition layer disposed between them.

[0028] For example, the seed layer may include a crystal structure that is not preferentially oriented to the (111) plane. Also, the nanotwinned copper may contain a plurality of columnar crystal grains, and at least a portion of the plurality of columnar crystal grains may contain nanotwin crystals. Furthermore, at least one columnar crystal grain of the nanotwinned copper containing nanotwin crystals may be tilted in the

[0111] direction at an angle greater than 0 degrees and less than or equal to 25 degrees with respect to the growth direction. On the other hand, one or more of the plurality of wiring layers 221, 222, 223, 224, 250 may include one or more of the following: wiring, rewiring, pads, and / or microbumps, which include such a seed layer, metal layer, and transition layer. On the other hand, a more specific description of the seed layer, metal layer, and transition layer may be substantially the same as the description given for the substrate 100 containing the nanotwinned metal layer in the example described above.

[0029] The components of an example printed circuit board 200 will be described in more detail below with reference to the drawings.

[0030] A substrate containing multiple insulating layers 211, 212, 213, 241, 242, multiple wiring layers 221, 222, 223, 224, 250, and multiple via layers 231, 232, 233 can be a core-type multilayer substrate. For example, the substrate includes a core insulating layer 211, first and second core wiring layers 221 and 222 arranged on the upper and lower surfaces of the core insulating layer 211, respectively, a core via layer 231 that penetrates the core insulating layer 211 and connects the first and second core wiring layers 221 and 222, one or more first build-up insulating layers 212 arranged on the upper surface of the core insulating layer 211, one or more first build-up wiring layers 223 arranged on or within one or more first build-up insulating layers 212, one or more first build-up via layers 232 that penetrate one or more of the one or more first build-up insulating layers 212, one or more second build-up insulating layers 213 arranged on the lower surface of the core insulating layer 211, and one or more layers arranged on or within one or more second build-up insulating layers 213. The multilayer substrate may include, however, a second build-up wiring layer 224, one or more second build-up via layers 233 that penetrate one or more of the one or more second build-up insulating layers 213, a first outermost insulating layer 241 placed on the uppermost of the one or more first build-up insulating layers 212, a second outermost insulating layer 242 placed on the lowermost of the one or more second build-up insulating layers 213, and an outermost wiring layer 250 placed on the uppermost of the one or more first build-up wiring layers 223, at least partially covered by the first outermost insulating layer 241, with at least a portion of the other protruding above the first outermost insulating layer 241. However, it is not limited thereto, and the multilayer substrate may be a coreless type multilayer substrate. Furthermore, the multilayer substrate may be a hybrid multilayer substrate that includes both a core-type substrate portion and a coreless type substrate portion.

[0031] The core insulating layer 211 may include an organic insulating material. The organic insulating material may include, but is not limited to, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material obtained by mixing these insulating resins with an inorganic filler such as silica, or a resin impregnated with an inorganic filler into a core material such as glass fiber (glass cloth, glass fabric), such as an insulating layer of CCL (copper-clad laminate). The core insulating layer 211 may be thicker than each of the one or more first and second build-up insulating layers 212 and 213, but is not limited to this.

[0032] The first and second build-up insulating layers 212 and 213 may each contain an organic insulating material. The organic insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material obtained by mixing these insulating resins with an inorganic filler such as silica, or a resin impregnated with an inorganic filler into a core material such as glass fiber. Examples of insulating materials include prepreg, ABF (Ajinomoto Build-up Film), PID (Photo Imageble Dielectric), and RCC (Resin Coated Copper). The first and second build-up insulating layers 212 and 213 may each consist of multiple layers. In this case, the number of layers in the first and second build-up insulating layers 212 and 213 is not particularly limited and they may have the same number of layers, but this is not the case.

[0033] The first and second core wiring layers 221 and 222 can each contain a metal. Examples of metals that can be used include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Preferably, they can contain copper (Cu). The first and second core wiring layers 221 and 222 can each include a seed layer and a metal layer formed by plating on the seed layer. The seed layer can be a rolled copper foil or electrolytic copper foil of CCL (Copper Clad Laminate). Alternatively, the seed layer can be formed by electroless copper plating or electroless nickel plating. If necessary, it may also be formed by electrolytic nickel plating. The metal layer may be formed by electrolytic plating, or by the plating for nanotwin copper formation described above. The first and second core wiring layers 221 and 222 can perform a variety of functions depending on the design of the layer. For example, these can include ground patterns, power patterns, signal patterns, etc. These patterns can each include lines, traces, planes, pads, etc.

[0034] The first and second build-up wiring layers 223 and 224 can each contain a metal. Examples of metals that can be used include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Preferably, they can contain copper (Cu). The first and second build-up wiring layers 223 and 224 can each include a seed layer and a metal layer formed by plating on the seed layer. The seed layer can be rolled copper foil or electrolytic copper foil of RCC (Resin Clad Copper). Alternatively, the seed layer may be formed by electroless copper plating or electroless nickel plating. If necessary, it may also be formed by electrolytic nickel plating. The metal layer may be formed by electrolytic plating, or by the plating for forming nanotwinned copper described above. The first and second build-up wiring layers 223 and 224 can perform a variety of functions depending on the design of the layer. For example, ground patterns, power patterns, signal patterns, etc., may be included. These patterns may each include lines, traces, planes, pads, etc. The first and second build-up wiring layers 223 and 224 may each have multiple layers. In this case, the number of layers of the first and second build-up wiring layers 223 and 224 is not particularly limited and they may have the same number of layers, but are not limited to this.

[0035] The core via layer 231 may include through vias. Through vias can fill at least a portion of the through hole. Through vias may contain metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Preferably, it may contain copper (Cu). Through vias may include a seed layer formed on the wall surface of the through hole and a metal layer formed by plating on the seed layer. The seed layer may be formed by electroless copper plating or electroless nickel plating. If necessary, it may also be formed by electrolytic nickel plating. The metal layer may be formed by electrolytic plating, or by plating for the formation of nanotwinned copper as described above. Through vias can perform a variety of functions depending on the design. For example, they may include ground vias, power vias, signal vias, etc. Through vias may have a substantially hourglass shape or a cylindrical shape. There may be multiple through vias.

[0036] The first and second build-up via layers 232 and 233 may each include connecting vias. Each connecting via in the first and second build-up via layers 232 and 233 may be a filled via that fills a via hole, or a conformal via that is positioned along the wall of a via hole. Each connecting via in the first and second build-up via layers 232 and 233 may be arranged in a stacked type and / or staggered type. Each connecting via in the first and second build-up via layers 232 and 233 may contain metal, which may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Preferably, it may contain copper (Cu). Each connecting via of the first and second build-up via layers 232 and 233 may include a seed layer formed on the wall of a through-hole formed on the wall of a via hole, and a metal layer formed by plating on the seed layer. The seed layer may be formed by electroless copper plating or electroless nickel plating. If necessary, it may also be formed by electrolytic nickel plating. The metal layer may be formed by electrolytic plating, or by the plating for nanotwin copper formation described above. Each connecting via of the first and second build-up via layers 232 and 233 can perform a variety of functions depending on the design. For example, it may include ground vias, power vias, signal vias, etc. Each connecting via of the first and second build-up via layers 232 and 233 may have a substantially tapered shape, for example, tapered in opposite directions to each other. Each connecting via of the first and second build-up via layers 232 and 233 may be multiple. Each of the first and second build-up via layers 232 and 233 may be multiple layers. In this case, the number of layers in the first and second build-up via layers 232 and 233 is not particularly limited and may be the same as the number of layers in each layer, but is not limited to this.

[0037] The first and second outermost insulating layers 241 and 242 may each contain an organic insulating material. The organic insulating material may be, but is not limited to, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material obtained by mixing these insulating resins with an inorganic filler such as silica, such as ABF (Ajinomoto Build-up Film) or SR (Solder Resist). The first and second outermost insulating layers 241 and 242 are positioned on the uppermost and lowermost sides of the substrate to protect the internal structure. If necessary, the second outermost insulating layer 242 may have multiple SMD (Solder Mask Defined) and / or NSMD (Non-Solder Mask Defined) type openings.

[0038] The outermost wiring layer 250 may include microbumps. The microbumps may be columnar in shape, but are not limited to this. The microbumps may be made of metal. Examples of metals that can be used include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Preferably, copper (Cu) may be included. The microbumps may include a seed layer and a metal layer formed by plating on the seed layer. The seed layer may be formed by electroless copper plating or electroless nickel plating. If necessary, it may be formed by electrolytic nickel plating. The metal layer may be formed by electrolytic plating, or by the plating for nanotwin copper formation described above. Depending on the design, the microbumps can perform a variety of functions. For example, they may include ground bumps, power bumps, signal bumps, etc. There may be multiple microbumps.

[0039] Figures 5 to 7 show schematic cross-sectional images of nanotwinned copper, respectively.

[0040] Figure 5 may be a cross-sectional image of nanotwinned copper formed on rolled copper foil. Such a cross-sectional image can be obtained by photographing the cross-section of the nanotwinned metal layer using an electron microscope, such as an SEM (Scanning Electron Microscope) or TEM (Transmission Electron Microscope). On the other hand, the rolled copper foil may be copper foil of CCL (Copper Clad Laminate) used as a core layer in printed circuit boards. Referring to the drawing, nanotwinned copper can be well formed on such rolled copper foil. In this case, the

[0111] direction of the columnar crystal grains of the formed nanotwinned copper can be tilted in the growth direction. Therefore, the above-mentioned technical effects can be obtained. Such a cross-sectional image can be applied to the substrate 100 and / or printed circuit board 200 containing the nanotwinned metal layer described above.

[0041] Figure 6 may be a cross-sectional image of nanotwinned copper formed on an electrolytic nickel layer, which is also obtained by photographing the cross-section of the nanotwinned metal layer using an electron microscope as described above. Referring to the figure, nanotwinned copper can be well formed on an electrolytic nickel layer which may be used for package substrates, etc., and the

[0111] direction of the columnar crystal grains of nanotwinned copper can be tilted in the growth direction. Therefore, the above-mentioned technical effects can be obtained. Such a cross-sectional image can also be applied to the substrate 100 and / or printed circuit board 200 containing the nanotwinned metal layer described above.

[0042] Figure 7 may be a cross-sectional image of an electroless copper layer, for example, when nanotwinned copper is formed on chemical copper, and this too is obtained by photographing the cross-section of the nanotwinned metal layer using an electron microscope as described above. Referring to the figure, nanotwinned copper can be well formed on an electroless copper layer, for example, chemical copper, which can be used as a seed layer for circuit formation on a printed circuit board, and the

[0111] direction of the columnar crystal grains of nanotwinned copper can be tilted in the growth direction. Therefore, the above-mentioned technical effects can be obtained. Such a cross-sectional image can also be applied to the substrate 100 and / or printed circuit board 200 containing the nanotwinned metal layer described above.

[0043] In this invention, the expression "cover" can include not only covering the entire surface but also covering at least a part of it, and can include not only covering directly but also covering indirectly. Similarly, the expression "fill" can include not only filling completely but also filling at least a part of it, and can also include filling generally. For example, it can include cases where there are some gaps or voids. Furthermore, the expression "enclose" can include not only completely enclosing but also partially enclosing and generally enclosing. Additionally, "expose" can include not only completely exposing but also partially exposing, and exposure can mean exposure from the embedding layer of the component. For example, an opening exposing a pad may mean exposing the pad from the outermost insulating layer, and a surface treatment layer or the like may be further placed on the exposed pad.

[0044] In this invention, "substantially" can be determined by including process errors, positional deviations, measurement errors, etc. that occur during the manufacturing process. For example, having a substantially certain shape can include not only having that shape completely, but also having that shape generally. Similarly, being substantially tapered can include not only a perfectly tapered shape, but also a roughly tapered shape. For example, this can be determined by the overall shape.

[0045] In this invention, "on a cross-section" can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. "On a plane" can mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed from the top or bottom.

[0046] In this invention, terms such as "lower side," "lower part," and "lower surface" are used for convenience to mean the downward direction relative to the cross-section in the drawing, while terms such as "upper side," "upper part," and "upper surface" are used to mean the opposite direction. However, this is merely a definition of direction for explanatory purposes, and it goes without saying that the scope of rights in the claims is not particularly limited by such descriptions of direction, and the concepts of "upper" and "lower" may change at any time.

[0047] In this invention, "connected" refers not only to directly connected components but also to indirectly connected components, such as those connected through an adhesive layer. Furthermore, "electrically connected" refers to both physically connected and non-connected components. The terms "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without exceeding the scope of the rights, the first component may be named as the second component, and similarly, the second component may be named as the first component.

[0048] In this invention, the crystal structure, thickness, etc., can be measured based on the cross-section obtained by polishing or cutting the printed circuit board. For example, after obtaining a sample including the cut cross-section, necessary experiments can be carried out based on it. The cut cross-section may be a vertical or horizontal cross-section, and the respective values ​​can be measured based on the required cut cross-section. On the other hand, when measuring values, if the values ​​are not constant, the values ​​can be determined by the average value of the values ​​measured at any five points.

[0049] The expression "an example" as used in this invention does not mean that each embodiment is identical to the others, but is provided to highlight and explain the unique and distinct features of each embodiment. However, the examples presented above do not preclude their realization in combination with features of other examples. For example, even if a matter described in one example is not described in another example, it can be understood as a description related to the other example, as long as there is no contradictory or contrary explanation of that matter in the other example.

[0050] The terms used in this invention are used merely to illustrate an example and are not intended to limit the invention. In this context, singular expressions include plural expressions unless they clearly have a different meaning. [Explanation of symbols]

[0051] 1000:Electronic equipment 1010: Mainboard 1020: Chip-related components 1030: Network-related components 1040: Other parts 1050: Camera 1060: Antenna 1070: Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Motherboard 1120: Parts 1121: Parts Package 1130: Camera module 1140: Speaker 100: Substrate containing nanotwinned metal layer 110: Circuit board 121: Seed layer 122: Nanotwined metal layer 123: Transition layer 200: Printed circuit board 211, 212, 213, 241, 242: Insulating layer 221, 222, 223, 224, 250: Wiring layer 231, 232, 233: Beer layer GD: Growth direction θ: Angle

Claims

1. circuit board and A seed layer disposed on the substrate, The seed layer comprises a nanotwinned metal layer disposed on the seed layer, The seed layer includes one or more of the following: a randomly oriented crystal structure, a crystal structure with preferred orientation to the (200) plane, and a crystal structure with preferred orientation to the (220) plane. A substrate containing a nanotwinned metal layer.

2. The seed layer includes one or more of the following: electrolytic copper foil, rolled copper foil, electrolytic copper layer, electroless copper layer, electrolytic nickel layer, and electroless nickel layer. A substrate comprising the nanotwin metal layer described in claim 1.

3. The aforementioned nanotwin metal layer contains nanotwin copper, A substrate comprising the nanotwin metal layer described in claim 1.

4. The aforementioned nanotwinned copper contains a plurality of columnar crystal grains, At least a portion of the plurality of columnar crystal grains contains nanotwin crystals. A substrate comprising the nanotwin metal layer described in claim 3.

5. At least one columnar crystal grain containing the nanotwin of the nanotwin copper is tilted in the [111] direction at an angle greater than 0 degrees and less than or equal to 25 degrees with respect to the growth direction. A substrate comprising the nanotwin metal layer described in claim 4.

6. The nanotwinned metal layer has (111) plane nanotwinned copper making up 80% or more and less than 100% on the cross-section, and 90% or more and less than 100% on the surface. A substrate comprising the nanotwin metal layer described in claim 3.

7. The aforementioned nanotwin metal layer has a thickness of 1 μm to 10 μm. A substrate comprising the nanotwin metal layer described in claim 3.

8. The transition layer is disposed in the boundary region between the seed layer and the nanotwin metal layer and further includes a transition layer comprising a portion of each of the seed layer and the nanotwin metal layer. A substrate comprising the nanotwin metal layer described in claim 1.

9. The aforementioned substrate is an insulating layer containing an organic insulating material. A substrate comprising the nanotwin metal layer described in claim 1.

10. Insulating layer and, The insulating layer includes a wiring layer disposed on the insulating layer, The aforementioned wiring layer is A seed layer comprising one or more of the following: electrolytic copper foil, rolled copper foil, electrolytic copper layer, electroless copper layer, electrolytic nickel layer, and electroless nickel layer, Displaced on the seed layer, and including a metal layer containing nanotwinned copper, Printed circuit board.

11. The seed layer includes a crystal structure that is not preferentially oriented to the (111) plane. A printed circuit board according to claim 10.

12. The aforementioned nanotwinned copper contains a plurality of columnar crystal grains, At least a portion of the plurality of columnar crystal grains contains nanotwin crystals. A printed circuit board according to claim 10.

13. At least one columnar crystal grain containing the nanotwin of the nanotwin copper is tilted in the [111] direction at an angle greater than 0 degrees and less than or equal to 25 degrees with respect to the growth direction. The printed circuit board according to claim 12.

14. The aforementioned wiring layer is Displaced in the boundary region between the seed layer and the metal layer, further comprising a transition layer which includes a portion of each of the seed layer and the metal layer, A printed circuit board according to claim 10.

15. The wiring layer includes one or more of the following: wiring, rewiring, pads, and microbumps, each including the seed layer and the metal layer. A printed circuit board according to claim 10.

Images