Composite electronic components
Patent Information
- Application Number
- JP2025154521
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-12-24
- Filing Date
- 2025-09-17
- Publication Date
- 2026-07-06
AI Technical Summary
【0011】 本発明の様々な効果のうち一つは、キャパシタとバンプを結合する過程で最外層のSnめっき層の過度の形成を抑制して、複合電子部品の実装不良が発生するという問題を緩和することである。
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Figure 2026112384000001_ABST
Abstract
Claims
1. A capacitor comprising a dielectric layer, a body including internal electrodes arranged alternately with the dielectric layer, and external electrodes arranged on the body, The main body includes a bump positioned on the lower side and connected to the external electrode, The external electrode includes an electrode layer in contact with the internal electrode, a Ni plating layer disposed on the electrode layer, a first compound layer disposed on the Ni plating layer, a first Sn plating layer disposed on the first compound layer, a second compound layer disposed on the first Sn plating layer, and a second Sn plating layer disposed on the second compound layer. The bump is a composite electronic component comprising a bump body containing a conductive metal, a bump Ni plating layer disposed on the bump body, a first bump compound layer disposed on the bump Ni plating layer, a first bump Sn plating layer disposed on the first bump compound layer, a second bump compound layer disposed on the first bump Sn plating layer, and a second bump Sn plating layer disposed on the second bump compound layer.
2. The composite electronic component according to claim 1, wherein the first bump compound layer has surface roughness.
3. The composite electronic component according to claim 1, wherein the first bump compound layer has surface roughness on the capacitor side.
4. The composite electronic component according to claim 3, wherein the ten-point average roughness (Rz) of the first bump compound layer is 1.3 or less.
5. The composite electronic component according to claim 1, wherein the first Sn plating layer and the second Sn plating layer are in contact with the second compound layer.
6. The composite electronic component according to claim 1, wherein the first bump Sn plating layer and the second bump Sn plating layer are in contact with the second bump compound layer.
7. The composite electronic component according to claim 1, wherein the first compound layer, the second compound layer, the first bump compound layer, and the second bump compound layer each contain an intermetallic compound including Ni and Sn.
8. The composite electronic component according to claim 7, wherein the ratio of Sn element to Ni element in each of the first compound layer, the second compound layer, the first bump compound layer, and the second bump compound layer is 1 / 3 or more and 4 / 3 or less.
9. The composite electronic component according to any one of claims 1 to 8, wherein the first Sn plating layer is in contact with the first bump Sn plating layer, the second compound layer is in contact with the second bump compound layer, and the second Sn plating layer is in contact with the second bump Sn plating layer.
10. The aforementioned bump body comprises Cu, a composite electronic component according to any one of claims 1 to 8.
11. The composite electronic component according to any one of claims 1 to 8, wherein the electrode layer contains Cu.
12. The bump body includes Cu and O, The composite electronic component according to any one of claims 1 to 8, wherein the content of O relative to Cu is 0.5 at% or less.
Citation Information
Patent Citations
Multilayer ceramic capacitor
JP2023170119A
