Composite electronic components

JP2026112384APending Publication Date: 2026-07-06SAMSUNG ELECTRO MECHANICS CO LTD
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Patent Information

Application Number
JP2025154521
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-12-24
Filing Date
2025-09-17
Publication Date
2026-07-06

AI Technical Summary

Benefits of technology

【0011】 本発明の様々な効果のうち一つは、キャパシタとバンプを結合する過程で最外層のSnめっき層の過度の形成を抑制して、複合電子部品の実装不良が発生するという問題を緩和することである。

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Abstract

This mitigates the insufficient coupling force between the capacitor and the bump. [Solution] The composite electronic component includes a main body 110 including a dielectric layer 111, internal electrodes 121 and 122 arranged alternately with the dielectric layer, a capacitor including external electrodes 130 and 140 on the main body, and bumps 230 and 240 arranged on the lower side of the main body and connected to the external electrodes. The external electrode consists of electrode layers 131 and 141 in contact with the internal electrode, followed by Ni plating layers 132 and 142, first compound layers 135 and 145, first Sn plating layers 133 and 143, second compound layers 136 and 146, and second Sn plating layers 134 and 144, arranged in that order. The bump consists of a bump body 231 and 241 containing a conductive metal, followed by bump Ni plating layers 232 and 242, first bump compound layers 235 and 245, first bump Sn plating layers 233 and 243, second bump compound layers 236 and 246, and second bump Sn plating layers 234 and 244, arranged in that order.
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Claims

1. A capacitor comprising a dielectric layer, a body including internal electrodes arranged alternately with the dielectric layer, and external electrodes arranged on the body, The main body includes a bump positioned on the lower side and connected to the external electrode, The external electrode includes an electrode layer in contact with the internal electrode, a Ni plating layer disposed on the electrode layer, a first compound layer disposed on the Ni plating layer, a first Sn plating layer disposed on the first compound layer, a second compound layer disposed on the first Sn plating layer, and a second Sn plating layer disposed on the second compound layer. The bump is a composite electronic component comprising a bump body containing a conductive metal, a bump Ni plating layer disposed on the bump body, a first bump compound layer disposed on the bump Ni plating layer, a first bump Sn plating layer disposed on the first bump compound layer, a second bump compound layer disposed on the first bump Sn plating layer, and a second bump Sn plating layer disposed on the second bump compound layer.

2. The composite electronic component according to claim 1, wherein the first bump compound layer has surface roughness.

3. The composite electronic component according to claim 1, wherein the first bump compound layer has surface roughness on the capacitor side.

4. The composite electronic component according to claim 3, wherein the ten-point average roughness (Rz) of the first bump compound layer is 1.3 or less.

5. The composite electronic component according to claim 1, wherein the first Sn plating layer and the second Sn plating layer are in contact with the second compound layer.

6. The composite electronic component according to claim 1, wherein the first bump Sn plating layer and the second bump Sn plating layer are in contact with the second bump compound layer.

7. The composite electronic component according to claim 1, wherein the first compound layer, the second compound layer, the first bump compound layer, and the second bump compound layer each contain an intermetallic compound including Ni and Sn.

8. The composite electronic component according to claim 7, wherein the ratio of Sn element to Ni element in each of the first compound layer, the second compound layer, the first bump compound layer, and the second bump compound layer is 1 / 3 or more and 4 / 3 or less.

9. The composite electronic component according to any one of claims 1 to 8, wherein the first Sn plating layer is in contact with the first bump Sn plating layer, the second compound layer is in contact with the second bump compound layer, and the second Sn plating layer is in contact with the second bump Sn plating layer.

10. The aforementioned bump body comprises Cu, a composite electronic component according to any one of claims 1 to 8.

11. The composite electronic component according to any one of claims 1 to 8, wherein the electrode layer contains Cu.

12. The bump body includes Cu and O, The composite electronic component according to any one of claims 1 to 8, wherein the content of O relative to Cu is 0.5 at% or less.

Citation Information

Patent Citations

  • Multilayer ceramic capacitor

    JP2023170119A