Logic synthesis apparatus, processing method for logic synthesis apparatus, and program

Abstract

This will reduce the effort required to generate synthetic netlists. [Solution] The logic synthesis apparatus includes: an extraction means for extracting from a netlist portions that are logically equivalent to asset circuit formulas registered in a database as an extracted netlist; a circuit structure determination means for determining the structure of the circuit to be used in the extracted netlist from the database based on the frequency of the extracted netlist and the frequency of the logically equivalent asset circuit formulas registered in the database; a timing margin calculation means for calculating the timing margin based on the determined circuit structure; a cell characteristic determination means for determining the characteristics of the cells to be used in the extracted netlist from the database based on the timing margin calculated by the timing margin calculation means; and a logic synthesis means for converting the netlist into a synthesized netlist having physical characteristics using the circuit structure determined by the circuit structure determination means and the cell characteristics determined by the cell characteristic determination means.

Description

Technical Field

[0001] The present invention relates to a logic synthesis device, a processing method of the logic synthesis device, and a program.

Background Art

[0002] As a design procedure for a large-scale integrated circuit (hereinafter referred to as LSI), generally the following flow is known.

[0003] First, the requirements specification of the LSI is defined. Next, the operation of a logic circuit corresponding to the requirements specification is described in a hardware description language (hereinafter referred to as HDL) such as VHDL, Verilog HDL, or SyntemVerilog, and RTL is created. Next, logic synthesis is performed using a cell library and a timing constraint file for setting the operating frequency of the circuit. In the cell library, physical characteristics such as basic logic gates (hereinafter referred to as primitive cells) such as AND and OR, logic gates realized by combinations of primitive cells (hereinafter referred to as composite cells), and the shapes and capacitance values of flip-flops (hereinafter referred to as FFs) are defined. As a result of logic synthesis, the RTL is converted into a gate-level synthesized netlist described in primitive cells, composite cells, and FFs (hereinafter referred to as cells), and the connection relationships of the respective cells. Finally, each cell described in the synthesized netlist is physically placed and wired, and the process proceeds to the manufacturing process of the LSI.

[0004] Here, the correspondence relationship between the RTL and the synthesized netlist is not uniquely determined, and varies depending on the circuit structure of the arithmetic unit selected during logic synthesis and the characteristics of the cells. Also, depending on the circuit structure of the arithmetic unit selected and the characteristics of the cells, the quality aspects such as area and performance also change. In logic synthesis, a circuit that satisfies the criteria of area and performance is realized by repeatedly adjusting these items.

[0005] The increasing size of circuits has led to an increase in the effort required to optimize the circuit structure and cell characteristics of arithmetic units (hereinafter referred to as circuit optimization). However, development time is limited, making it difficult to dedicate a significant amount of time to iterative circuit optimization. Therefore, a technique has been developed to reuse the results of circuit structure selection for arithmetic units from previous logic synthesis processes.

[0006] Patent Document 1 discloses a method for reducing the man-hours involved in selecting the circuit structure of an arithmetic unit by comparing the logically equivalent sections of an existing and a new composite netlist in terms of delay time and area, and adopting the logic structure used in the existing composite netlist in the new composite netlist if the existing composite netlist is superior.

[0007] Furthermore, Patent Document 2 discloses a method for reducing the man-hours involved in selecting the circuit structure of an arithmetic unit by registering existing circuits in a database as pairs of RTL corresponding to Boolean expressions and the logic structure of the arithmetic unit that implements those expressions, and reusing the RTL for Boolean expressions that match the database when synthesizing a new circuit. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 11-353334 [Patent Document 2] Japanese Patent Publication No. 2019-197266 [Overview of the project] [Problems that the invention aims to solve]

[0009] However, the technology disclosed in the aforementioned patent documents reduces the man-hours required to select the circuit structure of the arithmetic unit, but it has the problem that it does not reduce the man-hours required to select the characteristics of the cells. In other words, it is necessary to optimize the characteristics of the cells after selecting the circuit structure of the arithmetic unit, so the reduction in man-hours is limited. [Means for solving the problem]

[0010] The logic synthesis apparatus includes: an extraction means for extracting from a netlist portions that are logically equivalent to asset circuit formulas registered in a database as an extracted netlist; a circuit structure determination means for determining the structure of the circuit to be adopted in the extracted netlist from the database based on the frequency of the extracted netlist extracted by the extraction means and the frequency of the logically equivalent asset circuit formulas registered in the database; a timing margin calculation means for calculating the timing margin based on the circuit structure determined by the circuit structure determination means; a cell characteristic determination means for determining the characteristics of the cells to be adopted in the extracted netlist from the database based on the timing margin calculated by the timing margin calculation means; and a logic synthesis means for converting the netlist into a synthesized netlist having physical characteristics using the circuit structure determined by the circuit structure determination means and the cell characteristics determined by the cell characteristic determination means. [Effects of the Invention]

[0011] According to the present invention, the effort required to generate a composite netlist can be reduced. [Brief explanation of the drawing]

[0012] [Figure 1] This is a block diagram showing an example of the functional configuration of a logic synthesis apparatus according to this embodiment. [Figure 2] This figure shows an example of a database according to this embodiment. [Figure 3] This flowchart shows the processing procedure of the logic synthesis apparatus according to this embodiment. [Figure 4] This figure shows an example of reusing the logic synthesis method according to this embodiment. [Figure 5] This is a block diagram showing an example of the hardware configuration of a logic synthesis apparatus according to this embodiment. [Modes for carrying out the invention]

[0013] Hereinafter, preferred embodiments of the present invention will be described in detail based on the accompanying drawings. For equivalent elements among the drawings, the same reference numerals are assigned, and repeated descriptions are omitted.

[0014] FIG. 5 is a block diagram showing a hardware configuration example of the logic synthesis device 120 according to this embodiment. The logic synthesis device 120 is, for example, a computer. The logic synthesis device 120 includes a bus 500, a CPU 501, a ROM 502, a RAM 503, an external storage device 504, a data communication I / F 505, an input device control unit 506, an input device 507, a display device control unit 508, and a display device 509.

[0015] The CPU (Central Processing Unit) 501 is a central processing unit and performs processing according to a specified program.

[0016] The ROM (Read Only Memory) 502 is a non-volatile storage and can store data and programs used in the processing of this embodiment.

[0017] The RAM (Random Access Memory) 503 is a volatile storage and temporarily holds programs and data.

[0018] ]END]]The external storage device 504 is a non-volatile storage and holds programs and data.

[0019] The CPU 501 receives programs and data stored in the ROM 502, the RAM 503, and the external storage device 504 and performs arithmetic processing.

[0020] The data communication I / F (Data Transfer interface) 505 controls the transmission and reception of data to and from an external device via a network. As the connection method for this data transmission and reception, a wired connection such as USB, IEEE 1394, or LAN, or a wireless connection such as Bluetooth or WiFi can be used.

[0021] The input device control unit 506 is an I / F that acquires information operated by the user with the input device 507 and transmits control information to each processing unit.

[0022] The input device 507 is a HID (Human Interface Device) such as a keyboard or a mouse. The user can perform an input operation via the input device 507.

[0023] The display device control unit 508 controls the data of the ROM 502, RAM 503, and external storage device 504 to be displayed on the display device 509.

[0024] Hereinafter, referring to FIG. 1, a functional configuration example of the logic synthesis device 120 according to the present embodiment will be described.

[0025] The logic synthesis device 120 includes a logic block library 121, a structure analysis unit 122, a database 123, an extraction unit 124, a circuit structure determination unit 125, a timing margin calculation unit 126, a cell characteristic determination unit 127, a logic synthesis unit 128, and a quality evaluation unit 129. By the CPU 501 executing a program, the functional configuration units in FIG. 1 can be realized. The external storage device 504 stores the logic block library 121 and the database 123.

[0026] The circuit description 100 describes the operation of the LSI. The circuit description 100 is described as RTL using HDL.

[0027] The timing constraint file 101 sets the operating frequency of the circuit description 100. The timing constraint file 101 is generally written according to Synopsys Design Constraints (SDC) and defines information such as the clock type, operating frequency, and external delay time.

[0028] The cell library 110 defines the physical information of all cells usable by the logic synthesis unit 128, which will be described later. The cell library 110 registers cells that realize various logics, and even for a single logic, multiple types of cells with different characteristics such as threshold voltage, drive capability, and gate length are registered. Since the physical characteristics of the cells depend on the technology, the cell library 110 is used differently for each technology.

[0029] Subset 111 is a subset of cell library 110 and is a standard cell library that defines the physical information of cells that can be used by the timing margin calculation unit 126 described later.

[0030] The logic synthesis unit 120 converts the circuit description 100 into a synthesized netlist 130, which will be described later. The following describes each element that makes up the logic synthesis unit 120.

[0031] The logic block library 121 defines logic blocks such as AND and OR that can be used in the structural analysis unit 122 described later. Unlike the cells defined in the cell library 110, the logic blocks defined in the logic block library 121 do not have physical characteristics and only represent input / output logic.

[0032] The structural analysis unit 122 converts the circuit description 100 into a technology-independent netlist that does not have physical characteristics, using the logic block library 121. The technology-independent netlist is represented as the connection relationships of logic blocks and is linked to timing information such as clock type, operating frequency, and external delay time by the timing constraint file 101.

[0033] Database 123 contains two or more asset circuit formulas that have undergone circuit optimization in the past. Asset circuit formulas are logical formulas that express the arithmetic and logical operation parts of a circuit using Boolean algebra, and are expressed using only a few Boolean operators for the sake of versatility when reused. In addition, each asset circuit formula is associated with two or more frequencies and, for each frequency, the logical structure and cell configuration that are suitable in terms of quality such as area and performance, as well as the characteristics of the cells, which are the result of circuit optimization.

[0034] When the logic synthesis unit 120 is used for the first time, the database 123 is empty, as no past circuit optimizations are registered. Furthermore, each time the logic synthesis unit 120 is used, database 123 is updated according to certain conditions. Details of these conditions will be described later.

[0035] The extraction unit 124 extracts logically equivalent sections from the technology-independent netlist to the asset circuit formulas registered in the database 123. Logically equivalent sections are parts of the technology-independent netlist where the number of inputs and outputs matches that of the asset circuit formula being compared, and where the output value matches that of the asset circuit formula being compared for all possible input value combinations. These sections are extracted from the technology-independent netlist as the extracted netlist.

[0036] The circuit structure determination unit 125 determines the circuit structure to be used in the extracted netlist. First, the circuit structure determination unit 125 compares the frequencies associated with the extracted circuit formula and the logically equivalent asset circuit formulas. If the frequency difference between the extracted circuit formula and the asset circuit formula with the closest frequency is below a preset threshold, the circuit structure, including the logical structure and cell configuration associated with that asset circuit formula, is adopted in the extracted netlist.

[0037] The timing margin calculation unit 126 calculates the timing margin of the extracted netlist. First, the timing margin calculation unit 126 converts the extracted netlist into the logic structure determined by the circuit structure determination unit 125.

[0038] Next, the timing margin calculation unit 126 replaces each logic block constituting the logical structure of the extracted netlist with the cell configuration determined by the circuit structure determination unit 125, using standard cells of the same logic included in the standard cell library 111.

[0039] The standard cell library 111 is limited to only one type each of threshold voltage, drive capability, and gate length, and there is a one-to-one correspondence between logic and cells. While methods for limiting the types include selecting the cell with the minimum threshold voltage, drive capability, and gate length, there are no specific restrictions. However, this is uniquely determined for a given cell library and is commonly used when creating the database 123 and when calculating timing margins within the logic synthesis unit 120.

[0040] Next, the timing margin calculation unit 126 obtains the clock period from the rising edge of the clock input to the first stage FF of the extracted netlist replaced with standard cells, to the rising edge of the clock input to the final stage FF. Finally, the timing margin calculation unit 126 calculates the timing margin by subtracting the delay time of the path that has the largest sum of the delay times of the standard cells and wiring between the two FFs from that clock period, and then dividing the result by the clock period.

[0041] Note that the method for calculating the timing margin is not limited to this; any value that serves as an indicator of the margin of time relative to the setup time constraint of the extracted netlist is acceptable.

[0042] The cell characteristic determination unit 127 determines the cell characteristics that the extracted netlist should adopt. Among the asset circuit formulas registered in the database 123 that are logically equivalent to the extracted netlist, if the timing margin difference between the extracted netlist and the asset circuit formula with the closest timing margin is less than or equal to a preset threshold, the cell characteristic determination unit 127 adopts the cell characteristics of that asset circuit formula for the extracted netlist.

[0043] The logic synthesis unit 128 converts the technology-independent netlist into a synthesized netlist 130. First, the logic synthesis unit 128 selects a logic structure for each circuit expression in the technology-independent netlist. In this process, for the portion of the technology-independent netlist corresponding to the extracted netlist, the logic synthesis unit 128 selects a logic structure determined in advance based on the results of the circuit structure determination unit 125.

[0044] Next, the logic synthesis unit 128 replaces each logic block constituting the logic structure of the technology-independent netlist with a cell from the cell library 110. In this process, for the portion of the technology-independent netlist corresponding to the extracted netlist, the logic synthesis unit 128 adopts the configuration and characteristics of the cells determined in advance based on the results of the circuit structure determination unit 125 and the cell characteristic determination unit 127. Finally, the logic synthesis unit 128 performs optimization processing on the entire circuit, including the boundaries of the extracted netlist, to obtain a gate-level synthesized netlist 130.

[0045] The quality evaluation unit 129 quantitatively calculates evaluation values ​​for the quality of the synthetic netlist, such as its area, based on predetermined items.

[0046] Figure 2 shows an example of database 123. Database 123 registers combinations of asset circuit formulas 201 that have been optimized in the past, the frequencies 202 that drive asset circuit formulas 201, the logic structures 203 of the arithmetic units used, and the cell configurations 204. In the example in Figure 2, three combinations of conditions 210, 220, and 230 are registered, which yielded favorable results in terms of quality, such as area and performance, when 8-bit adder circuits were logically synthesized at 500MHz, 750MHz, and 1000MHz, respectively.

[0047] The logic structure 203 for the arithmetic unit includes either an RCA (Ripple-Carry Adder), which has a long delay time but a small circuit size, or a CLA (Carry Look-Ahead Adder), which has a large circuit size but a short delay time.

[0048] Cell configuration 204 includes configurations where the cells realizing the circuit consist only of primitive cells, or configurations that also use composite cells.

[0049] Numbers 206-208 contain the final optimized usage ratios for threshold voltage, drive capability, and gate length, based on combinations of numbers 201 through 204.

[0050] For example, a threshold voltage ratio of 206 in a 210 combination indicates that cells with low, medium, and high threshold voltages are used in a 0:0:1 ratio, meaning that 100 percent of the cells used are those with high threshold voltages, long delay times, and low power consumption.

[0051] In a combination of 210, a drive capability ratio of 207 indicates that the low, medium, and high drive capability cells are used in a 1:0:0 ratio, meaning that 100 percent of the cells with low drive capability, long latency, but low power consumption and small area are utilized.

[0052] Furthermore, in the 210 combination, a gate length ratio of 208 indicates that the ratio of short-gate-length to long-gate-length cells is 0:1, meaning that 100 percent of the cells used are those with short gate lengths, long delay times, but low power consumption.

[0053] In this embodiment, there are three types of threshold voltage and drive capability, and two types of gate length. However, the number of elements may vary depending on the cell library and LSI application used.

[0054] Entry 205 contains the timing margin calculated from the combinations of 201 to 204.

[0055] Next, using the example of database 123 in Figure 2 and the flowchart in Figure 3, the procedure for processing by the logic synthesis device 120 having the configuration in Figure 1 will be explained.

[0056] First, in step S300, the structural analysis unit 122 converts the circuit description 100, which represents the operation of the logic circuit, into a technology-independent netlist that represents the connection relationships of logic blocks that do not have physical characteristics.

[0057] Then, the structural analysis unit 122, based on the timing constraint file 101, links the technology-independent netlist with timing information such as clock type, operating frequency, and external circuit delay time, and then proceeds to step S301.

[0058] In step S301, the extraction unit 124 uses the database 123 to search for a logically equivalent location in the technology-independent netlist to an asset circuit expression registered in the database 123.

[0059] In step S302, the extraction unit 124 determines whether or not logically equivalent sections were found as a result of the search in step S301. If logically equivalent sections are found, the process proceeds to step S303. If no logically equivalent sections are found, the process proceeds to step S311.

[0060] In step S303, the extraction unit 124 extracts the locations found in step S301 as an extracted netlist and proceeds to step S304. Figure 4 shows an example of how the extracted netlist is transformed by utilizing the data registered in the database 123.

[0061] Figure 4(a) shows an example immediately after the extracted netlist 410 is extracted in step S303. The addition logic of 8-bit signals a and b operating at a frequency of 800 MHz 402 has been extracted as the extracted netlist 401.

[0062] In step S304, the circuit structure determination unit 125 calculates the difference between the frequency of the extracted netlist extracted in step S303 and the frequency of the logically equivalent asset circuit formula registered in the database 123, and proceeds to step S305.

[0063] In step S305, the circuit structure determination unit 125 determines whether the minimum value of the frequency difference calculated in step S304 is less than or equal to a preset threshold. If the result of the determination is less than or equal to the threshold, the process proceeds to step S306; otherwise, the process proceeds to step S311.

[0064] In step S306, the circuit structure determination unit 125 determines the circuit structure to be adopted from the extracted netlist extracted in step S303 using the database 123, and proceeds to step S307. The adopted circuit structure is the logic structure and cell configuration linked to the asset circuit formula that minimizes the frequency difference calculated in step 305. The circuit structure is a combination of the logic structure of the arithmetic unit and the cell configuration used to realize that logic structure.

[0065] The circuit structure determination unit 125 adopts the circuit structure of the closest asset circuit as the circuit structure of the extracted netlist if the minimum difference between the frequency of the extracted netlist and the frequency of the asset circuit that is logically equivalent to the extracted netlist and has the closest frequency among the asset circuit formulas registered in the database 123 is less than or equal to a first threshold.

[0066] In Figure 2, the asset circuit formula with a frequency closest to 800 MHz is the 750 MHz formula with 220 combinations. Here, assuming that the pre-set frequency difference threshold is 100 MHz, the logic structure 403 of the arithmetic unit and the cell configuration 404 of the arithmetic unit with 220 combinations are adopted in the extracted netlist 410 in Figure 4(b) to satisfy the adoption criteria. The result is shown in Figure 4(b).

[0067] In step S307, the timing margin calculation unit 126 calculates the timing margin based on the standard cell library 111 and the circuit structure determined in step S306, and proceeds to step S308. In the example shown in Figure 4(c), a timing margin of 405 of 0.10 is calculated.

[0068] The timing margin calculation unit 126 calculates the timing margin by subtracting the delay time of the path that maximizes the sum of the delay times of the standard cells and wiring between the first-stage FF and the last-stage FF from the time from the rising edge of the clock input to the first-stage FF to the rising edge of the clock input to the last-stage FF of the extracted netlist obtained by replacing the circuit structure determined by the circuit structure determination unit 125 with standard cells that are logically equivalent to the circuit structure, and then dividing the result by the clock period.

[0069] In step S308, the cell characteristic determination unit 127 calculates the difference between the timing margin calculated in step S307 and the timing margin associated with the asset circuit that is logically equivalent to the extracted netlist, which is registered in the database 123, and proceeds to step S309.

[0070] In step S309, the cell characteristic determination unit 127 determines whether the minimum difference calculated in step S308 is less than or equal to a preset threshold. If the result of the determination is that it is less than or equal to the threshold, the process proceeds to step S310; otherwise, the process proceeds to step S311.

[0071] In step 310, the cell characteristic determination unit 127 determines the characteristics of the cells to be adopted from the extracted netlist extracted in step S303 from the database 123, and proceeds to step S311. The characteristics of the cells to be adopted are those of the cells associated with the asset circuit formula that minimizes the difference in timing margin calculated in step 308.

[0072] The cell characteristic determination unit 127 adopts the characteristics of the closest asset circuit cell as the characteristics of the cell in the extracted netlist if the difference between the timing margin calculated by the timing margin calculation unit 126 and the timing margin of the asset circuit formula that is logically equivalent to the extracted netlist of asset circuit formulas registered in the database 123 and has the closest timing margin is less than or equal to a second threshold.

[0073] Among the timing margins of 205 in Figure 2, the combination closest to 0.10 is 0.05 in 210. Assuming that the pre-set threshold for the difference in timing margins is 0.10, the threshold voltage ratio 406, drive capability ratio 407, and gate length ratio 408 of the extracted netlist 410 in Figure 4(d) are set to 206, drive capability ratio 207, and gate length ratio 208, respectively, from the combination in 210. The result is shown in Figure 4(d).

[0074] The cell characteristics include at least a combination of ratios of threshold voltages of cells used in the circuit, a combination of ratios of drive capabilities used in the circuit, or a combination of ratios of gate lengths used in the circuit. As shown in Figure 2, the database 123 registers multiple circuit structures 203-204 and cell characteristics 206-208 corresponding to multiple frequencies 202 for the asset circuit formula 201.

[0075] In step S311, the logic synthesis unit 128 performs a logic synthesis process for each circuit expression in the technology-independent netlist, including the selection of circuit structure and cell characteristics, to generate a synthesized netlist with physical characteristics. Then, it proceeds to step S312. At this time, for the portion of the technology-independent netlist corresponding to the extracted netlist, the logic synthesis unit 128 selects the circuit structure determined in step S306 and the cell characteristics determined in step S310. Finally, the logic synthesis unit 128 performs optimization processing on the entire circuit, including the boundaries of the extracted netlist. Details of the logic synthesis process, excluding the selection of circuit structure and cell characteristics, are known techniques and are therefore omitted here. The logic synthesis unit 128 converts the technology-independent netlist into a synthesized netlist with physical characteristics using the circuit structure determined by the circuit structure determination unit 125 and the cell characteristics determined by the cell characteristic determination unit 127.

[0076] In step S312, the quality evaluation unit 129 calculates quantitative evaluation values ​​for quality aspects of the composite netlist 130, such as area and performance, and proceeds to step S313. Possible calculation methods include, but are not limited to, the sum of the values ​​obtained by multiplying the area value by a certain coefficient and the power value by a certain coefficient.

[0077] In step S313, the quality evaluation unit 129 determines whether the evaluation value from step S312 satisfies a predetermined threshold. If the threshold is satisfied, the process proceeds to step S316; otherwise, the process proceeds to step S314.

[0078] In step S316, the quality evaluation unit 129 does not reuse the circuit structure and cell characteristics from the database 123. Instead, for the circuit formula for which the circuit structure or cell characteristics were newly selected in step S311, it links the frequency, circuit structure, and cell characteristics and registers them in the database 123, then terminates the process. At this time, the quality evaluation unit 129 also registers the timing margin calculated by the timing margin calculation unit 126 in the database 123.

[0079] If the evaluation value satisfies the third threshold, the quality evaluation unit 129 registers the frequency, circuit structure, cell characteristics, and timing margin used in the asset circuit formula in the database 123.

[0080] In step S314, the quality evaluation unit 129 determines whether the number of times the loop repeats steps S315, S311, and S312 is less than a predetermined upper limit. If it is less than the upper limit, the process proceeds to step S315; otherwise, the process proceeds to step S316.

[0081] In step S315, the logic synthesis unit 128 modifies the circuit structure and cell characteristics of the circuit that underwent new circuit optimization in step S311, according to any unmet criteria. In this case, the logic synthesis unit 128 may also modify circuits that reuse the circuit structure and cell characteristics, or only the cell characteristics, from the database 123. In that case, the logic synthesis unit 128 updates the corresponding items in the database 123 to reflect the modified circuit structure and cell characteristics. Subsequently, the processes from step S315 to steps S311 and S312 are repeated until the threshold is met in step S313 or the loop count reaches the upper limit in step S314.

[0082] If the evaluation value does not satisfy the third threshold, the logic synthesis unit 128 modifies the circuit structure or cell characteristics, and uses the modified circuit structure or cell characteristics to convert the technology-independent netlist into a synthesized netlist with physical characteristics.

[0083] In this embodiment, the circuit description 100 is assumed to be written as RTL, but it may also be a composite netlist. In that case, the processing in step S300 is omitted.

[0084] Furthermore, although the database 123 is configured to be located inside the logic synthesis unit 120, it may also be configured to be located externally. By separating the database 123 from the logic synthesis unit 120, for example, multiple people using different logic synthesis units 120 can update the common database 123, making it possible to develop a higher-quality database more quickly.

[0085] As described above, according to this embodiment, by extracting and reusing suitable circuit structures and cell characteristics, it is possible to reduce the man-hours required for circuit optimization in the logic synthesis unit 128.

[0086] The logic synthesis unit 120 enables a significant reduction in man-hours by reusing not only the selection of the circuit structure of the arithmetic unit but also the selection method for the characteristics of the cells. The logic synthesis unit 120 can reduce the man-hours required for circuit optimization through a circuit structure determination unit 125 based on frequency, a timing margin calculation unit 126 based on the circuit structure, and a cell characteristic determination unit 127 based on the timing margin.

[0087] (Other embodiments) This disclosure can also be implemented by supplying a program that implements one or more of the functions of the embodiments described above to a system or device via a network or storage medium, and by having one or more processors in the computer of that system or device read and execute the program. It can also be implemented by a circuit (e.g., an ASIC) that implements one or more functions.

[0088] Although preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and changes are possible within the scope of its gist.

[0089] This embodiment includes the following configuration. (Item 1) An extraction means for extracting a netlist from a netlist that contains logically equivalent sections of asset circuit formulas registered in the database, A circuit structure determination means determines the circuit structure to be adopted in the extracted netlist from the database based on the frequencies of the extracted netlist extracted by the extraction means and the frequencies of logically equivalent asset circuit formulas registered in the database. A timing margin calculation means calculates the timing margin based on the circuit structure determined by the circuit structure determination means, A cell characteristic determination means that determines the characteristics of the cells to be used in the extracted netlist from the database based on the timing margin calculated by the timing margin calculation means, A logic synthesis means that converts the netlist into a synthesized netlist having physical characteristics using the circuit structure determined by the circuit structure determination means and the cell characteristics determined by the cell characteristics determination means. A logic synthesis device characterized by having the following features. (Item 2) The system further includes a structural analysis means that converts a circuit description representing the operation of a logic circuit into a netlist representing the connection relationships of logic blocks that do not have physical characteristics. The logic synthesis apparatus according to item 1, characterized in that the extraction means extracts the extracted netlist from the netlist converted by the structural analysis means. (Item 3) The logic synthesis apparatus according to item 1 or 2, characterized in that the structure of the circuit is a combination of the logic structure of an arithmetic unit and the configuration of cells used to realize the logic structure. (Item 4) The logic synthesis apparatus according to any one of items 1 to 3, characterized in that the characteristics of the cell are a combination of the ratios of the threshold voltages of the cells used in the circuit. (Item 5) The logic synthesis apparatus according to any one of items 1 to 4, characterized in that the characteristics of the cell are a combination of ratios of drive capabilities used in the circuit. (Item 6) The logic synthesis apparatus according to any one of items 1 to 5, characterized in that the characteristics of the cell are a combination of ratios of gate lengths used in the circuit. (Item 7) The logic synthesis apparatus according to any one of items 1 to 6, characterized in that the database registers the circuit structure and cell characteristics corresponding to multiple frequencies for the asset circuit formula. (Item 8) The logic synthesis apparatus according to any one of items 1 to 7, characterized in that the circuit structure determination means adopts the circuit structure of the closest asset circuit as the circuit structure of the extracted netlist when the difference between the frequency of the extracted netlist and the frequency of the asset circuit that is logically equivalent to the extracted netlist and has the closest frequency among the asset circuit formulas registered in the database is less than or equal to a first threshold. (Item 9) The timing margin calculation means is characterized by calculating the timing margin by subtracting the delay time of the path that maximizes the sum of the delay times of the standard cells and wiring between the first stage FF and the last stage FF from the time from the rising edge of the clock input to the first stage FF to the rising edge of the clock input to the last stage FF of the extracted netlist obtained by replacing the circuit structure determined by the circuit structure determination means with standard cells logically equivalent to the circuit structure, and then dividing the result by the clock period. This is the logic synthesis apparatus according to any one of items 1 to 8. (Item 10) The logic synthesis apparatus according to any one of items 1 to 9, characterized in that the cell characteristic determination means adopts the characteristics of the closest asset circuit cell as the characteristics of the cell in the extracted netlist when the difference between the timing margin calculated by the timing margin calculation means and the timing margin of the asset circuit cell that is logically equivalent to the extracted netlist among the asset circuit cell formulas registered in the database and has the closest timing margin is less than or equal to a second threshold. (Item 11) The logic synthesis apparatus according to any one of items 1 to 10, further comprising a quality evaluation means for calculating the quality of the synthesized netlist as a quantitative evaluation value. (Item 12) The logic synthesis apparatus according to item 11, characterized in that, if the evaluation value does not satisfy a third threshold, the logic synthesis means changes the structure of the circuit or the characteristics of the cell, and uses the changed circuit structure or characteristics of the cell to convert the netlist into a synthesized netlist having physical characteristics. (Item 13) The logic synthesis apparatus according to item 11 or 12, characterized in that, if the evaluation value satisfies a third threshold, the quality evaluation means registers the frequency, circuit structure, cell characteristics, and timing margin used in the asset circuit formula in the database. (Item 14) Extraction step: Extracts a netlist from the netlist that contains logically equivalent sections of the asset circuit formulas registered in the database. A circuit structure determination step in which the circuit structure to be adopted in the extracted netlist is determined from the database based on the frequencies of the extracted netlist extracted in the extraction step and the frequencies of logically equivalent asset circuit formulas registered in the database, A timing margin calculation step, which calculates the timing margin based on the circuit structure determined in the circuit structure determination step, A cell characteristic determination step, which determines the characteristics of the cells to be used in the extracted netlist from the database based on the timing margin calculated in the timing margin calculation step, A logic synthesis step which converts the netlist into a synthesized netlist having physical characteristics using the circuit structure determined in the circuit structure determination step and the cell characteristics determined in the cell characteristics determination step. A processing method for a logic synthesis apparatus, characterized by having the following features. (Item 15) A program to cause a computer to function as a logic synthesis device as described in any one of items 1 through 13. [Explanation of Symbols]

[0090] 100: Circuit Description 101: Timing constraint file 110: Cell Library 111: Standard Cell Library 120: Logic Synthesis Unit 121: Logical Block Library 122: Structural analysis department 123: Database 124: Extraction part 125:Circuit structure determination section 126: Timing margin calculation unit 127: Cell characteristic determination unit 128: Logic Synthesis Unit 129: Quality Evaluation Department 130: Synthetic Netlist

Claims

1. An extraction means for extracting a netlist from a netlist that contains logically equivalent sections of asset circuit formulas registered in the database, A circuit structure determination means determines the circuit structure to be adopted in the extracted netlist from the database based on the frequencies of the extracted netlist extracted by the extraction means and the frequencies of logically equivalent asset circuit formulas registered in the database. A timing margin calculation means calculates the timing margin based on the circuit structure determined by the circuit structure determination means, A cell characteristic determination means that determines the characteristics of the cells to be used in the extracted netlist from the database based on the timing margin calculated by the timing margin calculation means, A logic synthesis means that converts the netlist into a synthesized netlist having physical characteristics using the circuit structure determined by the circuit structure determination means and the cell characteristics determined by the cell characteristics determination means. A logic synthesis device characterized by having the following features.

2. The system further includes a structural analysis means that converts a circuit description representing the operation of a logic circuit into a netlist representing the connection relationships of logic blocks that do not have physical characteristics. The logic synthesis apparatus according to claim 1, characterized in that the extraction means extracts the extracted netlist from the netlist converted by the structural analysis means.

3. The logic synthesis apparatus according to claim 1, characterized in that the structure of the circuit is a combination of the logic structure of the arithmetic unit and the configuration of the cells used to realize the logic structure.

4. The logic synthesis apparatus according to claim 1, characterized in that the characteristics of the cell are a combination of the ratios of threshold voltages of cells used in the circuit.

5. The logic synthesis apparatus according to claim 1, characterized in that the characteristics of the cell are a combination of ratios of drive capabilities used in the circuit.

6. The logic synthesis apparatus according to claim 1, characterized in that the characteristics of the cell are a combination of ratios of gate lengths used in the circuit.

7. The logic synthesis apparatus according to claim 1, characterized in that the database registers the circuit structure and cell characteristics corresponding to multiple frequencies for the asset circuit formula.

8. The logic synthesis apparatus according to claim 1, characterized in that the circuit structure determination means adopts the circuit structure of the closest asset circuit as the circuit structure of the extracted netlist when the difference between the frequency of the extracted netlist and the frequency of the asset circuit that is logically equivalent to the extracted netlist and has the closest frequency among the asset circuit formulas registered in the database is less than or equal to a first threshold.

9. The logic synthesis apparatus according to claim 1, characterized in that the timing margin calculation means calculates the timing margin by subtracting the delay time of the path that maximizes the sum of the delay times of the standard cells and wiring between the first stage FF and the final stage FF from the time from the rising edge of the clock input to the first stage FF of the extracted netlist obtained by replacing the circuit structure determined by the circuit structure determination means with standard cells logically equivalent to the circuit structure, to the rising edge of the clock input to the final stage FF, and then dividing the result by the clock period.

10. The logic synthesis apparatus according to claim 1, wherein the cell characteristic determination means adopts the characteristics of the closest asset circuit cell as the characteristics of the cell in the extracted netlist when the difference between the timing margin calculated by the timing margin calculation means and the timing margin of the asset circuit formula that is logically equivalent to the extracted netlist and has the closest timing margin among the asset circuit formulas registered in the database is less than or equal to a second threshold.

11. The logic synthesis apparatus according to claim 1, further comprising a quality evaluation means for calculating the quality of the synthesized netlist as a quantitative evaluation value.

12. The logic synthesis apparatus according to claim 11, characterized in that, if the evaluation value does not satisfy a third threshold, the logic synthesis means changes the structure of the circuit or the characteristics of the cell, and uses the changed circuit structure or cell characteristics to convert the netlist into a synthesized netlist having physical characteristics.

13. The logic synthesis apparatus according to claim 11, characterized in that, if the evaluation value satisfies a third threshold, the quality evaluation means registers the frequency, circuit structure, cell characteristics, and timing margin used in the asset circuit formula in the database.

14. Extraction step: Extracts a netlist from the netlist that contains logically equivalent sections of the asset circuit formulas registered in the database. A circuit structure determination step in which the circuit structure to be adopted in the extracted netlist is determined from the database based on the frequencies of the extracted netlist extracted in the extraction step and the frequencies of logically equivalent asset circuit formulas registered in the database, A timing margin calculation step, which calculates the timing margin based on the circuit structure determined in the circuit structure determination step, A cell characteristic determination step, which determines the characteristics of the cells to be used in the extracted netlist from the database based on the timing margin calculated in the timing margin calculation step, A logic synthesis step which converts the netlist into a synthesized netlist having physical characteristics using the circuit structure determined in the circuit structure determination step and the cell characteristics determined in the cell characteristics determination step. A processing method for a logic synthesis apparatus, characterized by having the following features.

15. A program for causing a computer to function as a logic synthesis apparatus according to any one of claims 1 to 13.

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