Ultra-temporary cache replacement

Abstract

The cache replacement policy is described. According to the described technology, when a request for data is received, the cache replacement policy controls how the controller responds to the request. Depending on whether the request is a cache miss requiring the evicting of at least one cache line, the cache replacement policy assigns each cache line a priority value indicating whether the cache line should be preserved over other cache lines. The cache replacement policy decrements the priority value until at least one cache line reaches the minimum priority value, at which point the cache line is evicted. The cache replacement policy designates certain cache lines as protected, either through a separate protected indicator or through the cache line priority value, thereby prioritizing the preservation of protected cache lines in the cache while selecting unprotected cache lines for evicting.

Description

Technical Field

[0001] (Related Application) This application claims priority to U.S. Patent Application 18 / 332,112 (filed on June 9, 2023, titled "Super-Temporal Cache Replacement Policy"), the entire disclosure of which is hereby incorporated by reference in its entirety.

Background Art

[0002] A cache is a hardware or software component that stores data (at least temporarily) so that future requests for the data can be served more quickly than if the data were supplied from main memory. A "cache hit" occurs when the requested data can be found within the cache, while a "cache miss" occurs when the requested data cannot be found within the cache. A cache miss can occur, for example, in a scenario where the requested data has not yet been loaded into the cache or when the requested data has been evicted from the cache prior to the request. A cache replacement policy defines rules for selecting which cache line, if any, of the cache to evict in order to be able to load the requested data into a selected cache line in response to a cache miss.

[0003] The detailed description will be described with reference to the accompanying drawings.

Brief Description of the Drawings

[0004] [Figure 1] FIG. 1 is a block diagram of a non-limiting exemplary system having a cache and a controller with a guided cache replacement policy according to one or more embodiments. [Figure 2]This figure shows a non-limiting example in one or more embodiments where the cache line priority values ​​of protected and unprotected cache lines are updated according to an inductive cache replacement policy. [Figure 3] This figure shows the procedure in an exemplary embodiment of the technology described herein for changing the priority values ​​of protected and unprotected cash lines and evicting cash lines based on those priority values. [Figure 4] This figure shows a non-limiting example in one or more embodiments where the cache line priority value is updated for the default and maximum thresholds of protected and unprotected cache lines. [Figure 5] This figure shows the procedure in an exemplary embodiment of the technology described herein for changing the priority values ​​of protected and unprotected cash lines and evicting cash lines based on those priority values. [Modes for carrying out the invention]

[0005] A cache is a hardware or software component that stores data, resulting in faster delivery of future requests for data than if the data were supplied from main memory. Because a cache can only store a limited amount of data, it is beneficial to keep data that is continuously accessed or will be accessed in the future within the cache to perform computational tasks. Therefore, a cache improves the performance of a computing system when it stores data related to the computational task being performed.

[0006] In embodiments where the data required to perform a computation task is not stored in a cache, the processing device performing the computation task (e.g., executing) must retrieve the data from the system's main memory, which introduces latency into the execution of the computation task, creates a bottleneck on the communication channel (e.g., data bus) connecting the processing device to the main memory, requires additional time to retrieve the data, and degrades the overall performance of the processing device performing the computation task.

[0007] The cache replacement policy determines which data currently stored in the cache should be replaced (for example, whether it should be written to main memory or evicted from the cache without being written to main memory) when new data is needed to perform a computation task but is not currently stored in the full cache.

[0008] A cache replacement policy defines rules for selecting which cache lines to evicte within the cache so that requested data can be loaded into a selected cache line (e.g., in response to a cache miss for requested data). Traditional cache replacement policies include the Longest Unused (LRU) algorithm and the Rereference Interval Prediction (RRIP) algorithm. The LRU algorithm works by prioritizing the retention of the most recently used data object in the cache (e.g., returned in response to a data request) as part of performing a computational task. While the LRU algorithm is suitable for a variety of computational tasks, it is relatively expensive because it requires dedicated hardware (e.g., dedicated bits in the cache) to track the age of every single cache line whenever a data object is read from or written to the cache and to update this information.

[0009] The RRIP algorithm shares similar considerations with the LRU algorithm, but without explicitly tracking the age of cache lines. Rather, the RRIP algorithm predicts different values ​​(e.g., generally indicating soon, later, even later, and much later) that indicate when data stored in the cache might be needed. This avoids the LRU assumption that different data maintained in the cache will be accessed again with the same probability, thereby allowing for the priority of evicting cache lines that are not expected to be used again immediately to perform computational tasks. However, a significant limitation of the RRIP algorithm is that it does not have prior information indicating whether data will be reused. Rather, the RRIP algorithm is limited to observing when data is reused and then predicting values ​​that indicate when the data might be needed again after observing data reuse. Consequently, traditional cache replacement policy techniques require considerable hardware resources to function properly and cannot consider pre-runtime input or guidance that describes specific instances of data reused during the execution of computational tasks.

[0010] To address these conventional problems, a cache replacement policy is described that operates on a binary indicator of whether data stored in a cache line should be protected or not. This binary protected / unprotected indicator allows a programmer or developer of a given computation task to simply specify whether the computation task would benefit from storing certain data objects involved in the computation task in the cache, or from storing data retrieved from memory storage locations where data is read / written during the execution of the computation task in the cache. In some embodiments, the cache replacement policy described includes specifying certain bits of the cache line to identify a priority value for retaining the cache line in the cache, and specifying at least one bit to identify whether the cache line is protected or unprotected. Cache lines designated as protected are referred to herein as “super-temporal” cache lines and are preferred to be retained in the cache for longer durations than unprotected cache lines.

[0011] The guiding logic of the cache replacement policy causes the priority value of a cache line to increase toward the maximum priority value or adjust in other ways in scenarios where the cache line stores data requested for use when performing a computation task. Conversely, in scenarios where the requested data is not stored in any cache line (e.g., in response to a cache miss), the cache replacement policy guiding logic causes the priority value of each cache line to decrement or adjust toward the minimum priority value. Through the use of protected indicators, the cache replacement policy guiding logic prioritizes decrementing the priority value of unprotected cache lines before decrementing the priority value of protected cache lines so that protected cache lines remain in the cache more than unprotected cache lines in the event of a cache miss. In this way, the priority values ​​describe the order in which cache lines are evicted based on a cache miss. Advantageously, to avoid cache plaque, the cache replacement policy guiding logic ensures that the priority value of protected cache lines is also decremented when a cache line is evicted, thus preventing scenarios where a cache line is always retained in the cache.

[0012] Alternatively, in some embodiments, the cache replacement policy uses only the relevant priority values ​​and defines a particular cache line as trans-transient, independently of separate protected / unprotected indicators. For example, in some embodiments, the inductive logic of the cache replacement policy defines default and maximum thresholds for protected and unprotected cache lines. In a specific example, the cache replacement policy defines a default unprotected value that is assigned as the priority value of a cache line when inserting unprotected data into the cache. In this specific example, the cache replacement policy also defines a default protected value that is assigned as the priority value of a cache line when inserting protected data into the cache, and the protected default value is different from the unprotected default value.

[0013] In embodiments where the cache replacement policy includes decrementing the priority value until a threshold is met that allows data evicting, the default protected value is greater than the default unprotected value. Alternatively, if the cache replacement policy includes incrementing the priority value until an evicting threshold is met, the default protected value is less than the default unprotected value. The cache replacement policy further defines maximum priority values ​​for protected and unprotected cache lines, which constrain how cache line priority values ​​are incremented in response to cache hits. For example, in some embodiments, protected cache lines are allowed to have priority values ​​that meet an unprotected maximum threshold (e.g., greater than or equal to the unprotected maximum threshold), but unprotected cache lines are not. In embodiments where the cache replacement policy includes decrementing the priority value until a threshold is met that allows data evicting, meeting an unprotected maximum threshold means having a priority value greater than or equal to the unprotected maximum threshold. Alternatively, in embodiments where the cache replacement policy includes incrementing the priority value until an evicting threshold is met, meeting an unprotected maximum threshold means having a priority value less than or equal to the unprotected maximum threshold.

[0014] A cache replacement policy that includes decrementing a cache line priority value toward an evicting threshold in response to a cache miss decrements the cache line priority value toward the evicting threshold until at least one cache line satisfies the minimum priority value threshold (e.g., is associated with the minimum priority value threshold). As described herein, the minimum priority value threshold indicates that a cache line is eligible for evicting. The data contained in such a cache line is evicted to make space for inserting different data as a different cache line in the cache (e.g., written back to main memory or otherwise cleared from the cache). Thus, the cache replacement policies described herein select the cache lines to evict in a manner that is advantageous to the preservation of data objects identified as critical to a given computational task.

[0015] Advantageously, the cache replacement policy is enabled via a binary indicator of whether the associated data object or memory location is critical, thereby avoiding the fine-grained manual input required by some conventional methods and the expensive hardware tracking elements required by other conventional methods. Thus, the cache replacement policy described herein represents an improvement in time, speed, and / or power consumption compared to conventional cache replacement policies.

[0016] In some embodiments, the technology described herein relates to a system including a cache, inductive logic for inducing a determination of a cache replacement policy by prioritizing the eviction of unprotected cache lines over the eviction of protected cache lines, and a controller for selecting cache lines to be evicted in response to a cache miss, based on the cache replacement policy and the inductive logic.

[0017] In some embodiments, the technology described herein relates to a system in which the controller is further configured to evict previous data stored in a cache line and load data into the cache line, and the data loaded into the cache line is retrieved for requests that caused a cache miss.

[0018] In some embodiments, the techniques described herein relate to a system in which the induced logic is generated based on instructions for an application executed by a processor that requests data from a cache.

[0019] In some embodiments, the technology described herein relates to a system in which the inductive logic includes information specifying at least one data object, and the controller is configured to specify, based on the inductive logic, a cache line storing at least one data object as protected.

[0020] In some embodiments, the technology described herein relates to a system in which the inductive logic includes information specifying at least one data storage location, and the controller is configured to specify, based on the inductive logic, a cache line storing data retrieved from at least one data storage location as protected.

[0021] In some embodiments, the techniques described herein relate to a system in which each cache line of the cache includes a configurable bit that provides a binary indicator of whether the cache line is protected or not.

[0022] In some embodiments, the technology described herein relates to a system, wherein the controller is further configured to receive a first request for data, identify that the data requested by the first request is stored in a first cache line of the cache, return the data requested by the first request to the source from which the first request was received, and increment the priority value of the first cache line.

[0023] In some embodiments, the techniques described herein relate to a system where a controller receives a second request for data and identifies that the data requested by the second request is not stored in the cache and that the second request caused a cache miss, and further configured to identify a second cache line as having a priority value that permits eviction, the second cache line being selected for eviction in response to the cache miss.

[0024] In some embodiments, the techniques described herein relate to a system where in response to a cache miss, the inductive logic causes the controller to identify a priority value threshold for permitting eviction from the cache replacement policy, identify that each cache line of the cache is associated with a priority value that does not meet the priority value threshold, and decrement the priority value associated with the unprotected cache line until the priority value associated with the unprotected cache line meets the priority value threshold for permitting eviction.

[0025] In some embodiments, the techniques described herein relate to a system where the controller decrements the priority value associated with an unprotected cache line independently of changing the priority value associated with a protected cache line of the cache.

[0026] In some embodiments, the techniques described herein relate to a system where the controller decrements the priority value associated with a protected cache line in response to evicting data in response to a cache miss.

[0027] In some embodiments, the technology described herein relates to a system in which at least two unprotected cache lines have associated priority values ​​that satisfy a priority value threshold that permits eviction, in response to decrementing the priority value associated with an unprotected cache line, and inductive logic causes a controller to select one of the at least two unprotected cache lines for data eviction based on the addresses of the at least two unprotected cache lines.

[0028] In some embodiments, the techniques described herein, relating to a system, control the loading of data into the cache by causing the controller to assign a default unprotected value to the data loaded into the cache depending on whether the data was loaded from a data storage location indicated as not protected by the guidance logic, or to assign a default protected value to the data loaded into the cache depending on whether the data was loaded from a data storage location indicated as being protected by the guidance logic.

[0029] In some embodiments, the techniques described herein relate to a method that includes receiving a request to access a cache containing multiple cache lines, and updating a priority value of at least one of the multiple cache lines to prioritize the evicting of an unprotected cache line from the multiple cache lines based on the request, wherein the priority value describes the order in which the multiple cache lines are evicted in response to a cache miss.

[0030] In some embodiments, the technique described herein further comprises initializing a plurality of cache lines such that, based on instructions for a computation task to be performed by a processor that has received a request, the cache lines include information describing at least some of a plurality of cache lines that are protected cache lines.

[0031] In some embodiments, the techniques described herein relate to a method for updating the priority of at least one of a plurality of cache lines, which includes incrementing the priority value of at least one of the plurality of cache lines in response to a cache hit for a request.

[0032] In some embodiments, the techniques described herein relate to methods, wherein incrementing the priority value of at least one of a plurality of cache lines includes, depending on whether at least one of the plurality of cache lines is an unprotected cache line, incrementing the priority value of at least one of the plurality of cache lines to an unprotected threshold, or depending on whether at least one of the plurality of cache lines is a protected cache line, incrementing the priority value of at least one of the plurality of cache lines to a protected threshold.

[0033] In some embodiments, the techniques described herein, with respect to a method, include updating the priority value of at least one of a plurality of cache lines, in response to a cache miss for a request, by decrementing the priority value of at least one of a plurality of cache lines.

[0034] In some embodiments, the techniques described herein relate to a method in which updating the priority value of at least one of a plurality of cache lines is performed independently of modifying the priority value of a protected cache line among the plurality of cache lines.

[0035] In some embodiments, the techniques described herein include a method for receiving a request to access data, identifying that the request results in a cache miss in a cache comprising multiple cache lines, adjusting the priority value of at least one unprotected cache line toward an evicting threshold, independently of adjusting the priority value of at least one protected cache line toward an evicting threshold until the priority value of at least one unprotected cache line toward an evicting threshold, and evicting data stored in at least one unprotected cache line toward

[0036] Figure 1 is a block diagram of a non-limiting exemplary system 100 having a cache and controller with an inductive cache replacement policy, according to several embodiments. Specifically, the system includes a cache 102, a cache client 104, a data store 106, and a controller 108 including a cache replacement policy 110 induced by inductive logic 112. According to the described technology, the cache 102, cache client 104, and data store 106 are coupled to each other via wired connections, wireless connections, or a combination thereof. Exemplary wired connections include, but are not limited to, buses connecting two or more of the cache 102, cache client 104, and data store 106. Exemplary wireless connections include wireless, cellular, Wi-Fi®, Bluetooth®, Near Field Communication (NFC), 5G, and similar data communication paths connecting two or more of the cache 102, cache client 104, and data store 106.

[0037] The cache 102 is a hardware component, software component, or combination thereof that stores data (for example, at least temporarily), and therefore future requests for data are supplied faster from the cache 102 than from the data store 106. In one or more embodiments, the cache 102 is at least one of the following: smaller than the data store 106, faster at supplying data to the cache client 104 than the data store 106, or more efficient at supplying data to the cache client 104 than the data store 106. Additionally or alternatively, the cache 102 is located closer to the cache client 104 than the data store 106. In this way, the cache 102 has additional or different properties that favor supplying at least some data from the cache 102 to the cache client 104 (for example, in relation to supplying the same data from the data store 106).

[0038] In one or more embodiments, the cache 102 is a memory cache such as a specific level of cache (e.g., L1 cache), where the specific level is part of a hierarchy of multiple cache levels (e.g., L0, L1, L2, L3, L4). In some modifications, the cache 102 is a hardware component incorporated into and used by a cache client 104. In other examples, the cache 102 is implemented at least partially in software, such as in at least one scenario where the cache client 104 is a web browser or a web server. Furthermore, the cache 102 can be implemented in different ways without departing from the spirit or scope of the described technology.

[0039] A cache client 104 is a component that requests access to data in order to perform one or more operations related to such data. Examples of cache clients 104 include, but are not limited to, a central processing unit, a parallel acceleration processor (e.g., a graphics processing unit), a digital signal processor, a hardware accelerator, an operating system, a web browser, a web server, and a lower-level cache (e.g., a cache hierarchy lower than cache 102).

[0040] In various embodiments, the cache client 104 provides a request 114 for access to data. For example, the request 114 is a request for write access to data or a request for read access to data. According to the technique described, the request 114 is received to attempt to access the cache and find data in the cache 102. For example, the request 114 is received by the controller 108. In response to the request 114, the controller 108 searches the cache 102 to determine whether the data is stored in the cache 102. If, by searching the cache 102, the controller 108 identifies that the data is stored in the cache 102, the controller 108 then provides access to the data in the cache 102. As described herein, a “cache hit” occurs when the controller 108 identifies that the data (requested by, for example, the request 114) is stored in the cache 102. If the request 114 is for write access, upon a cache hit, the controller 108 modifies (e.g., updates) the data in the cache 102 identified by the request 114. If request 114 is for a read access, upon a cache hit, the controller 108 retrieves the data in cache 102 identified by request 114. In the example shown, the data retrieved from cache 102 based on request 114 is shown as cached data 116. The controller 108 provides the cached data 116 to the cache client 104.

[0041] The example shown also shows the requested data 118. The requested data 118 corresponds to the data provided to the cache client 104 in response to request 114. If the data identified in request 114 is supplied from cache 102, for example, upon a cache hit, the requested data 118 corresponds to the cached data 116. However, in one or more scenarios, the data identified in request 114 is supplied from data store 106. In scenarios where the data is not found in cache 102 and is flagged as being stored in a non-cacheable location in data store 106, for example, the requested data 118 corresponds to the data provided to the cache client 104 from data store 106. As described herein, a “cache miss” occurs when controller 108 does not identify the data identified by request 114 in cache 102. A cache miss occurs, for example, if the data identified by request 114 has not yet been loaded into cache 102, or if the data identified by request 114 was evicted from cache 102 before request 114.

[0042] In various scenarios, the controller 108 loads the data identified by the request from datastore 106 into cache 102 in response to a cache miss. In the example shown, the data retrieved from datastore 106 and loaded into cache 102 is shown as datastore data 120. When a cache miss is determined, for example, the data requested by request 114 is identified in datastore 106 and loaded from datastore 106 into one or more "locations" in cache 102 (e.g., one or more cache lines in cache 102). This allows future requests for the data to be supplied from cache 102 rather than from datastore 106. As will be described in more detail below, the controller 108 loads the data from datastore 106 (e.g., datastore data 120) into cache 102 based on the cache replacement policy 110.

[0043] According to the technology described herein, the datastore 106 is a computer-readable storage medium for storing data. Examples of the datastore 106 include, but are not limited to, main memory (e.g., random access memory), high-level cache (e.g., L2 cache when cache 102 is an L1 cache), secondary storage (e.g., mass storage device), and removable media (e.g., flash drive, memory card, compact disk, digital video disk). Examples of the datastore 106 also include virtual memory that leverages the underlying secondary storage of a computing device according to one or more memory management techniques. While described herein in the context of several exemplary configurations, the datastore 106 can be configured in a variety of ways without departing from the spirit or scope of the technology described.

[0044] As described above, the controller 108 loads data from the datastore 106 to the cache 102 (for example, in response to a cache miss). Specifically, the controller 108 loads data according to the cache replacement policy 110. The cache replacement policy 110 controls which cache line in the cache 102 has the previous data that was loaded by evicting the data from the datastore 106 corresponding to request 114. In one or more embodiments, the cache replacement policy 110 is or includes a hardware maintenance structure that manages the replacement of cache lines according to an underlying algorithm (e.g., guidance logic 112). Alternatively or additionally, the cache replacement policy 110 is or includes a computer program that manages the replacement of cache lines according to an underlying algorithm (e.g., guidance logic 112).

[0045] In accordance with the techniques described, the guide logic 112 guides the determination of an algorithm for a cache replacement policy 110, which is performed in relation to selecting cache lines for evicting and loading data. For example, the guide logic 112 assigns priority values ​​to different cache lines of cache 102 based on the data stored in each cache line. In some embodiments, the guide logic 112 is generated or otherwise controlled by instructions of an application or other computational task executed by a processor requesting data from cache 102 (e.g., cache client 104). For example, the guide logic 112 includes information indicating that a particular data object and / or a particular data location is protected for a given computational task (e.g., information encoded in one or more instructions of a computational task that specify that a particular data object and location is important to the computational task). In response to loading a protected content object, or data retrieved from a protected data storage location, into a cache line of cache 102, the guide logic assigns data to the cache line indicating that the cache line is protected and to be contrasted with unprotected cache lines of cache 102 (e.g., one or more bits of the cache line).

[0046] In embodiments where request 114 results in a cache hit, the guidance logic 112 causes the priority value of the cache line to increase toward the maximum priority value or to adjust it in other ways. Similarly, in embodiments where request 114 results in a cache miss, the guidance logic 112 causes the priority value of the cache line to decrement or to adjust it in other ways toward the minimum priority value. In some exemplary embodiments, the guidance logic 112 causes the priority value of an unprotected cache line to adjust toward the minimum priority value independently of (e.g., without adjustment) adjusting the priority value of a protected cache line. In these exemplary embodiments, the guidance logic 112 prefers to retain stored data using protected cache lines in cache 102 rather than unprotected cache lines (e.g., in response to request 114 that results in a cache miss).

[0047] The guide logic 112 can be implemented in various ways according to the techniques described. For example, the guide logic 112 may be implemented in software by inserting additional code into the code that implements the hypertransient evicting algorithm of the cache replacement policy 110. In at least one such example, the additional code causes the cache line priority values ​​of cache 102 to be adjusted based on whether the request is fulfilled. For example, the additional code causes the cache line priority values ​​of cache 102 to be adjusted differently based on whether the request 114 results in a cache hit or a cache miss. Alternatively or additionally, the guide logic 112 may be implemented by one or more hardware components. For example, the guide logic 112 may be implemented by one or more hardware components (e.g., one or more integrated circuits) that implement the cache replacement policy 110 according to the hypertransient evicting algorithm.

[0048] Although the cache replacement policy 110 is shown to include guidance logic 112 in the illustrated example, in one or more embodiments, the guidance logic 112 is not included as part of the cache replacement policy 110 but is accessible by the cache replacement policy 110, for example, while identifying the cache line to select for evicting and loading data. The guidance logic 112 is implemented in different ways in one or more embodiments without departing from the spirit or scope of the described technology.

[0049] As will be explained in more detail below, the guidance logic 112 and the cache replacement policy 110 collectively represent a cache retention system that prioritizes the preservation of protected cache lines in the cache over unprotected cache lines in response to a cache miss. Exemplary embodiments of how the cache replacement policy 110 and the guidance logic 112 are configured are described in more detail below with reference to Figures 2 to 5.

[0050] Figure 2 shows an example 200 in which the cache line priority values ​​of protected and unprotected cache lines are updated according to an inductive cache replacement policy, according to one or more embodiments.

[0051] In illustrated Example 200, cache 102 is shown as including cache lines 204, 206, 208, and 210 in the first state 202. For simplicity, it is shown as including four cache lines in Example 200, but cache 102 represents a cache having any suitable number of cache lines (e.g., two or more cache lines) according to the techniques described herein, and the examples shown are not limiting. Each cache line of cache 102 is shown as being associated with a corresponding priority value 212 and a corresponding protected indicator 214. The priority value 212 can be composed in any suitable way, such as one or more bits of data associated with (e.g., included, appended to, etc.) the cache line, and represents information describing the relative priority (e.g., relative to other cache lines in cache 102) that the cache line should maintain within cache 102. Similarly, the protected indicator 214 can be configured in any suitable way, such as a single bit that provides a binary indicator (e.g., 1 or 0) indicating whether the cache line should be treated as more important to maintain within the cache 102 than an unprotected cache line. In embodiments, a cache line having the associated protected indicator 214 that identifies the cache line as important is referred to as a “hypertransient” cache line, which indicates how the cache line is intended to be stored within the cache 102 for an extended duration.

[0052] As shown in illustrated example 200, in the first state 202, cache line 204 is assigned a priority value of 3, cache line 206 is assigned a priority value of 3, cache line 208 is assigned a priority value of 3, and cache line 210 is assigned a priority value of 2. In the first state 202, cache line 204 has a protected value of 0, cache line 206 has a protected value of 0, cache line 208 has a protected value of 1, and cache line 210 has a protected value of 1. Therefore, the protected indicator 214 indicates that cache lines 204 and 206 are not considered protected, and further indicates that cache lines 208 and 210 are protected (for example, that cache lines 204 and 206 are not important to cache lines 208 and 210).

[0053] According to the techniques described herein, each cache line of cache 102 can be assigned, in various ways, its respective protected value, its respective priority value, or a combination thereof.

[0054] For example, in some embodiments, individual cache lines are assigned protected values ​​based on the computation task being performed by the source from which the request 114 is received (for example, the protected values ​​are assigned by the application code of a computer application being run by the cache client 104, and running the computer application involves processing the requested data 118). In such exemplary scenarios, the developer of the computer program or the author of the code that is executed as part of performing the computation task can predefine (for example, at compile time or before the runtime of the computation task) one or more data objects, one or more locations in the data store 106, or a combination thereof, which should be treated as protected or important during the execution of the computation task.

[0055] Continuing this exemplary scenario, when a data object designated as important is loaded into cache 102, one or more cache lines used to store the important data object are configured with a protected indicator 214 that identifies this importance (for example, one or more cache lines used to store the data object designated as protected are configured to include a “protected value bit” such that it has a value of 1 instead of a value of 0). Alternatively or additionally, the techniques described herein enable a programmer or compute task developer to designate at least one memory region (e.g., one or more storage locations in data store 106) as important and thus protect it for continued storage in cache 102. For example, consider an exemplary scenario in which a developer writes executable code for a compute task to store data objects (e.g., data objects that are frequently and / or repeatedly used as part of performing the compute task) in a particular region of memory.

[0056] In this exemplary scenario, the techniques described herein enable developers to provide information (e.g., as part of induction logic 112) indicating that a particular region of memory stores important data during the execution of a computational task. Such an indicator informs the controller 108 that data retrieved from a particular region of memory should be prioritized for continued storage in the cache 102 (e.g., over data retrieved from a region of memory other than the particular region of memory indicated as important by induction logic 112). In this way, the controller 108 is configured to identify which cache line in the cache 102 should be treated as storing important data, assign a protected indicator 214 representing this importance to the corresponding cache line, and thus prioritize the cache line for storage in the cache 102. The information describing the data objects, data storage locations, or combinations thereof that should be prioritized for retention in the cache 102 can be constructed in a variety of ways.

[0057] For example, important or "protected" data and / or data storage information is contained in the application code of a computation task performed by the cache client 104. Alternatively or additionally, protected information is stored in a hardware register of the system 100 via one or more bits in a page table entry that is communicated to the controller 108 with the request 114. Alternatively or additionally, protected information for the cache lines of the cache 102 is contained in a buffer descriptor (e.g., application or computation task-specific metadata) associated with a data allocation and loaded into the controller 108 before the system 100 executes an instruction that involves buffering data from memory (e.g., data store 106). Alternatively or additionally, in some embodiments, the determination of whether information is "protected" is made entirely by hardware. For example, the hardware of system 100 (e.g., dedicated reuse prediction hardware) observes the access rate, hit rate and other historical behavior for a particular cache line address or region of a cache line, and designates one or more cache lines as protected (e.g., as ultra-temporary) independently of any instructions provided by the software (e.g., an application or computation task being performed by system 100).

[0058] The illustrated example 200 shows how the controller 108 implements the cache replacement policy 110 to evict a specific cache line from the cache 102 (for example, depending on whether request 114 is a cache miss) based on the priority value 212 and protected indicator 214 associated with each cache line. As described above, the first state 202 represents the initial state of the cache 102, such as the state of the cache 102 before the controller 108 received request 114. States 216, 218, 220, and 222 represent how the controller 108 resolves which cache line should be evicted according to the inductive logic 112 of the cache replacement policy 110 (for example, depending on whether request 114 is a cache miss where the cache line needs to be evicted to make space for storing datastore data 120 in the cache 102).

[0059] In the context of Example 200, the priority value 212 ranges from 0 to 3, where a priority value of 0 indicates that the cache line is eligible for evicting from the cache, and a value of 3 represents the maximum value for prioritizing the retention (e.g., continued storage) of the cache line within cache 102. Although illustrated and described with respect to this particular range from 0 to 3, the priority value 212 can be configured to span any numerical range according to the techniques described herein. By spanning from 0 to 3, Example 200 represents an example where each priority value 212 is assigned one of four different integers (e.g., 0, 1, 2, or 3), and thus each priority value 212 can be configured using 2 bits for each cache line in cache 102. Thus, such a 2-bit priority value configuration is useful for prioritizing different cache lines for storage within cache 102 while minimizing the amount of data required to do so.

[0060] In the illustrated example 200, the cache replacement policy 110 causes the controller 108 to iteratively decrement the priority value 212 of unprotected cache lines until, first, an unprotected cache line has a minimum priority value (e.g., a priority value of 0 indicating that the cache line is eligible for eviction). For example, state 216 shows how the priority values ​​212 of cache lines 204 and 206 are decremented by 1 each (e.g., from 3 to 2) while the priority values ​​212 of cache lines 208 and 210 are maintained (e.g., to 3 and 2, respectively). Since none of the cache lines in the first state 202 or state 216 have a priority value of 0 (e.g., no cache lines eligible for eviction), the cache replacement policy 110 causes the controller 108 to continue decrementing the priority value 212 of unprotected cache lines.

[0061] For example, state 218 represents how the priority values ​​212 of cache lines 204 and 206 have been decremented from 2 to 1, and state 220 represents how the priority values ​​212 of cache lines 204 and 206 have been decremented from 1 to 0. Conversely, priority values ​​212 or cache lines 208 and 210 are maintained through the first states 202 to 216, 218 and 220 due to having the associated protected indicator 1 (as opposed to the unprotected value 0 assigned to cache lines 204 and 206). When cache lines 204 and 206 reach state 222, which is associated with a priority value of 0, the controller 108 evictes one of the cache lines with a priority value of 0.

[0062] In embodiments, in scenarios where the cache 102 includes multiple cache lines that are candidates for eviction (e.g., multiple cache lines with associated minimum priority values), the controller 108 selects which cache line to evict based on the way index of the cache lines. As described herein, the cache way index refers to the mechanism of the cache 102 for determining the location of data within the cache. In some embodiments, the controller 108 selects the cache line with the lowest way index as the cache line to be evicted. For example, in the example shown in Figure 2, if cache line 204 has a lower way index than cache line 206, cache line 204 is selected for eviction because it has the lowest way index among the cache lines with the minimum priority value (e.g., a priority value of 0). An exemplary flow of the actions performed by the controller 108 when implementing the cache replacement policy 110 shown with respect to Figure 2 is described in more detail below with respect to Figure 3.

[0063] Figure 3 shows procedure 300 for changing the priority values ​​of protected and unprotected cache lines and evicting cache lines based on those priority values.

[0064] First, a data request is received (block 302). The controller 108 receives request 114 from, for example, the cache client 104. Upon receiving the data request, a decision is made as to whether the request resulted in a cache hit (block 304). The controller 108 identifies, for example, whether the data requested by the cache client 104 is stored in the cache 102. In response to the decision that request 114 resulted in a cache hit (for example, the decision of "yes" in block 304 based on the identification that the requested data is stored in the cache 102), the priority value of the hit cache line is increased (block 306).

[0065] The controller 108 identifies, for example, the cache line that stores the data requested by request 114, and increments the priority value 212 corresponding to each cache line that stores the requested data. In some embodiments, the controller 108 increments the priority value of the hit cache line up to the maximum priority value. For example, in the example shown in Figure 2, depending on whether request 114 is a request for data stored in cache line 210, the controller 108 increases the priority value of cache line 210 from 2 to 3. Alternatively, in some embodiments, the controller 108 increments the priority value of the hit cache line to a value less than the maximum priority value. For example, the controller 108 increments the priority value of the hit cache line by a single integer value or a set of integer values ​​so that it is less than the maximum priority value.

[0066] In some embodiments, request 114 is received with an indicator (e.g., via one or more bits appended to request 114) indicating whether the data access request is hypertransient. In such embodiments, detecting a cache hit in block 304 results in adjusting the priority value of the hit cache line in any appropriate way, such as by adjusting the priority value to downgrade the cache line from hypertransient to non-hypertransient, or by adjusting the priority value to upgrade a non-hypertransient cache line to have hypertransient status. For example, in an exemplary embodiment, where request 114 is received with an indicator that the request is hypertransient, and the hit cache line in block 304 was previously associated with a non-hypertransient priority value, the controller 108 increases the priority value of the cache line to a hypertransient priority value in block 306. As another example, consider a scenario where request 114 is received with an indicator that the data access request is not hypertransient, and the hit cache line is associated with a hypertransient priority value. In such a scenario, the controller 108 is configured to adjust the priority value of the hit cache line to a non-hypertransitive value (e.g., the upper limit or a value near the upper limit of the non-hypertransitive priority value range). Thus, block 306 represents the function of the controller 108 to adjust the priority value of the hit cache line to any appropriate value.

[0067] Alternatively, depending on whether it is determined that request 114 will result in a cache hit (for example, a "no" decision in block 304 depending on whether it is determined that request 114 will result in a cache miss because the requested data is not stored in cache 102), a decision is made as to whether the cache line has a minimum priority value (block 308). The controller 108 checks, for example, whether the cache line in cache 102 is associated with a minimum priority value (for example, a priority value of 0 for example 200). Depending on whether it is determined that the cache line is currently associated with a minimum priority value (for example, a "yes" decision in block 308), the cache line having a minimum priority value is evicted from the cache (block 310). The controller 108 identifies, for example, cache lines 204 and 206 as being associated with a minimum priority value of zero, and selects cache line 204 for evicting so that the data requested by request 114 (for example, datastore data 120) can be stored in cache 102 instead of the data that previously occupied cache line 204.

[0068] Alternatively, depending on whether it is identified that there are no cache lines currently associated with the minimum priority value (e.g., the "No" decision in block 308), a decision is made as to whether the cache contains at least one unprotected cache line (block 312). Depending on whether it is identified that the cache contains at least one protected cache line (e.g., the "Yes" decision in block 312), the priority value of each unprotected cache line is decremented until at least one unprotected cache line has the minimum priority (block 314). The controller 108 identifies, for example, that the cache 102 contains at least one cache line with an associated priority value of 0. Depending on whether it is identified that at least one cache line has the minimum associated priority value (e.g., zero), the controller 108 iteratively decrements the priority values ​​of all unprotected cache lines, as represented by the progression from the first state 202 to state 216, state 218, and state 220 in Figure 2, so that each of cache lines 204 and 206 has a minimum priority value of zero.

[0069] After decrementing the priority value of each unprotected cache line until at least one unprotected cache line has a priority value of 0, or depending on whether it has been identified that a cache line in the cache is unprotected (e.g., a "No" decision in block 312), the priority value of each protected cache line is decremented (block 316). The controller 108 decrements the priority values ​​of protected cache lines 208 and 210, for example, as represented by the progression from state 220 to state 222 in Figure 2. By forcing the controller 108 to decrement the priority value of each protected cache line after decrementing the priority values ​​of the unprotected cache lines until at least one unprotected cache line meets the condition for eviction (e.g., has a minimum priority value), the cache replacement policy 110 avoids scenarios in which protected cache lines are permanently retained in the cache 102, and thus avoids the accumulation of cache plaques or scenarios in which a computation task inadvertently instructs all data to be permanently retained in the cache.

[0070] After decrementing the priority value of each protected cache line, the operation of step 300 returns to block 308. This return to block 308 allows the operation to proceed to block 310 after decrementing the priority value of at least one unprotected cache line to its minimum priority value. Alternatively, this also considers a scenario where all cache lines in the cache are protected, in which case the operation of step 300 continues until at least one cache line, whether protected or unprotected, has the minimum associated priority value, at which point the cache line is evicted in block 310. Step 300 is configured to be repeated upon receipt of subsequent requests 114 for any number of requests received by controller 108, as indicated by the dashed arrows returning from block 306 and block 310 to block 302.

[0071] As described above, each cache line has a separate indicator (e.g., a separate protected indicator) that describes whether it is protected to have priority in the cache over unprotected cache lines (e.g., a hypertransient cache line), but in some embodiments, this protected information is included in the cache line priority information. By encoding the cache line protection information into a priority identifier, some embodiments avoid the need to specify a particular bit of the cache line to indicate whether or not the cache line is hypertransient. For further explanation of how the cache line protection information is encoded into the cache line priority value, consider Figures 4 and 5.

[0072] Figure 4 shows an example 400 in which cache line priority values ​​are updated for the default and maximum thresholds of protected and unprotected cache lines according to one or more embodiments. In the illustrated example 400, the priority value key 402 contains information representing how different priority values ​​are assigned to protected and unprotected cache lines according to the cache replacement policy 110. Specifically, the priority value key 402 indicates that a priority value of 7 represents the maximum priority value eligible for assignment to a protected cache line. The priority value key 402 further indicates that a priority value of 3 represents the maximum priority value eligible for assignment to an unprotected cache line.

[0073] Priority value key 402 further describes how a default value of 5 is assigned to protected cache lines when inserted (e.g., when written to cache 102), and how a default value of 1 is assigned to unprotected cache lines when inserted into the cache. Finally, priority value key 402 indicates that a minimum cache line priority value of zero represents when a cache line is eligible for eviction (e.g., in accordance with request 114 being a cache miss). In this way, priority value key 402 effectively defines different ranges of priority values ​​for protected cache lines (e.g., hypertransient cache lines) and unprotected cache lines (e.g., non-hypertransient cache lines or aged-out hypertransient cache lines). Specifically, priority value key 402 defines that cache lines with priority values ​​from 4 to 7 are hypertransient and are protected within cache 102 or otherwise stored. Conversely, priority value key 402 defines that cache lines with priority values ​​from 0 to 3 are either not hypertransient cache lines, or instances of hypertransient cache lines that have aged and lost their hypertransient status, and should be evicted from cache 102 in a more favorable manner than hypertransient cache lines.

[0074] In the context of priority value key 402, state 404 represents an exemplary state of cache 102, where priority value 414 can be used to define the priority of which different cache lines are maintained within cache 102, while also considering whether a particular cache line should be designated to be protected (for example, as instructed by the program code of a computation task with request 114). Specifically, state 404 shows that cache 102 includes cache line 406 with priority value 1, cache line 408 with priority value 4, cache line 410 with priority value 5, and cache line 412 with priority value 2.

[0075] In some embodiments, the cache replacement policy 110 causes the controller 108 to update the priority values ​​of cache lines 406, 408, 410, and 412 based on the result of request 114. For example, in embodiments where request 114 results in a cache hit, the cache replacement policy 110 causes the cache replacement policy 110 to increment the priority value associated with the cache line containing the data requested by request 114. In some embodiments, the controller 108 increments the cache line priority value relative to the cache line's current priority value. For example, in embodiments where the cache line priority value indicates that the cache line should be protected (e.g., the cache line priority value is greater than the maximum priority value that can be assigned to an unprotected cache line), the controller 108 may increment the cache line priority value to the maximum unprotected priority value.

[0076] For example, upon identifying that the data requested by request 114 is stored in cache line 408, controller 108 identifies that cache line 408 previously had a priority value of 4, which is greater than the maximum priority value of an unprotected cache line (for example, as indicated by state 404 for priority value key 402). In response to such identification, cache replacement policy 110 causes controller 108 to increment the priority value of cache line 408 to the maximum priority value of 7 (for example, for a protected cache line as specified by priority value key 402), which results in state 416 for cache 102.

[0077] As an alternative, upon identifying that the data requested by request 114 is stored in cache line 412, controller 108 identifies that cache line 412 previously had a priority value of 2, which is lower than the maximum priority value for an unprotected cache line (for example, as indicated by state 404 for priority value key 402). In response to such identification, cache replacement policy 110 causes controller 108 to increment the priority value of block 312 to the maximum priority value of 3 (for example, for an unprotected cache line as specified by priority value key 402), which results in state 418 for cache 102.

[0078] As yet another example, upon identifying that the data requested by request 114 is not stored in any of the cache lines of cache 102 (e.g., a cache miss), the cache replacement policy 110 causes the controller 108 to decrement the priority value of each cache line until at least one cache line achieves a minimum priority value and becomes eligible for eviction. For example, state 420 represents the state of cache 102 resulting from state 404, where request 114 results in a cache miss. Specifically, while cache line 406 is associated with a minimum priority value of zero, the priority values ​​414 of each of cache lines 408, 410, and 412 are decremented so that they each have priority values ​​that are above the minimum priority value (e.g., relative to state 404).

[0079] In such an exemplary scenario, the cache replacement policy 110 causes the controller 108 to evict cache line 406 to create space in cache 102 for the data requested by request 114. In embodiments where the requested data replacing the evicted cache line 406 is shown to be protected, the requested data is inserted into cache 102 with a priority value of 5. Alternatively, if the requested data replacing the evicted cache line 406 is not shown to be protected, the requested data is inserted into cache 102 with a priority value of 1. An exemplary flow of the actions performed by the controller 108 when implementing the cache replacement policy 110 shown with respect to Figure 4 is described in more detail below with respect to Figure 5.

[0080] Figure 5 shows procedure 500 for changing the priority values ​​of protected and unprotected cache lines and evicting cache lines based on those priority values.

[0081] First, a cache line is inserted into the cache (block 502). The controller 108 initializes the cache 102 by inserting data into the cache 102 as instructed by the program code of a computation task being executed by the cache client 104, for example. In a specific example, in some embodiments, an application developer instructs the cache to populate specific data objects involved in executing a computation task. In another example, the controller 108 inserts data store data 120 into the cache line of the cache 102 (for example, depending on whether request 114 is a request for data stored in data store 106).

[0082] For each inserted cache line, a decision is made as to whether the inserted cache line is protected (block 504). The guidance logic 112 of the cache replacement policy 110 notifies the controller 108, for example, whether the data represented by the inserted cache line is indicated to be protected for the purpose of a particular computation task performed by the cache client 104 (for example, based on the program code created by the developer of the computation task, based on the fact that the data storage location from which the data of the inserted cache line is retrieved is defined as a protected memory location, or a combination of these).

[0083] Depending on whether the inserted cache line is identified as not designated or otherwise indicated as a protected cache line (e.g., the "No" decision in block 504), an unprotected default priority value is assigned to the cache line (block 506). The controller 108 assigns the inserted cache line to have a priority value of 3, for example, according to the value of priority value key 402. Alternatively, depending on whether the inserted cache line is identified as not designated or otherwise indicated as a protected cache line (e.g., the "Yes" decision in block 504), a protected default priority value is assigned to the cache line (block 508). The controller 108 assigns the inserted cache line to have a priority value of 5, for example, according to the value of priority value key 402.

[0084] The operation of step 500 then proceeds from either block 506 or block 508 to block 510, where a data request is received. The controller 108 receives request 114, for example, from cache client 104. Upon receiving the data request, a decision is made (block 512) as to whether the request resulted in a cache hit. Based on the determination that request 114 resulted in a cache hit (for example, a "yes" decision in block 512 based on the identification that the requested data is stored in cache 102), a decision is made (block 514) as to whether the hit cache line has an associated priority value greater than the maximum priority value of an unprotected cache line.

[0085] The controller 108 compares, for example, the priority value of the cache line used to store the data requested by request 114 with a threshold defined by the cache replacement policy 110 (e.g., the priority value shown in priority value key 402). Depending on whether it is determined that the hit cache line has an associated priority value that is not greater than the maximum priority value of an unprotected cache line (e.g., a "no" decision in block 514), the hit cache line priority value is set to the maximum unprotected priority value (block 516). The controller 108 identifies, for example, that the data requested by request 114 is stored in cache line 412. The controller 108 further identifies that cache line 412 has an associated priority value of 2, which is less than the maximum unprotected priority value of 3 shown in priority value key 402 at the time request 114 was received. In response to a cache hit, the controller 108 updates the cache line 412 to have a priority value of 3 (for example, the highest priority value for an unprotected cache line) and transitions the cache 102 from state 404 to state 418.

[0086] Alternatively, depending on whether it is determined that the hit cache line has an associated priority value greater than, or equal to, the maximum priority value of the protected cache line (e.g., the "yes" decision in block 514), the hit cache line priority value is set to the maximum protected priority value (block 518). The controller 108 identifies, for example, that the data requested by request 114 is stored in cache line 408. The controller 108 further identifies that cache line 408 has an associated priority value of 4, which is greater than the maximum unprotected priority value of 3 indicated by priority value key 402 at the time request 114 was received.

[0087] In response to a cache hit, the controller 108 updates the cache line 408 to have a priority value of 7 (for example, the maximum priority value of a protected cache line) and transitions the cache 102 from state 404 to state 416, as shown in Figure 4. Alternatively, in some embodiments, the cache replacement policy 110 causes the controller 108 to increment the priority value of the hit cache line to a value less than the maximum value of a protected cache line or the maximum value of an unprotected cache line.

[0088] In some embodiments, the controller 108 is configured to deviate from the flow shown in Figure 5 based on an indicator of whether a request (e.g., request 114) is hypertransient or non-hypertransient. For example, in an exemplary embodiment where a "no" decision in block 514 causes the controller to proceed to block 516, a request received with an indicator that the request is hypertransient will cause the controller to proceed to block 518 instead and set the priority value of the hit cache line to indicate a hypertransient priority value (e.g., protected maximum). Alternatively, in an exemplary embodiment where a "yes" decision in block 514 causes the controller to proceed to block 518, a request received with an indicator that the request is non-hypertransient will cause the controller to proceed to block 516 instead and set the priority value of the hit cache line to indicate a non-hypertransient priority value (e.g., unprotected maximum). In this way, the cache replacement policy 110 can be configured to cause the controller 108 to update the priority values ​​of cache lines that store data actively involved in performing computation tasks, so that recently used data is promoted for retention in the cache 102. The operation of procedure 500 then returns to serving another request at will, as indicated by the dashed arrows from blocks 516 and 518 back to block 512.

[0089] Alternatively, in embodiments where a request (e.g., request 114) results in a cache miss (e.g., a "no" decision in block 512), a decision is made as to whether the cache line has a minimum priority value (block 520). The controller 108 checks, for example, whether the cache line of cache 102 is associated with a minimum priority value (e.g., a priority value of 0 with respect to example 400). In response to identifying that the cache line is currently associated with a minimum priority value (e.g., a "yes" decision in block 520), the cache line having the minimum priority value is evicted from the cache (block 522). The controller 108 identifies, for example, cache line 406 of cache 102 in state 420 as being associated with a minimum priority value of 0, and evictes the data stored in cache line 406 from cache 102.

[0090] Alternatively, depending on whether it has been identified that there is no cache line currently associated with the minimum priority value (e.g., the "No" decision in block 520), the priority value of each cache line is decremented (block 524). The controller 108 then decreases each of the priority values ​​414 in cache 102 by at least 1. The operation then returns to block 520, where the controller 108 again determines whether any cache lines contain the minimum priority value (e.g., resulting from the decrement performed in block 524). This operation process, represented by blocks 520 and 524, continues until at least one cache line is associated with the minimum priority value, at which point the cache line with the minimum priority value is evicted from the cache (block 522). The operation of step 500 then optionally returns to block 502, where, for example, the data requested by request 114 is inserted into cache 102 as a cache line in place of the cache line evicted in block 522.

[0091] Thus, the inductive logic 112 of the cache replacement policy 110 can be configured such that each individual cache line may be associated with extended bit information (e.g., data encoded with two or more bits) that describes the priority of cache line retention. Such extended bit information allows for defining thresholds in a program-specific manner to generate policies that promote the retention of critical data and / or data retrieved from protected memory locations, in order to curate a tailored cache management policy for a particular computation task, independently of (e.g., without) the need for separate protected / unprotected indicators. With regard to the examples described and illustrated in the context of Figures 4 and 5, such information may be encoded using only three bits per cache line.

[0092] Alternatively, in exemplary embodiments, more than three bits per cache line are used to define custom cache substitution policies for computation tasks. For example, in one exemplary embodiment, each cache line includes a binary protection bit indicator and three or more bits representing the cache line's priority value. Alternatively or additionally, in some embodiments, each cache line comprises information defining a counter representing the maximum number of requests (e.g., the maximum number of requests 114) that the cache line is allowed to hold in cache 102 (e.g., independently of the cache line's associated priority value). In yet another example, in some embodiments, prefetched data is inserted into cache 102 along with an associated priority value defined as the condition for prefetching. For example, in one particular example, data that is prefetched by system 100 (e.g., inserted into cache 102 before a request 114 for the data) is assigned a priority value indicating that the data should be treated as protected (e.g., to prevent the prefetched data from being inadvertently flushed from cache 102 before it is actually used).

[0093] Many modifications are possible based on the disclosures herein. While features and elements are described above in specific combinations, each feature or element can be used alone without other features and elements, or in various combinations with or without other features and elements. For example, the manifestations of the inductive logic described herein can be configured to form part of a cache replacement policy, that is, a cache replacement policy includes the inductive logic described herein.

[0094] The various functional units shown in the figures and / or described herein (including, where appropriate, the cache 102, cache client 104, data store 106, controller 108, cache replacement policy 110, and inductive logic 112) are implemented in any of the various different forms, such as hardware circuitry, software or firmware running on a programmable processor, or any combination of two or more of hardware, software, and firmware. The methods provided are implemented in any of the various devices, such as general-purpose computers, processors, or processor cores. Suitable processors include, by example, general-purpose processors, dedicated processors, conventional processors, digital signal processors (DSPs), graphics processing units (GPUs), parallel accelerators, multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application-specific integrated circuits (ASICs), field-programmable gate array (FPGA) circuits, any other type of integrated circuit (IC), and / or state machines.

[0095] In one or more embodiments, the methods and procedures provided herein are implemented in computer programs, software, or firmware embedded in a non-temporary computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-temporary computer-readable storage media include read-only memory (ROM), random-access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. It is a system, Cache and, Inducing logic to guide the decision on the cache replacement policy by prioritizing the eviction of unprotected cache lines over the eviction of protected cache lines, A controller that selects a cache line from which the cache is evicted in response to a cache miss, based on the cache replacement policy and the guidance logic, comprises: system.

2. The aforementioned controller, This involves removing previous data stored in the aforementioned cache line, The process involves loading data into the aforementioned cache line, wherein the data loaded into the cache line is retrieved for the request that caused the cache miss. It is configured to do, The system according to claim 1.

3. The aforementioned induction logic is generated based on instructions from an application executed by the processor, and the application requests data from the cache. The system according to claim 1.

4. The guidance logic includes information specifying at least one data object, and the controller is configured to specify, based on the guidance logic, a cache line storing the at least one data object as protected. The system according to claim 1.

5. The guidance logic includes information specifying at least one data storage location, and the controller is configured to specify, based on the guidance logic, a cache line that stores data retrieved from the at least one data storage location as protected. The system according to claim 1.

6. Each cache line of the cache includes a configurable bit that provides a binary indicator of whether or not the cache line is protected. The system according to claim 1.

7. The aforementioned controller, Receiving the first request for data, Identifying that the data requested by the first request is stored in the first cache line of the cache, The data requested by the first request is returned to the source of the first request, Incrementing the priority value of the first cache line, It is configured to do, The system according to claim 1.

8. The aforementioned controller, Receiving a second request for data, Identifying that the data requested by the second request is not stored in the cache, and that the second request caused the cache miss, Identifying a second cache line as having a priority value that allows for evicting, wherein the second cache line is selected to be evicted in response to a cache miss, It is configured to do, The system according to claim 1.

9. The aforementioned induction logic, in response to the cache miss, From the aforementioned cache replacement policy, identify the priority value threshold that allows eviction, Identifying that each cache line of the cache is associated with a priority value that does not satisfy the priority value threshold, Decrement the priority value associated with the unprotected cache line until the priority value associated with the unprotected cache line meets the priority value threshold that permits the evicting. The controller is instructed to perform the following actions: The system according to claim 1.

10. The controller decrements the priority values ​​associated with the unprotected cache lines, independently of changing the priority values ​​associated with the protected cache lines of the cache. The system according to claim 9.

11. The controller decrements the priority value associated with the protected cache line in response to evicting data in response to a cache miss. The system according to claim 10.

12. In response to decrementing the priority value associated with the unprotected cache line, at least two unprotected cache lines have associated priority values ​​that satisfy the priority value threshold that permits eviction, and the induction logic causes the controller to select one of the at least two unprotected cache lines for data eviction based on the addresses of the at least two unprotected cache lines. The system according to claim 9.

13. The aforementioned cache replacement policy is: In response to data being loaded from a data storage location indicated by the aforementioned guidance logic as unprotected, assign a default unprotected value to the data loaded into the cache, or Depending on whether the data is loaded from a data storage location indicated to be protected by the aforementioned guidance logic, assign default protection to the data loaded into the cache. By having the controller perform this action, the loading of data into the cache is controlled. The system according to claim 1.

14. It is a method, Receiving a request to access a cache that includes multiple cache lines, The process includes updating the priority value of at least one of the cache lines to prioritize the evicting of unprotected cache lines among the cache lines based on the aforementioned request, wherein the priority value describes the order in which the cache lines are evicted in response to a cache miss, method.

15. The process includes initializing the plurality of cache lines to include information describing at least some of the plurality of cache lines that are protected cache lines, based on the instructions for a computation task to be performed by the processor that received the request. The method according to claim 14.

16. Updating the priority value of at least one of the plurality of cache lines includes incrementing the priority value of at least one of the plurality of cache lines in response to a cache hit for the request. The method according to claim 14.

17. Incrementing the priority value of at least one of the aforementioned multiple cache lines is: Depending on whether at least one of the plurality of cache lines is an unprotected cache line, the priority value of at least one of the plurality of cache lines is incremented to the unprotected threshold, or Depending on whether at least one of the plurality of cache lines is a protected cache line, the priority value of at least one of the plurality of cache lines is incremented to the protected threshold. The method according to claim 16.

18. Updating the priority value of at least one of the plurality of cache lines includes decrementing the priority value of at least one of the plurality of cache lines in response to a cache miss for the request. The method according to claim 14.

19. Updating the priority value of at least one of the aforementioned cache lines is performed independently of changing the priority value of a protected cache line among the aforementioned cache lines. The method of claim 18.

20. It is a method, Receiving requests to access data, Identifying that the aforementioned request will result in a cache miss for a cache containing multiple cache lines, Adjusting the priority value of at least one unprotected cache line toward the evicting threshold, independently of adjusting the priority value of at least one protected cache line toward the evicting threshold, until the priority value of at least one unprotected cache line toward the evicting threshold. The process includes evicting data stored in the at least one unprotected cache line in response to the at least one unprotected cache line satisfying the evicting threshold, method.

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