Method for manufacturing silicon carbide semiconductor device

Abstract

To suppress peeling between an ohmic electrode including metal silicide and wiring or an electrode pad formed thereon.SOLUTION: A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a Poly-Si layer 201 as a silicon layer before forming a metal film 202 for forming an ohmic electrode composed of a silicide electrode when forming the ohmic electrode; forming a metal silicide layer 202a by reacting a metal film 202 and the Poly-Si layer 201 by performing heat treatment at a relatively low temperature as first heat treatment; creating an Si rich state on an n+ type substrate 101 side in the metal silicide layer; and forming an ohmic electrode including the metal silicide layer 202a by siliciding the metal film to a rear surface of the n+ type substrate 101 by performing heat treatment at a high temperature than the first heat treatment as second heat treatment.SELECTED DRAWING: Figure 2C

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a silicon carbide (hereinafter referred to as SiC) semiconductor device having a semiconductor element made of SiC. [Background technology]

[0002] When forming semiconductor elements such as power devices using SiC substrates, it is required to form an ohmic electrode with reduced contact resistance when forming an electrode for connecting the device to an electric circuit, such as a drain electrode on the back side of the substrate in a vertical MOSFET.

[0003] Ohmic contact in SiC requires the formation of a metal silicide, which is an alloy layer between SiC and a metal. For this reason, a metal film that serves as the contact base material is formed on a SiC substrate, and then high-temperature treatment is performed to form a metal silicide at the interface with the SiC substrate to form an ohmic electrode. However, since SiC contains carbon (C), a carbon layer is precipitated at the interface of the metal silicide during heat treatment. Because the adhesion between this carbon layer and metal is poor, when wiring or electrode pads are formed on an ohmic electrode containing metal silicide, they tend to peel off at the interface between the carbon layer and the metal, which reduces the reliability of the device.

[0004] For this reason, Patent Document 1 proposes a method of removing the carbon layer that precipitates during the formation of metal silicide by performing plasma etching in an atmosphere containing oxygen gas or argon gas. By performing plasma etching containing oxygen gas, the carbon content is converted to CO or CO2 and removed, and by performing plasma etching containing argon gas, the upper surface of the electrode is physically etched to remove the carbon content. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2003-243323 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, it is difficult to accurately remove the carbon layer by plasma etching, and if the carbon layer cannot be completely removed, there is a concern that peeling may occur between the ohmic electrode and the wiring or electrode pad formed thereon.

[0007] In addition, when performing plasma etching using argon gas, the upper surface of the electrode is physically etched to remove carbon, which damages the surface of the ohmic electrode, and this may cause deterioration of the electrical connection between the ohmic electrode and the wiring or electrode pad.

[0008] In view of the above, an object of the present invention is to provide a method for manufacturing a SiC semiconductor device that can suppress peeling between an ohmic electrode containing metal silicide and the wiring or electrode pad formed thereon. [Means for solving the problem]

[0009] In order to achieve the above object, the present invention provides a method for manufacturing a SiC semiconductor device having a SiC semiconductor substrate (101) having a main surface (101a) and a back surface (101b) which is the opposite surface thereof, and an ohmic electrode (113) which is ohmic-contacted to one surface of the SiC on at least one of the main surface side and the back surface side of the SiC semiconductor substrate, the method comprising the steps of: forming a silicon layer (201) on the SiC to be ohmic-contacted; forming a metal film (202) for forming the ohmic electrode on the silicon layer; performing a first heat treatment after forming the metal film to react with the silicon layer and form a metal silicide layer (202a) by silicidating the metal film; performing a second heat treatment after the first heat treatment to further advance the formation of the metal silicide layer; One side of the silicon carbide is also silicided,and forming an ohmic electrode that is a silicide electrode including a metal silicide layer.

[0010] In this way, the silicon layer is formed before forming the metal film for forming the ohmic electrode. In addition, the first heat treatment reacts the metal film with the silicon layer to form a metal silicide layer, and the SiC substrate side of the metal silicide layer is made Si-rich. Then, the second heat treatment is performed after this, and the SiC substrate side of the metal silicide layer is made Si-rich. one side The metal silicide layer is silicided to the surface of the semiconductor substrate, forming an ohmic electrode including the metal silicide layer.

[0011] This makes it possible to suppress the precipitation of a carbon layer at the interface of the metal silicide layer, thereby making it possible to suppress peeling between an ohmic electrode including a metal silicide layer and a wiring or electrode pad formed thereon.

[0012] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view of a SiC semiconductor device described in a first embodiment of the present invention. [Figure 2A] 5A to 5C are cross-sectional views showing a process of forming an ohmic electrode. [Figure 2B] 2B is a cross-sectional view showing a step of forming an ohmic electrode subsequent to FIG. 2A. [Figure 2C] FIG. 2C is a cross-sectional view showing a step of forming an ohmic electrode subsequent to FIG. 2B. [Figure 2D] FIG. 2D is a cross-sectional view showing a step of forming an ohmic electrode subsequent to FIG. 2C. [Figure 2E] FIG. 2E is a cross-sectional view showing a step of forming an ohmic electrode subsequent to FIG. 2D. [Figure 3A] 1A to 1C are cross-sectional views showing a conventional process for forming an ohmic electrode. [Figure 3B] FIG. 3B is a cross-sectional view showing a step of forming an ohmic electrode subsequent to FIG. 3A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0015] (First embodiment) First, the SiC semiconductor device according to the present embodiment will be described with reference to Fig. 1. Here, a SiC semiconductor device including a vertical power MOSFET with a trench gate structure as a SiC semiconductor element will be described as an example, but a SiC semiconductor device including other semiconductor elements may be used as long as it has an ohmic electrode formed of a silicide electrode.

[0016] One cell of a vertical MOSFET is shown in Figure 1. A cell region is formed by arranging multiple vertical MOSFET cells shown in this figure in the left-right direction of the page, and a SiC semiconductor device is formed by providing a peripheral breakdown voltage structure (not shown) that surrounds the cell region.

[0017] As shown in FIG. 1, the SiC semiconductor device is a n-type semiconductor device made of SiC. + It is formed using a mold substrate 101. + The mold substrate 101 has a front surface 101a and a back surface 101b opposite thereto, and the back surface 101b corresponds to a drain region connected to a drain electrode 113 corresponding to a back surface electrode described later, in other words, a back surface high concentration region connected to the back surface electrode. + On the surface 101a of the mold substrate 101, + The n-type substrate 101 has a lower impurity concentration than the n-type substrate 101. - A low concentration layer 102 is epitaxially grown.

[0018] n - The low concentration layer 102 is +A narrow JFET section 102a is formed at a position away from the substrate 101, and p-type deep layers 103 are formed on both sides of the JFET section 102a. The p-type deep layers 103 are configured to have the same thickness as the JFET section 102a. Furthermore, a p-type base region 104 is formed on the JFET section 102a and the p-type deep layer 103, and an n-type base region 104 is formed on the p-type base region 104. + type source region 105 and p + A contact region 106 is formed. + The source region 105 is an n - The p-type low concentration layer 102 has a higher impurity concentration than the p-type low concentration layer 102, and is formed on a portion of the p-type base region 104 that corresponds to the JFET portion 102a. + The p-type contact region 106 has a higher impurity concentration than the p-type base region 104 , and is formed on a portion of the p-type base region 104 corresponding to the p-type deep layer 103 .

[0019] The p-type base region 104 and the n + A gate trench 107 is formed so as to penetrate through the p-type source region 105 and reach the JFET section 102a. The p-type base region 104 and the n-type base region 105 are in contact with the side surfaces of the gate trench 107. + 1 as a width direction, a direction normal to the paper surface as a length direction, and a vertical direction of the paper surface as a depth direction. Although only one gate trench 107 is shown in FIG. 1, a plurality of gate trenches 107 are arranged at equal intervals in the horizontal direction of the paper surface. As shown in FIG. 1, the gate trenches 107 are arranged so as to be sandwiched between the p-type deep layers 103, forming a stripe shape.

[0020] In addition, the portion of the p-type base region 104 located on the side surface of the gate trench 107 becomes an n +The gate trench 107 is formed on the inner wall surface of the gate trench 107, which includes the channel region, and has a gate insulating film 108 formed thereon. A gate electrode 109 made of doped poly-Si is formed on the surface of the gate insulating film 108, and the inside of the gate trench 107 is filled with the gate insulating film 108 and the gate electrode 109. This forms a trench gate structure.

[0021] n + Type source region 105 and p + An interlayer insulating film 110 is formed on the surface of the type contact region 106 and the trench gate structure. A source electrode 111 corresponding to a surface electrode and a gate wiring layer (not shown) are formed as a conductor pattern on the interlayer insulating film 110. A contact hole 110a and the like are formed in the interlayer insulating film 110. The source electrode 111 is connected to the n-type contact region 106 through the contact hole 110a. + Type source region 105 and p + 1. The gate wiring layer is electrically connected to the gate electrode 109 through another contact hole in a cross section different from that in FIG.

[0022] Also, n + The back surface 101b side of the substrate 101, that is, the surface opposite to the side on which the source electrode 111 is formed, is provided with an n + A drain electrode 113 corresponding to a back electrode electrically connected to the mold substrate 101 is formed. The drain electrode 113 is an ohmic electrode made of a silicide electrode, and is made of a metal material that can be turned into a silicide, such as nickel (Ni), Mo (molybdenum), or titanium (Ti). The metal constituting the drain electrode 113 does not need to be a single type of material, and may be a combination of two or more of the materials listed here, such as Mo / Ni. The material constituting the drain electrode 113 may contain impurities.

[0023] The drain electrode 113 is +The interface with the mold substrate 101 is a silicided metal silicide layer 202a (see FIG. 2E described later), and the silicide electrode including the metal silicide layer 202a serves as an ohmic electrode. Carbon precipitation at the interface of the metal silicide layer 202a included in this drain electrode 113 is suppressed.

[0024] With this structure, a SiC semiconductor device including a vertical MOSFET with an n-channel type inversion type trench gate structure is configured. Since carbon deposition is suppressed at the interface of the metal silicide layer 202a included in the drain electrode 113, peeling at the interface of the metal silicide layer 202a included in the drain electrode 113 can be suppressed. This makes it possible to suppress deterioration of the electrical connection between the drain electrode 113 and the wiring or electrode pad (not shown).

[0025] Next, a method for manufacturing the SiC semiconductor device configured as above will be described. However, since the basic method for manufacturing the vertical power MOSFET according to this embodiment is similar to the conventional method, the method for forming the drain electrode 113, which is different from the conventional method, will be mainly described.

[0026] The vertical power MOSFET according to this embodiment is manufactured through the manufacturing steps shown in FIGS. 2A to 2E.

[0027] First, as shown in Figure 2A, + A mold substrate 101 is prepared. + The substrate 101 is manufactured by slicing and then polishing an n-type impurity-doped SiC ingot, for example. + A device formation process is carried out on the front surface 101a of the mold substrate 101 to form at least a part of the components of a semiconductor device. - After epitaxial growth of the low concentration p-type layer 102, a process of forming a p-type deep layer 103 by ion implantation using a mask (not shown) and a process of forming a p-type base region 104 by epitaxial growth are performed.+ The process of forming the p-type source region 105 by ion implantation + The process includes a step of forming a mold contact region 106, a step of forming a gate trench 107 by anisotropic etching, and a step of forming a gate insulating film 108 by thermal oxidation or the like. In addition, the process includes a step of forming a gate electrode 109 by depositing doped Poly-Si and etching it back, a step of forming and patterning an interlayer insulating film 110, and a step of forming and patterning a source electrode 111 and a gate wiring layer. Through these steps, the front side structure of the components of the semiconductor element is formed.

[0028] After that, the n + A part of the back surface 101b side of the mold substrate 101 is removed, and + A thinning process is performed to thin the mold substrate 101. For example, + The back surface 101b of the mold substrate 101 is turned to the front, and the other surface is attached to a glass substrate, and then CMP (Chemical Mechanical Polishing) or the like is performed to form a n + A part of the back surface 101b side of the mold substrate 101 is removed and flattened. Then, the steps shown in FIGS. 2B to 2E are performed to obtain a thin-film n + A step of forming a drain electrode 113 on the rear surface 101b of the mold substrate 101 is carried out.

[0029] Specifically, in the process shown in FIG. 2B, after thinning, +A Poly-Si layer 201 corresponding to a silicon layer is formed on the back surface 101b of the mold substrate 101. Next, as a process shown in FIG. 2C, a metal film 202 for forming the drain electrode 113 is formed on the Poly-Si layer 201. The Poly-Si layer 201 may be non-doped Poly-Si that is not doped with impurities, or may be doped Poly-Si that is doped with impurities. The silicon layer is not limited to the Poly-Si layer 201, and may be made of single crystal silicon. The metal film 202 may be made of Ni, Mo, Ti, or the like, which are metal materials that cause a silicide reaction, and Ni is used here. The thicknesses of the Poly-Si layer 201 and the metal film 202 are arbitrary, but the thickness of the Poly-Si layer 201 may be thick enough to cause a silicide reaction with the metal film 202 in the process shown in FIG. 2D.

[0030] Specifically, when the metal film 202 is made of Ni, Tp / Tm≦0.5 is satisfied, where Tp is the thickness of the Poly-Si layer 201 and Tm is the thickness of the metal film 202. The thickness Tm of the metal film 202 is arbitrary, but can be, for example, 100 nm to 200 nm. When the thickness Tm is 100 nm, the thickness Tp of the Poly-Si layer 201 should be 50 nm or less.

[0031] The appropriate value of Tp / Tm varies depending on the metal material used to form the metal film 202, and should be determined in accordance with the metal material.

[0032] In the subsequent step shown in FIG. 2D, the sample that has been subjected to the step shown in FIG. 2C is heated using a heating device as the first heat treatment, thereby causing a reaction between the Poly-Si layer 201 and the metal film 202. For example, heating is performed for 10 minutes or more at a heating temperature of 300 to 350° C. Any heating device may be used, but a heating device that does not affect the front side structure of the components of the semiconductor element is used. Here, the first heat treatment is performed at a relatively low temperature, and the effect on the front side structure is small, so the entire sample is heated collectively using a heater heating device or the like, but local heating may also be performed.

[0033] As a result, a metal silicide layer 202a is formed. When the metal film 202 is made of Ni, the metal silicide layer 202a made of nickel silicide (NiSi) is formed. The metal silicide layer 202a has a n + It is preferable that the metal silicide layer 202a is formed to the rear surface 101b of the mold substrate 101. However, at the stage of the process shown in FIG. 2D, the metal silicide layer 202a and the n + The polysilicon layer 201 may remain between the back surface 101b of the mold substrate 101 and the polysilicon layer 201. In either case, the n-type metal silicide layer 202a may be + The side of the n-type substrate 101 is in a Si-rich state in which silicon elements are more abundant than carbon elements. In addition, the metal film 202 is not entirely silicided, so that the n-type substrate 101 is sandwiched between the metal silicide layer 202a. + On the side opposite to the mold substrate 101, a remainder 202b of the metal material constituting the metal film 202 remains as it is.

[0034] Then, as a step shown in FIG 2E, a second heat treatment is performed using a heating device. In the second heat treatment, n of the metal silicide layer 202a is removed by the step shown in FIG 2D. + This is done in a state where the substrate 101 side is Si-rich. +The formation of the metal silicide layer 202a is further advanced so that the rear surface 101b of the mold substrate 101 is silicided, and the drain electrode 113 can be formed as a silicide electrode including the metal silicide layer 202a.

[0035] The second heat treatment is performed at a higher temperature than the first heat treatment, for example, at a heating temperature of 950 to 1000°C for a time of 10 nsec to 0.1 sec. Any heating device may be used for the second heat treatment, but it is preferable not to affect the front side structure of the components of the semiconductor element. For this reason, it is preferable to use a device that can perform localized heating such as a laser annealing device or a device that can perform instantaneous heating such as a flash lamp annealing device. Here, a heating device different from the heating device used for the first heat treatment is used for the second heat treatment, but the same heating device may be used. In that case, in addition to being able to perform each heat treatment using a common heating device, transportation between devices is not required.

[0036] In this way, the n-type metal silicide layer 202a + When the second heat treatment is performed in a state where the mold substrate 101 side is Si-rich, it is possible to suppress the precipitation of carbon at the interface of the metal silicide layer 202a included in the drain electrode 113. This makes it possible to suppress the peeling at the interface of the metal silicide layer 202a included in the drain electrode 113. This makes it possible to suppress the deterioration of the electrical connection between the drain electrode 113 and the wiring or electrode pad (not shown).

[0037] In this way, drain electrode 113 is formed as shown in Fig. 2E. After this, although not shown, dicing is performed to divide the substrate into chip units, thereby completing the SiC semiconductor device.

[0038] As described above, in this embodiment, when forming the drain electrode 113 constituting the silicide electrode, the Poly-Si layer 201 is formed before forming the metal film 202 for forming the drain electrode 113. In addition, by performing a heat treatment at a relatively low temperature as the first heat treatment, the metal film 202 and the Poly-Si layer 201 are reacted to form the metal silicide layer 202a, and the n-type portion of the metal silicide layer 202a is removed. + The side of the mold substrate 101 is made to be Si-rich. Then, the second heat treatment is performed at a higher temperature than the first heat treatment, so that the n + The back surface 101b of the mold substrate 101 is also silicided to form a drain electrode 113 including a metal silicide layer 202a.

[0039] This makes it possible to suppress the precipitation of a carbon layer at the interface of the metal silicide layer 202a, and therefore makes it possible to suppress peeling between the drain electrode 113 constituting a silicide electrode including the metal silicide layer 202a and the wiring and electrode pad formed thereon.

[0040] In addition, in the conventional manufacturing method, that is, as shown in FIG. + When a metal film 202 is formed directly on a mold substrate 101 and then heated at a heating temperature of 950 to 1000° C. as a heat treatment, a carbon layer 300 is precipitated on the surface of the metal film 202 including the metal silicide layer 202a, as shown in FIG 3B. For this reason, a process of removing the carbon layer 300 by plasma etching is performed.

[0041] However, the manufacturing method of this embodiment makes it possible to suppress peeling at the interface of the metal silicide layer 202a, and therefore it is not necessary to remove the carbon layer 300 by using plasma etching as in the conventional method. Therefore, it is possible to prevent physical damage caused by plasma etching on the drain electrode 113, and to suppress deterioration of the electrical connection between the drain electrode 113 and wiring or an electrode pad (not shown) caused by such damage.

[0042] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0043] (1) For example, in the above embodiment, the manufacturing method according to the present invention has been described as being applied to an ohmic electrode on the back side of a device in which each component is formed on the front side of a SiC substrate as an example of a silicide electrode. However, the manufacturing method according to the present invention is applicable not only to the case where an ohmic electrode is formed on the back side of a device in which each component is formed on the front side of a SiC substrate. That is, as long as an ohmic electrode is formed on either the front side or the back side of a SiC substrate, the manufacturing method according to the present invention can be applied to any part in which an ohmic electrode is formed, for example, to the case where an ohmic electrode is formed on the front side of a SiC substrate. Even in this case, when forming an ohmic electrode after forming each component of the device, it is possible to suppress the influence on the device by using a heating device capable of performing local heat treatment, such as a laser annealing device.

[0044] (2) In the above first embodiment, the SiC semiconductor device including a vertical power MOSFET as a semiconductor element has been described as an example, but this is also merely one example, and the SiC semiconductor device may include other semiconductor elements such as a diode, an IGBT, etc. In other words, any SiC semiconductor device may be used as long as it has an ohmic electrode for a semiconductor element formed on a SiC semiconductor substrate. [Explanation of symbols]

[0045] 101n + Mold Board 113 Drain electrode 201 Poly-Si layer 202 Metal Film 202a Metal silicide layer

Claims

1. A method for manufacturing a silicon carbide semiconductor device comprising: a silicon carbide semiconductor substrate (101) having a main surface (101a) and a back surface (101b) opposite thereto; and an ohmic electrode (113) that is ohmic-contacted to one surface of silicon carbide on at least one of the main surface side and the back surface side of the silicon carbide semiconductor substrate, the method comprising: forming a silicon layer (201) on the silicon carbide to be ohmic-contacted; forming a metal film (202) for forming the ohmic electrode on the silicon layer; After forming the metal film, a first heat treatment is performed to react the metal film with the silicon layer and form a metal silicide layer (202a) by silicidating the metal film; performing a second heat treatment after the first heat treatment to further advance the formation of the metal silicide layer and silicide one surface of the silicon carbide, thereby forming the ohmic electrode with a silicide electrode including the metal silicide layer; The method for manufacturing a silicon carbide semiconductor device includes:

2. 2 . The method for manufacturing a silicon carbide semiconductor device according to claim 1 , wherein said first heat treatment extends said metal silicide layer up to a position reaching said silicon carbide.

3. The method for manufacturing a silicon carbide semiconductor device according to claim 1 , wherein the second heat treatment is performed at a temperature higher than that of the first heat treatment.

4. The first heat treatment is carried out at a heating temperature of 300 to 350° C., 4. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the second heat treatment is performed at a heating temperature of 950 to 1000.degree.

5. The method for manufacturing a silicon carbide semiconductor device according to claim 1 , wherein the second heat treatment is performed by laser annealing or flash lamp annealing.

6. In the forming of the metal film, the metal film is made of Ni; 6. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein forming the silicon layer and forming the metal film are performed such that Tp / Tm≦0.5, where Tp is a thickness of the silicon layer and Tm is a thickness of the metal film.

7. In the forming of the metal film, the metal film is made of Ni, 7. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein, in forming said silicon layer, said silicon layer is constituted by a Poly-Si layer.

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