Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device and a method of manufacturing a silicon carbide semiconductor device, enabling improvement of the reliability and yield thereof.SOLUTION: The type, size, and position of a crystal defect in an epitaxial layer of a semiconductor wafer 50 made of silicon carbide is detected by a PL image of a crystal defect inspection device. The crystal defect to be detected are polytype triangular lamination faults 71 generated in the epitaxial layer during epitaxial growth, and high-density BPD 72 extending from the lamination fault 71 and existing between a complete crystal and the lamination faults 71 while forming a bundle. A chip region not including the polytype triangular lamination fault and not including the high-density BPD at the inside from a prescribed position (in an active region and a withstanding voltage structure) is selected as a non-defective product. A semiconductor chip to be considered as the non-defective product may include the high-density BPD outside the prescribed position.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, in SiC-MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS-type field effect transistors with an insulated gate made of a three-layer structure of metal-oxide-semiconductor), which use silicon carbide (SiC) as a semiconductor material, n + On the starting substrate of type n - A semiconductor chip is used in which the epitaxial layers that will become the p-type drift region and p-type base region are epitaxially grown in sequence. Basal plane dislocations (BPDs) occur inside the epitaxial layer of the semiconductor chip due to propagation from the starting substrate during epitaxial growth or process damage.

[0003] The p-type base region and n-type - When the parasitic diode (body diode) formed by the pn junction with the type drift region becomes conductive, the bipolar action of the body diode - Minority carriers (holes) injected into the n-type drift region recombine with electrons. If this recombination occurs near the BPD, Shockley-type stacking faults grow (expand) in the epitaxial layer starting from the BPD, degrading the forward characteristics of the body diode and the on-voltage characteristics of the MOSFET. - By placing an n-type buffer region (epitaxial layer) between the pn junction and the BPD, the number of holes reaching the BPD from the pn junction is reduced, suppressing the growth of Shockley-type stacking faults.

[0004] Conventional silicon carbide semiconductor devices include n + On the starting substrate which will become the type cathode region, - Type drift region, p +Type anode region and p ++ A device has been proposed in which epitaxial layers that become high-doped n-type regions are stacked in order (see, for example, Patent Document 1 below). - Invaded from the type drift region and p + The electrons that are not captured by the holes in the anode region are transported to the front surface (p ++ Before reaching the surface of the highly doped region, ++ The recombination of electrons and holes near defect nuclei, which are captured by holes in the highly doped region and are largely localized near the front surface, is suppressed, thereby suppressing the occurrence of stacking faults originating from the defect nuclei and suppressing an increase in the forward voltage of the bipolar semiconductor device.

[0005] Another silicon carbide semiconductor device has been proposed in which a crystal growth surface is a surface having an off angle θ of 8 degrees with respect to the C-plane (carbon plane) of a starting substrate made of silicon carbide, and epitaxial layers such as a buffer region and a drift region are epitaxially grown on this growth surface at a growth rate (increase in thickness) per hour (h) of 10 μm / h or more (see, for example, Patent Document 2 below). In Patent Document 2 below, the growth rate of the epitaxial layer is increased by three times or more compared to the conventional method, and the critical supersaturation of the C-plane is relatively increased, thereby suppressing the propagation of basal plane dislocations, which are the starting points for the growth of stacking faults, and suppressing deterioration of the forward characteristics of the bipolar semiconductor device. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2009-010120 A [Patent Document 2] JP 2005-167035 A Summary of the Invention [Problem to be solved by the invention]

[0007] In conventional SiC-MOSFETs, when the body diode is conducting,+ The holes injected from the n-type contact region and passing through the main junction (pn junction) recombine with electrons in the n-type buffer region and disappear. + From the n-type contact region to the n-type buffer region (n + When a Shockley-type BPD is present in the n-type drain region, the n-type buffer region suppresses hole injection, making it difficult for holes to reach the vicinity of the BPD, suppressing the degradation of the on-state voltage characteristics of the MOSFET. - If a Shockley-type BPD exists in the drift region, hole injection near the BPD is not suppressed, and the n - Shockley-type stacking faults grow in the drift region, degrading the on-state voltage characteristics of the MOSFET.

[0008] n - Among the multiple types of stacking faults newly generated in the epitaxial layer during epitaxial growth, stacking faults with high density BPDs are Shockley type BPDs generated in the type drift region. Figure 11 is an explanatory diagram that shows a schematic view of the crystal defects detected in a semiconductor wafer observed from the front surface (the surface on the epitaxial layer side). Figure 11 (a) and (b) respectively show a differential interference contrast (DIC) image and a photoluminescence (PL) image of a triangular stacking fault 111 of a polytype (crystal polymorphism) detected by a crystal defect inspection device.

[0009] The triangular polytype stacking fault 111 is newly generated in the epitaxial layer due to polytype inclusion during epitaxial growth, and is accompanied by high-density BPDs 112 around it. The high-density BPDs 112 are BPDs that exist in bundles at the boundary between the triangular polytype stacking fault 111 and a perfect crystal (SiC single crystal in the epitaxial layer). The high-density BPDs 112 propagate (extend) in the <1-100> direction in the epitaxial layer during epitaxial growth. Therefore, depending on the position where the triangular polytype stacking fault 111 is generated, it may invade another chip region 101 (101b) adjacent to the chip region 101 (101a) where the stacking fault 111 is generated.

[0010] Conventionally, surface abnormalities of a semiconductor wafer 100 are detected by a DIC image of a crystal defect inspection device, and chip regions 101 are classified as good or bad according to the presence or absence of the surface abnormalities. As shown in FIG. 11(a), in the DIC image, only abnormalities (surface irregularities) appearing on the surface of the semiconductor wafer 100 are observed. All chip regions 101a (parts above the dicing line 102) in which surface abnormalities such as triangular stacking faults 111 of the polytype are detected are removed as defective chips. Chip regions 101b (parts below the dicing line 102) in which no surface abnormalities are detected are released to the market as good products (good chips) even if high-density BPDs 112 are propagated from the adjacent chip regions 101a.

[0011] As shown in FIG. 11(b), the PL image is used to observe abnormalities inside the semiconductor wafer 100. In the PL image, it is possible to detect a triangular polytype stacking fault 111 generated in a predetermined chip region 101a, a high-density BPD 112 generated around the stacking fault 111, and a state in which the high-density BPD 112 propagates from the chip region 101a to the adjacent chip region 101b. The chip region 101 is a portion of the semiconductor wafer 100 that is diced (cut) into individual semiconductor chips. The chip region 101 has a substantially rectangular planar shape, and a plurality of chip regions 101 are arranged in a matrix. A dicing line 102 is formed at the boundary between adjacent chip regions 101.

[0012] The inventors have confirmed through their intensive research that the high-density BPDs 112 may be the starting point for the growth of Shockley-type stacking faults when the body diode is conductive, or may cause an increase in the leakage current Idss during long-term operation of the MOSFET. For this reason, it is assumed that all chip regions 101b in which the high-density BPDs 112 are detected are removed as defective chips, but if all chip regions 101b in which the high-density BPDs 112 have propagated even in small amounts are deemed defective, the yield will decrease. For this reason, it is desirable to prevent chip regions 101b in which the high-density BPDs 112 are detected from being released onto the market and to select chip regions 101b in which the reliability is not reduced as non-defective products.

[0013] In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can improve reliability and yield. [Means for solving the problem]

[0014] In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a silicon carbide semiconductor device according to the present invention is a method for manufacturing a vertical silicon carbide semiconductor device having electrodes on both main surfaces of a semiconductor chip formed by epitaxially growing an epitaxial layer on a starting substrate made of silicon carbide, and has the following features: A pre-process is performed to prepare a semiconductor wafer formed by epitaxially growing the epitaxial layer on a starting wafer made of silicon carbide that serves as the starting substrate; A detection process is performed to detect crystal defects in the epitaxial layer; and A formation process is performed to form a predetermined element structure in the semiconductor wafer.

[0015] After the forming step, a cutting step is performed in which the semiconductor wafer is diced to separate the semiconductor chips. A first selection step is performed in which predetermined semiconductor chips are selected as non-defective products based on the results of the detection step. The semiconductor chips include an active region in which the element structure is provided, a termination region surrounding the active region, and a pn junction formed within the epitaxial layer and constituting a main junction of the device structure; In the detection step, stacking faults and BPDs extending from the stacking faults are detected inside the epitaxial layer. In the first selection step, the semiconductor chips that do not include the stacking faults and do not include the BPDs inside a predetermined position in the termination region that has been acquired in advance are selected as non-defective products.

[0016] In addition, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, a boundary between the active region and the termination region is formed by The above The specified position is an outer end of the pn junction. The specified position is a position that is 60% of the length of the termination region in a direction parallel to the main surface of the semiconductor chip from the boundary between the active region and the termination region.

[0017] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the specified position is a limit position reached by a hole current flowing toward the starting substrate so as to spread outward from the pn junction when a diode formed by the pn junction is conductive, with a hole density contributing to growth of Shockley stacking faults originating from the BPDs.

[0018] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the detection step detects a position of a triangular stacking fault of a polytype generated during epitaxial growth of the epitaxial layer, and a termination position of the BPD extending from the stacking fault.

[0019] In the method for manufacturing a silicon carbide semiconductor device according to the present invention, a plurality of chip regions that will become the semiconductor chips after the cutting step are arranged adjacent to each other on the semiconductor wafer, and the first sorting step is characterized in that the semiconductor chips obtained by singulating the chip regions that do not contain the stacking faults and the BPDs and the semiconductor chips obtained by singulating the chip regions that do not contain the stacking faults and in which the BPDs intruding from the adjacent chip regions terminate outside the specified position are sorted as non-defective products.

[0020] In the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the detecting step detects the crystal defects using a photoluminescence image of the semiconductor wafer.

[0021] The method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, it further includes an inspection step and a second sorting step. In the inspection step, electrical characteristics of the semiconductor chips sorted in the first sorting step are inspected. In the second sorting step, the semiconductor chips sorted in the first sorting step are further sorted to those which satisfy predetermined characteristics from the semiconductor chips sorted in the first sorting step based on the results of the inspection step.

[0022] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the forming step forms a breakdown voltage structure between a boundary between the active region and the termination region and the specified position.

[0023] Furthermore, in order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention is a vertical silicon carbide semiconductor device having electrodes on both main surfaces of a semiconductor chip formed by epitaxially growing an epitaxial layer on a starting substrate made of silicon carbide, and has the following features: An active region and a termination region are provided in the semiconductor chip. The termination region surrounds the periphery of the active region. A predetermined element structure is provided in the active region. The semiconductor chip comprises: a pn junction forming a main junction of the element structure is provided inside the epitaxial layer;It does not include a triangular polytype stacking fault generated in the epitaxial layer during epitaxial growth, and does not include a BPD generated between the stacking fault and a perfect crystal extending from the stacking fault during epitaxial growth inside a specified position in the termination region.

[0024] Further, the present invention provides a silicon carbide semiconductor device, ,before The boundary between the active region and the termination region is an outer end of the pn junction, and the specified position is a position that is a distance that is 60% of the length of the termination region from the boundary between the active region and the termination region in a direction parallel to a main surface of the semiconductor chip.

[0025] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the specified position is a limit position reached by a hole current flowing toward the starting substrate so as to spread outward from the pn junction when a diode formed by the pn junction is conductive, with a hole density contributing to growth of Shockley stacking faults originating from the BPD.

[0026] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the semiconductor chip includes the BPD outside the specified position.

[0027] According to the above-mentioned invention, it is possible to prevent semiconductor chips that may have reduced reliability due to the inclusion of high-density BPDs (BPDs extending from triangular stacking faults of a polytype generated in the epitaxial layer during epitaxial growth) from being released onto the market. In addition, by setting a range (inside a specified position) in which high-density BPDs should not be included in a semiconductor chip, it is possible to determine that a semiconductor chip that has predetermined characteristics even if it contains high-density BPDs is a good product. Effect of the Invention

[0028] Advantageous Effects of Invention According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention, it is possible to improve the reliability and the yield. [Brief description of the drawings]

[0029] [Figure 1] 1 is a plan view showing a layout viewed from the front surface side of a semiconductor wafer on which silicon carbide semiconductor devices according to an embodiment are manufactured. FIG. [Diagram 2] 2 is a plan view showing a layout of a semiconductor chip cut from the semiconductor wafer of FIG. 1 as viewed from the front surface side. [Diagram 3] 3 is a cross-sectional view showing an example of a cross-sectional structure of the active region in FIG. 2. [Figure 4] 3 is a cross-sectional view showing an example of a cross-sectional structure of the edge termination region of FIG. 2. [Diagram 5] 1 is a flowchart outlining a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 6] 6 is an explanatory diagram illustrating a schematic shape of a crystal defect detected in the process of step S3 in FIG. 5. [Figure 7] 6 is an explanatory diagram illustrating a schematic shape of a crystal defect detected in the process of step S3 in FIG. 5. [Figure 8] 1 is a table showing the results of measuring hole diffusion distances in experimental examples. [Figure 9] 13 is a table showing the results of calculating the ratio of hole diffusion lengths in experimental examples. [Figure 10] FIG. 1 is an explanatory diagram showing a schematic view of a range in which Shockley stacking faults grow in an experimental example, as observed from the front surface side of a semiconductor chip. [Figure 11] 1 is an explanatory diagram illustrating a state in which crystal defects detected in a semiconductor wafer are observed from the front surface side. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p. Note that in the following description of the embodiments and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted. In this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before an index represents a negative index.

[0031] (Embodiment) FIG. 1 is a plan view showing a layout viewed from the front surface side of a semiconductor wafer on which a silicon carbide semiconductor device according to an embodiment has been manufactured (fabricated). FIG. 2 is a plan view showing a layout viewed from the front surface side of a semiconductor chip cut from the semiconductor wafer of FIG. 1. FIG. 2 shows a state after cutting of one chip region 51 of the semiconductor wafer 50 of FIG. 1. FIGS. 3 and 4 are cross-sectional views showing examples of the cross-sectional structures of the active region and edge termination region of FIG. 2, respectively. FIG. 4 shows a simplified pn junction 36 of the main junction of the MOSFET of FIG. 3. + Type region 37 and n + 3. A pn ​​junction 36 in a type region 38 is shown.

[0032] Silicon carbide semiconductor device 10 according to the embodiment shown in Figures 2 and 3 is fabricated (manufactured) in each chip region 51 (see Figure 1) of semiconductor wafer 50 using silicon carbide (SiC) as a semiconductor material by a general manufacturing method, and chip region 51 is singulated into individual semiconductor chips (semiconductor substrates) 30. Semiconductor wafer 50 is made of n + Starting wafer (n in Figure 3 after dicing) + 3. An epitaxial layer (which will become epitaxial layer 35 in FIG. 3 after dicing) is epitaxially grown on the mold starting substrate 31.

[0033] The semiconductor wafer 50 may have, for example, an orientation flat (a linear notch provided on a part of an edge) 54 or a notch (a V-shaped notch provided on a part of an edge: not shown) indicating the surface orientation. Each chip region 51 of the semiconductor wafer 50 is cut (diced) along dicing lines 52 to be singulated into individual semiconductor chips 30. All of the semiconductor chips 30 singulated from the same semiconductor wafer 50 have the same epitaxial layer 35 (see FIG. 3) and the same element structure (here, a trench gate structure: see FIG. 3) formed in the same process.

[0034] The chip regions 51 have a substantially rectangular planar shape, and are arranged in a matrix in the substantially central portion of the semiconductor wafer 50. Adjacent chip regions 51 are arranged so as to share one side, for example. Dicing lines 52 are formed at the boundaries between adjacent chip regions 51. The dicing lines 52 surround the chip regions 51 in a lattice pattern. The dicing lines 52 are grooves formed in the main surface of the semiconductor wafer 50 (the surface on the epitaxial layer 35 side in FIG. 3). Within the dicing lines 52, marks (position specifying marks: not shown) are formed for specifying a position (coordinates) in a direction parallel to the surface of the semiconductor wafer 50.

[0035] The position specifying marks are markers for specifying the position of each chip region 51 and the position of a crystal defect. The position specifying marks are, for example, convex or concave portions of a predetermined planar shape (for example, a cross shape) formed by etching within the dicing lines 52. The position specifying marks may be provided in the invalid region 53 of the semiconductor wafer 50. The invalid region 53 is a portion between the outermost chip region 51 of the semiconductor wafer 50 and the edge of the semiconductor wafer 50 that is not used as a semiconductor chip 30. As the position specifying marks, alignment marks for aligning each portion of the element structure formed in the chip region 51 may be used.

[0036] The silicon carbide semiconductor device 10 according to the embodiment shown in Figures 2 and 3 is, for example, an n-channel vertical MOSFET having a trench gate structure on the front surface side of a semiconductor chip 30 made of silicon carbide in an active region 41. The active region 41 is a region through which a main current (drift current) flows when the silicon carbide semiconductor device 10 (MOSFET) is in an on-state, and multiple unit cells (functional units of an element) of the MOSFET having the same structure are arranged adjacent to each other. Figure 3 shows one unit cell of the MOSFET. The active region 41 is, for example, arranged approximately in the center (chip center) of the semiconductor chip 30, and is surrounded by an edge termination region 42.

[0037] The edge termination region 42 is a region between the active region 41 and the end (chip end) of the semiconductor chip 30. The edge termination region 42 has a function of alleviating the electric field on the front surface side of the semiconductor chip 30 to maintain a breakdown voltage. The breakdown voltage is the limit voltage at which the leakage current does not increase excessively and the silicon carbide semiconductor device 10 does not malfunction or break down. The breakdown voltage is determined by the n - It is determined by the impurity concentration and thickness t1 of the n-type drift region 2b. - The thickness t1 of the drift region 2b is the thickness + The n-type buffer region 2a (if the n-type buffer region 2a is not provided), + 1) is the distance to the gate electrode.

[0038] The length of the edge termination region 42 (the distance from the active region 41 to the chip edge) w1 is n - Based on the thickness t1 of the type drift region 2b, the rated voltage, and the breakdown voltage structure, the voltage applied to the edge termination region 42 is determined to be equal to or lower than a predetermined voltage. The rated voltage is the voltage applied to the active region 41, and is the usage limit voltage at which the performance of the silicon carbide semiconductor device 10 can be guaranteed. The boundary 43 between the active region 41 and the edge termination region 42 is the outermost end position (chip end side) of the pn junction 36 described later, and more specifically, the outermost p + The p-type region 22 (in FIG. 4, it is collectively referred to as a p-type region) + This is the location of the outer edge of the mold area (shown as 37).

[0039] In edge termination region 42, a breakdown voltage structure (not shown), such as a field limiting ring (FLR) structure or a junction termination extension (JTE) structure, is disposed between the boundary between active region 41 and edge termination region 42 and a prescribed position 44, which will be described later. The outer end position of the breakdown voltage structure disposed in edge termination region 42 is prescribed position 44. In other words, if the breakdown voltage structure is an FLR structure or a JTE structure, the outer end position of the outermost p-type region among the multiple p-type regions that make up the breakdown voltage structure is prescribed position 44.

[0040] The trench gate structure includes a p-type base region 4, a n + Type source region 5, p ++ The semiconductor chip 30 is made of n-type contact region 6, trench 7, gate insulating film 8, and gate electrode 9. + On the front surface of the starting substrate 31, n-type buffer regions 2a, - The epitaxial layers 32 to 34 (collectively indicated by reference numeral 35 in FIG. 3) which become the n-type drift region 2b and the p-type base region 4 are epitaxially grown in sequence. The main surface of the semiconductor chip 30 on the epitaxial layer 35 side is the front surface, and + The main surface (n + The back surface of the mold starting substrate 31 is referred to as the back surface.

[0041] The semiconductor chip 30 does not include a triangular polytype stacking fault 71 (see FIGS. 6 and 7) detected by a photoluminescence (PL) image or a differential interference contrast (DIC) image of a crystal defect inspection device. The semiconductor chip 30 does not include a high-density BPD 72 (see FIGS. 6 and 7) detected by a PL image of a crystal defect inspection device in the entire active region 41 and in a portion from a boundary 43 between the active region 41 and the edge termination region 42 to a position (hereinafter referred to as a specified position) 44 that is a predetermined distance w2 outward in a direction parallel to the front surface of the semiconductor chip 30 (horizontal direction). The semiconductor chip 30 may include a high-density BPD 72 as long as it is outside the specified position 44.

[0042] The crystal defect inspection device is, for example, a SiC wafer defect inspection / review device SICA88 manufactured by Lasertec Corporation. The triangular polytype stacking fault 71 is a triangular defect newly generated in the epitaxial layer 35 due to polytype inclusions during epitaxial growth, and is accompanied by high-density BPDs 72 around it. The triangular polytype stacking fault 71 is a killer defect that causes a significant decrease in the tolerance, reliability, and electrical characteristics of the silicon carbide semiconductor device 10. For this reason, the semiconductor chip 30 is determined to be a non-defective product standard not to include the triangular polytype stacking fault 71.

[0043] The high-density BPD 72 is a BPD loop that exists at the boundary between the triangular stacking fault 71 in the polytype and a perfect crystal (the SiC single crystal of the epitaxial layer 35). The BPD loop is a BPD that extends from the triangular stacking fault 71 in the polytype so as to connect two points of the stacking fault 71. The BPD loops that make up the high-density BPD 72 spread in a ripple-like bundle from each of the multiple points of the triangular stacking fault 71 in the polytype, and include threading edge dislocations (TEDs) and threading screw dislocations (TSDs).

[0044] The high-density BPD 72 is the starting point for the growth (expansion) of Shockley-type stacking faults when the parasitic diode (body diode) formed at the main junction (pn junction 36) of the MOSFET is conductive (forward direction) and causes an increase in leakage current Idss during long-term operation of the MOSFET, but the inventor's extensive research has newly revealed that these problems will not occur if the high-density BPD 72 is located outside of the specified position 44 of the semiconductor chip 30. This specified position 44 is a position that is a distance w2 (w2=w1×0.6) that is about 60% of the length w1 of the edge termination region 42 in the horizontal direction from the boundary 43 between the active region 41 and the edge termination region 42.

[0045] The reason why the specified position 44 of the semiconductor chip 30 is set to the above-mentioned position is as follows. When the body diode is conductive, a current flows from the front surface electrode 14 through the pn junction 36 to the n-type current diffusion regions 3 and 4, which will be described later. - n-type drift region 2b, n-type buffer region 2a and n + In Figure 4, these n-type regions are grouped together as one n + A hole current (indicated by an arrow in FIG. 4 ) flows through the active region 41 and the edge termination region 42, and reaches the end 45 of the back electrode 15, via the active region 41 and the edge termination region 42, because the back electrode 15 is provided on the entire back surface of the semiconductor chip 30.

[0046] The electric field applied to the semiconductor chip 30 becomes weaker toward the outside of the semiconductor chip 30, and the hole density of the hole current flowing when the body diode is conductive becomes smaller. The limit position at which the hole current flowing to spread outward from the active region 41 when the body diode is conductive reaches a hole density high enough to contribute to the growth of Shockley stacking faults is a position that is a distance w2 that is about 60% of the length w1 of the edge termination region 42 in the horizontal direction from the boundary 43 between the active region 41 and the edge termination region 42. This limit position is defined as a specified position 44, and the non-existence of high-density BPDs 72 inside the specified position 44 of the semiconductor chip 30 is defined as a non-defective product standard.

[0047] If the high-density BPDs 72 are located between the chip end and the specified position 44 (from the chip end to a position that is about 40% of the length w1 of the edge termination region 42 in the horizontal direction), the amount of hole injection (hole density) required for the growth of Shockley-type stacking faults is not supplied regardless of the depth position of the high-density BPDs 72, so they do not become the starting point for the growth of Shockley-type stacking faults. In addition, it is presumed that the leakage current Idss increases when the high-density BPDs 72 including TEDs and TSDs are generated overlapping the breakdown voltage structure. If the high-density BPDs 72 are located between the chip end and the specified position 44, they do not overlap the breakdown voltage structure, so they do not become a factor in increasing the leakage current Idss.

[0048] n +The starting substrate 31 is n + The n-type drain region 1 is an n-type buffer region 2a. The n-type buffer region 2a is formed by recombining minority carriers (holes) generated at the interface of the pn junction 36 when the body diode is conductive with electrons in the n-type buffer region 2a and annihilat- ing them. + The n-type buffer region 2a has a function of preventing the n-type semiconductor layer 1 from reaching the starting substrate 31. + This can suppress the growth of Shockley-type stacking faults in the epitaxial layers 33, 34 starting from the Shockley-type BPDs in the starting substrate 31. The n-type buffer region 2a does not necessarily have to be provided.

[0049] n - The drift region 2b is formed by a p-type base region 4 and an n-type buffer region 2a (or an n-type buffer region 2a if no n-type buffer region 2a is provided). + The p-type base region 4 and the n-type drain region 1 are disposed in contact with each other. - Between the n-type drift region 2b, an n-type current diffusion region 3 and a p-type + Mold regions 21 and 22 may be provided. In this case, n - The n-type drift region 2b is - The n-type epitaxial layer 33 includes an n-type current spreading region 3 and a p-type + The n-type current diffusion region 3 and the p-type regions 21 and 22 are excluded. + The n-type regions 21 and 22 are located closer to the bottom of the trench 7 than the n-type regions 21 and 22. + The trench is provided at a deep position on the drain region 1 side.

[0050] The n-type current spreading region 3 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. + The mold regions 21 and 22 have the function of reducing the electric field applied to the gate insulating film 8 at the bottom of the trench 7. + The p-type region 21 is provided apart from the p-type base region 4 and faces the bottom surface of the trench 7 in the depth direction. + The mold region 21 may reach the bottom surface of the trench 7. +The p-type region 22 is disposed between the adjacent trenches 7. + The trench 7 is provided apart from the p-type region 21 and is in contact with the p-type base region 4 .

[0051] The p-type base region 4 is connected to the front surface of the semiconductor chip 30 and - The p-type base region 4 is provided between the n-type drift region 2b and the p-type epitaxial layer 34. + Type source region 5 and p ++ This is the portion excluding the contact region 6. + Type source region 5 and p ++ The n-type contact region 6 is selectively provided between the front surface of the semiconductor chip 30 and the p-type base region 4. + Type source region 5 and p ++ The p-type contact region 6 is in contact with the p-type base region 4, and is in ohmic contact with an ohmic electrode 13 through a contact hole in an interlayer insulating film 11, which will be described later.

[0052] p ++ The p-type contact region 6, the p-type base region 4 and the p + p-type regions 21 and 22 (in FIG. 4, these p-type regions are collectively referred to as one p + 37) and n-type current spreading region 3, - n-type drift region 2b, n-type buffer region 2a and n + Type drain region 1 (n in Figure 4 + The body diode of the MOSFET is formed by the pn junction 36 and the back electrode 15 (type region 38). When the MOSFET is off, a negative voltage with respect to the front electrode 14 is applied to the back electrode 15, so that a forward current flows through the body diode. For example, this body diode can be used as a free wheeling diode (FWD) for regenerating a current in the opposite direction to the voltage applied by an inverter or the like by passing it through the MOSFET.

[0053] p ++ The contact region 6 may not be provided. ++ When the contact region 6 is not provided,++ Instead of the n-type contact region 6, the p-type base region 4 is in ohmic contact with the ohmic electrode 13. + type area 21,22,n + Type source region 5 and p ++ The contact region 6 is a diffusion region formed by ion implantation and is selectively provided inside the epitaxial layer 35. The trench 7 is + The n-type current diffusion region 3 (or the n-type current diffusion region 3 if the n-type current diffusion region 3 is not provided) penetrates the p-type source region 5 and the p-type base region 4. - The drift region 2b) is reached.

[0054] A gate electrode 9 is provided inside the trench 7 with a gate insulating film 8 interposed therebetween. The gate electrode 9 is electrically connected to a gate pad 61 (see FIGS. 6 and 7) through a gate runner 62 and gate fingers 63. The gate pad 61 is a metal wiring layer provided at the same level as the front surface electrode 14. The gate runner 62 and the gate fingers 63 are conductive layers provided on the front surface of the semiconductor chip 30 with a field oxide film interposed therebetween. The gate runner 62 is provided along the boundary 43 between the active region 41 and the edge termination region 42 on the outer periphery of the active region 41, and surrounds the periphery of the central portion in which the element structure of the active region 41 is provided.

[0055] The gate finger 63 extends, for example, in a straight line passing through the center of the semiconductor chip 30. The interlayer insulating film 11 is provided on the front surface of the semiconductor chip 30 and covers the gate electrode 9. A barrier metal 12 for preventing diffusion of metal atoms of the front surface electrode from the front surface electrode 14 side to the gate electrode 9 side may be provided on the entire surface between the interlayer insulating film 11 and a front surface electrode 14 described later. The ohmic electrode 13 is a silicide film provided on the front surface of the semiconductor chip 30 in a contact hole of the interlayer insulating film 1 ... connected to the p-type base region 4, the n-type base region 5, the p-type base region 6, the n-type base region 7, the n-type base region 8, the n-type base region 9, and the n-type base region 10. + Type source region 5 and p ++ The contact region 6 is electrically connected to the contact area 6 .

[0056] The front surface electrode 14 is provided over substantially the entire front surface of the semiconductor chip 30 in the active region 41 so as to fill the contact hole in the interlayer insulating film 11. The front surface electrode 14 is connected to the p-type base region 4, the n-type + Type source region 5 and p ++ The barrier metal 12, the ohmic electrode 13 and the front surface electrode 14 function as a source electrode. The back surface electrode 15 is electrically connected to the back surface (n + The back surface of the starting substrate 31 is provided on the entire surface of the substrate. + The back electrode 15 is electrically connected to the drain region 1. The back electrode 15 functions as a drain electrode.

[0057] Next, a method for manufacturing a silicon carbide semiconductor device 10 according to an embodiment will be described. FIG. 5 is a flow chart showing an outline of the method for manufacturing a silicon carbide semiconductor device according to an embodiment. FIGS. 6 and 7 are explanatory diagrams showing the shapes of crystal defects detected in the process of step S3 in FIG. 5. FIGS. 6 and 7 show, among a plurality of chip regions 51 formed on a semiconductor wafer 50, a chip region 51a in which stacking faults 71 accompanied by high-density BPDs 72 have been generated, and a chip region 51b to which high-density BPDs 72 have propagated from the adjacent chip region 51a. FIGS. 6 and 7 show the cases in which the chip region 51b is a non-defective product and a defective product, respectively.

[0058] First, a semiconductor wafer (SiC wafer) 50 using silicon carbide as a semiconductor material is prepared (step S1: pre-process). The semiconductor wafer 50 is a starting wafer made of silicon carbide (n in FIG. 3). + The semiconductor wafer 50 is formed by epitaxially growing an epitaxial layer (corresponding to epitaxial layer 35 in FIG. 3) on a mold starting substrate 31. In the process of step S1, a starting wafer made of silicon carbide may be prepared to fabricate the semiconductor wafer 50, or the semiconductor wafer 50 itself may be purchased. Next, a position specifying mark (not shown) is formed on the main surface of the semiconductor wafer 50 (the surface on the epitaxial layer 35 side) (step S2).

[0059] In the process of step S2, position specifying marks (not shown) are formed on the main surface of the semiconductor wafer 50 within the dicing lines 52 by photolithography and etching. The position specifying marks serve as a reference for specifying the positions (coordinates in a direction parallel to the wafer surface) of crystal defects in the semiconductor wafer 50. If the dicing lines 52 are not formed on the semiconductor wafer 50 prepared in the process of step S1, the dicing lines 52 (see FIG. 1) may be formed on the main surface of the semiconductor wafer 50 by photolithography and etching after the process of step S1 and before the process of step S2.

[0060] Next, the size (length, surface area, etc.) and position information of triangular polytype stacking faults 71 and high density BPDs 72 associated with stacking faults 71 inside epitaxial layer 35 are detected using a PL image of semiconductor wafer 50 obtained by a crystal defect inspection device (step S3: detection step). In the process of step S3, after stacking faults 71 appearing on the surface of semiconductor wafer 50 are detected using a DIC image of semiconductor wafer 50 obtained by a crystal defect inspection device, size and position information of high density BPDs 72 around stacking faults 71 may be obtained using a PL image. The size and position information of the crystal defects may be obtained based on the position identification mark.

[0061] Next, various processes are performed to form a predetermined element structure (see, for example, FIG. 3) in each chip region 51 of the semiconductor wafer 50 (step S4: forming step). At this time, it is not necessary to form an element structure in the chip region 51 that will become a defective chip after the processing of step S6 described later. Next, the semiconductor wafer 50 is cut (diced) along dicing lines 52 (thick lines) to separate each chip region 51 into individual semiconductor chips 30 (SiC chips: see FIG. 2) (step S5: cutting step). Next, semiconductor chips 30 that are candidates for non-defective products are selected based on the information acquired in the processing of step S3 (step S6: first selection step).

[0062] Specifically, in the process of step S6, a semiconductor chip 30 that satisfies both of the following two conditions (the two above-mentioned standards for good products) is selected as a good product candidate. The first condition is that the semiconductor chip 30 does not contain triangular polytype stacking faults 71. The second condition is that high-density BPDs 72 do not invade (propagate) from the adjacent chip region 51a (not shown), or that high-density BPDs 72 that invade from the adjacent chip region 51a terminate between the chip end and the specified position 44 (chip region 51b in FIG. 6). The limit position for the growth of Shockley-type stacking faults, which depends on the amount of holes injected into the high-density BPDs 72, is obtained in advance according to the element structure and set as the specified position 44.

[0063] A semiconductor chip 30 that includes a triangular polytype stacking fault 71 (chip region 51a) or has high-density BPDs 72 penetrating from an adjacent chip region 51a to the inside of the specified position 44 (chip region 51b in FIG. 7), or both, is removed as a defective chip. For this reason, in the process of step S3, the position of the chip region 51a that includes the triangular polytype stacking fault 71 and the end position of the high-density BPDs 72 that extend from the stacking fault 71 in the chip region 51a to the adjacent chip region 51b are obtained. A chip region 51b (see FIG. 6) that does not include a triangular polytype stacking fault 71 and does not include high-density BPDs 72 on the inside of the specified position 44 is a candidate semiconductor chip 30 for a non-defective product.

[0064] Next, electrical characteristics such as on-voltage characteristics, withstand voltage characteristics, and leakage current characteristics are inspected for each semiconductor chip 30 that is determined to be a good product candidate by a general reliability test (step S7: inspection step). In the process of step S7, various other tests may be performed to confirm or evaluate conditions that do not affect the withstand voltage or reliability. The process of step S7 and other tests may be performed after the process of step S5 and before the process of step S6, if there is no problem in performing them in the state of the semiconductor wafer 50. Next, the semiconductor chips 30 that are good products (good chips) are selected based on the results of step S7 (step S8: second selection step), thereby completing the silicon carbide semiconductor device 10.

[0065] In the method for manufacturing the silicon carbide semiconductor device 10 according to the embodiment described above, the processes of steps S7 and S8 may be omitted, and the semiconductor chip 30 selected in the process of step S6 may be regarded as a non-defective product. + When forming the mold regions 21 and 22, n - n-type drift region 2b - After epitaxial growth of the p-type epitaxial layer 33, and before epitaxial growth of the p-type epitaxial layer 34 that will become the p-type base region 4, n - They may be selectively formed inside the type epitaxial layer 33 .

[0066] The method for manufacturing the silicon carbide semiconductor device 10 described in this embodiment can be realized by executing a previously prepared program on a computer such as a personal computer or a workstation, or on a database server or a web server. The size and position information of the crystal defect acquired by the program or the process of step S3 is recorded on a computer-readable recording medium such as a solid state drive (SSD), a hard disk, a Blu-ray (registered trademark) Disc (BD), a flexible disk, a USB flash memory, a CD-ROM, an MO, or a DVD, and is executed by being read from the recording medium by a computer or a server. The program may also be a transmission medium that can be distributed via a network such as the Internet.

[0067] As described above, according to the embodiment, triangular polytype stacking faults and high density BPDs generated in the epitaxial layer of a semiconductor wafer are detected by a PL image of a crystal defect inspection device. A position that is horizontally outward from the boundary between the active region and the edge termination region by a distance of about 60% of the length of the edge termination region is acquired in advance as a specified position. Then, a semiconductor chip that does not include triangular polytype stacking faults and does not include high density BPDs inside the specified position (active region and breakdown voltage structure) is determined to be a good product (or a candidate for a good product). A semiconductor chip that is determined to be a good product may include high density BPDs outside the specified position.

[0068] This makes it possible to prevent semiconductor chips that contain high-density BPDs and may reduce reliability from being released onto the market. This improves reliability compared to the conventional method (see FIG. 11(a)) that uses DIC images to detect only surface abnormalities (surface irregularities). Furthermore, by setting a range (inside a specified position) that must not contain high-density BPDs, semiconductor chips that can obtain the specified characteristics even if they contain high-density BPDs can be selected as non-defective products. This improves yield compared to the conventional method (see FIG. 11(b)) that removes all semiconductor chips that contain high-density BPDs.

[0069] Furthermore, according to the embodiment, the range (prescribed position) that should not contain high-density BPDs can be set appropriately according to the element structure, so that application to an existing element structure does not require design changes to the existing element structure.

[0070] (Experimental Example) The horizontal distance w2 (hereinafter referred to as hole diffusion distance) between the boundary 43 between the active region 41 and the edge termination region 42 and the limit position (prescribed position 44) reached at a high enough hole density that the hole current flowing outward from the pn junction 36 of the active region 41 during body diode conduction contributes to the growth of Shockley stacking faults. FIG. 8 is a chart showing the results of measuring the hole diffusion distance in an experimental example. FIG. 9 is a chart showing the results of calculating the ratio of the hole diffusion distance in an experimental example. FIG. 8 shows the results of measuring the hole diffusion distance w2 of a MOSFET (hereinafter referred to as an experimental example) having the structure of the silicon carbide semiconductor device 10 (see FIGS. 2 to 4) according to the embodiment described above.

[0071] As experimental examples, multiple samples (hereinafter referred to as samples 1 to 5) with different combinations of withstand voltage and body diode current-carrying conditions were prepared. The withstand voltage of samples 1 and 2 was 1.2 kV, the withstand voltage of sample 3 was 1.7 kV, and the withstand voltage of samples 4 and 5 was 3.3 kV. Samples with the same withstand voltage (samples 1 and 2, and samples 4 and 5) were compared using n - The thickness t1 of the drift region 2b is equal to that of the current pulse 36. The forward current (height of the current pulse), junction temperature (heat generation temperature near the pn junction 36), duty ratio (ratio of the off time to the on time of the current pulse), and current flow time during body diode conduction were set for the samples 1 to 5, as shown in FIG.

[0072] From the results of Samples 4 and 5 shown in Figure 8, it was confirmed that, regardless of the body diode current-carrying conditions (forward current, junction temperature, duty ratio, and current-carrying time), if the breakdown voltage is the same, the length w1 of the edge termination region 42 is almost the same, and therefore the hole diffusion distance w2 is almost the same. Also, from the results of Samples 1 to 5 shown in Figure 8, it was confirmed that the hole diffusion distance w2 is n - depends on the thickness t1 of the drift region 2b, n - It has been confirmed that the hole diffusion distance w2 increases as the thickness t1 of the drift region 2b increases. In other words, the hole diffusion distance w2 is n - It depends on the thickness t1 of the drift region 2b, the rated voltage, and the breakdown voltage structure.

[0073] FIG. 9 shows the results of calculating the ratio (=w2 / w1) of hole diffusion distance w2 to length w1 of edge termination region 42 for samples 1, 3, and 4 of the experimental example. The results for samples 2 and 5 are almost the same as those for samples 1 and 4. From the results shown in FIG. 9, it was confirmed that in all of samples 1 to 5, hole diffusion distance w2 is about 60% of length w1 of edge termination region 42 in the horizontal direction from boundary 43 between active region 41 and edge termination region 42. Therefore, it was confirmed that if hole diffusion distance w2 for setting specified position 44 is about 60% of length w1 of edge termination region 42, Shockley type stacking faults starting from high density BPD72 do not grow outside specified position 44.

[0074] Further, the range in which Shockley stacking faults grow was examined for Samples 2 to 5 of the experimental example. FIG. 10 is an explanatory diagram that shows a schematic view of the range in which Shockley stacking faults grow in the experimental example, observed from the front surface side of the semiconductor chip. In FIG. 10, the boundary 43 between the active region 41 and the edge termination region 42 is shown by a fine dashed line, and the specified position 44 is shown by a coarse dashed line. Reference numerals 61, 63, and 64 respectively denote a gate pad, a gate finger, and an electrode pad for measuring gate resistance. In FIG. 10, the gate runner 62 (see FIGS. 6 and 7) is omitted. The chip sizes (size of the semiconductor chip 30) of Samples 2 to 5 are different from each other.

[0075] Shockley stacking faults 91 (hatched areas) grown by body diode conduction in Samples 2 to 5 of the experimental example are shown in PL images observed by a crystal defect inspection device in (b), (a), (c), and (d) of FIG. 10, respectively. From the results shown in FIG. 10, it was confirmed that in all of Samples 2 to 5, Shockley stacking faults 91 grow outward from active region 41 beyond boundary 43 between active region 41 and edge termination region 42, and terminate at a predetermined position within edge termination region 42. It is presumed that the amount of hole injection required for the growth of Shockley stacking faults 91 is restricted by the distance in the horizontal direction (growth direction) or the device structure of active region 41.

[0076] Therefore, the position where the growth of Shockley type stacking faults 91 terminates in the edge termination region 42 is acquired in advance and set as the specified position 44. For chip region 51b into which high density BPDs 72 have invaded from adjacent chip region 51a (chip region 51 in which triangular polytype stacking faults have been generated), the termination position of the high density BPDs 72 is detected by a PL image of a crystal defect inspection device. If the high density BPDs 72 terminate between the chip end and the specified position 44, Shockley type stacking faults 91 starting from the high density BPDs 72 do not grow, and it has been confirmed that this chip region 51b can be determined as a non-defective product (see FIG. 6).

[0077] The present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention may be applied to a Schottky Barrier Diode (SBD), a pin (p-intrinsic-n) diode, or an IGBT (Insulated Gate Bipolar Transistor). The present invention is also applicable when the conductivity type (n-type, p-type) is reversed. [Industrial Applicability]

[0078] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device and the method for manufacturing a silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and are particularly suitable for SiC-MOSFETs. [Explanation of symbols]

[0079] 1n + Type drain region 2a n-type buffer region 2b n - Type Drift Region 3 n-type current diffusion region 4 p-type base region 5n + Type Source Area 6 p ++ Mold Contact Area 7. Trench 8 Gate insulating film 9 Gate electrode 10 Silicon carbide semiconductor device 11 Interlayer insulating film 12 Barrier metal 13 Ohmic electrode 14 Front electrode 15 Back electrode 21,22 p + type area 30 Semiconductor Chips 31 n + Starting substrate 32 n-type epitaxial layer 33n - Type epitaxial layer 34 p-type epitaxial layer 35 Epitaxial layer 41 Active area 42 Edge Termination Area 43 Boundary between active area and edge termination area 44 Defined position 50 Semiconductor Wafers 51, 51a, 51b Chip area of ​​semiconductor wafer 52 Semiconductor wafer dicing line 53 Ineffective Area of ​​Semiconductor Wafer 61 Gate Pad 62 Gate Runner 63 Gate Finger 64 Electrode pad for gate resistance measurement 71 Polytype triangular stacking faults 72 High density BPD w1 Length of edge termination area w2 hole diffusion length t1 n - Mold drift region thickness

Claims

1. A method for manufacturing a vertical silicon carbide semiconductor device, comprising the steps of: epitaxially growing an epitaxial layer on a starting substrate made of silicon carbide; forming a semiconductor chip having electrodes on both main surfaces of the semiconductor chip; a front-end process of preparing a semiconductor wafer by epitaxially growing the epitaxial layer on a starting wafer made of silicon carbide that serves as the starting substrate; a detection step of detecting crystal defects in the epitaxial layer; forming a predetermined element structure on the semiconductor wafer; a cutting step of dicing the semiconductor wafer into individual semiconductor chips after the forming step; a first sorting step of sorting out predetermined semiconductor chips as non-defective products based on a result of the detection step; Including, The semiconductor chip comprises: an active region in which the element structure is provided; a termination region surrounding the active region; a pn junction formed within the epitaxial layer to form a main junction of the device structure; In the detection step, stacking faults and BPDs extending from the stacking faults are detected in the epitaxial layer, In the first selection step, the semiconductor chips that do not include the stacking faults and do not include the BPDs inside a predetermined position in the termination region that has been previously acquired are selected as non-defective products; a boundary between the active region and the termination region being an outer edge of the pn junction; a first insulating layer formed on the first substrate and a second insulating layer formed on the second substrate, the second insulating layer being spaced apart from the first insulating layer and extending in a direction parallel to a main surface of the semiconductor chip;

2. A method for manufacturing a vertical silicon carbide semiconductor device, comprising the steps of: epitaxially growing an epitaxial layer on a starting substrate made of silicon carbide; forming a semiconductor chip having electrodes on both main surfaces of the semiconductor chip; a front-end process of preparing a semiconductor wafer by epitaxially growing the epitaxial layer on a starting wafer made of silicon carbide that serves as the starting substrate; a detection step of detecting crystal defects in the epitaxial layer; forming a predetermined element structure on the semiconductor wafer; a cutting step of dicing the semiconductor wafer into individual semiconductor chips after the forming step; a first sorting step of sorting out predetermined semiconductor chips as non-defective products based on a result of the detection step; Including, The semiconductor chip comprises: an active region in which the element structure is provided; a termination region surrounding the active region; a pn junction formed within the epitaxial layer to form a main junction of the device structure; In the detection step, stacking faults and BPDs extending from the stacking faults are detected in the epitaxial layer, In the first selection step, the semiconductor chips that do not include the stacking faults and do not include the BPDs inside a predetermined position in the termination region that has been previously acquired are selected as non-defective products; the specified position is a limit position reached by a hole current flowing toward the starting substrate so as to spread outward from the pn junction when a diode formed by the pn junction is conductive, with a hole density that contributes to growth of Shockley stacking faults originating from the BPD.

3. In the detection step, the location of the triangular stacking faults of polytype generated during epitaxial growth of the epitaxial layer; 3 . The method for manufacturing a silicon carbide semiconductor device according to claim 1 , further comprising the steps of: detecting a termination position of the BPD extending from the stacking fault;

4. The semiconductor wafer has a plurality of adjacent chip regions that will become the semiconductor chips after the cutting step, In the first selection step, the semiconductor chip obtained by singulating the chip region that does not include the stacking faults and the BPDs; the semiconductor chip being obtained by singulating the chip region that does not include the stacking fault and in which the BPD intruding from the adjacent chip region terminates outside the specified position; 4. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising selecting as a non-defective product any one of the silicon carbide semiconductor devices that is formed by the above-mentioned steps.

5. A method for manufacturing a silicon carbide semiconductor device described in any one of claims 1 to 4, characterized in that in the detection process, the crystal defects are detected by a photoluminescence image of the semiconductor wafer.

6. An inspection process for inspecting electrical characteristics of the semiconductor chips selected in the first sorting process; a second sorting step of further sorting the semiconductor chips that satisfy predetermined characteristics from the semiconductor chips sorted in the first sorting step based on a result of the inspection step; The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 5, further comprising:

7. A method for manufacturing a silicon carbide semiconductor device described in any one of claims 1 to 6, characterized in that in the formation process, a voltage-resistant structure is formed between the boundary between the active region and the termination region and the specified position.

8. A vertical silicon carbide semiconductor device having electrodes on both main surfaces of a semiconductor chip formed by epitaxially growing an epitaxial layer on a starting substrate made of silicon carbide, an active region provided on the semiconductor chip; a termination region provided on the semiconductor chip and surrounding the active region; A predetermined element structure provided in the active region; Equipped with The semiconductor chip comprises: a pn junction forming a main junction of the element structure is provided inside the epitaxial layer; does not contain triangular stacking faults of polytype generated in said epitaxial layer during epitaxial growth; and does not include BPDs extending from the stacking faults during epitaxial growth and generated between the stacking faults and perfect crystals on the inner side of a specified position in the termination region, the boundary between the active region and the termination region is an outer edge of the pn junction; a first region formed on said first terminal of said first electrode and a second region formed on said second terminal of said first electrode; a second region formed on said first terminal of said first electrode and a second region formed on said second terminal of said first electrode;

9. A vertical silicon carbide semiconductor device having electrodes on both main surfaces of a semiconductor chip formed by epitaxially growing an epitaxial layer on a starting substrate made of silicon carbide, an active region provided on the semiconductor chip; a termination region provided on the semiconductor chip and surrounding the active region; A predetermined element structure provided in the active region; Equipped with The semiconductor chip comprises: a pn junction forming a main junction of the element structure is provided inside the epitaxial layer; does not contain triangular stacking faults of polytype generated in said epitaxial layer during epitaxial growth; and does not include BPDs extending from the stacking faults during epitaxial growth and generated between the stacking faults and perfect crystals on the inner side of a specified position in the termination region, the specified position is a limit position reached by a hole current flowing toward the starting substrate so as to spread outward from the pn junction when a diode formed by the pn junction is conductive, with a hole density that contributes to the growth of Shockley stacking faults originating from the BPDs.

10. A silicon carbide semiconductor device as described in claim 8 or 9, characterized in that the semiconductor chip includes the BPD outside the specified position.

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