Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device and a manufacturing method for the same.SOLUTION: A semiconductor device includes a channel layer, a channel supply layer provided on the channel layer, a channel separation pattern provided on the channel supply layer, a gate electrode pattern provided on the channel separation pattern, and an electric field relieving pattern that protrudes along a first direction parallel to an upper surface of the channel layer from a first side surface of the gate electrode pattern. The channel layer includes a channel formed adjacent to an interface between the channel layer and the channel supply layer. The size of the gate electrode pattern along the first direction is different from the size of the channel separation pattern along the first direction. The gate electrode pattern and the electric field relieving pattern form a single structure.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] High electron mobility transistors (HEMs) are a type of power semiconductor device. These transistors have a heterojunction structure in which semiconductor material layers with different bandgaps are adjacent to each other. By forming the heterojunction structure using materials with different bandgaps, a two-dimensional electron gas (2DEG) layer is induced in the semiconductor material layer with a smaller bandgap, which can improve the electron mobility. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved by the present invention is to provide a semiconductor device with improved electrical characteristics.

[0004] Another problem to be solved by the present invention is to provide a method for manufacturing a semiconductor device with improved electrical characteristics.

[0005] Another object of the present invention is to provide a method for manufacturing a semiconductor device with improved process efficiency.

[0006] However, the problem to be solved by the present invention is not limited to the above disclosure. [Means for solving the problem]

[0007] In one aspect, a semiconductor device may be provided that includes a channel layer, a channel supply layer provided on the channel layer, a channel separation pattern provided on the channel supply layer, a gate electrode pattern provided on the channel separation pattern, and an electric field relaxation pattern protruding from a first side of the gate electrode pattern along a first direction parallel to an upper surface of the channel layer, wherein the channel layer includes a channel formed adjacent to an interface between the channel layer and the channel supply layer, and the size of the gate electrode pattern along the first direction is different from the size of the channel separation pattern along the first direction, and the gate electrode pattern and the electric field relaxation pattern form a single structure.

[0008] The size of the gate electrode pattern along the first direction is smaller than the size of the channel isolation pattern along the first direction.

[0009] The gate electrode pattern may expose a first upper surface of the channel isolation pattern, and the first upper surface of the channel isolation pattern may face a bottom surface of the electric field relaxation pattern.

[0010] The size of the bottom surface of the electric field relaxation pattern along the first direction is greater than the size of the first upper surface of the channel separation pattern along the first direction.

[0011] The gate electrode pattern exposes a second upper surface of the channel isolation pattern, the first and second upper surfaces of the channel isolation pattern are spaced apart from each other along a first direction, and the size of the first upper surface of the channel isolation pattern along the first direction is also different from the size of the second upper surface of the channel isolation pattern along the first direction.

[0012] The semiconductor device may further include a first passivation film provided between the electric field relaxation pattern and the channel supply layer, the channel isolation pattern being provided between the first passivation film and the channel supply layer, and the gate electrode pattern penetrating the first passivation film and directly contacting the channel isolation pattern.

[0013] The semiconductor device may further include a first passivation pattern provided between the first passivation film and the channel isolation pattern, and the first passivation film and the first passivation pattern may include different insulating materials.

[0014] The first passivation film may include a nitride, and the first passivation pattern may include an oxide.

[0015] A first passivation pattern is also provided on a first side of the gate electrode pattern.

[0016] The gate electrode pattern may further include a second passivation pattern provided on a second side of the gate electrode pattern opposite to the first side of the gate electrode pattern, and the second passivation pattern may also be provided between the first passivation film and the channel isolation pattern.

[0017] One side of the first passivation pattern and one side of the channel isolation pattern that are immediately adjacent to each other may be coplanar with each other, and one side of the second passivation pattern and the other side of the channel isolation pattern that are immediately adjacent to each other may be coplanar with each other.

[0018] The semiconductor device further includes a drain electrode pattern spaced apart from the gate electrode pattern in the first direction, a source electrode pattern provided on an opposite side of the drain electrode pattern with respect to the gate electrode pattern, and a second auxiliary drain electrode pattern protruding from a side of the drain electrode pattern, wherein the second auxiliary drain electrode pattern is also provided on the first passivation film.

[0019] The semiconductor device may further include a second passivation film provided between the first passivation film and the electric field relaxation pattern, and an additional electric field relaxation pattern provided between the second passivation film and the first passivation film, wherein the additional electric field relaxation pattern is provided between the gate electrode pattern and the second auxiliary drain electrode pattern, and the gate electrode pattern may penetrate the second passivation film and the first passivation film and be in direct contact with the channel isolation pattern.

[0020] The semiconductor device may further include a third passivation film provided on the gate electrode pattern, the electric field relaxation pattern, and the second passivation film, an additional electric field relaxation film provided on the third passivation film, and a first auxiliary drain electrode pattern provided on the third passivation film, wherein the additional electric field relaxation film is electrically connected to the source electrode pattern, the first auxiliary drain electrode pattern is electrically connected to the drain electrode pattern, and the additional electric field relaxation film and the first auxiliary drain electrode pattern may be spaced apart from each other.

[0021] The semiconductor device may further include a first passivation pattern provided between the first passivation film and the channel isolation pattern, and a second passivation pattern provided on an opposite side of the first passivation pattern with respect to the gate electrode pattern, wherein the first passivation film and the first passivation pattern may include different insulating materials, and the first passivation pattern and the second passivation pattern may include the same material.

[0022] The first passivation film may include a nitride, and the first passivation pattern and the second passivation pattern may include an oxide.

[0023] The semiconductor device further includes a second passivation film provided on the first passivation film and on the gate electrode pattern, a drain electrode pattern spaced apart from the gate electrode pattern along a first direction, a source electrode pattern provided on the opposite side of the drain electrode pattern with respect to the gate electrode pattern, an additional field relaxation film provided on the second passivation film, and a first auxiliary drain electrode pattern provided on the drain electrode pattern, wherein the field relaxation pattern is disposed between the second passivation film and the first passivation film, the additional field relaxation film overlaps the source electrode pattern along a second direction perpendicular to the top surface of the channel layer, the additional field relaxation film is electrically connected to the source electrode pattern, and the first auxiliary drain electrode pattern is also electrically connected to the drain electrode.

[0024] The gate electrode pattern may further include a protruding pattern protruding from a second side of the gate electrode pattern disposed opposite to the first side of the gate electrode pattern, and the protruding pattern and the gate electrode pattern may form a single structure.

[0025] The size of the electric field relaxation pattern along the first direction is greater than the size of the protruding pattern along the first direction.

[0026] The size of the channel separation pattern along the first direction decreases as the pattern becomes farther from the channel supply layer.

[0027] The size of the gate electrode pattern in the first direction increases as the gate electrode pattern is farther from the channel supply layer.

[0028] The semiconductor device may further include a first passivation film provided between the electric field relaxation pattern and the channel supply layer, a drain electrode pattern spaced apart from the gate electrode pattern along the first direction, and a source electrode pattern provided on the opposite side of the drain electrode pattern with respect to the gate electrode pattern, wherein the source electrode pattern and the drain electrode pattern may penetrate the first passivation film and the channel supply layer and contact the channel.

[0029] In one aspect, a method for manufacturing a semiconductor device may be provided, including the steps of sequentially forming a channel supply layer and a channel isolation pattern on a channel layer, forming a first passivation film on the channel supply layer and the channel isolation pattern, forming an opening in the first passivation film to expose an upper surface of the channel isolation pattern, and forming a conductive material pattern on the channel isolation pattern, wherein the channel layer includes a channel formed adjacent to an interface between the channel layer and the channel supply layer, and the conductive material pattern extends from inside to outside the opening.

[0030] The opening can expose a portion of the top surface of the channel separation pattern.

[0031] The distance between the opening and one side surface of the channel separation pattern is different from the distance between the opening and the other side surface of the channel separation pattern.

[0032] The width of the opening is narrower as it comes closer to the channel separation pattern, and the width of the opening is also the size of the opening along a first direction parallel to the top surface of the channel layer.

[0033] Forming the conductive material pattern may include forming a conductive material film extending along an upper surface of the first passivation film and filling the opening, and patterning the conductive material film, wherein the conductive material pattern may include a gate electrode pattern extending in a second direction perpendicular to the upper surface of the channel layer and overlapping the opening, and an electric field relaxation pattern protruding from a first side of the gate electrode pattern.

[0034] The conductive material pattern further includes a protruding pattern protruding from a second side of the gate electrode pattern, and the conductive material film is patterned so that the electric field relaxation pattern and the protruding pattern have different lengths, and the lengths of the electric field relaxation pattern and the protruding pattern are also the sizes of the electric field relaxation pattern and the protruding pattern, respectively, along a first direction parallel to the top surface of the channel layer.

[0035] The method may further include the steps of: forming a second passivation film on the first passivation film and on the conductive material pattern; forming a source electrode pattern and a drain electrode pattern penetrating the second passivation film, the first passivation film, and the channel supply layer; and forming a second auxiliary drain electrode pattern protruding from a side of the drain electrode pattern between the first passivation film and the second passivation film, wherein the source electrode pattern and the drain electrode pattern may be spaced apart with the conductive material pattern interposed therebetween.

[0036] The method may further include forming an additional electric field mitigation film on the second passivation film, the additional electric field mitigation film also being electrically connected to the source electrode pattern.

[0037] The formation of the additional electric field mitigation film may include the steps of: forming a preliminary additional electric field mitigation film on the source electrode pattern along an upper surface of the second passivation film and extending onto the drain electrode pattern; and patterning the preliminary additional electric field mitigation film to expose an upper surface of the second passivation film between the conductive material pattern and the drain electrode pattern.

[0038] The distance between the additional electric field mitigating film and the drain electrode pattern is shorter than the distance between the conductive material pattern and the drain electrode pattern.

[0039] By patterning the preliminary additional electric field relaxation film, an auxiliary drain electrode pattern can be formed on the drain electrode pattern.

[0040] The method further includes the steps of forming a source electrode pattern and a drain electrode pattern penetrating the first passivation film and the channel supply layer, forming an additional electric field relaxation pattern on the first passivation film, forming a second auxiliary drain electrode pattern protruding from a side of the drain electrode pattern onto the first passivation film, and forming a second passivation film on the additional electric field relaxation pattern, the second auxiliary drain electrode pattern, and the first passivation film, wherein the source electrode pattern and the drain electrode pattern are spaced apart from each other with a channel separation pattern therebetween, and the opening penetrates the second passivation film and the first passivation film to expose an upper surface of the channel separation pattern.

[0041] The method further includes the steps of forming a third passivation film on the second passivation film and the conductive material pattern, and forming an additional electric field mitigating film and a first auxiliary drain electrode pattern on the third passivation film, but the formation of the additional electric field mitigating film and the first auxiliary drain electrode pattern includes the steps of forming a preliminary additional electric field mitigating film on the source electrode pattern along the upper surface of the third passivation film and extending onto the drain electrode pattern, and patterning the preliminary additional electric field mitigating film to expose the upper surface of the third passivation film between the conductive material pattern and the drain electrode pattern, and the additional electric field mitigating film is electrically connected to the source electrode pattern, and the first auxiliary drain electrode pattern is also electrically connected to the drain electrode pattern.

[0042] The method may further include forming a passivation pattern on the channel isolation pattern before performing the first passivation film forming process, wherein the passivation pattern has an etch selectivity with respect to the channel isolation pattern, and the first passivation film has an etch selectivity with respect to the passivation pattern.

[0043] Forming the opening may include performing a first selective etching process on the first passivation film to expose an upper surface of the passivation pattern, and performing a second selective etching process on the passivation pattern to expose an upper surface of the channel isolation pattern.

[0044] The first passivation film may include a nitride, and the passivation pattern may include an oxide.

[0045] In one aspect, a semiconductor device may be provided, including a semiconductor layer, a p-type semiconductor pattern provided on the semiconductor layer, a conductive material pattern provided on the p-type semiconductor pattern, and a source electrode pattern and a drain electrode pattern spaced apart from each other along a direction parallel to an upper surface of the semiconductor layer and sandwiching the conductive material pattern, wherein a width of a lower portion of the conductive material pattern is different from a width of the p-type semiconductor pattern and a width of an upper portion of the conductive material pattern is wider than the width of the lower portion of the conductive material pattern, the semiconductor layer includes a two-dimensional electron gas (2DEG) layer, and the two-dimensional electron gas (2DEG) layer has a depletion region below the p-type semiconductor pattern.

[0046] The width of the bottom of the conductive material pattern is narrower than the width of the p-type semiconductor pattern.

[0047] The distance between the top of the conductive material pattern and the drain electrode pattern is shorter than the distance between the bottom of the conductive material pattern and the drain electrode pattern.

[0048] The distance between the top of the conductive material pattern and the drain electrode pattern is shorter than the distance between the p-type semiconductor pattern and the drain electrode pattern.

[0049] The width of the top of the conductive material pattern is wider than the width of the p-type semiconductor pattern.

[0050] The semiconductor device may further include an additional electric field mitigation film provided on the conductive material pattern, and the distance between the additional electric field mitigation film and the drain electrode pattern is shorter than the distance between an upper portion of the conductive material pattern and the drain electrode pattern.

[0051] The semiconductor device may further include an auxiliary drain electrode pattern protruding from a side of the drain electrode pattern toward the conductive material pattern, and an additional electric field relaxation pattern provided between the conductive material pattern and the auxiliary drain electrode pattern.

[0052] The distance between the top of the conductive material pattern and the source electrode pattern is shorter than the distance between the bottom of the conductive material pattern and the source electrode pattern.

[0053] The upper portion of the conductive material pattern includes an electric field relaxation pattern protruding from a first side of the lower portion of the conductive material pattern toward the drain electrode pattern, and a protruding pattern protruding from a second side of the lower portion of the conductive material pattern toward the source electrode pattern, and the width of the electric field relaxation pattern is wider than the width of the protruding pattern.

[0054] The semiconductor device may further include a first passivation pattern and a second passivation pattern provided on a first upper surface and a second upper surface of the p-type semiconductor pattern exposed by the conductive material pattern, respectively, and the first passivation pattern and the second passivation pattern may be spaced apart from each other with the conductive material pattern therebetween. [Effects of the Invention]

[0055] The present disclosure can provide a semiconductor device with improved electrical characteristics.

[0056] The present disclosure can provide a method for manufacturing a semiconductor device with improved electrical characteristics.

[0057] The present disclosure can provide a method for manufacturing a semiconductor device with improved process efficiency.

[0058] However, the effects of the present invention are not limited to the above disclosure. [Brief explanation of the drawings]

[0059] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 2] 2A to 2C are cross-sectional views for explaining a method for manufacturing the semiconductor device of FIG. [Figure 3] 2A to 2C are cross-sectional views for explaining a method for manufacturing the semiconductor device of FIG. [Figure 4] 2A to 2C are cross-sectional views for explaining a method for manufacturing the semiconductor device of FIG. [Figure 5] 2A to 2C are cross-sectional views for explaining a method for manufacturing the semiconductor device of FIG. [Figure 6] 2A to 2C are cross-sectional views for explaining a method for manufacturing the semiconductor device of FIG. [Figure 7] 2A to 2C are cross-sectional views for explaining a method for manufacturing the semiconductor device of FIG. [Figure 8] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 9] 9A to 9C are cross-sectional views for explaining a method for manufacturing the semiconductor device of FIG. 8. [Figure 10] 9A to 9C are cross-sectional views for explaining a method for manufacturing the semiconductor device of FIG. 8. [Figure 11] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 12] 12A to 12C are cross-sectional views for explaining a method for manufacturing the semiconductor device of FIG. [Figure 13] 12A to 12C are cross-sectional views for explaining a method for manufacturing the semiconductor device of FIG. [Figure 14] 12A to 12C are cross-sectional views for explaining a method for manufacturing the semiconductor device of FIG. [Figure 15] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 16] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 17]1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 18] FIG. 18 is an enlarged view of a portion AA in FIG. 17. [Figure 19] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 20] 20A and 20B are cross-sectional views for explaining a method for manufacturing the semiconductor device of FIG. 19. [Figure 21] 20A and 20B are cross-sectional views for explaining a method for manufacturing the semiconductor device of FIG. 19. [Figure 22] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 23] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0060] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0061] In the following drawings, the same reference numerals refer to the same elements, and the size of each element may be exaggerated in the drawings for clarity and convenience of explanation. Meanwhile, the embodiments described below are merely examples, and various modifications are possible from such embodiments.

[0062] In the following description, the terms "upper" and "above" may include not only something that is directly above in contact with something, but also something that is above without contacting something.

[0063] The singular expression includes the plural expression unless the context clearly indicates otherwise. Furthermore, when a part "comprises" a certain element, it does not mean that it excludes other elements, but that it may further include other elements, unless otherwise specified to the contrary.

[0064] Furthermore, terms such as "... unit" used in the specification refer to a unit that processes at least one function or operation, and may be embodied by hardware or software, or by a combination of hardware and software.

[0065] FIG. 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0066] Referring to FIG. 1 , a semiconductor device 10 may be provided. The semiconductor device 10 may be a power semiconductor device. For example, the semiconductor device 10 may be a high electron mobility transistor (HEMT). The semiconductor device 10 may include a channel layer 110, a channel supply layer 120, a channel isolation pattern 200, a first passivation film 410, a conductive material pattern 300, a second passivation film 420, a source electrode pattern 510, a drain electrode pattern 520, an additional field reduction film 610, and a first auxiliary drain electrode pattern 700. The channel layer 110 may include a III-V compound semiconductor. For example, the channel layer 110 may include GaN.

[0067] The channel supply layer 120 may be a semiconductor layer different from the channel layer 110. The channel supply layer 120 may form a two-dimensional electron gas (2DEG) layer 130 in the channel layer 110. For example, the two-dimensional electron gas (2DEG) layer 130 also serves as the channel of the semiconductor device 10. The two-dimensional electron gas (2DEG) layer 130 may also be formed in the channel layer 110 adjacent to the interface between the channel supply layer 120 and the channel layer 110. For example, the two-dimensional electron gas (2DEG) layer 130 extends in a first direction D1 parallel to the top surface of the channel layer 110. The channel supply layer 120 may differ from the channel layer 110 in at least one of polarization characteristics, energy band gap, and lattice constant. The channel supply layer 120 may include one or more materials selected from nitrides containing at least one of Al, Ga, In, and B. For example, the channel supply layer 120 may include at least one of AlGaN, AlInN, InGaN, AlN, and AlInGaN. The channel supply layer 120 may have a single-layer structure or a multi-layer structure.

[0068] A channel isolation pattern 200 may be provided on the channel supply layer 120. The channel isolation pattern 200 may enhance the energy band of a portion of the channel supply layer 120 thereunder. A depletion region (not shown) may be formed in the two-dimensional electron gas (2DEG) layer 130 under the channel isolation pattern 200. The two-dimensional electron gas (2DEG) layer 130 may be cut off in a region adjacent to the channel isolation pattern 200 by the depletion region. This allows the semiconductor device 10 to have normally-off characteristics.

[0069] The channel isolation pattern 200 may include a III-V nitride semiconductor. For example, the channel isolation pattern 200 may include at least one of GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN. The channel isolation pattern 200 may be a p-type semiconductor layer or a layer doped with p-type impurities. For example, the channel isolation pattern 200 may be doped with p-type impurities such as Mg. For example, the channel isolation pattern 200 may be a p-type GaN layer or a p-type AlGaN layer.

[0070] A first passivation film 410 may be provided on the channel supply layer 120 and the channel isolation pattern 200. The first passivation film 410 also extends along the channel supply layer 120. The first passivation film 410 may cover the channel isolation pattern 200. The first passivation film 410 may include an opening (not shown) exposing the top surface of the channel isolation pattern 200. For example, the opening may expose a portion of the top surface of the channel isolation pattern 200. The first passivation film 410 may include an insulating material. For example, the first passivation film 410 may include an oxide, a nitride, or a combination thereof. For example, the first passivation film 410 may include SiO2, Al2O3, and Si x N y may include at least one of the following:

[0071] A conductive material pattern 300 may be provided on the channel isolation pattern 200. The conductive material pattern 300 may include an electrically conductive material. For example, the conductive material pattern may include a metal. The conductive material pattern 300 may include a gate electrode pattern 310, an electric field relaxation pattern 320, and a protrusion pattern 330.

[0072] The gate electrode pattern 310 may overlap the channel isolation pattern 200 along a second direction D2 perpendicular to the top surface of the channel layer 110. For example, the gate electrode pattern 310 may overlap a portion of the top surface of the channel isolation pattern 200 exposed by the opening along the second direction D2. The gate electrode pattern 310 is provided within the opening and extends to the outside of the opening. For example, the gate electrode pattern 310 extends in the second direction D2. The width of the gate electrode pattern 310 is also different from the width of the channel isolation pattern 200. For example, the width of the gate electrode pattern 310 is narrower than the width of the channel isolation pattern 200. The width of the gate electrode pattern 310 is also the size of the gate electrode pattern 310 along the first direction D1. The width of the channel isolation pattern 200 is also the size of the channel isolation pattern 200 along the first direction D1. When the width of the gate electrode pattern 310 is narrower than the width of the channel isolation pattern 200, the gate electrode pattern 310 and the channel isolation pattern 200 are also referred to as a stepped gate structure. Since the gate electrode pattern 310 has a width narrower than that of the channel isolation pattern 200, leakage current flowing along the side of the gate electrode pattern 310 and the side of the channel isolation pattern 200 can be reduced, and electric field concentration on the side of the gate electrode pattern 310 can be prevented.

[0073] The electric field relaxation pattern 320 also protrudes from a first side surface 312 of the gate electrode pattern 310. The first side surface 312 of the gate electrode pattern 310 is also a side surface of the gate electrode pattern 310 facing the drain electrode pattern 520. The electric field relaxation pattern 320 also extends along the top surface of the first passivation film 410. The electric field relaxation pattern 320 also extends from the first side surface 312 of the gate electrode pattern 310 toward the drain electrode pattern 520. For example, the electric field relaxation pattern 320 also extends along the first direction D1. In one example, the electric field relaxation pattern 320 may further extend along the top surface of the first passivation film 410 toward the drain electrode pattern 520. The electric field relaxation pattern 320 may be disposed closer to the drain electrode pattern 520 than the channel separation pattern 200. The distance between the electric field relaxation pattern 320 and the drain electrode pattern 520 is also different from the distance between the channel separation pattern 200 and the drain electrode pattern 520. For example, the distance between the electric field relaxation pattern 320 and the drain electrode pattern 520 is shorter than the distance between the channel separation pattern 200 and the drain electrode pattern 520. The electric field relaxation pattern 320 may mitigate electric field concentration on the side of the channel separation pattern 200. The electric field relaxation pattern 320 may overlap with an upper portion of the gate electrode pattern 310 along a first direction D1. The electric field relaxation pattern 320 may overlap with the channel separation pattern 200 along a second direction D2. The bottom surface of the electric field relaxation pattern 320 may face the top surface of the channel separation pattern 200. The electric field relaxation pattern 320 may form a single structure with the gate electrode pattern 310. In other words, the electric field relaxation pattern 320 and the gate electrode pattern 310 may be connected to each other without an interface.

[0074] The protruding pattern 330 also protrudes from a second side surface 314 of the gate electrode pattern 310. The second side surface 314 of the gate electrode pattern 310 is also a side surface of the gate electrode pattern 310 facing the source electrode pattern 510. The protruding pattern 330 also extends along the top surface of the first passivation film 410. For example, the protruding pattern 330 also extends along a first direction D1. In one example, the protruding pattern 330 may further extend along the top surface of the first passivation film 410 toward the source electrode pattern 510. While the length of the protruding pattern 330 is illustrated as being shorter than the length of the electric field relaxation pattern 320, this is not limiting. In another example, the length of the protruding pattern 330 is the same as or longer than the length of the electric field relaxation pattern 320. The protruding pattern 330 may form a single structure with the gate electrode pattern 310. In other words, the protruding pattern 330 and the gate electrode pattern 310 may be connected to each other without an interface. Therefore, the gate electrode pattern 310, the electric field relaxation pattern 320, and the protruding pattern 330 can form a single structure.

[0075] The second passivation film 420 is also provided on the first passivation film 410 and the conductive material pattern 300. The second passivation film 420 also extends along the top surface of the first passivation film 410. The second passivation film 420 may cover the conductive material pattern 300. The second passivation film 420 may include an insulating material. For example, the second passivation film 420 may include an oxide, a nitride, or a combination thereof. For example, the second passivation film 420 may include SiO2, Al2O3, and Si x N y may include at least one of the following:

[0076] The source electrode pattern 510 and the drain electrode pattern 520 may be spaced apart from each other with the gate electrode pattern 310 interposed therebetween. The source electrode pattern 510 and the drain electrode pattern 520 may be spaced apart from each other in a first direction D1. The source electrode pattern 510 and the drain electrode pattern 520 may penetrate the second passivation film 420, the first passivation film 410, and the channel supply layer 120. The source electrode pattern 510 and the drain electrode pattern 520 may be electrically connected to the two-dimensional electron gas (2DEG) layer 130. For example, the source electrode pattern 510 and the drain electrode pattern 520 may extend into the channel layer 110 and directly contact the two-dimensional electron gas (2DEG) layer 130. The source electrode pattern 510 and the drain electrode pattern 520 may make ohmic contact with the channel supply layer 120. In another exemplary embodiment, an ohmic contact layer (not shown) may be inserted between the source electrode pattern 510 and the channel layer 110, and between the drain electrode pattern 520 and the channel layer 110. The source electrode pattern 510 and the drain electrode pattern 520 may have a single-layer structure or a multi-layer structure. For example, the source electrode pattern 510 and the drain electrode pattern 520 may include at least one of titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au).

[0077] An additional field-reducing film 610 may be provided on the second passivation film 420. The additional field-reducing film 610 may extend along the second passivation film 420 on the source electrode pattern 510. The additional field-reducing film 610 may also be electrically connected to the source electrode pattern 510. For example, the additional field-reducing film 610 may be in direct contact with the source electrode pattern 510. As a result, the source electrode pattern 510 and the additional field-reducing film 610 may have the same potential. The additional field-reducing film 610 may overlap the conductive material pattern 300 and the channel separation pattern 200 along the second direction D2. The additional field-reducing film 610 may also be disposed to be closer to the drain electrode pattern 520 than the field-reducing pattern 320. The distance between the additional field-reducing film 610 and the drain electrode pattern 520 is shorter than the distance between the field-reducing pattern 320 and the drain electrode pattern 520. The additional field-reducing film 610 may include an electrically conductive material. For example, the additional electric field mitigating film 610 may include a metal. The additional electric field mitigating film 610 can prevent an electric field from concentrating between the conductive material pattern 300 and the drain electrode pattern 520.

[0078] A first auxiliary drain electrode pattern 700 may be provided on the drain electrode pattern 520. The first auxiliary drain electrode pattern 700 may extend onto the second passivation film 420. The first auxiliary drain electrode pattern 700 may be spaced apart from the additional electric field reduction film 610. The first auxiliary drain electrode pattern 700 may also be electrically connected to the drain electrode pattern 520. For example, the first auxiliary drain electrode pattern 700 may be in direct contact with the drain electrode pattern 520. The first auxiliary drain electrode pattern 700 may include an electrically conductive material. For example, the first auxiliary drain electrode pattern 700 may include a metal.

[0079] The gate electrode pattern 310 of the present disclosure may have a width different from that of the channel isolation pattern 200. This reduces or prevents leakage current flow through the side surfaces of the gate electrode pattern 310 and the channel isolation pattern 200. The electric field mitigating pattern 320, the additional electric field mitigating film 610, and the first auxiliary drain electrode pattern 700 of the present disclosure can reduce or prevent electric field concentration between the gate electrode pattern 310 and the drain electrode pattern 520. The present disclosure can provide a semiconductor device 10 with improved electrical characteristics.

[0080] FIG. 2 is a cross-sectional view for explaining a method for manufacturing the semiconductor device of FIG. 1. FIG. 3 is a cross-sectional view for explaining a method for manufacturing the semiconductor device of FIG. 1. FIG. 4 is a cross-sectional view for explaining a method for manufacturing the semiconductor device of FIG. 1. FIG. 5 is a cross-sectional view for explaining a method for manufacturing the semiconductor device of FIG. 1. FIG. 6 is a cross-sectional view for explaining a method for manufacturing the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view for explaining a method for manufacturing the semiconductor device of FIG. 1. For simplicity of explanation, content that is substantially the same as that explained with reference to FIG. 1 will not be explained.

[0081] 2, the channel layer 110 and the channel supply layer 120 may be stacked in order. For example, the channel layer 110 and the channel supply layer 120 may be formed on a substrate (not shown) by an epitaxial growth process. For example, the epitaxial growth process may include at least one of a metal organic chemical vapor deposition process, a liquid phase epitaxy process, a hydride vapor phase epitaxy process, a molecular beam epitaxy process, or a metal organic vapor phase epitaxy process. For example, the substrate may be a silicon substrate, a SiC substrate, a GaN substrate, a diamond substrate, or a sapphire substrate.

[0082] The channel layer 110 may include a III-V compound semiconductor. For example, the channel layer 110 may include GaN. The channel supply layer 120 may be a semiconductor layer different from the channel layer 110. The channel supply layer 120 may differ from the channel layer 110 in at least one of polarization characteristics, energy band gap, and lattice constant. The channel supply layer 120 may include one or more materials selected from nitrides containing at least one of Al, Ga, In, and B. For example, the channel supply layer 120 may include at least one of AlGaN, AlInN, InGaN, AlN, and AlInGaN. The channel supply layer 120 may have a single-layer structure or a multi-layer structure.

[0083] The channel supply layer 120 may form a two-dimensional electron gas (2DEG) layer 130 in the channel layer 110. The two-dimensional electron gas (2DEG) layer 130 is also formed in the channel layer 110 adjacent to the interface between the channel supply layer 120 and the channel layer 110. The two-dimensional electron gas (2DEG) layer 130 also extends along a first direction D1 parallel to the top surface of the channel layer 110.

[0084] The channel isolation pattern 200 may be formed on the channel supply layer 120. The formation of the channel isolation pattern 200 may include forming a channel isolation film (not shown) on the channel supply layer 120 and patterning the channel isolation film. For example, the channel isolation film may also be formed on the channel supply layer 120 by an epitaxial growth process.

[0085] The channel isolation film may include a III-V compound semiconductor. For example, the channel isolation film may include at least one of GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN. The channel isolation film may be a p-type semiconductor layer or a layer doped with p-type impurities. For example, the channel isolation film may be doped with p-type impurities such as Mg. For example, the channel isolation film may be a p-type GaN layer or a p-type AlGaN layer.

[0086] In one example, the channel isolation film is also patterned by an etching process using an etching mask (not shown). The patterned channel isolation film is also referred to as a channel isolation pattern 200. The channel isolation pattern 200 can enhance the energy band of a portion of the channel supply layer 120 thereunder. A depletion region (not shown) can be formed in the two-dimensional electron gas (2DEG) layer 130 under the channel isolation pattern 200. The two-dimensional electron gas (2DEG) layer 130 can be cut in a region adjacent to the channel isolation pattern 200 by the depletion region. As a result, the semiconductor device 10 can have normally-off characteristics. The etching mask is removed during or after the etching process.

[0087] 3, a first passivation film 410 may be formed on the channel supply layer 120 and the channel isolation pattern 200. The process of forming the first passivation film 410 may include depositing an insulating material on the channel supply layer 120 and the channel isolation pattern 200. For example, the first passivation film 410 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. For example, the first passivation film 410 may include an oxide, a nitride, or a combination thereof. For example, the first passivation film 410 may be formed using a material selected from the group consisting of SiO2, Al2O3, and Si. x N y may include at least one of the following:

[0088] An opening OP may be formed in the first passivation film 410. The process of forming the opening OP may include performing an etching process on the first passivation film 410 using an etching mask. The etching process may be performed until the top surface of the channel isolation pattern 200 is exposed. In other words, the opening OP may penetrate the first passivation film 410 and expose the top surface of the channel isolation pattern 200. The etching mask may be removed during or after the etching process.

[0089] Referring to FIG. 4 , a conductive material film 302 may be formed on a first passivation film 410. The conductive material film 302 may extend along the first passivation film 410. The conductive material film 302 may also extend into the opening OP. While the conductive material film 302 is illustrated as filling the entire opening OP, this is not limiting. In another example, the conductive material film 302 may fill only a portion of the opening OP. The conductive material film 302 may be in direct contact with the channel isolation pattern 200. The process of forming the conductive material film 302 may include depositing an electrically conductive material on the first passivation film 410. For example, the conductive material film 302 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. For example, the conductive material film 302 may include a metal.

[0090] Referring to FIG. 5, a conductive material pattern 300 may be formed. The conductive material pattern 300 may be formed by an etching process using an etching mask performed on a conductive material layer. The conductive material pattern 300 may be formed to extend from within an opening OP to the outside of the opening OP. The conductive material pattern 300 may include a gate electrode pattern 310, an electric field relaxation pattern 320, and a protruding pattern 330. The gate electrode pattern 310, the electric field relaxation pattern 320, and the protruding pattern 330 are substantially the same as those described with reference to FIG. 1. Since the gate electrode pattern 310 and the electric field relaxation pattern 320 are formed simultaneously, process time, process complexity, and process costs may be reduced compared to forming the gate electrode pattern 310 and the electric field relaxation pattern 320 in separate processes. The etching mask may be removed during or after the etching process.

[0091] 6, a second passivation film 420 is formed on the conductive material pattern 300 and the first passivation film 410. The process of forming the second passivation film 420 may include depositing an insulating material on the first passivation film 410 and the conductive material pattern 300. For example, the second passivation film 420 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. For example, the second passivation film 420 may include an oxide, a nitride, or a combination thereof. For example, the second passivation film 410 may be formed of SiO2, Al2O3, and Si x N y may include at least one of the following:

[0092] 7, a source electrode pattern 510 and a drain electrode pattern 520 may be formed. The formation of the source electrode pattern 510 and the drain electrode pattern 520 may include performing an etching process to remove the second passivation film 420, the first passivation film 410, and the channel supply layer 120 in two regions spaced apart from each other across the conductive material pattern 300, and filling the two regions where the etching process was performed with an electrically conductive material. During the etching process, the upper portion of the channel layer 110 may also be removed. For example, the etching process may be performed to a position deeper than the depth at which the two-dimensional electron gas (2DEG) layer 130 is formed in the channel layer 110. As a result, the source electrode pattern 510 and the drain electrode pattern 520 may be in direct contact with the two-dimensional electron gas (2DEG) layer.

[0093] 1 , an additional field-relieving film 610 and a first auxiliary drain electrode pattern 700 may be formed on the source electrode pattern 510 and the drain electrode pattern 520, respectively. The formation of the additional field-relieving film 610 and the first auxiliary drain electrode pattern 700 may include forming an electrically conductive film (not shown) on the source electrode pattern 510, the second passivation film 420, and the drain electrode pattern 520, and etching a portion of the electrically conductive film. The etching process may also be performed on the electrically conductive film between the conductive material pattern 300 and the drain electrode pattern 520. The etching process may be performed until the top surface of the second passivation film 420 is exposed. As a result, the electrically conductive film may be separated into the additional field-relieving film 610 and the first auxiliary drain electrode pattern 700. The additional field-relieving film 610 and the first auxiliary drain electrode pattern 700 are substantially the same as those described with reference to FIG. 1 .

[0094] In the present disclosure, the gate electrode pattern 310 and the electric field relaxation pattern 320 are formed simultaneously. Therefore, compared to forming the gate electrode pattern 310 and the electric field relaxation pattern 320 in separate processes, the process time, process complexity, and process cost can be reduced. As a result, a method for manufacturing a semiconductor device with improved process efficiency can be provided.

[0095] 8 is a cross-sectional view of a semiconductor device according to an exemplary embodiment. For the sake of brevity, the description will not be made of substantially the same content as that described with reference to FIG.

[0096] 8, a semiconductor device 11 may be provided. The semiconductor device 11 may include a channel layer 110, a channel supply layer 120, a channel isolation pattern 200, a first passivation film 410, a source electrode pattern 510, a drain electrode pattern 520, a second auxiliary drain electrode pattern 522, a second passivation film 420, and a conductive material pattern 300. The channel layer 110, the channel supply layer 120, and the channel isolation pattern 200 may be substantially the same as those described with reference to FIG.

[0097] A first passivation film 410 may be provided on the channel supply layer 120 and the channel isolation pattern 200. The first passivation film 410 may also extend along the channel supply layer 120. The first passivation film 410 may cover the channel isolation pattern 200. The first passivation film 410 may include an insulating material.

[0098] The source electrode pattern 510 and the drain electrode pattern 520 may be spaced apart from each other with the gate electrode pattern 310 interposed therebetween. The source electrode pattern 510 and the drain electrode pattern 520 may be spaced apart from each other in a first direction D1. The source electrode pattern 510 and the drain electrode pattern 520 may penetrate the first passivation film 410 and the channel supply layer 120. The source electrode pattern 510 and the drain electrode pattern 520 may be electrically connected to the two-dimensional electron gas (2DEG) layer 130. For example, the source electrode pattern 510 and the drain electrode pattern 520 may extend into the channel layer 110 and be in direct contact with the two-dimensional electron gas (2DEG) layer 130. The source electrode pattern 510 and the drain electrode pattern 520 may be in ohmic contact with the channel supply layer 120. The source electrode pattern 510 and the drain electrode pattern 520 may have a single-layer structure or a multi-layer structure. For example, the source electrode pattern 510 and the drain electrode pattern 520 may include at least one of titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au).

[0099] The second passivation film 420 is also provided on the first passivation film 410, the source electrode pattern 510, and the drain electrode pattern 520. The second passivation film 420 also extends along the top surface of the first passivation film 410. The second passivation film 420 may cover the source electrode pattern 510 and the drain electrode pattern 520. The second passivation film 420 may include an insulating material.

[0100] The second auxiliary drain electrode pattern 522 is also provided between the drain electrode pattern 520, the first passivation film 410, and the second passivation film 420. The second auxiliary drain electrode pattern 522 is also provided on a side of the drain electrode pattern 520 and is disposed between the first passivation film 410 and the second passivation film 420. The second auxiliary drain electrode pattern 522 is also electrically connected to the drain electrode pattern 520. For example, the second auxiliary drain electrode pattern 522 may be in direct contact with the drain electrode pattern 520. In one example, the second auxiliary drain electrode pattern 522 may form a single structure with the drain electrode pattern 520. In other words, the second auxiliary drain electrode pattern 522 and the drain electrode pattern 520 may be connected to each other without a boundary therebetween. The second auxiliary drain electrode pattern 522 may include an electrically conductive material. For example, the second auxiliary drain electrode pattern 522 may include a metal.

[0101] The conductive material pattern 300 extends onto the second passivation film 420 on the channel isolation pattern 200. The gate electrode pattern 310 may penetrate the second passivation film 420 and the first passivation film 410 and be in direct contact with the channel isolation pattern 200. The gate electrode pattern 310 also protrudes onto the top surface of the second passivation film 420. The electric field relaxation pattern 320 also protrudes from a first side surface 312 of the gate electrode pattern 310 toward the drain electrode pattern 520. The electric field relaxation pattern 320 also extends along the top surface of the second passivation film 420. The protruding pattern 330 also protrudes from a second side surface 314 of the gate electrode pattern 310 toward the source electrode pattern 510. The protruding pattern 330 also extends along the top surface of the second passivation film 420.

[0102] The gate electrode pattern 310 of the present disclosure may have a width different from that of the channel isolation pattern 200. This reduces or prevents leakage current flow through the side surfaces of the gate electrode pattern 310 and the channel isolation pattern 200. The electric field relaxation pattern 320 and the second auxiliary drain electrode pattern 522 of the present disclosure can reduce or prevent electric field concentration between the gate electrode pattern 310 and the drain electrode pattern 520. The present disclosure can provide a semiconductor device 11 with improved electrical characteristics.

[0103] Figure 9 is a cross-sectional view for explaining a method for manufacturing the semiconductor device of Figure 8. Figure 10 is a cross-sectional view for explaining a method for manufacturing the semiconductor device of Figure 8. For the sake of simplicity, details that are substantially the same as those described with reference to Figures 2 to 7 will not be described.

[0104] 9, a channel layer 110, a channel supply layer 120, a channel isolation pattern 200, a first passivation film 410, a source electrode pattern 510, a drain electrode pattern 520, a second auxiliary drain electrode pattern 522, and a second passivation film 420 may be formed. The formation of the channel layer 110, the channel supply layer 120, the channel isolation pattern 200, and the first passivation film 410 may be substantially the same as that described with reference to FIGS. 2 and 3.

[0105] A source electrode pattern 510 and a drain electrode pattern 520 may be formed. The formation of the source electrode pattern 510 and the drain electrode pattern 520 may include performing an etching process to remove the second passivation film 420, the first passivation film 410, and the channel supply layer 120 in two regions spaced apart from each other across the conductive material pattern 300, and filling the two regions where the etching process was performed with an electrically conductive material. During the etching process, the upper portion of the channel layer 110 may also be removed. For example, the etching process may be performed to a position deeper than the depth at which the two-dimensional electron gas (2DEG) layer 130 is formed in the channel layer 110. As a result, the source electrode pattern 510 and the drain electrode pattern 520 are also formed to be electrically connected to the two-dimensional electron gas (2DEG) layer.

[0106] The second auxiliary drain electrode pattern 522 is also formed on a side surface of the drain electrode pattern 520. The second auxiliary drain electrode pattern 522 also protrudes from the side surface of the drain electrode pattern 520 onto the first passivation film 410. In one example, the second auxiliary drain electrode pattern 522 may be formed simultaneously with the source electrode pattern 510 and the drain electrode pattern 520. The second auxiliary drain electrode pattern 522 and the drain electrode pattern 520 may be connected to each other without a boundary therebetween. In another example, the second auxiliary drain electrode pattern 522 may be formed by a process different from the process for forming the source electrode pattern 510 and the drain electrode pattern 520. For example, after the source electrode pattern 510 and the drain electrode pattern 520 are formed, the second auxiliary drain electrode pattern 522 may be formed on the first passivation film 410 immediately adjacent to the drain electrode pattern 520.

[0107] A second passivation film 420 may be formed on the first passivation film 410. The second passivation film 420 may cover the first passivation film 410, the second auxiliary drain electrode pattern 522, the source electrode pattern 510, and the drain electrode pattern 520. The process of forming the second passivation film 420 may include depositing an insulating material on the first passivation film 410. For example, the second passivation film 420 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. For example, the second passivation film 420 may include an oxide, a nitride, or a combination thereof. For example, the second passivation film 420 may be formed by a material selected from the group consisting of SiO2, Al2O3, and Si. x N y may include at least one of the following:

[0108] 10, openings OP may be formed in the second passivation film 420 and the first passivation film 410. The process of forming the openings OP may include performing an etching process on the second passivation film 420 and the first passivation film 410 using an etching mask. The etching process may be performed until the top surface of the channel isolation pattern 200 is exposed. In other words, the openings OP may penetrate the second passivation film 420 and the first passivation film 410 to expose the top surface of the channel isolation pattern 200. The etching mask may be removed during or after the etching process.

[0109] A conductive material film 302 may be formed on the second passivation film 420. The conductive material film 302 may extend along the second passivation film 420 and fill the opening OP. The conductive material film 302 may be in direct contact with the channel isolation pattern 200. The process of forming the conductive material film 302 may include depositing an electrically conductive material on the second passivation film 420. For example, the conductive material film 302 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. For example, the conductive material film 302 may include a metal.

[0110] Referring again to FIG. 8, a conductive material pattern 300 may be formed. The conductive material pattern 300 may be formed by an etching process using an etching mask (not shown) performed on a conductive material layer. The etching mask may be removed during or after the etching process. After the etching process, a portion of the conductive material layer adjacent to the opening OP may remain. This portion of the conductive material layer may also be referred to as the conductive material pattern 300. The conductive material pattern 300 may be formed to extend from within the opening OP to outside the opening OP. The conductive material pattern 300 may include a gate electrode pattern 310, an electric field relaxation pattern 320, and a protrusion pattern 330. The gate electrode pattern 310, the electric field relaxation pattern 320, and the protrusion pattern 330 may be substantially the same as those described with reference to FIG. 8.

[0111] In the present disclosure, the gate electrode pattern 310 and the electric field relaxation pattern 320 are formed simultaneously. Therefore, compared to forming the gate electrode pattern 310 and the electric field relaxation pattern 320 in separate processes, the process time, process complexity, and process cost can be reduced. As a result, a method for manufacturing a semiconductor device with improved process efficiency can be provided.

[0112] 11 is a cross-sectional view of a semiconductor device according to an exemplary embodiment. For the sake of brevity, details that are substantially the same as those described with reference to FIG. 1 will not be described.

[0113] 11 , a semiconductor device 12 may be provided. The semiconductor device 12 may include a channel layer 110, a channel supply layer 120, a channel isolation pattern 200, a first passivation pattern 430a, a second passivation pattern 430b, a first passivation film 410, a conductive material pattern 300, a second passivation film 420, a source electrode pattern 510, a drain electrode pattern 520, an additional electric field reduction film 610, and a first auxiliary drain electrode pattern 700.

[0114] Unlike the configuration described with reference to FIG. 1 , the semiconductor device 12 may further include a first passivation pattern 430a and a second passivation pattern 430b. The first passivation pattern 430a and the second passivation pattern 430b are also provided between the first passivation film 410, the channel isolation pattern 200, and the gate electrode pattern 310. The first passivation pattern 430a and the second passivation pattern 430b are also provided on the first upper surface 202 and the second upper surface 204 of the channel isolation pattern 200, respectively, exposed by the gate electrode pattern 310. The first upper surface 202 and the second upper surface 204 of the channel isolation pattern 200 are also exposed on the first side surface 312 and the second side surface 314 of the gate electrode pattern 310, respectively. The first passivation pattern 430a and the second passivation pattern 430b may directly contact the first side surface 312 and the second side surface 314 of the gate electrode pattern 310, respectively. A side surface of the first passivation pattern 430a and one side surface of the channel isolation pattern 200 immediately adjacent to the side surface of the first passivation pattern 430a may be coplanar. A side surface of the second passivation pattern 430b and another side surface of the channel isolation pattern 200 immediately adjacent to the side surface of the second passivation pattern 430b may be coplanar. The first passivation pattern 430a and the second passivation pattern 430b may have a high etch selectivity with respect to the channel isolation pattern 200. For example, the first passivation pattern 430a and the second passivation pattern 430b may have an etch selectivity greater than 1 with respect to the channel isolation pattern 200. The first passivation pattern 430a and the second passivation pattern 430b may have a low etch selectivity with respect to the first passivation film 410. For example, the first passivation pattern 430a and the second passivation pattern 430b may have an etching selectivity less than 1 with respect to the first passivation film 410.For example, the first passivation pattern 430a and the second passivation pattern 430b may include an oxide, for example, SiO 2 .

[0115] The gate electrode pattern 310 of the present disclosure may have a width different from that of the channel isolation pattern 200. This reduces or prevents leakage current flow through the side surfaces of the gate electrode pattern 310 and the channel isolation pattern 200. The electric field relaxation pattern 320 of the present disclosure reduces or prevents electric field concentration between the gate electrode pattern 310 and the drain electrode pattern 520. The present disclosure may provide a semiconductor device 12 with improved electrical characteristics.

[0116] The present disclosure can eliminate the requirement for an etching selectivity between the first passivation film 410 and the channel isolation pattern 200. This can broaden the range of materials that can be used for the first passivation film 410. As a result, a semiconductor device 12 with improved electrical characteristics can be provided.

[0117] Figure 12 is a cross-sectional view for explaining a method for manufacturing the semiconductor device of Figure 11. Figure 13 is a cross-sectional view for explaining a method for manufacturing the semiconductor device of Figure 11. Figure 14 is a cross-sectional view for explaining a method for manufacturing the semiconductor device of Figure 11. For the sake of simplicity of explanation, content that is substantially the same as that explained with reference to Figures 2 to 7 will not be explained.

[0118] 12, a channel supply layer 120 is formed on a channel layer 110, and a two-dimensional electron gas (2DEG) layer 130 may be formed in the channel layer 110. The formation of the channel layer 110 and the channel supply layer 120 is substantially the same as that described with reference to FIG.

[0119] A channel isolation pattern 200 and a preliminary passivation pattern 432 may be sequentially stacked on the channel supply layer 120. The formation of the channel isolation pattern 200 and the preliminary passivation pattern 432 may include forming a channel isolation film (not shown) on the channel supply layer 120, forming a preliminary passivation film (not shown) on the channel isolation film, and patterning the preliminary passivation film and the channel isolation film. The formation of the channel isolation film is substantially the same as that described with reference to FIG. 2.

[0120] The formation of the preliminary passivation film may include a deposition process. For example, the preliminary passivation film may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. The preliminary passivation film may include an insulating material. The preliminary passivation film may include a material having an etching selectivity with respect to the channel isolation film. For example, the preliminary passivation film may have an etching selectivity greater than 1 with respect to the channel isolation film. For example, the preliminary passivation film may include an oxide. For example, the preliminary passivation film may include SiO2.

[0121] The preliminary passivation film and the channel isolation film are also patterned by an etching process using an etching mask. The patterned preliminary passivation film is also referred to as a preliminary passivation pattern 432. The patterned channel isolation film is also referred to as a channel isolation pattern 200. The etching mask is removed during or after the etching process.

[0122] 13, a first passivation film 410 may be formed on the channel supply layer 120 and the preliminary passivation pattern 432. The process of forming the first passivation film 410 may include depositing an insulating material on the channel supply layer 120 and the preliminary passivation pattern 432. The first passivation film 410 may have an etching selectivity with respect to the preliminary passivation pattern 432. For example, the first passivation film 410 may have an etching selectivity greater than 1 with respect to the preliminary passivation pattern 432. For example, the first passivation film 410 may include a nitride. For example, the first passivation film 410 may include a Si x N y For example, the first passivation film 410 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process.

[0123] An opening OP may be formed in the first passivation film 410. The process of forming the opening OP may include performing a first selective etching process on the first passivation film 410 using an etching mask (not shown). The first selective etching process may be performed until the top surface of the preliminary passivation pattern 432 is exposed. In other words, the opening OP may penetrate the first passivation film 410 and expose the top surface of the preliminary passivation pattern 432. Since the preliminary passivation pattern 432 has a low etching selectivity relative to the first passivation film 410, it also serves as an etch stop layer in the first selective etching process.

[0124] 14, a second selective etching process may be performed on the preliminary passivation pattern 432 to form a first passivation pattern 430a and a second passivation pattern 430b. The second selective etching process may be performed until the top surface of the channel isolation pattern 200 is exposed. Accordingly, the opening OP may be further extended. The opening OP may penetrate the preliminary passivation pattern 432 to expose the top surface of the channel isolation pattern 200. Because the channel isolation pattern 200 has a low etch selectivity relative to the preliminary passivation pattern 432, the channel isolation pattern 200 also serves as an etch stop layer in the second selective etching process. The etching mask may be removed during the first selective etching process, after the first selective etching process, during the second selective etching process, or after the second selective etching process.

[0125] 11, a conductive material pattern 300, a second passivation film 420, a source electrode pattern 510, a drain electrode pattern 520, an additional field buffer film 610, and a first auxiliary drain electrode pattern 700 may be formed. The formation of the conductive material pattern 300 is substantially the same as that described with reference to FIGS. 4 and 5. The formation of the second passivation film 420 is substantially the same as that described with reference to FIG. 6. The formation of the source electrode pattern 510 and the drain electrode pattern 520 is substantially the same as that described with reference to FIG. 7. The formation of the additional field buffer film 610 and the first auxiliary drain electrode pattern 700 is substantially the same as that described with reference to FIG. 1.

[0126] In the present disclosure, the gate electrode pattern 310 and the electric field relaxation pattern 320 are formed simultaneously. Therefore, compared to forming the gate electrode pattern 310 and the electric field relaxation pattern 320 in separate processes, the process time, process complexity, and process cost can be reduced. As a result, a method for manufacturing a semiconductor device with improved process efficiency can be provided.

[0127] The first passivation film 410 of the present disclosure may have an etching selectivity with respect to the preliminary passivation pattern 432, and the preliminary passivation pattern 432 may have an etching selectivity with respect to the channel isolation pattern 200. This may improve the accuracy of the etching process. In addition, a wider range of materials may be used for the first passivation film 410, which may reduce the difficulty of the process.

[0128] 15 is a cross-sectional view of a semiconductor device according to an exemplary embodiment. For the sake of brevity, details that are substantially the same as those described with reference to FIG.

[0129] 15, a semiconductor device 13 may be provided. The semiconductor device 13 may include a channel layer 110, a channel supply layer 120, a channel isolation pattern 200, a first passivation film 410, a conductive material pattern 300, a second passivation film 420, a source electrode pattern 510, a drain electrode pattern 520, an additional electric field reduction film 610, and a first auxiliary drain electrode pattern 700.

[0130] Unlike the configuration described with reference to FIG. 1 , the channel isolation pattern 200 is also tapered in the second direction D2. That is, the width W200 of the channel isolation pattern 200 also narrows in the second direction D2. The width W200 of the channel isolation pattern 200 is also the size of the channel isolation pattern 200 in the first direction D1. The width W200 of the channel isolation pattern 200 also narrows as it approaches the gate electrode pattern 310. The width W200 of the channel isolation pattern 200 also widens as it approaches the channel supply layer 120.

[0131] The gate electrode pattern 310 of the present disclosure may have a width different from that of the channel isolation pattern 200. This reduces or prevents leakage current flow through the side surfaces of the gate electrode pattern 310 and the channel isolation pattern 200. The electric field mitigation pattern 320 and the additional electric field mitigation film 610 of the present disclosure can reduce or prevent electric field concentration between the gate electrode pattern 310 and the drain electrode pattern 520. The present disclosure can provide a semiconductor device 13 with improved electrical characteristics.

[0132] 16 is a cross-sectional view of a semiconductor device according to an exemplary embodiment. For the sake of brevity, details that are substantially the same as those described with reference to FIG.

[0133] 16, a semiconductor device 14 may be provided. The semiconductor device 14 may include a channel layer 110, a channel supply layer 120, a channel isolation pattern 200, a first passivation film 410, a conductive material pattern 300, a second passivation film 420, a source electrode pattern 510, a drain electrode pattern 520, an additional electric field reduction film 610, and a first auxiliary drain electrode pattern 700.

[0134] 1, the gate electrode pattern 310 also has an inverse tapered shape in the second direction D2. That is, the width W310 of the gate electrode pattern 310 also increases in the second direction D2. The width W310 of the gate electrode pattern 310 is also the size of the gate electrode pattern 310 in the first direction D1. The width W310 of the gate electrode pattern 310 also increases as it approaches the bottom surface of the electric field relaxation pattern 320. The width W310 of the gate electrode pattern 310 also decreases as it approaches the channel isolation pattern 200.

[0135] The gate electrode pattern 310 of the present disclosure may have a width W310 different from that of the channel isolation pattern 200. This reduces or prevents leakage current flow through the side surfaces of the gate electrode pattern 310 and the channel isolation pattern 200. The electric field mitigation pattern 320 and the additional electric field mitigation film 610 of the present disclosure can reduce or prevent electric field concentration between the gate electrode pattern 310 and the drain electrode pattern 520. The present disclosure can provide a semiconductor device 14 with improved electrical characteristics.

[0136] Fig. 17 is a cross-sectional view of a semiconductor device according to an exemplary embodiment. Fig. 18 is an enlarged view of a portion AA in Fig. 17. For simplicity of explanation, the contents that are substantially the same as those described with reference to Fig. 1 will not be described.

[0137] 17 and 18, a semiconductor device 15 may be provided. The semiconductor device 15 may include a channel layer 110, a channel supply layer 120, a channel isolation pattern 200, a first passivation film 410, a conductive material pattern 300, a second passivation film 420, a source electrode pattern 510, a drain electrode pattern 520, an additional electric field reduction film 610, and a first auxiliary drain electrode pattern 700.

[0138] The channel isolation pattern 200 may include a first upper surface 202 and a second upper surface 204. The first upper surface 202 and the second upper surface 204 may be spaced apart with the gate electrode pattern 310 sandwiched therebetween. The width W202 of the first upper surface 202 and the width W204 of the second upper surface 204 may be different from each other. The width W202 of the first upper surface 202 and the width W204 of the second upper surface 204 are also the dimensions of the first upper surface 202 and the second upper surface 204, respectively, along the first direction D1. For example, the width W202 of the first upper surface 202 is wider than the width W204 of the second upper surface 204. However, the relative widths of the width W202 of the first upper surface 202 and the width W204 of the second upper surface 204 are not limited. In another example, the width W202 of the first upper surface 202 is narrower than the width W204 of the second upper surface 204. On the channel isolation pattern 200, the position of the gate electrode pattern 310 can be determined as needed.

[0139] The gate electrode pattern 310 of the present disclosure may be freely disposed on the channel isolation pattern 200. The gate electrode pattern 310 of the present disclosure may have a width different from that of the channel isolation pattern 200. This reduces or prevents leakage current flow through the side surfaces of the gate electrode pattern 310 and the channel isolation pattern 200. The electric field relaxation pattern 320 and the additional electric field relaxation film 610 of the present disclosure may reduce or prevent electric field concentration between the gate electrode pattern 310 and the drain electrode pattern 520. The present disclosure may provide a semiconductor device 15 with improved electrical characteristics.

[0140] 19 is a cross-sectional view of a semiconductor device according to an exemplary embodiment. For the sake of brevity, details that are substantially the same as those described with reference to FIGS. 1 and 8 will not be described.

[0141] 19, a semiconductor device 16 may be provided. The semiconductor device 16 may include a channel layer 110, a channel supply layer 120, a channel isolation pattern 200, a first passivation film 410, a conductive material pattern 300, a second passivation film 420, a source electrode pattern 510, a drain electrode pattern 520, a second auxiliary drain electrode pattern 522, and an additional electric field relaxation pattern 620. The channel layer 110, the channel supply layer 120, the channel isolation pattern 200, the first passivation film 410, the second passivation film 420, the source electrode pattern 510, the drain electrode pattern 520, and the second auxiliary drain electrode pattern 522 may be substantially the same as those described with reference to FIG.

[0142] The additional electric field relaxation pattern 620 may also be provided between the conductive material pattern 300 and the second auxiliary drain electrode pattern 522. The conductive material pattern 300 and the second auxiliary drain electrode pattern 522 may be spaced apart with the additional electric field relaxation pattern 620 sandwiched therebetween. The additional electric field relaxation pattern 620 may also be provided between the first passivation film 410 and the second passivation film 420. For example, the bottom surface of the additional electric field relaxation pattern 620 may be in direct contact with the first passivation film 410, and the side and top surfaces of the additional electric field relaxation pattern 620 may be in direct contact with the second passivation film 420. The additional electric field relaxation pattern 620 may include an electrically conductive material. For example, the additional electric field relaxation pattern 620 may include a metal. When the semiconductor device 16 is operated, a voltage may be applied to the additional electric field relaxation pattern 620. For example, the additional electric field relaxation pattern 620 may have the same potential as the source electrode pattern 510. However, the additional electric field relaxation pattern 620 may not be provided if necessary.

[0143] The gate electrode pattern 310 of the present disclosure may have a width different from that of the channel isolation pattern 200. This reduces or prevents leakage current flow through the side surfaces of the gate electrode pattern 310 and the channel isolation pattern 200. The electric field relaxation pattern 320, the additional electric field relaxation pattern 620, and the second auxiliary drain electrode pattern 522 of the present disclosure may reduce or prevent electric field concentration between the gate electrode pattern 310 and the drain electrode pattern 520. The present disclosure may provide a semiconductor device 16 with improved electrical characteristics.

[0144] Figure 20 is a cross-sectional view for explaining a method for manufacturing the semiconductor device of Figure 19. Figure 21 is a cross-sectional view for explaining a method for manufacturing the semiconductor device of Figure 19. For the sake of simplicity, details that are substantially the same as those described with reference to Figures 2 to 7 and Figures 9 to 10 will not be described.

[0145] 20, a channel layer 110, a channel supply layer 120, a channel isolation pattern 200, a first passivation film 410, a source electrode pattern 510, a drain electrode pattern 520, an additional electric field relaxation pattern 620, a second auxiliary drain electrode pattern 522, and a second passivation film 420 may be formed. The formation of the channel layer 110, the channel supply layer 120, the channel isolation pattern 200, and the first passivation film 410 may be substantially the same as that described with reference to FIGS. 2 and 3.

[0146] The formation of the source electrode pattern 510 and the drain electrode pattern 520 may include performing an etching process to remove the first passivation film 410 and the channel supply layer 120 in two regions spaced apart from each other across the channel isolation pattern 200, forming an electrically conductive film (not shown) that fills the two regions where the etching process was performed and extends along the top surface of the first passivation film 410, and patterning the electrically conductive film. The electrically conductive film may also be formed by depositing an electrically conductive material. For example, the electrically conductive film may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. For example, the electrically conductive film may include a metal. The source electrode pattern 510 and the drain electrode pattern 520 may fill the two regions. A portion of the source electrode pattern 510 and a portion of the drain electrode pattern 520 also protrude from the top surface of the first passivation film 410 in the second direction D2. During the etching process, the upper portion of the channel layer 110 may also be removed. For example, the etching process may be performed to a position deeper than the depth at which the two-dimensional electron gas (2DEG) layer 130 is formed within the channel layer 110. This allows the source electrode pattern 510 and the drain electrode pattern 520 to be in direct contact with the two-dimensional electron gas (2DEG) layer.

[0147] The second auxiliary drain electrode pattern 522 is also formed on a side surface of a portion of the drain electrode pattern 520. In one example, the second auxiliary drain electrode pattern 522 may be formed simultaneously with the formation of the source electrode pattern 510 and the drain electrode pattern 520. For example, when the electrically conductive layer is patterned, a portion of the electrically conductive layer disposed on the first passivation layer 410 immediately adjacent to the drain electrode pattern 520 is not removed. This portion of the electrically conductive layer is also referred to as the second auxiliary drain electrode pattern 522. The second auxiliary drain electrode pattern 522 and the drain electrode pattern 520 may be connected to each other without a boundary therebetween. In another example, the second auxiliary drain electrode pattern 522 may be formed by a process different from the process of forming the source electrode pattern 510 and the drain electrode pattern 520. For example, after the formation of the source electrode pattern 510 and the drain electrode pattern 520, the second auxiliary drain electrode pattern 522 may be formed on the first passivation layer 410 immediately adjacent to the drain electrode pattern 520. A boundary may be provided between the second auxiliary drain electrode pattern 522 and the drain electrode pattern 520 .

[0148] The additional electric field relaxation pattern 620 may also be formed between the channel separation pattern 200 and the drain electrode pattern 520. The additional electric field relaxation pattern 620 may be spaced apart from the channel separation pattern 200, the drain electrode pattern 520, and the second auxiliary drain electrode pattern 522. In one example, the additional electric field relaxation pattern 620 may be formed simultaneously with the formation of the source electrode pattern 510 and the drain electrode pattern 520. For example, when the electrically conductive layer is patterned, a portion of the electrically conductive layer disposed between the drain electrode pattern 520 and the channel separation pattern 200 is not removed. This portion of the electrically conductive layer is also referred to as the additional electric field relaxation pattern 620. In another example, the additional electric field relaxation pattern 620 may be formed by a process different from the formation process of the source electrode pattern 510 and the drain electrode pattern 520. For example, after the formation of the source electrode pattern 510 and the drain electrode pattern 520, the additional electric field relaxation pattern 620 may be formed between the drain electrode pattern 520 and the channel separation pattern 200.

[0149] The second passivation film 420 is also formed on the first passivation film 410, the source electrode pattern 510, the drain electrode pattern 520, and the additional electric field relaxation pattern 620. The process of forming the second passivation film 420 may include depositing an insulating material on the first passivation film 410, the source electrode pattern 510, the drain electrode pattern 520, and the additional electric field relaxation pattern 620. For example, the second passivation film 420 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. For example, the second passivation film 420 may include an oxide, a nitride, or a combination thereof. For example, the second passivation film 410 may be formed of SiO2, Al2O3, and Si x N y may include at least one of the following:

[0150] 21 , openings OP may be formed in the first passivation film 410 and the second passivation film 420. The process of forming the openings OP may include performing an etching process on the first passivation film 410 and the second passivation film 420 using an etching mask. The etching process may be performed until the top surface of the channel isolation pattern 200 is exposed. In other words, the openings OP may penetrate the first passivation film 410 and the second passivation film 420 to expose the top surface of the channel isolation pattern 200. The etching mask may be removed during or after the etching process.

[0151] A conductive material film 302 may be formed on the second passivation film 420. The conductive material film 302 may extend along the second passivation film 420. The conductive material film 302 may also extend into the opening OP. Although the conductive material film 302 is illustrated as filling the entire opening OP, this is not limiting. In another example, the conductive material film 302 may fill only a portion of the opening OP. The conductive material film 302 may be in direct contact with the channel isolation pattern 200. The process of forming the conductive material film 302 may include depositing an electrically conductive material on the second passivation film 420. For example, the conductive material film 302 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. For example, the conductive material film 302 may include a metal.

[0152] Referring again to FIG. 19, a conductive material pattern 300 may be formed. The conductive material pattern 300 may be formed by an etching process performed on a conductive material film using an etching mask. The conductive material pattern 300 may be formed to extend from within an opening OP to the outside of the opening OP. The conductive material pattern 300 may include a gate electrode pattern 310, an electric field relaxation pattern 320, and a protruding pattern 330. The gate electrode pattern 310, the electric field relaxation pattern 320, and the protruding pattern 330 are substantially the same as those described with reference to FIG. 1. Since the gate electrode pattern 310 and the electric field relaxation pattern 320 are formed simultaneously, process time, process complexity, and process costs may be reduced compared to forming the gate electrode pattern 310 and the electric field relaxation pattern 320 in separate processes. The etching mask may be removed during or after the etching process.

[0153] In the present disclosure, the gate electrode pattern 310 and the electric field relaxation pattern 320 can be formed simultaneously. Therefore, compared to forming the gate electrode pattern 310 and the electric field relaxation pattern 320 in separate processes, the process time, process complexity, and process cost can be reduced. As a result, a method for manufacturing a semiconductor device with improved process efficiency can be provided.

[0154] 22 is a cross-sectional view of a semiconductor device according to an exemplary embodiment. For the sake of brevity, details that are substantially the same as those described with reference to FIGS. 1 and 19 will not be described.

[0155] 22, a semiconductor device 17 may be provided. The semiconductor device 17 may include a channel layer 110, a channel supply layer 120, a channel isolation pattern 200, a first passivation film 410, a source electrode pattern 510, a drain electrode pattern 520, a second auxiliary drain electrode pattern 522, an additional electric field relaxation pattern 620, a second passivation film 420, a conductive material pattern 300, a third passivation film 440, an additional electric field relaxation film 610, an additional electric field relaxation pattern 620, and a first auxiliary drain electrode pattern 700. The channel layer 110, the channel supply layer 120, the channel isolation pattern 200, the first passivation film 410, the electrode pattern 510, the drain electrode pattern 520, the second auxiliary drain electrode pattern 522, and the additional electric field relaxation pattern 620 are substantially the same as those described with reference to FIG. A third passivation film 440 may be formed on the conductive material pattern 300 and the second passivation film 420. The process of forming the third passivation film 440 may include depositing an insulating material on the conductive material pattern 300 and the second passivation film 420. For example, the third passivation film 440 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. For example, the third passivation film 440 may include an oxide, a nitride, or a combination thereof. For example, the third passivation film 440 may be formed using a material selected from the group consisting of SiO2, Al2O3, and Si. x N y may include at least one of the following:

[0156] The third passivation film 440 and the second passivation film 420 may expose the source electrode pattern 510 and the drain electrode pattern 520. For example, after the second passivation film 420 and the third passivation film 440 are formed to cover the source electrode pattern 510 and the drain electrode pattern 520, the second passivation film 420 and the third passivation film 440 on the source electrode pattern 510 and the drain electrode pattern 520 may be removed by an etching process using an etching mask. An additional electric field mitigating film 610 may also be provided on the third passivation film 440. The additional electric field mitigating film 610 may overlap the source electrode pattern 510, the conductive material pattern 300, and the additional electric field mitigating pattern 620 along the second direction D2. The additional electric field mitigating film 610 may also extend over the source electrode pattern 510. The additional electric field mitigating film 610 may be electrically connected to the source electrode pattern 510. For example, the additional electric field mitigating film 610 can be in direct contact with the source electrode pattern 510 .

[0157] The first auxiliary drain electrode pattern 700 may also be provided on the third passivation film 440. The first auxiliary drain electrode pattern 700 may be spaced apart from the additional electric field relaxation film 610. For example, the third passivation film 440 may be exposed between the first auxiliary drain electrode pattern 700 and the additional electric field relaxation film 610. The first auxiliary drain electrode pattern 700 may overlap the drain electrode pattern 520 and the second auxiliary drain electrode pattern 522 in the second direction D2. The first auxiliary drain electrode pattern 700 may also extend over the drain electrode pattern 520. The first auxiliary drain electrode pattern 700 may be electrically connected to the drain electrode pattern 520. For example, the first auxiliary drain electrode pattern 700 may be in direct contact with the drain electrode pattern 520.

[0158] The gate electrode pattern 310 of the present disclosure may have a width different from that of the channel isolation pattern 200. This reduces or prevents leakage current flow through the side surfaces of the gate electrode pattern 310 and the channel isolation pattern 200. The electric field relaxation pattern 320, the additional electric field relaxation pattern 620, the second auxiliary drain electrode pattern 522, the additional electric field relaxation film 610, and the first auxiliary drain electrode pattern 700 of the present disclosure can reduce or prevent electric field concentration between the gate electrode pattern 310 and the drain electrode pattern 520. The present disclosure can provide a semiconductor device 17 with improved electrical characteristics.

[0159] 23 is a cross-sectional view of a semiconductor device according to an exemplary embodiment. For the sake of brevity, details that are substantially the same as those described with reference to FIG. 22 will not be described.

[0160] 23 , a semiconductor device 18 may be provided. The semiconductor device 18 may include a channel layer 110, a channel supply layer 120, a channel isolation pattern 200, a first passivation pattern 430a, a second passivation pattern 430b, a first passivation film 410, a source electrode pattern 510, a drain electrode pattern 520, a second auxiliary drain electrode pattern 522, an additional electric field relaxation pattern 620, a second passivation film 420, a conductive material pattern 300, a third passivation film 440, the additional electric field relaxation film 610, and a first auxiliary drain electrode pattern 700. The channel layer 110, the channel supply layer 120, the channel separation pattern 200, the first passivation film 410, the second passivation film 420, the source electrode pattern 510, the drain electrode pattern 520, the second auxiliary drain electrode pattern 522, the additional electric field relaxation pattern 620, the third passivation film 440, the additional electric field relaxation film 610 and the first auxiliary drain electrode pattern 700 are substantially the same as those described with reference to FIG. 22.

[0161] The first passivation pattern 430a and the second passivation pattern 430b are also substantially the same as those described with reference to FIG.

[0162] 22, the semiconductor device 18 may include a first passivation pattern 430a and a second passivation pattern 430b. The first passivation pattern 430a and the second passivation pattern 430b are also provided between the first passivation film 410, the channel isolation pattern 200, and the gate electrode pattern 310. The first passivation pattern 430a and the second passivation pattern 430b are also provided on the first upper surface 202 and the second upper surface 204 of the channel isolation pattern 200, respectively, exposed by the gate electrode pattern 310. The first upper surface 202 and the second upper surface 204 of the channel isolation pattern 200 are also exposed on the first side surface 312 and the second side surface 314 of the gate electrode pattern 310, respectively. The first passivation pattern 430a and the second passivation pattern 430b may directly contact the first side surface 312 and the second side surface 314 of the gate electrode pattern 310, respectively. A side surface of the first passivation pattern 430a and one side surface of the channel isolation pattern 200 immediately adjacent to the side surface of the first passivation pattern 430a may be coplanar. A side surface of the second passivation pattern 430b and another side surface of the channel isolation pattern 200 immediately adjacent to the side surface of the second passivation pattern 430b may be coplanar. The first passivation pattern 430a and the second passivation pattern 430b may have a high etch selectivity with respect to the channel isolation pattern 200. For example, the first passivation pattern 430a and the second passivation pattern 430b may have an etch selectivity greater than 1 with respect to the channel isolation pattern 200. The first passivation pattern 430a and the second passivation pattern 430b may have a low etch selectivity with respect to the first passivation film 410. For example, the first passivation pattern 430a and the second passivation pattern 430b may have an etching selectivity less than 1 with respect to the first passivation film 410. For example, the first passivation pattern 430a and the second passivation pattern 430b may include an oxide.For example, the first passivation pattern 430a and the second passivation pattern 430b may include SiO 2 .

[0163] The gate electrode pattern 310 of the present disclosure may have a width different from that of the channel isolation pattern 200. This reduces or prevents leakage current flow through the side surfaces of the gate electrode pattern 310 and the channel isolation pattern 200. The electric field relaxation pattern 320 of the present disclosure reduces or prevents electric field concentration between the gate electrode pattern 310 and the drain electrode pattern 520. The present disclosure may provide a semiconductor device 18 with improved electrical characteristics.

[0164] The present disclosure may eliminate the requirement for the etching selectivity of the first passivation film 410 relative to the channel isolation pattern 200. This may broaden the range of materials that can be used as the first passivation film 410. As a result, a semiconductor device 18 with improved electrical characteristics may be provided.

[0165] The above description of the embodiments of the technical concept of the present invention provides examples for explaining the technical concept of the present invention. Therefore, the technical concept of the present invention is not limited to the above embodiments, and it is apparent that various modifications and changes can be made by those skilled in the art within the technical concept of the present invention, such as by combining and implementing the embodiments. [Explanation of symbols]

[0166] 10,11,12,13,14,15,16,17,18 Semiconductor devices 110 Channel Layer 120 Channel Supply Layer 130 Two-dimensional electron gas (2DEG) layer 200 channel separation patterns 310 Gate electrode pattern 320 Electric field relaxation pattern 330 protruding pattern 410 First passivation film 420 Second passivation film 430a, 430b Passivation pattern 440 Third passivation film 510 Source electrode pattern 520 Drain electrode pattern 522 Second auxiliary drain electrode pattern 610 Additional electric field relaxation film 620 Additional electric field relaxation pattern 700 First auxiliary drain electrode pattern

Claims

1. a channel layer; a channel supply layer provided on the channel layer; a channel separation pattern provided on the channel supply layer; a gate electrode pattern provided on the channel isolation pattern; an electric field relaxation pattern protruding from a first side surface of the gate electrode pattern along a first direction parallel to an upper surface of the channel layer, the channel layer includes a channel formed adjacent to an interface between the channel layer and the channel supply layer, a size of the gate electrode pattern along the first direction is different from a size of the channel isolation pattern along the first direction; the gate electrode pattern and the electric field relaxation pattern form a single structure, The semiconductor device further includes a first passivation film provided between the electric field relaxation pattern and the channel supply layer, The semiconductor device further includes a first passivation pattern provided between the first passivation film and the channel isolation pattern, a second passivation pattern provided on a second side of the gate electrode pattern opposite to the first side of the gate electrode pattern; one side of the first passivation pattern and one side of the channel isolation pattern that are immediately adjacent to each other are coplanar with each other; One side of the second passivation pattern and the other side of the channel isolation pattern, which are immediately adjacent to each other, are coplanar with each other.

2. The semiconductor device according to claim 1 , wherein the size of the gate electrode pattern along the first direction is smaller than the size of the channel isolation pattern along the first direction.

3. the gate electrode pattern exposes a first upper surface of the channel isolation pattern; The semiconductor device according to claim 2 , wherein the first upper surface of the channel isolation pattern and the bottom surface of the electric field relaxation pattern face each other.

4. 4. The semiconductor device according to claim 3, wherein a size of said bottom surface of said electric field relaxation pattern along said first direction is larger than a size of said first upper surface of said channel isolation pattern along said first direction.

5. the gate electrode pattern exposes a second upper surface of the channel isolation pattern; the first and second upper surfaces of the channel separation pattern are spaced apart from each other along the first direction; 4. The semiconductor device according to claim 3, wherein a size of the first upper surface of the channel isolation pattern along the first direction is different from a size of the second upper surface of the channel isolation pattern along the first direction.

6. the channel isolation pattern is provided between the first passivation film and the channel supply layer; The semiconductor device according to claim 1 , wherein the gate electrode pattern penetrates the first passivation film and directly contacts the channel isolation pattern.

7. The semiconductor device of claim 6 , wherein the first passivation film and the first passivation pattern include different insulating materials.

8. the first passivation film includes a nitride; The semiconductor device of claim 7 , wherein the first passivation pattern comprises an oxide.

9. The semiconductor device of claim 7 , wherein the first passivation pattern is provided on the first side of the gate electrode pattern.

10. The semiconductor device of claim 9 , wherein the second passivation pattern is provided between the first passivation film and the channel isolation pattern.

11. a drain electrode pattern spaced apart from the gate electrode pattern along the first direction; a source electrode pattern provided on an opposite side of the drain electrode pattern with respect to the gate electrode pattern; a second auxiliary drain electrode pattern protruding from a side of the drain electrode pattern, The semiconductor device according to claim 6 , wherein the second auxiliary drain electrode pattern is provided on the first passivation film.

12. a second passivation film provided between the first passivation film and the electric field relaxation pattern; an additional electric field relaxation pattern provided between the second passivation film and the first passivation film, the additional electric field relaxation pattern is provided between the gate electrode pattern and the second auxiliary drain electrode pattern, The semiconductor device according to claim 11 , wherein the gate electrode pattern penetrates the second passivation film and the first passivation film and is in direct contact with the channel isolation pattern.

13. a third passivation film provided on the gate electrode pattern, the electric field relaxation pattern, and the second passivation film; an additional electric field mitigation film provided on the third passivation film; a first auxiliary drain electrode pattern provided on the third passivation film, The additional electric field mitigating film is electrically connected to the source electrode pattern, the first auxiliary drain electrode pattern is electrically connected to the drain electrode pattern; The semiconductor device of claim 12 , wherein the additional electric field mitigating film and the first auxiliary drain electrode pattern are spaced apart from each other.

14. a first passivation pattern provided between the first passivation film and the channel isolation pattern; a second passivation pattern provided on an opposite side of the first passivation pattern with respect to the gate electrode pattern, the first passivation film and the first passivation pattern each include a different insulating material; The semiconductor device of claim 13 , wherein the first passivation pattern and the second passivation pattern include the same material.

15. the first passivation film includes a nitride; The semiconductor device of claim 14 , wherein the first passivation pattern and the second passivation pattern include an oxide.

16. a second passivation film provided on the first passivation film and on the gate electrode pattern; a drain electrode pattern spaced apart from the gate electrode pattern along the first direction; a source electrode pattern provided on an opposite side of the drain electrode pattern with respect to the gate electrode pattern; an additional field mitigation film provided on the second passivation film; a first auxiliary drain electrode pattern provided on the drain electrode pattern, the electric field relaxation pattern is disposed between the second passivation film and the first passivation film, the additional electric field mitigation film overlaps the source electrode pattern along a second direction perpendicular to the upper surface of the channel layer; The additional electric field mitigating film is electrically connected to the source electrode pattern, The semiconductor device of claim 6 , wherein the first auxiliary drain electrode pattern is electrically connected to the drain electrode pattern.

17. a protrusion pattern protruding from a second side of the gate electrode pattern disposed opposite to the first side of the gate electrode pattern, The semiconductor device according to claim 1 , wherein said protruding pattern and said gate electrode pattern form a single structure.

18. 18. The semiconductor device according to claim 17, wherein a size of said electric field relaxation pattern along said first direction is larger than a size of said protruding pattern along said first direction.

19. The semiconductor device according to claim 1 , wherein the size of the channel isolation pattern along the first direction decreases as the pattern becomes farther from the channel supply layer.

20. The semiconductor device according to claim 1 , wherein the size of the gate electrode pattern along the first direction increases as the gate electrode pattern is farther from the channel supply layer.

21. a first passivation film provided between the electric field relaxation pattern and the channel supply layer; a drain electrode pattern spaced apart from the gate electrode pattern along the first direction; a source electrode pattern provided on an opposite side of the drain electrode pattern with respect to the gate electrode pattern, The semiconductor device according to claim 1 , wherein the source electrode pattern and the drain electrode pattern penetrate the first passivation film and the channel supply layer and contact the channel.

22. forming a channel supply layer and a channel separation pattern on the channel layer in this order; forming a first passivation film on the channel supply layer and the channel isolation pattern; forming an opening in the first passivation layer to expose an upper surface of the channel isolation pattern; forming a conductive material pattern on the channel isolation pattern; forming a source electrode pattern and a drain electrode pattern penetrating the first passivation film and the channel supply layer; forming an additional electric field relaxation pattern on the first passivation layer; forming a second auxiliary drain electrode pattern protruding from a side of the drain electrode pattern onto the first passivation layer; forming a second passivation film on the additional electric field relaxation pattern, the second auxiliary drain electrode pattern, and the first passivation film; the channel layer includes a channel formed adjacent to an interface between the channel layer and the channel supply layer, the conductive material pattern extends from inside the opening to outside the opening; The method may further include forming a preliminary passivation pattern on the channel isolation pattern before performing the first passivation film forming process, wherein an insulating material of the first passivation film is different from an insulating material of the first passivation pattern, forming a third passivation film on the second passivation film and the conductive material pattern; forming an additional electric field mitigation film and a first auxiliary drain electrode pattern on the third passivation film; The formation of the additional electric field mitigation film and the first auxiliary drain electrode pattern includes: forming a preliminary additional electric field mitigation film on the source electrode pattern, along an upper surface of the third passivation film, and extending onto the drain electrode pattern; patterning the preliminary additional electric field mitigation film to expose an upper surface of the third passivation film between the conductive material pattern and the drain electrode pattern; the additional electric field mitigation film is electrically connected to the source electrode pattern; The first auxiliary drain electrode pattern is electrically connected to the drain electrode pattern.

23. The method for manufacturing a semiconductor device according to claim 22 , wherein the opening exposes a portion of the upper surface of the channel isolation pattern.

24. 24. The method for manufacturing a semiconductor device according to claim 23, wherein a distance between the opening and one side surface of the channel isolation pattern is different from a distance between the opening and another side surface of the channel isolation pattern.

25. the width of the opening is narrower as it is adjacent to the channel separation pattern, 24. The method for manufacturing a semiconductor device according to claim 23, wherein the width of the opening is a size of the opening along a first direction parallel to an upper surface of the channel layer.

26. The source electrode pattern and the drain electrode pattern are spaced apart from each other with the channel separation pattern therebetween, 23. The method of manufacturing a semiconductor device according to claim 22, wherein the opening penetrates the second passivation film and the first passivation film to expose the upper surface of the channel isolation pattern.

27. the preliminary passivation pattern has an etching selectivity with respect to the channel isolation pattern; 23. The method of manufacturing a semiconductor device according to claim 22, wherein the first passivation film has an etching selectivity with respect to the preliminary passivation pattern.

28. The formation of the openings is performing a first selective etching process on the first passivation film to expose an upper surface of the preliminary passivation pattern; 28. The method of claim 27, further comprising: performing a second selective etching process on the preliminary passivation pattern to expose the top surface of the channel isolation pattern.

29. the first passivation film includes a nitride; 28. The method of claim 27, wherein the preliminary passivation pattern comprises an oxide.

30. a semiconductor layer; a p-type semiconductor pattern provided on the semiconductor layer and on a depletion layer; a conductive material pattern provided on the p-type semiconductor pattern, a width of a bottom of the conductive material pattern in a first direction parallel to the top surface of the semiconductor layer is different from a width of the p-type semiconductor pattern in the first direction; a width of an upper portion of the conductive material pattern in the first direction is wider than a width of a lower portion of the conductive material pattern; a first passivation film provided between the conductive material pattern and the semiconductor layer; a first passivation pattern provided between the first passivation film and the p-type semiconductor pattern, the first passivation pattern being provided on a first side of the conductive material pattern; a second passivation pattern provided between the first passivation film and the p-type semiconductor pattern, the second passivation pattern being provided on a second side of the conductive material pattern; a source electrode pattern and a drain electrode pattern provided on the semiconductor layer, the source electrode pattern and the drain electrode pattern sandwiching the conductive material pattern and spaced apart from each other in the first direction; the semiconductor layer includes a two-dimensional electron gas (2DEG) layer; the two-dimensional electron gas (2DEG) layer includes a depletion region; one side of the first passivation pattern and one side of the p-type semiconductor pattern that are immediately adjacent to each other are coplanar with each other; One side of the second passivation pattern and the other side of the p-type semiconductor pattern, which are immediately adjacent to each other, are coplanar with each other.

31. The semiconductor device of claim 30 , wherein the width of the lower portion of the conductive material pattern is narrower than the width of the p-type semiconductor pattern.

32. 31. The semiconductor device of claim 30, wherein a distance between the upper portion of the conductive material pattern and the drain electrode pattern is smaller than a distance between the lower portion of the conductive material pattern and the drain electrode pattern.

33. The semiconductor device of claim 30 , wherein a distance between the top of the conductive material pattern and the drain electrode pattern is smaller than a distance between the p-type semiconductor pattern and the drain electrode pattern.

34. The semiconductor device of claim 30 , wherein the width of the top of the conductive material pattern is wider than the width of the p-type semiconductor pattern.

35. The method further includes providing an additional electric field mitigation film on the conductive material pattern, The semiconductor device of claim 30 , wherein a distance between the additional electric field mitigation film and the drain electrode pattern is smaller than a distance between the top of the conductive material pattern and the drain electrode pattern.

36. an auxiliary drain electrode pattern protruding from a side of the drain electrode pattern toward the conductive material pattern; The semiconductor device of claim 30 , further comprising: an additional electric field relaxation pattern provided between the conductive material pattern and the auxiliary drain electrode pattern.

37. 31. The semiconductor device of claim 30, wherein a distance between the upper portion of the conductive material pattern and the source electrode pattern is smaller than a distance between the lower portion of the conductive material pattern and the source electrode pattern.

38. The upper portion of the conductive material pattern is an electric field relaxation pattern protruding from a first side surface of the lower portion of the conductive material pattern toward the drain electrode pattern; a protrusion pattern protruding from a second side surface of the lower portion of the conductive material pattern toward the source electrode pattern, 38. The semiconductor device according to claim 37, wherein the width of said electric field relaxation pattern is wider than the width of said protruding pattern.

39. The semiconductor device further includes a first passivation pattern and a second passivation pattern provided on a first upper surface and a second upper surface of the p-type semiconductor pattern exposed by the conductive material pattern, respectively; 31. The semiconductor device of claim 30, wherein the first passivation pattern and the second passivation pattern are spaced apart with the conductive material pattern therebetween.

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