Electronic circuit, power conversion device, and data generation method

Abstract

To provide an electronic circuit which determines waveform data of a drive current so as to achieve both of reduction of a power loss and suppression of noise in the time of turn-on of a switching element.SOLUTION: An electronic circuit according to an embodiment includes a processing circuit. The processing circuit generates waveform data of the drive current supplied to the switching element, provides the waveform data to the drive circuit of the switching element, and corrects the waveform data on the basis of the load current flowing in a load connected to the switching element and the surge current of the switching element in the time of turn-on of the switching element.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present embodiment relates to an electronic circuit, a power conversion device, and a data generation method. [Background technology]

[0002] In the field of power electronics, semiconductor switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are used. In circuits that include these switching elements, power loss can be reduced by speeding up the switching operation of the elements. However, if the switching operation of the elements is made too fast, ringing occurs in the current that flows when the elements are turned on or off. This current ringing can cause noise to be generated. In other words, there is a trade-off between reducing power loss and suppressing noise.

[0003] Active gate control technology has been researched as a method for optimizing the above trade-off. In active gate control technology, the waveforms of the drive signals for turning on and off a switching element are determined experimentally or theoretically in advance so as to achieve both reduced power loss and noise suppression, and these waveform data are stored in a memory circuit. The drive circuit for the switching element generates a drive signal according to the waveform data provided by the memory circuit and drives the switching element using the drive signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6355775 Summary of the Invention [Problem to be solved by the invention]

[0005] The object of this embodiment is to provide an electronic circuit that generates waveform data of a drive current that achieves both a reduction in power loss and a suppression of noise when a switching element is turned on. [Means for solving the problem]

[0006] In order to solve the above problems, the electronic circuit according to this embodiment includes a processing circuit that generates waveform data of the drive current supplied to the switching element, provides the waveform data to a drive circuit for the switching element, and modifies the waveform data based on the load current flowing through a load connected to the switching element and the surge current of the switching element when the switching element is turned on.

[0007] In addition, the power conversion device according to this embodiment includes a power conversion circuit including two switching elements that form an arm pair and two drive circuits that supply drive currents to the two switching elements, respectively, and a processing circuit, and the processing circuit generates waveform data of the drive current, provides the waveform data to the drive circuit, and when the switching element is turned on, corrects the waveform data based on the load current flowing in a load connected to the switching element and the surge current of the switching element.

[0008] In addition, the data generation method according to this embodiment generates waveform data of the drive current supplied to the switching element, provides the waveform data to a drive circuit for the switching element, and when the switching element is turned on, modifies the waveform data based on the load current flowing through a load connected to the switching element and the surge current of the switching element. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing the configuration of a motor control system according to a first embodiment. [Figure 2] Equivalent circuit when the switching element is turned on. [Figure 3] 5 is a timing chart illustrating the operation of a switching element when it is turned on. [Figure 4] 5 is a timing chart illustrating a preferable operation when a switching element is turned on. [Figure 5] 6 is a timing chart illustrating undesirable behavior when a switching element is turned on. [Figure 6] 6 is a timing chart illustrating undesirable behavior when a switching element is turned on. [Figure 7] FIG. 1 is a diagram showing the internal configuration of an electronic circuit. [Figure 8] 5A and 5B are diagrams showing examples of a method for selecting waveform data by a selection circuit. [Figure 9] 10 is a flowchart illustrating an operation of determining waveform data by an electronic circuit. [Figure 10] FIG. 10 is a diagram showing a process until waveform data is determined. [Figure 11] FIG. 10 is a diagram showing an example of determined waveform data. [Figure 12] FIG. 10 is a diagram showing another example of determined waveform data. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, the present embodiment will be described with reference to the drawings. In the drawings, the same or corresponding elements are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

[0011] (Embodiment 1) 1 is a diagram showing the configuration of a motor control system 100 according to embodiment 1. The motor control system 100 includes a three-phase AC motor 1 as a load, a DC power supply Vdc, switching elements 11a-11f that constitute a three-phase inverter circuit 10, and drive circuits 12a-12f that drive the switching elements 11a-11f.

[0012] The switching elements 11a and 11b are N-channel MOSFETs. The switching elements 11a and 11b form a U-phase arm pair of the inverter circuit 10. The drive circuit 12a controls the gate current serving as the drive current for the switching element 11a to control the switching operation, i.e., turn-on and turn-off, of the switching element 11a. The drive circuit 12b controls the gate current for the switching element 11b to control the switching operation of the switching element 11b.

[0013] Similarly, switching elements 11c and 11d are N-channel MOSFETs. Switching elements 11c and 11d form a V-phase arm pair of inverter circuit 10. Drive circuit 12c controls the gate current of switching element 11c to control the switching operation of switching element 11c. Drive circuit 12d controls the gate current of switching element 11d to control the switching operation of switching element 11d.

[0014] Similarly, switching elements 11e and 11f are N-channel MOSFETs. Switching elements 11e and 11f form a W-phase arm pair of inverter circuit 10. Drive circuit 12e controls the gate current of switching element 11e to control the switching operation of switching element 11e. Drive circuit 12f controls the gate current of switching element 11f to control the switching operation of switching element 11f.

[0015] The motor control system 100 also includes an electronic circuit 20. Prior to operation of the motor control system 100, the electronic circuit 20 determines and stores waveform data of the gate currents of the switching elements 11a-11f. During operation of the motor control system 100, the electronic circuit 20 provides the waveform data of the gate currents to the drive circuits 12a-12f of the switching elements 11a-11f based on the U-phase, V-phase, and W-phase currents of the motor 1.

[0016] In detail, the electronic circuit 20 provides waveform data of gate currents to the drive circuits 12a and 12b based on the U-phase current of the motor 1. The drive circuit 12a generates a gate current in accordance with the waveform data provided from the electronic circuit 20 and supplies it to the switching element 11a. The drive circuit 12b generates a gate current in accordance with the waveform data provided from the electronic circuit 20 and supplies it to the switching element 11b.

[0017] Similarly, the electronic circuit 20 provides gate current waveform data to the drive circuits 12c and 12d based on the V-phase current of the motor 1. The drive circuit 12c generates a gate current in accordance with the waveform data provided from the electronic circuit 20 and supplies it to the switching element 11c. The drive circuit 12d generates a gate current in accordance with the waveform data provided from the electronic circuit 20 and supplies it to the switching element 11d.

[0018] Similarly, the electronic circuit 20 provides waveform data of gate currents to the drive circuits 12e and 12f based on the W-phase current of the motor 1. The drive circuit 12e generates a gate current in accordance with the waveform data provided from the electronic circuit 20 and supplies it to the switching element 11e. The drive circuit 12f generates a gate current in accordance with the waveform data provided from the electronic circuit 20 and supplies it to the switching element 11f.

[0019] Here, the operation of the switching elements 11a to 11f in Fig. 1 when they are turned on will be described. In the following explanation, we will focus on the switching element 11a and explain the operation when the switching element 11a is turned on. However, the following explanation also applies to the other switching elements 11b to 11f.

[0020] Figure 2 shows an equivalent circuit of the switching element 11a in Figure 1 when it is turned on. When the switching element 11a is turned on, the switching element 11b, which forms a U-phase arm pair together with the switching element 11a, is in the off state. In Figure 2, the switching element 11b in the off state is represented by the diode Dio and the parasitic capacitor Cdio.

[0021] The inductor Lload represents the inductance of the load, that is, the motor 1. The inductor Ld represents the parasitic inductance of the wiring connecting the drain terminals of the switching elements 11a and 11b together.

[0022] The switching element 11a has a parasitic capacitor Cgs between the gate and source, a parasitic capacitor Cgd between the gate and drain, and a parasitic capacitor Cds between the drain and source. The drive circuit 12a supplies a gate current Ig to the gate terminal of the switching element 11a.

[0023] Figure 3 is a time chart illustrating the operation of switching element 11a when it is turned on. In the initial state shown on the left side of Figure 3, the gate current Ig supplied from drive circuit 12a is 0, and the gate voltage of switching element 11a is also 0. Therefore, switching element 11a is in the off state, the drain current Id is 0, and the drain voltage Vd is equal to the voltage Vdio on the anode side of diode Dio.

[0024] At time t1, the drive circuit 12a increases the gate current Ig in a stepwise manner, which starts charging the parasitic capacitor Cgs between the gate and source of the switching element 11a, and the gate voltage of the switching element 11a increases.

[0025] At time t2, when the gate voltage of the switching element 11a exceeds the threshold voltage, a channel is formed and a drain current Id begins to flow. The drain current Id increases as the gate voltage increases. In Figure 3, the increase in the drain current Id is approximated by a linear function.

[0026] At this time, the diode Dio is on, and the voltage Vdio on its anode side remains constant. Meanwhile, the drain current Id flows, causing a voltage Vo to appear across the inductor Ld, and the drain voltage Vd drops.

[0027] At time t3, when the drain current Id becomes equal to the steady-state component of the current flowing through the inductor Lload, i.e., the load current Idc, the diode Dio turns off and the anode voltage Vdio begins to drop. At this point, a resonant loop is formed as shown in Figure 2, causing ringing in the drain current Id. The peak value of the ringing amplitude of the drain current Id, i.e., the magnitude of the surge current Isurge, is proportional to the voltage Vo across the inductor Ld at the start of resonance.

[0028] As described above, the first embodiment aims to achieve both a reduction in power loss and a suppression of noise when the switching element 11a is turned on.

[0029] First, from the perspective of reducing power loss, a larger gate current Ig is better. A larger gate current Ig causes the gate voltage to rise faster and the slope of the drain current Id to become steeper. As a result, the time until turn-on is completed is shortened, and power loss is reduced.

[0030] On the other hand, from the perspective of noise suppression, a smaller gate current Ig is better. As mentioned above, the peak value of the amplitude of the ringing of the drain current Id, which causes noise, i.e., the magnitude of the surge current Isurge, is proportional to the voltage Vo across the inductor Ld at the start of resonance. Therefore, by reducing the voltage Vo across the inductor Ld at the start of resonance, the surge current Isurge, which causes noise, can be reduced.

[0031] To reduce the voltage Vo across the inductor Ld at the start of resonance, it is better to have a small gate current Ig. A small gate current Ig reduces the slope of the drain current Id, which reduces the rate of change of the current flowing through the inductor Ld, thereby reducing the voltage Vo across the inductor Ld at the start of resonance. Therefore, from the perspective of noise suppression, a small gate current Ig is better.

[0032] From the above considerations, in order to achieve both reduction in power loss of the switching element 11a and suppression of noise, it is preferable to supply a large gate current (first current value Ig1) during the period TP from the start of supply of the gate current Ig to just before time t3 when the resonant loop is formed, as shown in Figure 4, and to supply a small gate current (second current value Ig2) during the period thereafter.

[0033] Supplying a large gate current until just before the resonant loop is formed shortens the time until turn-on is completed, reducing power loss. Also, supplying a small gate current just before the resonant loop is formed reduces the voltage Vo across the inductor Ld at the start of resonance, reducing the peak value of the ringing of the drain current Id, which causes noise, i.e., the surge current Isurge.

[0034] As shown in Figure 5, if the period TP is too long and the timing at which the gate current Ig decreases is delayed from the timing t3 at which the resonant loop is formed, power loss is reduced, but the ringing of the drain current Id, which causes noise, is not suppressed because the voltage Vo across the inductor Ld at the start of resonance is large.

[0035] Also, as shown in Figure 6, if the period TP is too short and the timing at which the gate current Ig decreases is too early compared to the timing t3 at which the resonant loop is formed, the ringing of the drain current Id that causes noise is suppressed, but the effect of reducing power loss is low.

[0036] Therefore, it is most preferable that the length of the period TP, that is, the timing at which the gate current Ig decreases, be immediately before the timing t3 at which the resonant loop is formed, as shown in FIG.

[0037] As described above, the timing t3 at which the resonant loop is formed is the timing at which the drain current Id becomes equal to the load current Idc flowing through the motor 1 and the diode Dio turns on. In other words, the timing t3 at which the resonant loop is formed varies depending on the value of the load current Idc flowing through the motor 1. Taking this into consideration, in the first embodiment, the length of the period TP of the first current value Ig1 in the gate current Ig is varied depending on the value of the load current Idc.

[0038] Fig. 7 is a diagram showing the internal configuration of the electronic circuit 20 of Fig. 1. The electronic circuit 20 includes a setting circuit 21, a generating circuit 22, a providing circuit 23, a determining circuit 24, a memory circuit 25, and a selecting circuit 26. The electronic circuit 20 also includes a first detecting circuit 27 that detects the load current Idc, which is the steady component of the current flowing through the motor 1, and a second detecting circuit 28 that detects the surge current Isurge, which is the peak value of the amplitude of the ringing of the drain current Id.

[0039] At least one of the setting circuit 21, the generating circuit 22, the providing circuit 23, the determining circuit 24, and the selecting circuit 26 may be included in the processing circuit 30. The processing circuit 30 is realized by at least one processor. The processor includes, for example, a control circuit and an arithmetic circuit, and is realized by a circuit that performs analog signal processing or a circuit that performs digital signal processing. The processor may be a CPU (Central Processing Unit), a DSP (Digital Signal Processor), a general-purpose processor, a microprocessor, an ASIC, an FPGA, a semiconductor chip, a discrete component, or a combination thereof.

[0040] The setting circuit 21 sets values ​​of N reference currents I1 to IN that serve as a reference for generating and selecting waveform data of the gate currents Ig of the switching elements 11a to 11f, where I1>...''>IN>0.

[0041] The generation circuit 22 generates waveform data of the gate current Ig supplied to the switching elements 11a-11f from the drive circuits 12a-12f when turning on the switching elements 11a-11f prior to operation of the motor control system 100. The generation circuit 22 also corrects the waveform data based on the load current Idc flowing through the motor 1 and the surge current Isurge of the switching elements 11a-11f.

[0042] Prior to operation of the motor control system 100, the providing circuit 23 provides the waveform data generated or modified by the generating circuit 22 to the driving circuits 12a to 12f of the switching elements 11a to 11f, thereby driving the switching elements 11a to 11f with gate currents Ig that correspond to the waveform data.

[0043] Prior to operation of the motor control system 100, the decision circuit 24 determines waveform data corresponding to the load current Idc flowing through the motor 1 and the surge current Isurge of the switching elements 11a-11f when the switching elements 11a-11f are turned on. The decision circuit 24 determines N pieces of waveform data each having a different length of the period TP of the first current value Ig1 according to the value of the load current Idc.

[0044] The memory circuit 25 includes N lookup tables (LUT_1 to LUT_N). N pieces of waveform data determined by the determination circuit 24 are stored in LUT_1 to LUT_N.

[0045] When the motor control system 100 is in operation, when the switching elements 11a to 11f are turned on, the selection circuit 26 selects one of the N pieces of waveform data stored in the LUT_1 to LUT_N of the memory circuit 25 based on the load current Idc of the motor 1 detected by the first detection circuit 27, and provides the selected waveform data to the drive circuits 12a to 12f of the switching elements 11a to 11f.

[0046] Specifically, when turning on the switching element 11a or 11b that constitutes the U-phase arm pair, the selection circuit 26 selects one from the N waveform data stored in the LUT_1 to LUT_N in the storage circuit 25 based on the U-phase load current Idc detected by the first detection circuit 27.

[0047] Similarly, when turning on the switching element 11c or 11d that constitutes the V-phase arm pair, the selection circuit 26 selects one from the N waveform data stored in the LUT_1 to LUT_N in the storage circuit 25 based on the V-phase load current Idc detected by the first detection circuit 27.

[0048] Similarly, when turning on the switching element 11e or 11f that constitutes the W-phase arm pair, the selection circuit 26 selects one from the N waveform data stored in the LUT_1 to LUT_N in the storage circuit 25 based on the W-phase load current Idc detected by the first detection circuit 27.

[0049] FIG. 8 is a diagram showing an example in the case of N = 3 regarding the method of selecting waveform data by the selection circuit 26. Waveform data D1 to D3 with different lengths of the period TP are stored in LUT_1 to LUT_3. Also, three reference currents I1 to I3 serving as criteria for selecting waveform data are defined. However, I1 > I2 > I3 > 0.

[0050] When the load current Idc is greater than or equal to the reference current I1, that is, when Idc ≧ I1, the waveform data D1 stored in LUT_1 is selected.

[0051] When the load current Idc is less than the reference current I1 and greater than or equal to the reference current I2, that is, when I2 ≦ Idc < I1, the waveform data D2 stored in LUT_2 is selected.

[0052] When the load current Idc is less than the reference current I2 and greater than or equal to the reference current I3, that is, when I3 ≦ Idc < I2, the waveform data D3 stored in LUT_3 is selected.

[0053] Next, a specific operation of the electronic circuit 20 according to the first embodiment when determining waveform data of the gate current Ig of the switching elements 11a to 11f will be described. Fig. 9 is a flowchart illustrating the operation of the electronic circuit 20 when determining waveform data of the gate current Ig. The following description will focus on the switching element 11a. However, the following description also applies to the other switching elements 11b to 11f.

[0054] In step S1, the setting circuit 21 sets the value of the reference current In (n=1 to N) that serves as a reference when generating waveform data of the gate current Ig. For example, when N=3, the setting circuit 21 sets values ​​of I1, I2, and I3, where I1>I2>I3>0. In step S2, the setting circuit 21 sets the value of the index n to 1.

[0055] In step S3, generation circuit 22 sets an initial value of the length of period TP according to the value of index n, and generates (temporary) waveform data Dn. For example, when n=1, the initial value of the length of period TP of waveform data D1 is set to the maximum value allowed by the specifications of switching element 11a. Also, when n>1, the initial value of the length of period TP of waveform data Dn is set to the length of period TP of waveform data Dn-1 determined in step S8, which will be described later.

[0056] In step S4, the providing circuit 23 provides the waveform data Dn generated in step S3 above or the waveform data Dn corrected in step S7, which will be described later, to the driving circuit 12a. For example, when n=1, the waveform data D1 is provided to the driving circuit 12a. The driving circuit 12a generates a gate current Ig in accordance with the provided waveform data Dn and supplies it to the switching element 11a. This starts turning on the switching element 11a, and the load current Idc of the motor 1, which is detected by the first detection circuit 27, increases.

[0057] In step S5, the determination circuit 24 obtains from the second detection circuit 28 a first surge current value when the load current Idc = the reference current In - ΔIa and a second surge current value when the load current Idc = the reference current In + ΔIb, where ΔIa and ΔIb are predetermined first and second minute values.

[0058] For example, when n=1, a first surge current value is obtained when the load current Idc=reference current I1-ΔIa, and a second surge current value is obtained when the load current Idc=reference current I1+ΔIb. The magnitudes of the first minute value ΔIa and the second minute value ΔIb are arbitrary, but are set to, for example, about 1 to 10 percent of the difference between the reference current In and the reference current In+1.

[0059] In step S6, the decision circuit 24 determines whether the difference between the first surge current value and the second surge current value is equal to or greater than a predetermined value ΔTH. If the difference between the first surge current value and the second surge current value is less than the predetermined value ΔTH (step S6=NO), the process proceeds to step S7. On the other hand, if the difference between the first surge current value and the second surge current value is equal to or greater than the predetermined value ΔTH (step S6=YES), the process proceeds to step S8.

[0060] In step S7, the generation circuit 22 corrects the waveform data Dn provided in step S4 to waveform data Dn in which the length of the period TP is shortened by a predetermined amount. For example, when n=1, the waveform data D1 is corrected to waveform data D1 in which the length of the period TP is shortened by a predetermined amount. Then, the process returns to step S4.

[0061] In step S8, the determination circuit 24 acquires the current value of the period TP from the generation circuit 22 and determines the length of the period TP of the waveform data Dn to be the acquired value. The determination circuit 24 stores the waveform data Dn having the determined period TP in the corresponding lookup table. For example, when n=1, the waveform data D1 having the determined period TP is stored in LUT_1.

[0062] In step S9, the setting circuit 21 determines whether the index n is equal to N. If n < N, that is, if the storage of the N waveform data in the look-up table has not been completed (step S9 = NO), the setting circuit 21 adds 1 to the value of the index n (step S10), and the process returns to step S3. On the other hand, if n = N, that is, if the storage of the N waveform data in the look-up table has been completed (step S9 = YES), the process ends.

[0063] FIG. 10 is a diagram showing a state until the length of the period TP of the waveform data D1 is shortened by a predetermined amount and determined. In the upper part of FIG. 10, the first surge current value and the second surge current value are equal and both are large values, and the difference between the two is less than a predetermined value ΔTH (step S6 = NO in FIG. 9). This means that due to the period TP being too long, the timing at which the gate current Ig decreases is delayed compared to the timing at which the resonance loop is formed. In this case, although the power loss is reduced, the ringing of the drain current Id, which causes noise, is not suppressed. Therefore, the generation circuit 22 shortens the length of the period TP of the waveform data D1 by a predetermined amount (step S7 in FIG. 9).

[0064] In the middle part of FIG. 10, the first surge current value and the second surge current value are slightly different but both are large values, and the difference between the two is less than a predetermined value ΔTH (step S6 = NO in FIG. 9). This means that due to the period TP still being too long, the timing at which the gate current Ig decreases is still delayed compared to the timing at which the resonance loop is formed. In this case, although the power loss is reduced, the ringing of the drain current Id, which causes noise, is not sufficiently suppressed. Therefore, the generation circuit 22 further shortens the length of the period TP of the waveform data D1 by a predetermined amount (step S7 in FIG. 9).

[0065] In the lower part of FIG. 10, the first surge current value and the second surge current value are significantly different from each other, and the difference between them is equal to or greater than a predetermined value ΔTH (step S6 in FIG. 9 = YES). That is, the surge current value changes suddenly near the point where the load current Idc is equal to the reference current I1. This means that the timing at which the gate current Ig decreases and the timing at which the resonant loop is formed are almost the same. In this case, power loss is reduced, and the ringing of the drain current Id, which causes noise, is also sufficiently suppressed. That is, power loss reduction and noise suppression are both achieved. Therefore, the decision circuit 24 sets the length of the period TP of the waveform data D to the current value (step S8 in FIG. 7).

[0066] 11 is a diagram showing an example of waveform data Dn determined according to the flowchart of FIG. 9 when N=3. Waveform data D1 to D3, each having a different length of period TP, are determined according to the value of load current Idc. In this case, the larger the value of load current Idc, the longer the period TP. This is because the larger the value of load current Idc, the longer it takes for the drain current Id to become equal to the load current Idc and form a resonant loop.

[0067] Fig. 12 is a diagram showing another example of waveform data. After time t3 after the waveform shown in Fig. 11 is determined, the gate current Ig may be increased again, as shown by the dotted line in the lower part of Fig. 12. By increasing the gate current Ig again, the time it takes for the gate voltage of the switching element to reach the power supply voltage of the drive circuit can be shortened, and unintended operation of the power device due to fluctuations in gate voltage caused by unexpected noise can be prevented.

[0068] As described above, the electronic circuit 20 according to the first embodiment includes the processing circuit 30. The processing circuit 30 executes a generation process for generating waveform data of a drive current supplied to a switching element, a provision process for providing the waveform data to a drive circuit of the switching element, and a determination process for correcting the waveform data based on a load current Idc flowing through a load connected to the switching element and a surge current Isurge of the switching element when the switching element is turned on, and determining waveform data corresponding to the load current Idc and the surge current Isurge.

[0069] Due to the above-mentioned features, the electronic circuit 20 according to the first embodiment can generate waveform data of a drive current that achieves both a reduction in power loss and a suppression of noise when a switching element is turned on.

[0070] Furthermore, in the electronic circuit 20 according to the first embodiment, the reference current In includes N reference currents I1 to IN. In the above-described determination process, the processing circuit 30 modifies and determines waveform data for each of the N reference currents I1 to IN. Specifically, the waveform data determined for the first reference current I1 is waveform data corresponding to the load current Idc being equal to or greater than the first reference current I1. The waveform data determined for the nth reference current In is waveform data corresponding to the load current Idc being equal to or greater than the nth reference current In and less than the n-1th reference current In-1.

[0071] Due to the above-mentioned features, the electronic circuit 20 according to the first embodiment can determine waveform data of the drive current that achieves both reduction in power loss and suppression of noise when the switching element is turned on, depending on the value of the load current Idc.

[0072] In the first embodiment, when determining the length of the period TP in step S8 of Fig. 7, the period may be modified to be even shorter than the current value. Providing a margin in this way makes it possible to more reliably suppress noise.

[0073] Furthermore, in the first embodiment described above, when correcting and determining the length of the period TP of the waveform data, the initial value of the period TP is set as long as possible and then shortened by a predetermined amount. This means that from an initial state where the effect of reducing power loss is large but noise suppression is insufficient, the effect of reducing power loss is gradually weakened, and the period TP is shortened until a state is reached where the surge current that causes noise is sufficiently suppressed. In other words, noise suppression is given more importance than power loss reduction.

[0074] Alternatively, when correcting or determining the length of the period TP of the waveform data, the initial value of the period TP may be set as short as possible and then extended by a predetermined amount. In this case, the period TP is extended from the initial state, where the noise suppression effect is sufficient but the power loss is large, to the limit where the noise suppression effect is maintained in order to reduce the power loss. In other words, this means that reducing power loss is given more importance than suppressing noise.

[0075] (Variation) In the first embodiment described above, the three-phase inverter circuit 10 is configured by the switching elements 11a to 11f. In each pair of switching elements, both elements are N-channel MOSFETs. Instead, for example, in a converter circuit, one switching element in each pair of switching elements is an N-channel MOSFET and the other switching element is a diode.

[0076] The switching elements 11a to 11f are not limited to MOSFETs. For example, the switching elements 11a to 11f may be IGBTs or BJTs (Bipolar Junction Transistors). Various materials, such as Si (Silicon), SiC (Silicon Carbide), or GaN (Gallium Nitride), can be used as semiconductors for the switching elements 11a to 11f.

[0077] Although several embodiments have been described, these embodiments are presented as examples and are not intended to limit the scope of the embodiments. These embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, and combinations can be made without departing from the spirit of the embodiments. These embodiments and their modifications are included in the scope and spirit of the embodiments, as well as in the scope of the claims and their equivalents.

[0078] This embodiment can also be configured as follows. [Item 1] generating waveform data of a drive current to be supplied to a switching element; providing the waveform data to a drive circuit for the switching element; an electronic circuit comprising a processing circuit that corrects the waveform data based on a load current flowing through a load connected to the switching element and a surge current of the switching element when the switching element is turned on; [Item 2] The processing circuit sets a reference current; 2. The electronic circuit of claim 1, wherein the processing circuit modifies the waveform data based on a first surge current value when the load current is smaller than the reference current by a predetermined first value and a second surge current value when the load current is larger than the reference current by a predetermined second value. [Item 3] the waveform data includes a period of a first current value and a period of a second current value that is smaller than the first current value; 3. The electronic circuit of claim 1, wherein the processing circuit modifies the waveform data by modifying a period of the first current value. [Item 4] The electronic circuit described in item 3, wherein the processing circuit shortens or extends the length of the period of the first current value by a predetermined amount, and determines the period of the first current value when the difference between the first surge current value and the second surge current value becomes equal to or greater than a predetermined value. [Item 5] the reference currents include N reference currents from first to Nth (N is an integer of 2 or more), 5. The electronic circuit according to any one of items 2 to 4, wherein the processing circuit determines the waveform data for each of the N reference currents. [Item 6] 6. The electronic circuit according to item 5, wherein the first value and the second value are values ​​in the range of 1 to 10 percent of the difference between an nth reference current (n is an integer from 1 to N) and an n+1th reference current. [Item 7] the waveform data determined for a first reference current is waveform data corresponding to when the load current is equal to or greater than the first reference current; 7. The electronic circuit according to item 5 or 6, wherein the waveform data determined for the nth (n is an integer from 2 to N) reference current is waveform data corresponding to when the load current is equal to or greater than the nth reference current and less than the n-1th reference current. [Item 8] 8. The electronic circuit according to any one of items 1 to 7, further comprising a first detection circuit that detects the load current. [Item 9] 9. The electronic circuit according to any one of items 1 to 8, further comprising a second detection circuit that detects the surge current. [Item 10] 10. The electronic circuit according to any one of items 1 to 9, further comprising a memory circuit that stores the corrected waveform data. [Item 11] The electronic circuit according to any one of items 1 to 10, The electronic circuit further comprises a drive circuit that generates a drive current in accordance with the waveform data of the drive current provided from the electronic circuit and supplies the drive current to the switching element. [Item 12] 12. The electronic circuit according to any one of items 1 to 11, further comprising the switching element driven by the drive current supplied from the drive circuit. [Item 13] Two switching elements constituting an arm pair; two drive circuits for supplying drive currents to the two switching elements, respectively; a power conversion circuit including: Processing circuit and Equipped with The processing circuitry generating the waveform data of the driving current; providing the waveform data to the driver circuit; The power conversion device corrects the waveform data based on a load current flowing through a load connected to the switching element and a surge current of the switching element when the switching element is turned on. [Item 14] Item 14. The power conversion device according to item 13, comprising three of the power conversion circuits. [Item 15] generating waveform data of a drive current to be supplied to a switching element; providing the waveform data to a drive circuit for the switching element; The data generating method modifies the waveform data based on a load current flowing through a load connected to the switching element and a surge current of the switching element when the switching element is turned on. [Explanation of symbols]

[0079] 1 Motor (load) 10 Inverter circuit 11a Switching element 11b Switching element 11c Switching element 11d Switching element 11e Switching element 11f switching element 12a Drive circuit 12b Drive circuit 12c Drive Circuit 12d Drive circuit 12e Drive circuit 12f drive circuit 20 Electronic circuits 21 Setting circuit 22 Generation circuit 23 Provided circuit 24 Decision Circuit 25 Memory circuit 26 Selection circuit 27 First detection circuit 28 Second detection circuit 30 Processing circuit Dn Waveform data Idc load current Id Drain current Ig Gate current (drive current) Ig1 First current value Ig2 Second current value In Reference current Isurge surge current IΔa first small value IΔb second small value TP period Vd Drain voltage Vo is the voltage across the inductor Ld

Claims

1. generating waveform data of a drive current to be supplied to a switching element; providing the waveform data to a drive circuit for the switching element; a processing circuit that corrects the waveform data based on a load current flowing through a load connected to the switching element and a surge current of the switching element when the switching element is turned on; the processing circuit sets a reference current, and modifies the waveform data based on a first surge current value when the load current is smaller than the reference current by a predetermined first value, and a second surge current value when the load current is larger than the reference current by a predetermined second value. electronic circuit.

2. the waveform data includes a period of a first current value and a period of a second current value that is smaller than the first current value; The electronic circuit of claim 1 , wherein the processing circuitry modifies the waveform data by modifying a period of the first current value.

3. 3. The electronic circuit according to claim 2, wherein the processing circuit shortens or extends the length of the period of the first current value by a predetermined amount, and determines the period of the first current value when a difference between the first surge current value and the second surge current value becomes equal to or greater than a predetermined value.

4. the reference currents include N reference currents from first to Nth (N is an integer of 2 or more), The electronic circuit of claim 1 , wherein the processing circuit determines the waveform data for each of the N reference currents.

5. 5. The electronic circuit of claim 4, wherein the first value and the second value are values ​​in the range of 1 to 10 percent of the difference between an nth reference current (n is an integer from 1 to N) and an n+1th reference current.

6. the waveform data determined for a first reference current is waveform data corresponding to when the load current is equal to or greater than the first reference current; 5. The electronic circuit of claim 4, wherein the waveform data determined for the nth (n is an integer from 2 to N) reference current is waveform data corresponding to when the load current is equal to or greater than the nth reference current and less than the n-1th reference current.

7. The electronic circuit of claim 1 , further comprising a first detection circuit for detecting the load current.

8. The electronic circuit of claim 1 , further comprising a second detection circuit for detecting the surge current.

9. The electronic circuit of claim 1 , further comprising a storage circuit for storing the modified waveform data.

10. An electronic circuit according to any one of claims 1 to 9, The electronic circuit further comprises a drive circuit that generates a drive current in accordance with the waveform data of the drive current provided from the electronic circuit and supplies the drive current to the switching element.

11. The electronic circuit according to claim 10 , further comprising the switching element driven by the drive current supplied from the drive circuit.

12. two switching elements constituting an arm pair; two drive circuits for supplying drive currents to the two switching elements, respectively; a power conversion circuit including: Processing circuit and Equipped with The processing circuitry generating waveform data of the driving current; providing the waveform data to the driver circuit; correcting the waveform data based on a load current flowing through a load connected to the switching element and a surge current of the switching element when the switching element is turned on; a reference current is set, and the waveform data is corrected based on a first surge current value when the load current is smaller than the reference current by a predetermined first value and a second surge current value when the load current is larger than the reference current by a predetermined second value; Power conversion device.

13. The power conversion device according to claim 12 , comprising three of the power conversion circuits.

14. generating waveform data of a drive current to be supplied to a switching element; providing the waveform data to a drive circuit for the switching element; correcting the waveform data based on a load current flowing through a load connected to the switching element and a surge current of the switching element when the switching element is turned on; a reference current is set, and the waveform data is corrected based on a first surge current value when the load current is smaller than the reference current by a predetermined first value and a second surge current value when the load current is larger than the reference current by a predetermined second value; Data generation method.

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