Method and circuit for reading and writing pi-state induced circulating currents into superconducting circuits containing magnetic Josephson junctions

Abstract

A write circuit for an MJJ-based memory circuit includes first and second current sources configured to generate first and second currents, respectively. The first current applies an easy axis magnetic field component to an MJJ in a selected memory cell during a write operation. The second current induces a third current through the MJJ in the selected memory cell, the third current being a seed current for setting a π-state current of the MJJ in a superconducting loop in the selected memory cell. The first current source is configured such that, during the write operation, the MJJ cell transitions from i) a π-state, in which current circulates in a clockwise or counterclockwise direction in the superconducting loop, to a zero-state, in which no current circulates in the superconducting loop, and back to the π-state; or ii) from the zero-state to the π-state; or iii) from the π-state to the zero-state.

Description

[Technical Field]

[0001] This application claims the benefit of and priority under 35 U.S.C. § 119 of U.S. patent application Ser. No. 18 / 478,140, ​​filed Sep. 29, 2023, and U.S. provisional patent application Ser. No. 63 / 434,654, filed Dec. 22, 2022, entitled "Reading and Writing Memory Circuits Having Magnetic Josephson Junctions," the disclosures of each of which are incorporated herein by reference in their entirety for all purposes.

[0002] The present invention relates generally to quantum and classical digital superconducting circuits and systems, and more particularly to improved techniques for reading and writing magnetic Josephson junctions that store states in superconducting memory circuits. [Background technology]

[0003] Superconducting Josephson junctions with magnetic barriers, also known as magnetic Josephson junctions (MJJs), serve as the basis for Josephson magnetic random-access memory (JMRAM). JMRAM relies on oscillations of relative Cooper pair phases using magnetic layer thickness to create junctions that exhibit either a zero or π Josephson phase depending on the relative magnetic layer orientation. This binary phase switching characteristic of the MJJ can be exploited to create superconducting memory elements capable of storing a logic "0" or logic "1" state, representing a zero or π Josephson phase, respectively. Memory unit elements can be arranged in arrays with read or write lines to create addressable memories fabricated on integrated circuit (IC) chips that can be cooled to cryogenic temperatures (e.g., approximately 4 degrees Kelvin).

[0004] More broadly, it is important to note that in addition to random-access memory (RAM), the term "superconducting memory" (or "memory") can refer to read-only memory (ROM), content-addressable memory (CAM), programmable logic array (PLA), and field-programmable gate array (FPGA). In the case of ROM, PLA, and FPGA, the underlying "state" memory defines the output or logic function.

[0005] JMRAM is considered an important approach to making cost-sensitive memory (high density, large capacity memory) for commercially viable superconducting systems and is therefore being actively developed. Unfortunately, previous attempts to successfully implement MJJ-based memory circuits are currently speculative at best. It is therefore clear that cost and reliability issues, such as manufacturing complexity (e.g., metal levels), remain that prevent the viable fabrication and commercialization of such superconducting memories. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent No. 11,476,842 [Patent Document 2] U.S. Patent No. 9,174,840 [Patent Document 3] U.S. Patent Application No. 17 / 993,586 [Patent Document 4] U.S. Patent No. 9,595,970 Summary of the Invention [Means for solving the problem]

[0007] The present invention provides systems, circuits, devices, and / or methods that enable reliable writing of magnetic Josephson junctions (MJJs), which can form the underlying memory elements (configuration memory elements) for setting the phase (e.g., Boolean state) of, for example, superconducting programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), read-only memories (ROMs), random access memories (RAMs), and pi-junction circuits, some of which are illustrated in one or more embodiments disclosed herein.

[0008] According to an embodiment of the present invention, a write circuit for writing a state into at least one memory cell in an MJJ-based storage circuit includes a first current source configured to generate a first current for applying an easy axis magnetic field component to an MJJ in at least one selected memory cell among a plurality of memory cells in the storage circuit during a write operation, and the write circuit further includes a second current source configured to generate a second current for inducing a third current in the at least one selected memory cell that passes through the MJJ in the at least one selected memory cell during the write operation, the third current being a seed current for setting a π-state current of the MJJ in at least one superconducting loop of the at least one selected memory cell for a subsequent read operation. At least a first current source is configured such that, during a write operation, the MJJ in a selected memory cell transitions: (i) from a pi (π) state, in which a clockwise or counterclockwise current circulates in the superconducting loop in the at least one memory cell, to a zero state, in which no current circulates in the superconducting loop, and back to the π state; or (ii) from the zero state to the π state; or (iii) from the π state to the zero state. In some embodiments, the write circuit further includes a control circuit coupled to the at least first current source, the control circuit configured to control a direction of the first current to control a direction of an easy axis field component applied to the MJJ in the at least one selected memory cell.

[0009] According to another embodiment, a method for writing a state into at least one selected MJJ in a memory cell of an MJJ-based storage circuit includes: applying an easy axis magnetic field oriented in a first direction to the selected MJJ, the selected MJJ comprising soft and hard layers arranged in a stacked structure, the selected MJJ being configured to be in a π state such that current circulates in a clockwise or counterclockwise direction in a superconducting loop containing the selected MJJ, where magnetic domain orientations of the soft and hard layers are parallel to one another; and further increasing the magnitude of the applied easy axis magnetic field in the first direction, such that the selected MJJ transitions to a zero state such that current does not circulate in the superconducting loop, where magnetic domain orientations of the soft and hard layers are antiparallel to one another. further increasing the magnitude of the easy axis magnetic field; further increasing the magnitude of the applied easy axis magnetic field in the first direction while simultaneously coupling a clockwise or counterclockwise seed current into the superconducting loop containing the selected MJJ, so that the selected MJJ transitions back to a π state where the magnetic domain orientations of the soft and hard layers are parallel to one another; and removing the applied easy axis magnetic field so that the selected MJJ is configured to be in a π state where the magnetic domain orientations of the soft and hard layers are aligned with one another and a circulating current is trapped in the superconducting loop containing the selected MJJ, the direction of the circulating current being a function of the direction of the seed current coupled into the superconducting loop.

[0010] According to another embodiment, there is provided a magneto-junction (MJJ) circuit having a three-phase circulating current for controlling a circuit function of an analog circuit and / or a digital circuit. The MJJ circuit includes a first superconducting loop comprising at least one magneto-junction (MJJ) and at least a first inductor. The MJJ circuit further includes a second superconducting loop comprising at least one Josephson junction and at least a second inductor. A clockwise current, a counterclockwise current, and / or zero current in the first superconducting loop are configured to control the circulating current in the second superconducting loop. In some embodiments, the first and second inductors are included in a transformer configured to result in a mutual inductance between the first inductor and the second inductor.

[0011] The term "facilitating" an action, as may be used herein, includes performing an action, making an action easier, assisting in performing an action, or causing an action to be performed. Thus, by way of example only and not limitation, in the context of a processor-implemented method, instructions executing on one processor may facilitate an action performed by instructions executing on a remote processor by sending appropriate data or commands to cause or assist in the action being performed. For the avoidance of doubt, an action may be performed by some entity or combination of entities even when the actor facilitates an action by another rather than performing the action.

[0012] One or more embodiments of the present invention, or elements thereof, may be embodied in the form of a computer program product including a computer-readable storage medium having computer-usable program code for performing the illustrated method steps. Furthermore, one or more embodiments of the present invention, or elements thereof, may be embodied in the form of a system (or apparatus) including a memory and at least one processor coupled to the memory and configured to perform the illustrated method steps.

[0013] Furthermore, in another aspect, one or more embodiments of the present invention or elements thereof may be embodied in the form of a means for performing one or more of the method steps described herein, which may include (i) a hardware module, (ii) a software module stored on a computer-readable storage medium (or multiple such media) and executed on a hardware processor, or (iii) a combination of (i) and (ii); any of (i)-(iii) implementing a particular technique or element thereof described herein.

[0014] The techniques of the present invention can provide significantly beneficial technical effects. By way of example only, and not by way of limitation, techniques for improving reading and writing of MJJs in an array of superconducting MJJs and for reducing the area of ​​a plurality of such MJJs and their supporting circuitry in accordance with one or more embodiments of the present invention can provide one or more of the following advantages, among others: To provide a write architecture (e.g., an array of logic gates; could be an array of memory cells) for use in a MJJ-based system / circuit (e.g., superconducting PLAs, FPGAs, ROMs, RAMs, and π-junction circuits) that allows for individual selection of MJJs for write / program operations within the system / circuit without adversely interfering with non-selected MJJs, for the purpose of improving data integrity within the system / circuit; To provide an improved write selection architecture and methodology for superconducting magnetic random access memory; To provide a write selection architecture for an MJJ-based system / circuit having a significantly increased tolerable write disturb margin, with the objective of reducing the sensitivity of the MJJ-based system / circuit to mismatch of MJJ devices, process variations, and / or other environmental factors within the MJJ-based system / circuit; Significantly transforming the field of MJJ-based systems / circuits by providing an improved write selection architecture and methodology for use with MJJ-based systems / circuits that not only allows for the selection of individual MJJs without adversely interfering with non-selected MJJs, but also reduces the overall sensitivity of the circuit to device mismatch, process variations, and other environmental factors, and further reduces power consumption during write operations; and Supporting operation as a three-state (i.e., having three logic states) memory element for digital or analog circuits.

[0015] These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments of the invention, which is to be read in connection with the accompanying drawings.

[0016] The following drawings are presented by way of example only, and not by way of limitation, in which like reference numerals (where used) indicate corresponding elements throughout the several views. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 1 is a schematic diagram illustrating an example MJJ-based storage circuit in accordance with one or more embodiments of the present invention. [Figure 2] FIG. 1 is a multi-element diagram illustrating a first write operation of a first write method for setting a positive or negative π-state current in a superconducting loop having an MJJ, where the sign of the π-state current indicates a state (e.g., Boolean) in a corresponding storage circuit (e.g., FIG. 1 ) in accordance with one or more embodiments of the present invention. [Figure 3] FIG. 1 is a multi-element diagram illustrating a second write operation of a first write method for setting a positive or negative π-state current in a superconducting loop having an MJJ, where the sign of the π-state current indicates a state (e.g., Boolean) in a corresponding storage circuit (e.g., FIG. 1 ) in accordance with one or more embodiments of the present invention. [Figure 4] 3 is a graph showing (i) the magnetic layer switching threshold and applied field as a function of the easy axis field and the hard axis field for the first write operation of the first write method depicted in FIG. 2 , and (ii) highlighting various transitions of the MJJ and superconducting loop in accordance with one or more embodiments of the present invention. [Figure 5] 4 is a graph showing (i) the magnetic layer switching threshold and applied field as a function of the easy axis field and the hard axis field for the second write operation of the first write method depicted in FIG. 3 , and (ii) highlighting various transitions of the MJJ and superconducting loop in accordance with one or more embodiments of the present invention. [Figure 6a] 1 is a graph illustrating the energy profile of the inductive loop as a function of phase (magnetic flux) across the MJJ in combination with a positive π phase setting current, in accordance with one or more embodiments of the present invention. [Figure 6b] 1 is a graph illustrating the energy profile of the inductive loop as a function of phase (magnetic flux) across the MJJ in combination with a positive π phase setting current, in accordance with one or more embodiments of the present invention. [Figure 6c] 1 is a graph illustrating the energy profile of the inductive loop as a function of phase (magnetic flux) across the MJJ in combination with a positive π phase setting current, in accordance with one or more embodiments of the present invention. [Figure 6d] 1 is a graph illustrating the energy profile of the inductive loop as a function of phase (magnetic flux) across the MJJ in combination with a positive π phase setting current, in accordance with one or more embodiments of the present invention. [Figure 6e] 1 is a graph illustrating the energy profile of the inductive loop as a function of phase (magnetic flux) across the MJJ in combination with a positive π phase setting current, in accordance with one or more embodiments of the present invention. [Figure 7]FIG. 1 is a multi-element diagram illustrating a second write method for setting a positive or negative π-state current in a superconducting loop having an MJJ, where the sign of the π-state current indicates a state (e.g., Boolean) in a corresponding storage circuit (e.g., FIG. 1 ) in accordance with one or more embodiments of the present invention. [Figure 8] FIG. 10 is a multi-element diagram illustrating a third write method for setting a positive or negative π-state current in a superconducting loop with an MJJ, where the sign of the π-state current indicates a state (e.g., Boolean) in a corresponding storage circuit (e.g., FIG. 1 ) in accordance with one or more embodiments of the present invention. [Figure 9] FIG. 1 is a multi-element diagram illustrating a first write operation of a fourth write method for setting a positive or negative π-state current in a superconducting loop having a multi-domain MJJ, where the sign of the π-state current indicates a state (e.g., Boolean) in a corresponding storage circuit (e.g., FIG. 1 ) in accordance with one or more embodiments of the present invention. [Figure 10] 1A-1C are diagrams outlining methods associated with write operations to magnetic storage circuits, according to various embodiments of the present invention. [Figure 11] 1A-1C are diagrams outlining methods associated with write operations to magnetic storage circuits, according to various embodiments of the present invention. [Figure 12] 1A-1C are diagrams outlining methods associated with write operations to magnetic storage circuits, according to various embodiments of the present invention. [Figure 13] 1A-1C are diagrams outlining methods associated with write operations to magnetic storage circuits, according to various embodiments of the present invention. [Figure 14] 1A-1C are diagrams outlining methods associated with write operations to magnetic storage circuits, according to various embodiments of the present invention. [Figure 15]1 is a graph illustrating the effective critical current of a two Josephson junction superconducting loop (i.e., a superconducting quantum interference device (SQUID)) in accordance with one or more embodiments of the present invention, where the effective applied magnetic flux is shown for three possible states. [Figure 16A] FIG. 1 is a schematic diagram illustrating an alternative flux shuttle and transmission line configuration for sweeping the energy (flux quanta) consumed in one write operation for the next write operation, in accordance with one or more embodiments of the present invention. [Figure 16B] FIG. 10 is a schematic diagram illustrating an alternative flux shuttle transmission line configuration for sweeping the energy (flux quanta) consumed in one write operation for the next write operation, in accordance with one or more embodiments of the present invention. [Figure 16C] FIG. 10 is a schematic diagram illustrating an alternative flux shuttle transmission line configuration for sweeping the energy (flux quanta) consumed in one write operation for the next write operation, in accordance with one or more embodiments of the present invention. [Figure 17A] 1A-1C are schematic diagrams collectively illustrating write row circuitry in accordance with one or more embodiments of the present invention. [Figure 17B] 1A-1C are schematic diagrams collectively illustrating write row circuitry in accordance with one or more embodiments of the present invention. [Figure 17C] FIG. 10 is a timing diagram used to conceptually illustrate the internal operation and external functions of first and second current direction flip-flops for determining successive positive and negative magnetic field applications (e.g., as depicted in FIGS. 4 and 5, respectively) in accordance with one or more embodiments of the present invention. [Figure 18] 1 is a schematic diagram illustrating a write circuit for a random access memory having an integrated MJJ-based storage circuit (e.g., FIG. 1 ) in accordance with one or more embodiments of the present invention. [Figure 19]FIG. 1 is a schematic diagram conceptually illustrating the magnetic field application portion of an exemplary MJJ write circuit, including an integrated write switch and MJJ domain orientation attributes, in accordance with one or more embodiments of the present invention. [Figure 20] FIG. 1 is a schematic diagram illustrating an example MJJ-based memory circuit including at least one integrated write switch and MJJ domain orientation attributes in accordance with one or more embodiments of the present invention. [Figure 21] FIG. 1 is a schematic diagram illustrating at least a portion of an example circuit for writing MJJs, including at least MJJ domain orientation attributes for each MJJ, in accordance with one or more alternative embodiments of the present invention. [Figure 22A] FIG. 1 is a schematic diagram illustrating at least a portion of an example MJJ-based storage circuit including at least one integrated write switch, as well as MJJ domain attributes and MJJ zero-state / zero circulating current attributes, in accordance with one or more embodiments of the present invention. [Figure 22B] FIG. 1 is a schematic diagram illustrating at least a portion of an example MJJ-based memory circuit including a MJJ superconducting loop that induces magnetic flux biases associated with the three persistent currents defined by the MJJ into a coupled superconducting circuit, in accordance with one or more embodiments of the present invention. [Figure 23] 22B is a multi-element diagram illustrating an example three-phase write operation within a corresponding storage circuit (e.g., the example storage circuit shown in FIG. 22A) in accordance with one or more embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0018] It will be appreciated that elements in the figures are shown for simplicity and clarity, and in order to facilitate reducing distraction in viewing the illustrated embodiments, common but well-understood elements that may be useful or necessary in commercially feasible embodiments are not necessarily shown.

[0019] As illustrated in one or more embodiments, the principles of the present invention are described herein in the context of quantum and classical digital superconducting circuits, and in particular, may provide systems, devices, and / or methods for enabling reliable writing of magnetic Josephson junctions (MJJs) embedded in superconducting loops. MJJs may be integrated into superconducting circuits to form superconducting RAMs, superconducting PLAs, FPGAs, and π-junction circuits, among other applications. MJJs may also be embedded in analog circuits. Thus, MJJs are shown to be highly versatile circuit elements in the context of this disclosure. Additionally, the possible state space of an MJJ in a superconducting loop may be three-phase, as discussed in connection with embodiments of the present invention. However, it should be recognized that the inventive concepts are not limited to only the specific devices, circuits, and / or methods illustratively shown and described herein. Rather, it will be apparent to those skilled in the art having the benefit of the teachings herein that many modifications may be made to the illustrated embodiments that are within the scope of the claimed invention. Thus, no limitation with respect to the embodiments shown and described herein is intended or should be implied.

[0020] Throughout this disclosure, the acronym "MJJ" for magnetic Josephson junction may be used broadly to define a programmable junction containing a magnetic spin valve (having a free magnetic layer and a fixed magnetic layer, or other combinations of layers and / or domains that result in the same or similar behavior), whereas the term "π junction" may broadly refer to a junction containing only a single magnetic layer in which the π phase variation remains fixed. It should be understood that a spin valve MJJ may be a preferred device for illustrative embodiments of the inventive concepts. However, in some cases, and particularly in some embodiments of the inventive concepts, the term "MJJ" may also describe a "π junction" and other variations of MJJs that differ from spin valve MJJs.

[0021] Generally, microwave signals, such as single flux quantum (SFQ) / multiple flux quantum (MFQ) pulses, can be used to control the states of memory cells in a memory array. During read / write operations, word lines and bit lines can be selectively activated by SFQ / MFQ pulses or by reciprocal quantum logic (RQL) pulses delivered via an address bus and separate read and write control signals. These pulses can then control word line driver circuits and bit line driver circuits adapted to selectively provide respective word line currents and bit line currents to associated memory cells in the memory array.

[0022] A Josephson magnetic random access memory (JMRAM) system can implement an array of JMRAM memory cells, each including a phase-hysteretic MJJ, which can be configured to include ferromagnetic material within an associated barrier. By way of example, the MJJ can be configured as a junction switchable between a zero-phase state and a π-phase state (henceforth abbreviated hereafter as "zero state" and "π state"), configured to selectively generate a superconducting phase. Each JMRAM memory cell can further include at least one Josephson junction (e.g., a pair of Josephson junctions in parallel with the MJJ). A fundamental element in SFQ, RQL, and JMRAM circuits is the Josephson junction, which emits a voltage-time spike with an integrated amplitude equal to a multiple of the integrated magnetic flux quanta (Φ) when the current through the Josephson junction exceeds a critical current, resulting in a manifestation voltage that opposes the current flow.

[0023] Exemplary embodiments of the inventive concept may be beneficially suited for use with conventional MJJs (e.g., in conventional memory circuits) that are switched / written using (i) magnetic fields alone, and (ii) a combination of magnetic field selection and phase-based torque.

[0024] In binary applications, the MJJ in the inductive loop can be configured to store a digital state corresponding to one of a first binary state (e.g., logic −1) or a second binary state (e.g., logic −0) in response to a write word current (also known as a write row current, passing between terminals “In_Out_2_magnetic field” and “In_Out_1_magnetic field” of the memory cell / storage circuit 100 of FIG. 1 ) and a write bit current (also known as a write column current, passing between terminals “In_Out_2_π phase setting” and “In_Out_1_π phase setting” of the memory cell / storage circuit 100 of FIG. 1 ) associated with the MJJ. For example, the first binary state can correspond to a positive π state, where a superconducting phase is indicated. By way of example, the write word current and the write bit current can be provided on an associated write word line and an associated write bit line (e.g., coupled to the MJJ), respectively, and together can set the logic state of the selected MJJ. As used herein, the term "selected" MJJ is defined as a MJJ selected for writing among multiple MJJs by initiating a current flow in its associated write bit line (WBL). The digital state can be written by a positive or negative current flow in its associated write bit line (WBL). Furthermore, if necessary to prevent the MJJ from being set to an undesired negative π state, the MJJ can include a directional write element configured to generate a directional bias current through the MJJ during a data write operation. Thus, the MJJ can be forced into a positive or negative π state to provide a superconducting phase in a predetermined direction.

[0025] The term "MJJ" when used herein in reference to a state (e.g., a "positive π-state") is intended to describe both the phase behavior of the junction and the circulating current state within the superconducting loop. Furthermore, as explained in more detail below, it should be understood that the terms "negative" and "positive" when used herein to define particular π-state configurations of an MJJ may be assigned arbitrarily and are used merely to distinguish one π-state configuration from another (e.g., having an associated clockwise or counterclockwise circulating current), and are not used to indicate a particular polarity associated with each π-state configuration of the MJJ.

[0026] Additionally, the MJJ in each JMRAM memory cell in the array can provide an indication of the stored digital state in response to the read word current and the read bit current. The superconducting phase can reduce the effective critical current associated with at least one Josephson junction in each JMRAM memory cell in a row of the array. Thus, the read bit current and a derivative of the read word current (which may be induced by the read word current flowing through a transformer) can be provided in combination to (i) trigger the Josephson junction to produce a voltage on the associated read bit line when the MJJ stores a digital state corresponding to a first binary state, and (ii) not trigger when the MJJ stores a digital state corresponding to a second binary state. Thus, the read bit line can have a current voltage whose magnitude varies depending on whether the digital state of the MJJ corresponds to a binary logic 1 state or a binary logic 0 state (e.g., between a non-zero amplitude and a zero amplitude). The term "triggering" as used herein in connection with a Josephson junction is intended to describe the phenomenon of a Josephson junction generating a discrete voltage pulse in response to current flow through the Josephson junction exceeding a predetermined critical current level.

[0027] MJJ and supercurrent nomenclature It is important to understand that spontaneous currents can flow (be induced) in opposite directions (clockwise or counterclockwise) in superconducting loops containing at least one of: (i) π junctions; (ii) spin-valve MJJs in the π state; and (iii) generally multilayer MJJs with multiple possible magnetic orientations that, when configured, drive each device in the π state, as induced by the presence of magnetic devices (e.g., magnetic Josephson junctions (MJJs)). These oppositely directed currents may be referred to hereinafter as "positive π-state current" and "negative π-state current," with the understanding that these terms may be assigned arbitrarily, as previously mentioned. Other currents may also exist in the superconducting loop.

[0028] As is known in the art, the thickness and / or orientation of the magnetic layer materials can be selected to set the magnetic device into a π state. Some confusion arises regarding MJJs that can be in a π state or a zero state (i.e., 0 state). In the absence of an applied magnetic field, clockwise or counterclockwise π state (circulating) currents, each of which has a stable state (both in a π state magnetic device in an appropriate inductive loop, given a double-well potential), are actually associated only with their own superconducting loop, which always contains a magnetic device in a π state. Thus, two different concepts exist: those that refer to the MJJ state, π state, or zero state; and those that refer to the energetically similar states of clockwise or counterclockwise π state (circulating) currents flowing in a superconducting loop that specifically contains an MJJ in a π state.

[0029] As used herein, the terms “zero state” and “π state” are intended to broadly refer to the respective MJJ layer orientations relative to one another and their associated layer properties, and are not intended to refer to the states of a memory cell. Cyclic or non-cyclic states of a circuit that can be used to store a first logic state, a second logic state, and even a third logic state (in the case of a three-phase memory operation) can be utilized in any combination suitable for the use and operation of a memory cell incorporating such MJJ devices. For example, any set of states can be used to represent first and second logic states (or first, second, and third logic states in the case of a three-phase memory configuration) for Boolean state storage, to the extent that such states are intended / stable states of the circuit.

[0030] As known to those skilled in the art, the magnetic layers of an MJJ have domains with two preferred stable directions to be oriented (within the magnetic system of interest for embodiments of the present invention). These directions will be referred to as “left” and “right,” with the understanding that these terms are merely discrete directions arbitrarily chosen for ease of reference in distinguishing different orientations in the context of a local directional magnetic field. The domains / layers are also responsive to fields along two axes that may be referred to as the “easy” and “hard” axes. When multiple magnetic layers are present in a given device, these may be referred to as “soft” (free) and “hard” (pinned) layers, with the understanding that these terminologies are borrowed from existing similar structures and that, in the context of the present invention, these terms may be used to describe faster-switching layers (soft / free layers) than slower-switching layers (pinned / hard layers). Thus, the term "pinned" layer as it may be used herein may not necessarily refer to a layer whose magnetic orientation does not change, but instead may refer to a layer whose magnetic orientation changes more slowly under the influence of a stronger magnetic field compared to a "free" layer whose magnetic orientation changes more rapidly.

[0031] Consideration of memory circuits 1 is a schematic diagram depicting at least a portion of an example storage circuit 100 in accordance with one or more embodiments of the present invention. The example storage circuit 100 can include at least one JJ 102, 104, at least one transformer 106, 108, at least one magnetic device (e.g., a magnetic Josephson junction, abbreviated as MJJ) 110, and at least one write line segment (WLS), where a non-zero angle exists between the write line segment (WLS) and the MJJ 110, the non-zero angle being indicated by the orientation of the major axis of the elliptical MJJ relative to the orientation of the WLS to assist in generating at least an easy axis field component for application to the MJJ 110. The easy axis field, as depicted in FIG. 1, is a magnetic field H WLS It can be a component of H WLS The subscript "WLS" in the figure indicates the current I conducted by the line segment WLS. WLS During a write operation, storage circuit 100 is configured such that when MJJ 110 is written using at least the easy axis magnetic field component in selection of storage circuit 100 for a write operation, it results in the MJJ 110 transitioning from the π state, via the zero state, and back to the π state, and remaining in the π state otherwise, such that in the case of a read operation targeted to storage circuit 100, and also in the case of state-holding enabled within storage circuit 100, the superconducting loop within storage circuit 100 flows a clockwise or counterclockwise (positive or negative) π state current I circ (The circulating current I is used to indicate that the π-state current circulates within the storage circuit 100 during standby / state maintenance.) circ This will allow the company to maintain its current system of payment (abbreviated as "payment").

[0032] A write operation for the exemplary storage circuit 100 differs from a conventional write operation. For example, in one or more embodiments, a write line segment current I passing through the write line segment WLS WLS(or the write row line current I WRL ) magnetic field H WLS The unique coupling of the easy axis field (preferably together with the hard axis field) to select a given MJJ for a write operation through the generation of is enabled by one or more embodiments of the present invention. It is important to note that in a random access memory (described with reference to FIG. 18), multiple serially connected write line segments WLS are referred to as write row lines WRL of the memory array.

[0033] As central to many embodiments of the present invention, easy axis coupling is exhibited on the example memory circuit 100 due to a non-zero angle orientation of the WLS with respect to the MJJ 110 (shown here as the orientation of the major axis of the elliptical MJJ with respect to the orientation of the WLS). Note that the labels WLS and MJJ 110 appear twice in FIG. 1 to link the circuit topology of the example memory cell 100 to the non-zero angle orientation constraint imposed on that MJJ 110. In later sections, more complex write circuits or write methods to assist in writing the write circuit 100 with such unique MJJ orientations are described and explained in terms of their physical characteristics.

[0034] In providing this brief introduction to one aspect of the write operation, the bidirectional current I WLS and π phase setting currents are used to (i) select the memory cell 100 for a write operation and (ii) control its internal circulating current I circ It is important to note that these bidirectional currents are related to the setting of the direction of the In_Out_2_magnetic field and the In_Out_1_magnetic field, respectively. These bidirectional currents are driven through pairs of terminals: (i) In_Out_1_π phase setting current and In_Out_2_π phase setting current.

[0035] The read operation for the exemplary storage circuit 100 has been previously described in the prior art, and the Boolean state of the storage circuit 100 is represented by the circulating current I circ15. This is expressed as clockwise and counterclockwise (positive and negative) π-state currents, as described above. To enable understanding of memory cell 100, a brief introduction to its read operation will be provided below. This discussion will be supplemented later by a detailed description of FIG. 15.

[0036] During a read operation, the storage circuit 100 of FIG. 1 can be modeled as two junction inductive loops with two sources of applied effective magnetic flux. As used herein, the term “effective magnetic flux” can refer to an applied current, magnetic field, or device configuration that deterministically changes the effective critical current of the inductive loop configuration. In some embodiments, the effective magnetic flux can be applied by a coupled magnetic field, treated as two superconducting lines coupled therebetween using superconducting transformers 106, 108. According to other embodiments, the effective magnetic flux can also be applied by driving the MJJ 110 into a π state, which creates a π phase difference across the MJJ within the inductive loop.

[0037] In some alternatives described in the prior art, the MJJ in the zero state provides no additional effective magnetic flux to the inductive loop, and therefore, a carefully selected read flux bias is not sufficient to generate a signal through its column line (CL) connection. Therefore, these memory cells 100 to memory cell connections remain in their superconducting state. In the π state, the additional effective magnetic flux of the MJJ, together with the read flux, may be sufficient to collectively drive the effective critical current of the inductive loop below the level required to generate a read signal (i.e., drive the inductive loop into one voltage state). In the absence of effective magnetic flux from the MJJ, the effective critical current of the inductive loop may be less than the read current, and therefore no output signal is generated. In the π state, the phase difference across the MJJ imposes an effective phase variation on the Josephson junctions 102, 104, similar to the effect of a current driven through the read line. Thus, the circuit can be configured such that it will require both the MJJ effective flux and the physically applied flux to drive the junctions 102, 104 into one voltage state.

[0038] By maintaining a π-state MJJ in both logic states and by inducing either a clockwise or counterclockwise (positive or negative) π-state current in memory cell 100, Boolean logic states can be defined by different circulating current states which (without loss of generality) can be associated with either a positive or negative magnetic flux in the loop. This is illustrated in the embodiment of the present invention by the column line CL (bit line) read current and the read row line read flux (read row line current I flowing in the read row line during a read operation). RRL This increases the read margin budget for the read current (generated by the read current). The read current can always provide a positive effective magnetic flux (which is always positive by convention, as shown in Figure 15). In general, programmable circulating currents can be used in both digital and analog circuits.

[0039] Exemplary Write Circuit FIG. 2 is a multi-element diagram conceptually illustrating an example write method for establishing a positive or negative π-state current in a superconducting loop having a MJJ 202 (e.g., a spin valve MJJ), according to one or more embodiments. Such a write approach can achieve a more reliable write operation by transitioning the MJJ from a π-state to a zero-state, regardless of which layer (designed to be soft or hard) switches first, where the conventional state circulating current associated with the π-state is nullified. As the MJJ transitions to the new π-state, its associated circulating current (e.g., I circ ) can be reliably set using the π-state seed current.

[0040] Before further discussing this write method, it is important to understand what is meant by a “superconducting loop with MJJ 202.” This phrase can describe, for example, two superconducting loops, each formed of series-connected components that are both part of the example memory cell 100 of FIG. 1 , where MJJ 202 is depicted in FIG. 1 as MJJ 110: (i) the first “loop” includes transformer 106 and MJJ 110, and (ii) the second “loop” includes transformer 108, MJJ 110, JJ 102, and JJ 104. It is also important to understand that, unlike the prior art, the unique non-zero angle orientation of MJJ 110 relative to the WLS in FIG. 1 enables coupling of the easy axis field to MJJ 110 to support the write methods of FIGS. 2 and 3 and all subsequent figures. All of these write methods require the inclusion of a memory element (e.g., depicted as first-second current direction flip-flop 1702 in FIG. 17A or as an MJJ domain orientation attribute in FIG. 20) in the “electrical periphery” of a memory cell (e.g., example memory cell 100 of FIG. 1 or example memory cell 2000 of FIG. 20) in a write circuit for the purpose of tracking the domain orientation in its π state of at least one magnetic layer, but possibly both layers, of at least one MJJ, depending on the particular write method. (The peripheral circuitry can include (Bi)CMOS circuitry residing in room-temperature electronics.) Furthermore, the domain orientation tracking memory element differentiates embodiments of the present invention from prior art embodiments and, therefore, forms the core of the device claims of the present invention. As will be explained, this informs the write circuit of the direction of the easy axis field (or easy axis field component) to be applied to at least one MJJ being written for the purpose of switching a particular domain in its magnetic layer, in accordance with the requirements of each write method embodiment.

[0041] 2 shows an example time evolution of the layers and their orientations of an example spin valve MJJ, with the soft (easy) layer progressing from 204 to 212 and the hard (pinned) layer progressing from 206 to 214, as well as the applied magnetic field direction 210, which may increase in strength (i.e., magnitude) over time. In the example write process shown in FIGS. 2, 3, 7, and 8, it should be understood that each diagram of a two / multilayer MJJ follows the following convention: the top layer (e.g., 204) is the soft (easy) layer and the bottom layer (e.g., 206) is the hard (pinned) layer, with a separation layer 208 between them.

[0042] In particular, time progresses from left to right in Figure 2. Below each magnetic field layer configuration, its corresponding associated minimum energy state of the inductive loop containing the MJJ is shown. In the left diagram showing the initial MJJ orientation 202, both layers 204, 206 have magnetic orientations pointing to the left, and a magnetic field 210 begins to be applied that is opposite to the initial MJJ orientation 202. In the steady state, the inductive loop can have two potential wells 220 (shown as gray dots indicating local degenerate minima), and only one of the two potential wells 220 can be occupied by a circulating current. When the top layer switches, a critical current I C decreases, resulting in a less localized minimum 222 indicated by a single black dot. In the center diagram, the top layer (e.g., soft layer 212) has a magnetic orientation pointing to the right, while the bottom layer (e.g., pinned layer 206) does not change its magnetic orientation and continues to point to the left, indicating that the field strength (i.e., magnitude) of the applied magnetic field 210 is sufficient to switch the soft layer 212 but not the hard layer 206. As shown between the left and center configuration / state diagrams, the energy levels 220, 222, and 224 of the inductive loop flatten out. When the MJJ is in its zero state (energy diagram with a single broad minimum 224), there is no circulating current and only one minimum exists (e.g., 224).

[0043] Continuing with FIG. 2, the diagram on the right shows both layers 212, 214 with a magnetic orientation pointing to the right as the applied field 210 is further increased. The MJJ is also in the π state, and the superconducting loop has two possible degenerate energy states / wells, as shown by the energy diagram 220 on the right; circ The MJJ-induced clockwise or counterclockwise (positive or negative) π-state current, where I is the phase-setting current, can determine which well is occupied. An applied seed current in the loop containing inductor L2 of the transformer 106 and MJJ 110 (see FIG. 1 ), driven through the transformer 106, can drive a first state transition / process 240 resulting in a first logic state, or a second state transition / process 242 resulting in a second logic state. The applied π-phase setting current can drive a bias current (I seed_π-phase ), which can produce variations in energy well profiles 230, 232 shown in the respective first and second state transitions 240, 242. (FIG. 6 can provide a more detailed explanation of this process.)

[0044] When process 240 reaches a first logic state, flat potential 222 can be split and swept into energy profile 230, which has a local minimum at a non-zero phase. When the seed current is removed, the energy profile returns to double-well potential 220, but now the state is categorically in the right well. Process 242 can be substantially the same, except the seed current is in the opposite direction and the local state is on the left side in energy profile states 232 and 220. Note that the left and right well pairs in the diagram associated with MJJs in the π state can be similar in energy but different in terms of the supporting circulating current.

[0045] In FIG. 2, writing an MJJ can be achieved by: (1) applying a right-handed (easy axis) magnetic field when the junction is in the left-left (LL) π state; (2) increasing the magnetic field, resulting in the easy / soft and hard layers switching to a right-left (RL) configuration corresponding to the zero state; (3) switching the orientation of the hard layers to a right-right (RR) configuration while coupling in a clockwise or counterclockwise (positive or negative) seed current as the field is increased; (4) removing the magnetic field while leaving the junction in the π state; and (5) trapping a circulating current in parallel with step (4), as set by a “seed” current applied by transformer 106 of FIG. 1 (which effectively forms the write bit line) to the superconducting loop containing the MJJ. Besides the dominant magnetic field direction, differences that can be seen between Figures 2 and 3 (to be discussed) include the different initial / final arrow directions and the first and second pinned and free layer orientations of the MJJ, which in both cases transition from the π state via the zero state and back to the π state.

[0046] The key step here is for the MJJ to transition to the zero state before transitioning back to the π state, which can be achieved by the antiparallel configuration of the magnetic layers. Note in FIGS. 2 and 3 that the state of the MJJ at the completion of the write operation is the same as the state of the MJJ before the write operation, except that the magnetic domains in the soft and hard layers of the MJJ shown in FIG. 2 are oriented to the right after the write operation and to the left after the write operation shown in FIG. 3. This novel process operates starting with the sequence depicted in FIG. 3 and continuing with the sequence depicted in FIG. 2. Two writes to the same MJJ return the orientation of the MJJ's layers to their same / original direction. Each individual write results in a state within the storage circuit 100 (FIG. 1) that can be stored and read.

[0047] Distinguishable from conventional approaches, one or more embodiments of the present invention may involve clearing the magnetic domain orientations of both the soft (free) and hard (pinned) layers during each write operation. As used herein, the term "parallel" in the context of the soft and hard layers of an MJJ refers to the respective magnetic domain orientations of the soft and hard layers being aligned (i.e., in the same direction) with respect to one another. Conversely, the term "anti-parallel" as used herein in the context of an MJJ refers to the respective magnetic domain orientations of the soft and hard layers being in opposite directions relative to one another.

[0048] Similar to FIG. 2, FIG. 3 illustrates the time evolution of the soft and pinned layers of an exemplary spin-valve MJJ and the applied magnetic field direction 310 (which preferentially increases in strength with time). It is also assumed in FIG. 3 that time progresses from left to right. Below each magnetic field layer configuration of the MJJ is shown its associated minimum-energy state 220, 222, 224, 230, 232 of the inductive loop containing the MJJ. In the left-hand diagram illustrating the initial MJJ orientation 202, when the magnetic field is first applied, both layers 212, 214 have magnetic orientations pointing to the right. In the steady state, the inductive loop can have two potential wells, only one of which is occupied by a circulating current. In the middle diagram, the top layer (e.g., soft layer 204) switches its magnetic orientation to point left in the presence of the left-pointing applied magnetic field 310, while the bottom layer (e.g., pinned layer 214) has a magnetic orientation that remains unchanged and points right. This indicates that the field strength of the applied magnetic field 310 is sufficient to switch the soft layer 204 but not the hard layer 214 .

[0049] As shown between the right and center configuration / state diagrams, the energy levels of the induced loop flatten out. When the MJJ is in the zero state, there is no circulating current and therefore only a single minimum. The diagram on the right shows both layers 204, 206 with an orientation pointing to the left as the applied magnetic field 310 is further increased. With the MJJ also in the π state, the superconducting loop has two possible degenerate energy states; which one is occupied is determined by the MJJ-induced circulating π-state current.

[0050] 3, the steps can be the same as those shown in FIG. 2, except that the influence of the magnetic field is reversed. Specifically, in one or more embodiments, writing an MJJ is accomplished by: (1) applying a left-handed (easy axis) magnetic field when the junction is in a right-right (RR) configuration corresponding to a π state; (2) increasing the applied magnetic field, resulting in the easy / soft and hard layers switching to a left-right (LR) configuration corresponding to the zero state of the MJJ; (3) as the applied field is increased, switching the orientation of the hard layers to a left-left (LL) configuration corresponding to a π state while coupling in a positive or negative seed current; (4) removing the applied magnetic field while leaving the junction in the π state; and (5) in parallel with step (4), applying a circulating current (I in FIG. 1) to the superconducting loop containing the MMJ, as set by a "seed" current applied by transformer 106 in FIG. 1 (which effectively forms the write bit line). circ ) in parallel.

[0051] In addition to the dominant magnetic field direction, differences visible between FIGS. 2 and 3 can be the different initial and final arrow directions and the first and second pinned and free layer orientations of the MMJ, which in both cases transition from the π state through the zero state and back to the π state. The key step here, consistent with the example write process shown in FIG. 2, is transitioning to the zero state before transitioning back to the π state, which can be achieved by the antiparallel configuration of the magnetic layers. Note that the final state of the MMJ in FIG. 2 (i.e., upon completion of the MJJ write operation) is the same as the starting state of the MJJ in FIG. 3, and vice versa. This process can similarly be performed, beginning with the sequence depicted in FIG. 3 and continuing with the sequence depicted in FIG. 2. Two writes to the same MJJ return the orientations of the MJJ's layers to their same (original) directions. Each individual write results in a state within the storage circuit 100 that can be stored and read.

[0052] Writing an MJJ with both hard (pinned) and soft (free) magnetic layers is accomplished in a manner similar to existing cell designs with a few significant differences. These differences include the use of an easy-axis field to transition the MJJ from a π state, through a zero state, and back to a π state during the write cycle; and the application of a clockwise or counterclockwise (positive or negative) seed current to establish a clockwise or counterclockwise (positive or negative) π-state current in the storage circuit. This seed current only needs to bias the cell toward the desired circulating current state. Once layer rotation is complete, the energy well minimum will result in the circulating current state without any externally applied fields. The strength of the seed current only needs to be strong enough to overcome any noise in the system and drive the desired circulating current state toward the lowest available energy state.

[0053] FIG. 4 conceptually illustrates ideal Stoner-Wohlfarth switching astroids for the easy (free) and hard / pinned layers of the MJJ in the example MJJ write circuit 100 of FIG. 1 for the example write method described in FIG. 2. The Stoner-Wohlfarth (SW) model may be the simplest model adequately describing magnetization reversal in nanoscale systems small enough to contain a single magnetic domain. In FIG. 4, the hard-axis field is represented by the y-axis (vertical axis) and the easy-axis field is represented by the x-axis (horizontal axis), normalized to the maximum uniaxial field for the hard / pinned layers. The Stoner-Wohlfarth astroid is essentially a polar plot showing the switching field under the assumption of coherent reversal. Referring to Figure 4, a smaller free-layer switched astroid is shown centered at the origin, and a larger (normalized magnitude ±1.0) fixed-layer switched astroid is shown centered at the origin and surrounding the free-layer switched astroid (i.e., concentric with the free-layer switched astroid). The free-layer switched astroid and fixed-layer switched astroid shown in Figure 4 are simplified to ignore any interaction between the free and fixed layers of the MJJ that would otherwise create an offset.

[0054] The boundaries of a switching astroid represent the magnetic field points on the curves above which the domains of a particular MJJ layer can be reversed, causing the MJJ to switch its phase state. These boundaries represent the hysteresis boundaries of the layer for switching from one domain orientation to another. Any combination of fields within the boundaries of the astroid results in no change in the overall magnetic orientation after removal of the fields. Any combination of fields outside the boundaries shown, when the applied field is opposite the domain orientation, results in a semi-permanent change as the field returns to zero.

[0055] In the illustration of Figure 4, it can be assumed, without loss of generality, that the MJJ is in the π state, with both the pinned and free layers of the MJJ pointing to the left. Here, the process of applying a magnetic field at an angle (along a 45-degree line, although embodiments of the present invention are not limited to any particular angle of applied field relative to the MJJ) to the easy axis of the MJJ is depicted. (Note that this is along normalized field strengths, and the actual orientation of the junction on the chip will be determined by the ratio of the actual minimum field strengths.)

[0056] Starting with "system mode (i)," where readout is possible at the origin of the diagram, increased fields are applied in both the easy and hard axes until the applied field exceeds the soft layer hysteresis minimum (i.e., defined by the free layer switching astroid); a point corresponding to transition zero-state (ii) is achieved. At this point, ignoring any dynamic effects, the soft and hard layers of the MJJ are oriented in opposite directions; the soft layer is on the right and the hard layer is on the left. Assuming the MJJ layer thicknesses are properly designed and fabricated, the junction transitions to a zero-state junction.

[0057] As the applied magnetic field increases along the same direction, the hard layer also passes through its hysteresis limit and, together with the soft layer, remains in its newly switched ("right") orientation, pointing right even when the field is removed. Simultaneously, a seed current is applied to bias the (iii) ground state (denoted (v) new π state) toward a clockwise or counterclockwise (positive or negative) π state current, as desired. The junction then transitions back to the new π state (v) and is able to support persistent current in the loop. The field must continue through the hard (and implicitly soft) hysteresis minimum, so that the π state is maintained when the field is removed. This point corresponds to the seed current induced in the MJJ loop (iii). A clockwise or counterclockwise (positive or negative) seed current can be supplied through the MJJ to split the degenerate energy states of the inductive loop containing the MJJ. When both layers of the MJJ are oriented in the same direction (right and left sides in Figures 2 and 4), a circulating current state (i.e., positive or negative π-state current) will be maintained in the absence of a driving current. The MJJ switching field can be removed (v) and readout is possible in this "system mode."

[0058] Figure 5 shows the Stoner-Wohlfarth astroid evolution for the example MJJ write operation of Figure 3. The evolution shown in Figure 5 is essentially the same as the evolution shown in Figure 4 (associated with the example write operation of Figure 2), except that the magnetic fields and magnetic layer orientations are reversed (i.e., the Stoner-Wohlfarth astroid evolution is essentially rotated about the origin).

[0059] Figure 1 shows the In_Out_1_π phase setting terminal and the In_Out_2_π phase setting terminal for the write seed current described herein. Unlike conventional MRAM write methods, write selection currents passing through row / word lines (formed by the In_Out_2_magnetic field terminal and the In_Out_1_magnetic field terminal) can generate easy-axis magnetic field components, and vice versa. Such write selection approaches can target at least one MJJ. Such write selection changes the topography of the potential well representing the circulating current to facilitate reliable establishment of clockwise and counterclockwise (positive or negative) π-state loop currents corresponding to the "1" or "0" stored states of the memory circuit, respectively. Moving from left to right in Figure 2, the direction of the applied magnetic field remains constant, but its magnitude can increase over time.

[0060] To reiterate, writing an MJJ is accomplished by: (1) applying a right-handed magnetic field with an easy-axis component 210 when the junction is in a left-left (LL) configuration corresponding to the π state; (2) increasing the magnetic field 210 to cause the easy / soft layers to change their orientation to the right, resulting in a right-left (RL) configuration where the MJJ is in the zero state; (3) as the field is increased, switching the orientation of the hard layers to the right-right configuration to place the MJJ in the π state while coupling in a π phase setting current (write bit line current) in the appropriate direction to create a seed current; (4) removing the magnetic field while leaving the junction in the π state; and (5) simultaneously trapping a circulating current as set by the seed current in step (4). The circulating current state can represent a stored logic state (e.g., “1” or “0”) in the circuit. Subsequent write operations follow the same process, but the right and left magnetic fields and layer orientations are swapped; nevertheless, the circulating seed current always sets / generates the final circulating current (positive or negative) that is stored as a result of the MJJ being in the π state.

[0061] By switching both layers during a write operation according to one or more embodiments of the inventive concepts, process variations in the thresholds of the hard and soft layers for orientation changes can be reduced. It is only important that the soft layer (actually the weaker of the two layers in a fabricated product) switches independently from the hard layer, thereby allowing a temporary zero-state junction before the hard layer switches to restore the π-state of the junction. Note that the zero state of the MJJ is purely a temporary state for the Boolean write operation and is in no way related to the particular Boolean logic state that is ultimately stored as a clockwise or counterclockwise current circulating in the superconducting loop comprising the MJJ.

[0062] It should be noted that three-phase bit storage can be achieved (if the MJJs are written one at a time). Three-phase writing is possible with only minor modifications to the methods 200 and 300 of Figures 2 and 3, respectively. This will be explained in conjunction with the description of Figures 22 and 23.

[0063] For Boolean writes, either a clockwise or counterclockwise (positive or negative) seed current can be applied to the MJJ during a transition from the zero state to the π state, thereby storing a clockwise or counterclockwise (positive or negative) π state current in the superconducting loop containing the MJJ. As the MJJ swings to the π state, the degenerate energy states can be split, resulting in a preferred energy state corresponding to a circulating current (e.g., a positive or negative π state current) in the storage circuit 100 as associated with the superconducting loop, which represents the logic state of the circuit.

[0064] 6a through 6e are energy profiles illustrating an exemplary evolution of a magnetic junction potential well and inductive loop circuit combination (e.g., formed by the MJJ 110 and the secondary winding / wire L2 of the transformer 106 shown in FIG. 1) during a write operation, according to an embodiment of the present invention, as this circuit combination is biased toward a particular circulating current to a stored state that is available for both read and sustain operations. By inductively coupling current into the superconducting loop containing the MJJ (e.g., via the transformer 106 in FIG. 1), a bias current (I induced by a positive or negative π phase setting current in FIG. 1) that sets the direction of the circulating current, be it clockwise or counterclockwise, can be applied. seed_ π-phase) can be applied.

[0065] Figure 6a corresponds to step (ii) of Figure 4 or Figure 5, where the layers of the MJJ are perturbed so that the MJJ behaves as a standard zero-state junction. There is only a single broad minimum, indicated by the black dot. As the applied magnetic field increases, the critical current decreases, and the junction becomes a π-junction at low critical current, the energy profile corresponds to Figure 6b, here step (iii) of Figure 4 or Figure 5. Corresponding to step (iv) of Figure 4 or Figure 5, Figure 6c shows the applied seed current perturbing the energy profile away from the zero minimum and instead toward a permanent nonzero applied phase. Simultaneously (also as part of step (iv) of Figure 4 or Figure 5), the π-junction nature of the junction is manifested, and a double-well profile begins to emerge, as shown in Figure 6d. In the final step (v) of Figure 4 or Figure 5, the seed current is removed, and the potential minimum is selected as the right well, as shown in Figure 6e. Without loss of generality, the process operates in the same way for the left well, with the corresponding seed current applied in step (iii).

[0066] First Alternative Writing Method 7 conceptually illustrates at least a portion of an exemplary alternative write method 700 for transitioning an MJJ from a π state to a zero state and back to a π state, according to one or more embodiments. In the write method 700, the initial orientation 702 of the MJJ is, in particular, the same as the final orientation of the MJJ; in this example, the top layer 704 and bottom layer 706 of the MJJ have equal starting and final domain orientations (left-left orientations), which differs from the above process of switching the domain orientations of both the pinned and free layers of the MJJ at each write cycle.

[0067] More specifically, Figure 7 shows the time evolution from left to right and right to left of the soft layers of the MJJ and the applied magnetic field directions 710, 712 (which may be assumed to vary in strength and direction with time) that drive such rotation. Below the magnetic field layer configuration are shown the respective minimum energy states 220, 222, 224, 224, 222, 230 (or 232), 220 of the inductive loop containing the MJJ. In the left-hand diagram showing the initial orientation 702 of the MJJ, both the top and bottom layers are oriented to the left 704, 706 when the magnetic field 710 begins to be applied. The superconducting loop has two potential wells in this initial π state, only one of which generates the circulating current I of Figure 1. circ Occupied by

[0068] In the diagram on the left-center side, the top layer points to the right 714, while the magnetic orientation of the bottom layer remains pointing to the left 706, indicating that the applied magnetic field strength is sufficient to switch the soft layer but not the hard layer. At the top of the diagram, the energy levels of the superconducting loop flatten out, as shown between the diagrams on the left and center left. When the MJJ is in the zero state, no circulating current energy state exists in the absence of an externally applied field. At this point, the field direction reverses, causing the soft layer to switch direction again and align with the hard layer, thereby creating the MJJ in the π state for read and sustain operations. However, unlike the example write operations shown in FIGS. 2 and 3, (i) the magnetic layers start and end in the same parallel direction (left-left 704-706), (ii) the applied magnetic field direction switches direction in a single write process, and (iii) it is never necessary for the pinned layers of all MJJs in the array to change direction if none of the MJJs in the array have an extremely low switching threshold, even though this may occur in some MJJs with low switching thresholds in a memory array having MJJs with non-uniform switching thresholds.

[0069] More specifically, in the alternative embodiment of FIG. 7 , the magnetic field reverses in a single write operation, instead of being reversed in each sequential write (i.e., across two write operations) as in the embodiment described with reference to FIGS. 2 and 3 . The transition of the MJJ from the π state to the zero state and back to the π state remains the same. However, in this case, the initial magnetic domain orientation (either right-right (RR) configuration or left-left (LL) configuration) of the soft and hard layers of the MJJ in the π state will be the same at the beginning and end of the write process for every write cycle. For non-limiting example purposes and without loss of generality, assume the MJJ is initially in the LL configuration (i.e., the magnetic domains in the top and bottom layers 704 and 706 point left). Writing the MJJ can be achieved by: (1) applying a right-handed magnetic field 710 (easy axis field component) when the junction is in the LL configuration corresponding to the π state; (2) increasing the magnetic field so that the easy / soft layer 714 and hard / pinned layer 706 change direction to a right-left (RL) configuration corresponding to the zero state; (3) removing the right-handed magnetic field 710; and (4) applying a left-handed magnetic field 712 so that the soft / easy layer changes direction to change the MJJ from the right easy layer 714 and left hard layer 706 to the LL configuration, where the soft layer 704 points left and the hard layer 706 points left, and the junction remains in the same π state as it started in; and (5) trapping a clockwise or counterclockwise current circulation in parallel with step (4), as set by a “seed” current for the superconducting loop containing the MJJ. The "seed" current can be induced by a negative or positive π phase setting current, which can be driven through voltage generator 106 of Figure 1. The final clockwise or counterclockwise π state current can be used to indicate a logic state (e.g., "1" or "0") to be stored in a storage circuit (e.g., 100 of Figure 1).

[0070] Second Alternative Burning Method 8 include the following: (i) the π state of the MJJ of FIG. 7 is a parallel magnetic orientation of the soft (free) and hard (pinned) layers, whereas the π state of the MJJ of FIG. 8 is designed to be an antiparallel orientation of the soft and hard layers through selection of the MJJ materials and their associated thicknesses; and conversely, (ii) the zero state of the MJJ of FIG. 7 is an antiparallel magnetic orientation of the soft (free) and hard (pinned) layers, whereas the zero state of the MJJ of FIG. 8 is a parallel orientation of the soft and hard layers. Either the π state or the zero state MJJ state can be designed as a function of one or more properties of the MJJ, including material types / properties, material thicknesses, and relative orientations of the pinned and free layers.

[0071] In alternative embodiments, the write process for an MJJ follows a similar process with MJJ layers of alternative orientations. As previously mentioned, the thicknesses of the ferromagnetic layers 804, 806 can be configured to result in an overall phase of zero across the junction when the soft and pinned layers are aligned parallel, and an overall phase of π across the junction when the layers are antiparallel. FIG. 8 illustrates an alternative process for transitioning from a π state to a zero state and back to a π state, according to one or more embodiments, where the magnetic domains of the layers start and end with a left-right orientation. Specifically, FIG. 8 illustrates an example time evolution of the magnetic layers of an MJJ from antiparallel to parallel and back to antiparallel. Associated applied magnetic field directions 810, 812 drive the magnetic layer evolution. The magnetic field can change in strength and direction over time. Below the magnetic field layer configuration, the superconducting loops (inductive loops) containing the MJJs are shown in their respective minimum energy states 220, 222, 224, 230, 232.

[0072] Referring to Figure 8, in the left-hand diagram 802, when a magnetic field 810 is applied (oriented to the right) in the initial state, the layers are oriented left / right (soft layer 804 and pinned layer 806, respectively). The MJJ has two potential wells 220, and one of the two potential wells (but not both) will be occupied by a circulating current. In the middle configuration, both the soft layer 814 and the hard layer 806 are oriented to point to the right, indicating that the field strength is sufficient to switch the soft layer. At the top of the diagram, the energy levels of the inductive loop flatten out (222 and 224), as shown between the left-hand and middle configurations. When the MJJ is in the zero state, no circulating current energy state can exist in the absence of an externally applied field. The applied magnetic field now reverses direction 812, causing the soft layer to switch direction again from 814 to 804, antiparallel to the hard layer 806, thereby setting the MJJ in the π state. 2 and 3, (i) here the magnetic layers start and end in their original antiparallel orientation, (ii) the applied magnetic field direction switches direction in a single write process, and (iii) the pinned layer does not change direction through the change of state of the MJJ (from the π state to the zero state and back to the π state) but rather remains in the same orientation 806. During a read operation or standby, the MJJ is similarly always in a π state, which has two possible energy states (positive and negative π states); which energy state is occupied can be determined by the circulating current passing through the MJJ (e.g., MJJ 110 of FIG. 1).

[0073] How to write a π junction Although the overall coherent rotation of the magnetic layers can preclude the π-junction from transitioning through the zero state according to Stoner-Wohlfarth theory, individual domain wall rotations at multiple domain wall π-junctions may not preclude such zero-state transitions.

[0074] FIG. 9 conceptually illustrates an example write method 900 for an MJJ having a ferromagnetic layer with multiple domains (i.e., composed of multiple domains), according to one or more embodiments. The write method 900 is illustrated in FIG. 9 by the left-to-right time evolution of the ferromagnetic layers of the MJJ with domain orientations 904, 906, and 908 and an applied magnetic field direction 910, which is assumed to vary in strength (but not direction) over time. Below the magnetic field layer configuration, the respective minimum-energy states 220, 222, 224, 230, and 232 of the inductive loop containing the MJJ are shown. In the initial left-hand illustration, when the magnetic field 910 is applied, the layer orientation 904 points to the left. The inductive loop has two potential wells in this state, only one of which is occupied by a circulating current.

[0075] In the center diagram, layer configuration 906 contains some domains pointing left and some domains pointing right. This can result in zero collective spin-valve Cooper pair phase shift when the MJJ and layers are configured with certain properties (some of which are described later), thereby driving the MJJ toward the zero state. As shown between center configuration 906 and right-hand configuration 908, the energy level 222 of the inductive loop flattens out. When the MJJ is in the zero state in configuration 906, no circulating current energy state can exist in the absence of an externally applied field. Right-hand configuration 908 shows all domains aligned and pointing right as the applied magnetic field 910 is further increased. In right-hand configuration 908, the MJJ is also in the π state and has two possible energy states (e.g., two possible circulating currents). The occupied energy state can be determined by the circulating current through the MJJ at the layer orientation 908.

[0076] As with other write processes described in this disclosure, the goal of this example write process may be to remove the barrier between circulating currents by entering a temporary zero state of the MJJ, thereby creating a single, low-energy state with zero circulating current before transitioning back to the π state. Such single-layer, multi-domain magnetic junctions can also achieve their goals if they have one or more of the following favorable properties: the layer can contain multiple domains, including domains stacked on top of each other along the direction of current flow; these domains can be individually aligned in opposite directions (e.g., left or right) in the absence of an applied magnetic field; these domains can be switched under varying field strengths such that their cumulative phase variation at repeatable field strengths is zero (i.e., the junction becomes a standard junction); and these domains can maintain their orientation over sufficiently long time scales in the absence of a field. The ferromagnetic layer can be fabricated so that the layer thickness (cross-section) achieves the properties recommended above and contains enough domains to produce an overall π phase variation across the junction when all domains are aligned. Note that this approach requires that the null state of the junction be accessible only when placed under an appropriate magnetic field; the configuration does not necessarily need to be accessible when the applied field is zero.

[0077] Writing method overview and summary Figures 10 through 14 are flow diagrams depicting at least a portion of an example write operation according to an embodiment of the inventive concept. As shown in Figures 10 and 11, in the example embodiments depicted in Figures 2 and 3, respectively, and in the π-junction write embodiment depicted in Figure 9, write operations 1000 and 1100 are coupled / paired (N and N+1) because the orientation of the MJJ in these embodiments is configured to switch to an orientation opposite its initial orientation after each write operation. Figures 12A and 12B depict write operations 1200 and 1250 for a selected half (i.e., a partially selected) MJJ that receives no applied magnetic field and only magnetic flux coupled from a π-phase setting current within its associated superconducting loop (e.g., the example loop including the secondary winding / wire L2 of transformer 106 and MJJ 110 of Figure 1). The connecting magnetic flux does not update its clockwise or counterclockwise circulating current because the barrier separating the two possible degenerate energy states is, statistically speaking, too high to allow such a change.

[0078] Referring to FIG. 10, it is important to note the three MJJ configurations and their order associated with the first write operation 1000: (i) MJJ configuration 1002 (π state, where the magnetic soft layer and magnetic hard layer point in a first direction); (ii) MJJ configuration 1004 (zero state, where the magnetic soft layer and magnetic hard layer point in opposite directions); and (iii) MJJ configuration 1006 (π state, where the magnetic soft layer and magnetic hard layer point in a second direction).

[0079] 11 , it is important to note the three MJJ configurations and even their order associated with the second write operation 1100: (i) MJJ configuration 1006 (π state, in which the magnetically soft and hard layers point in a second direction); (ii) MJJ configuration 1004 (π state, in which the magnetically soft and hard layers point in the opposite direction); and (iii) MJJ configuration 1002 (π state, in which the magnetically soft and hard layers point in a first direction). The progression of the write operation 1100 of FIG. 11 through these configurations is reversed relative to the example write operation 1000 of FIG. 10. It should also be noted that the “opposite” configuration 1002 can abstractly represent both antiparallel configurations LR (e.g., FIG. 10 ) and RL (e.g., FIG. 11 ).

[0080] The transitions between configurations 1002, 1004, and 1006 can be facilitated by application of a magnetic field (with an easy axis component). In the transition from configuration 1004 to 1006, parallel π-phase setting currents define the final state for storage circuit 100 shown in FIG.

[0081] By way of example only and not limitation, in the exemplary writing method 1000 shown in FIG. 10, actions may include: (i) A first step 1010 involves application of a magnetic field having an easy axis field component opposite to the first direction of the MJJ to transition from configuration 1002 to configuration 1004; (ii) The next step 1012 involves [1] application of a magnetic field with an easy axis field component oriented in the same direction as the first step 1010 of the MJJ, and [2] application of a positive or negative π phase setting current in transition of the MJJ from configuration 1004 to configuration 1006.

[0082] As shown by Figures 12A and 12B, a selected half write operation 1200, 1250 involving only the application of a π phase setting current and no application of a magnetic field to the MJJs of the "selected half" storage circuit does not change the state of the circulating currents (representing Boolean states) of the "selected half" storage circuit, which are coupled to the entire selected storage circuit via the write column lines, in the example embodiments depicted in Figures 2 and 3 and the π junction write embodiment depicted in Figure 9.

[0083] Figure 13 shows an example write method 1300 including write operations for the first and second alternative embodiments depicted in Figures 7 and 8, where the orientations of the soft and hard layers of the MJJ are specifically the same before and after each write operation. Similar to the write operations 1000 and 1100 of Figures 10 and 11, respectively, the applied magnetic field specifically needs to be reversed during the write operation 1300 to facilitate the transition of the MJJ from the π state through the zero state and back to the π state.

[0084] 13, it is important to note that the sequence of three MJJ configurations associated with a write operation 1300, according to one or more embodiments, is as follows: (i) MJJ configuration 1302 (π state, with the soft and hard magnetic layers pointing in a first direction); (ii) MJJ configuration 1304 (π state, with the soft and hard magnetic layers pointing in opposite directions); and (iii) MJJ configuration 1302 (π state, with the soft and hard magnetic layers pointing in a first direction). Notably, the starting configuration and the ending configuration are the same (i.e., MJJ configuration 1302).

[0085] The transition between configurations 1302 and 1304 can be facilitated by application of a magnetic field (with an easy axis component). Writing can also require a π-phase setting current to define the final state for the storage circuit 100 of FIG.

[0086] In the write method 1300 depicted in FIG. 13, one or more example actions may include: (i) A first step 1310 involves applying a magnetic field having an easy axis field component opposite to the first direction of the MJJ to transition from configuration 1002 to configuration 1004; (ii) The next step 1312 involves [1] applying a magnetic field having an easy axis field component oriented in line with the first direction of the soft layer of the MJJ, and [2] applying a positive or negative π phase setting current in transitioning the MJJ from configuration 1004 to configuration 1002.

[0087] 14 illustrates an example write method 1400 involving “selected half” write operations, according to one or more embodiments, that do not change the state of their corresponding partially selected (i.e., selected half) storage circuits because, by definition, their MJJs are not subjected to a magnetic field. The partially selected storage circuits may be connected to the fully selected storage circuits via write column lines carrying positive or negative π-phase setting currents, in the case of the first and second alternative embodiments illustrated in FIGS. 7 and 8.

[0088] It should be understood that the write operation corresponding to Figure 8 can be abstracted to be approximately equivalent to the write operation of Figure 7, which is abstracted by Figures 13 and 14, with the equal initial and final magnetic domain orientations of the soft and hard layers of the MJJ being antiparallel in the case of Figure 8, rather than parallel as in the case of Figure 7. Furthermore, the zero state in Figure 8 is specifically antiparallel, whereas it is parallel in the case of Figure 7.

[0089] Advantages of memory circuit read margin 15 conceptually illustrates the increased read margin advantage of a memory circuit, such as memory circuit 100 shown in FIG. 1, that may be written in accordance with one or more embodiments of the present invention. The effective critical current I of the memory inductive loop (the superconducting loop of memory circuit 100 containing elements 102, 104, 108, and 110 connected in series)C is shown as a function of applied flux Φ, which in this design includes both the flux applied via the current and transformer and the effective flux applied via the Cooper pair phase advance created by the MJJ. In this figure, applied fluxes 1502, 1506, and 1510 and effective fluxes 1504 and 1508 are shown to vary the effective critical current applied along the column line CL (or read bit line) in FIG. 1. A negative circulating current due to the effective flux (opposite to the direction of the circulating current induced by the read flux application) drives the state from zero to the left (arrow 1508 pointing left). A positive circulating current (also due to the π state of the MJJ) drives the state from zero to the right (arrow 1504 pointing right). The read flux is indicated by three right-pointing arrows. When applied against a positive circulating current (from arrow 1504), the readout flux is applied as obtuse arrow 1502, resulting in a flux shown by line 1520. When applied against zero MJJ flux, the readout flux is shown as obtuse arrow 1506, resulting in a flux shown by line 1522. The resulting effective I C The value is indicated using the difference by the double arrow 1532. These two states are the prior art operating states, and the critical current I C In the present invention, the negative effective magnetic flux indicated by the negative circulating current state is shown by arrow 1508. When a read flux is applied, the read flux is shown as an obtuse arrow 1510, with the total magnetic flux along vertical line 1524. The corresponding I C The values ​​are shown at the "+π" level, with the margin difference indicated by the (larger) double arrow 1530 (as opposed to the (smaller) double arrow 1532 of the viable prior art scheme). The vertical lines in the diagram indicate the resulting effective critical currents, indicated by the horizontal lines labeled +π and -π. For reference, the design utilizing zero effective magnetic flux (circulating current) is shown at the bottom as the obtuse arrow 1506 pointing to the right, with the corresponding I Cis shown as a horizontal line with π written as 0. While the absolute critical current threshold for read for one Boolean state (here the +π configuration, with a positive circulating current state in both cases) is equal, the effective critical current read threshold for the other logic state is significantly higher in this approach (-π level in this design, 0 level in the previous design), thereby increasing the read margin budget for the applied read flux and read current.

[0090] For the original design, the dashed horizontal line at 0 indicates the effective critical current during readout. For the π-to-π design, the dashed horizontal line at π indicates the effective critical current during readout. While the margin does not double, the difference can be noticeable and overcome changes in read pulse strength or coupling or changes in JJ device characteristics, all of which can worsen the read margin budget.

[0091] Alternative forms of write circuitry to assist in generating the alternating positive and negative magnetic fields necessary to support embodiments of the inventive concepts There may be many alternatives contemplated by the inventive concepts for generating and driving alternating positive and negative currents (row currents for RAM) required to generate corresponding alternating positive and negative magnetic fields that drive the π-0-π transitions of the disclosed MJJs across or during one or more writes to the MJJ. In general, alternating write operations according to embodiments of the present invention may require bidirectional current application for magnetic field generation and / or seed current generation.

[0092] Superconducting alternatives can utilize a flux shuttle to generate, store, and release magnetic flux quanta in a process that generates the required alternating positive and negative currents, which are essentially released magnetic flux quanta. While the prior art can describe (Bi)CMOS-based alternatives that can directly provide positive and negative currents, the prior art does not describe the need for, and the ability to apply, alternating positive and negative currents along specific write row lines across single or successive write operations. Additional alternatives with enhancements required by embodiments of the present invention are described in the following sections entitled "Superconducting Magnetic Field Driver" and "(Bi)CMOS Magnetic Field Driver Integrated in RAM."

[0093] Superconducting Magnetic Field Driver To apply a magnetic field to at least one magnetic Josephson junction in a superconducting circuit, a store-then-release method can be used to sequentially apply the maximum possible current to a series of junctions, in which magnetic flux (current) is built up and stored in a superconducting loop and then quickly released. An exemplary circuit that enables this functionality is commonly known as a "flux shuttle."

[0094] More specifically, in accordance with one or more embodiments of the present invention, a driver incorporating a flux shuttle for directing opposing currents to implement π-0-π state transitions of an MJJ across or during one or more write operations to the MJJ is described. In contrast to flux shuttle-based drivers, (Bi)CMOS circuits inject current to ground, thus effectively losing current and dissipating power. As used herein, the term “(Bi)CMOS” is intended broadly to refer to circuits and / or circuit elements that are non-superconducting. In some applications, such as those involving only one current direction, it may be preferable to reduce the current to ground in both the flux shuttle-based driver and the (Bi)CMOS driver approaches. However, with the reciprocating current required in some embodiments, there may be an opportunity to recapture the current used in one write cycle and apply this recapture current in the next write cycle. The flux quanta of a large multi-flux current pulse can be captured rather than lost as described by one or more embodiments of the present invention.

[0095] One possible configuration of a general row circuit is to couple the end of a write row line to the storage inductor of the flux shuttle via mutual inductance and mutual capacitance to drive current in the desired direction through the pump and storage loops. The trapping of magnetic flux artificially causes the junction in the pump to spontaneously reverse, thereby generating additional magnetic flux in the storage inductor of the flux shuttle in a single clock cycle. This configuration may require two write row lines. For example, the desired opposing magnetic fields can be applied by creating one magnetic field above the MJJ and the other below the MJJ. Extending the write row lines back to the same side allows for control on only one side. Furthermore, with appropriate selection of coupling and terminal values, a single write row line can be shared by superconducting flux shuttle-based drivers located on both sides of the memory array for launching and recovering the write current using the nonlinear properties of the junction to redirect the current.

[0096] As is known in the art, superconducting solutions exist for generating magnetic flux stored as DC current, such as linear flux shuttles (see, e.g., U.S. Pat. No. 11,476,842; "Superconducting current source system," the disclosure of which is incorporated herein by reference in its entirety) or flux shuttle loops (see, e.g., U.S. Pat. No. 9,174,840; "Josephson AC / DC converter systems and method," the disclosure of which is incorporated herein by reference in its entirety).

[0097] However, some embodiments of the present invention describe write driver circuits incorporating more than a pair of flux shuttles; such write driver circuits may also include dedicated flip-flops that evaluate and assert opposing current supplies when required by one or more embodiments of the present invention. According to embodiments of the present invention, the flux shuttle storage loops are configured to connect to write row lines, each of which passes near a row of MJJs, so that write currents carried by the write row lines during write operations can generate localized magnetic fields that can be coupled to the row of MJJs. The ends of the write row lines (write word lines) (abbreviated as WRLs) (for RAM) can be coupled (capacitively and / or inductively) to the storage inductors to transmit magnetic flux pulses to the storage inductors. To supply write current (write flux), both flux shuttles can be triggered, as is commonly done.

[0098] 16A is a schematic diagram depicting at least a portion of an exemplary superconducting AC system (write circuit) 1600, in accordance with one or more embodiments of the present invention. The superconducting write circuit 1600, when engaged, can drive negative and positive currents, and in this exemplary application circulates negative and positive currents back and forth through interconnects / transmission lines, thereby generating a magnetic field in the vicinity of the MJJ for the purpose of selecting negative and positive currents for the write operation. The superconducting write circuit 1600 includes at least a first JTL 1602. A and at least a first flux shuttle 1606 A and at least the first JJ1608 A and at least one coupling device (e.g., at least a first transformer 1612 A Or at least the first capacitor 1614 A ), at least a first matching impedance (e.g., a resistor) 1616A, and a first write row line (transmission line) 1620. A and at least a second JTL1602 Band at least a second flux shuttle 1606. B and at least the second JJ1608 B and at least a second coupling device (e.g., at least a second transformer 1612 B and / or at least a second capacitor 1614 B ) and at least a second matching impedance 1616 B and a second write row line (transmission line) 1620 B and includes the flux shuttle 1606 A , coupling element 1612 A or 1614 A , impedance matching element 1616, and Josephson junction 1608 A collectively referred to as current launch and recovery circuits (or "superconducting AC circuits") 1604 A Forming a current launch and recovery circuit 1604 A is the first write row line 1620 A generating a DC current in the second write row line 1620; B and recovering current from the second flux shuttle 1606. B , second coupling element 1612 B or 1614 B , second impedance matching element 1616 B , and Josephson junction 1608 B collectively, transmission lines 1620 A and 1620 B a second current launch and recovery circuit 1604 for launching and receiving current pulses back and forth in alternating sequence on the B Form.

[0099] The prior art describes several flux shuttles, one of which is a JTL ring-based flux shuttle. However, any such flux shuttle may be used in embodiments of the present invention. The only assumptions are that the current flows through a storage inductor (transformer 1612 in FIG. 16A) and AThe flux increases in the secondary inductor L2, but the flux shuttle 1606 A and Josephson junction 1608 A Any sufficiently large inductor in series that forms a loop with radiating to the passive transmission line will work.

[0100] JTL1602 A , 1602 B can begin to store flux in the flux shuttle. Note that this design is necessarily symmetrical to one another, and the operation of the circuit from half A to half B works exactly the same in the opposite direction. After the initial condition triggering single flux quantum triggers (either a positive SFQ to stop the pump or a negative SFQ), the flux shuttle starts and transformer 1612 A (or 1612, if appropriate) B ) generates a magnetic flux stored in the storage inductor L2 and a large control junction 1608 A (or 1608, if appropriate) B ) and the write line 1620 A (or 1620 if appropriate) B galvanically coupled to the second write row line 1620 to recapture the current / flux on the receiving end of the first write row line. B (or 1620 if appropriate) A ) and the other end of the transformer 1612 B (or 1612, if appropriate) A ) and this results in a transformer 1612 B (or 1612, if appropriate) A ) the input current in L1 and other flux shuttle 1606 B (or 1606, if appropriate) A ) Transformer 1612 B (or 1612, if appropriate) A ) to the storage inductor L2 in the transformer 1612. These may be capacitively coupled to improve efficiency and adjust impedance. BInductor L1 and capacitor 1614 B , and resistor 1616 B The end termination impedance matching achieved by the other flux shuttle 1606 B (or 1606, if appropriate) A ) to "overdrive" the flux shuttle (e.g., 1606 B ) by itself to increase the load on the storage inductor more quickly than would be possible if the write line 1620 A (or 1620 if appropriate) B ) current is used.

[0101] 16B is a block diagram illustrating an example write circuit 1650 according to one or more embodiments. The write circuit 1650 is a simplified version of the example write circuit shown in FIG. 16A to emphasize the symmetry of the configuration and to add an additional flip-flop 1652. Specifically, the superconducting write circuit 1650 includes at least a first launch and recovery circuit 1604. A (Flux Shuttle 1606 A and at least a second launch and recovery circuit 1604 B and at least a first JTL1602A and at least a second JTL1602 B and at least a first write row line (transmission line) 1620 A and at least a second write row line (transmission line) 1620 B and at least a third JTL1602 C and at least a first flip-flop element 1652, which are connected to the first write row line 1620. A generating a DC current in the transmission line 1620; A and 1620 B a second write row line 1620 for driving and receiving current pulses back and forth in an alternating sequence on BFIG. 16B shows an alternative arrangement in which the launch and recovery circuits (or "superconducting write circuits") are located close to each other, thus allowing the write row line 1620 A , 1620 B The flip-flop element 1652 must return to the same adjacent position, such as the same side of the array, on alternate write cycles. A and then the other flux shuttle 1604 B This is one example of a mechanism for controlling the flux shuttle and / or releasing the stored current. Other variations of these main embodiments are contemplated and may be better suited depending on the control logic and data encoding in a particular application.

[0102] As noted above, FIG. 16B shows a simplified version of write circuit 1650. For example, the logic function of flip-flop element 1652 may, in practice, be more complex than shown in FIG. 16B. In one or more embodiments, flip-flop element 1652 may include, in addition to a conventional flip-flop, an output gating (enable) function corresponding to row selection, as further described with reference to FIGS. 17A, 17B, 17C, and 18, which depict an entire (Bi)CMOS write row system for an MJJ-based RAM.

[0103] 16C illustrates an alternative embodiment of a read or write enable circuit 1670 having a single write row line 1672 shared by both launch and recovery, according to one or more embodiments. The superconducting read or write enable circuit 1670 includes at least a first JTL 1602 A and at least a first flux shuttle 1606 A and at least the first JJ1608 A and at least one coupling device (e.g., at least a first transformer 1612 A、 Or at least the first capacitor 1614 A) and at least a first matching impedance (e.g., a resistor) 1616 A a write row line (transmission line) 1672, and at least a second JTL 1602 B and at least a second flux shuttle 1606. B and at least the second JJ1608 B and at least a second coupling device (e.g., at least a second transformer 1612 B and / or at least a second capacitor 1614 B ) and at least a second matching impedance 1616 B and includes the flux shuttle 1606 A , coupling element 1612 A or 1614 A , impedance matching element 1616, and Josephson junction 1608 A collectively referred to as current launch and recovery circuits (or "superconducting AC circuits") 1604 A Forming a current launch and recovery circuit 1604 A write line 1620 A Similarly, a DC current can be generated within the second flux shuttle 1606. B , second coupling element 1612 B or 1614 B , second impedance matching element 1616 B , and Josephson junction 1608 B collectively, a second current launch and recovery circuit 1604 for launching and receiving current pulses. B and the transmission of the current pulse is performed by the JTL1602 on the transmission line 1672. A , 16002 B The switching is performed back and forth in an alternating operation sequence monitored by the coupling capacitor 1614. A , 1614 B and transformer 1612 A , 1612 BCommon circuit elements such as are shown in similar configurations. By appropriately selecting element parameters, impedance can be matched or energy capture can be prioritized. Escape junctions (JJ1608 A , 1608 B ) will increase the inductance as current comes in from transmission line 1672, redirecting the current towards L1, thereby pulling current in the opposite direction through L2, causing flux shuttle 1606 A , 1606 B In all diagrams, an additional termination resistor may be included to dissipate power rather than reflect it.

[0104] A read use case for the superconducting read or write enable circuit 1670 is described with reference to FIG. 22A.

[0105] (Bi)CMOS magnetic field driver integrated into RAM By way of example only and without limitation, and without loss of generality, Figures 17A and 17B are schematic diagrams depicting example circuits suitable for use in connection with RAM write circuitry (examples of RAM write circuitry are discussed with reference to Figure 18) in accordance with one or more embodiments of the present invention. These example circuits are directed to performing the example write operations described in conjunction with Figures 2-6 and 10-12B. However, it should be understood that modifications to these example circuits may enable any of the write operations described herein and are within the scope of embodiments of the inventive concepts.

[0106] 17A is a schematic diagram illustrating at least an example hybrid superconducting and (Bi)CMOS write address decoder 1700 featuring current reversal control according to one or more embodiments. The superconducting and (Bi)CMOS write address decoder 1700 can include a (Bi)CMOS write address decoder 1712, a conversion circuit 1714 configured to convert a superconducting signal to a (Bi)CMOS signal suitable for use with the (Bi)CMOS write address decoder 1712, and a current reversal control circuit 1710 operably connected to the (Bi)CMOS write address decoder 1712.

[0107] The superconducting signal (referred to as an "encoded write address") may be converted to a (Bi)CMOS signal with the aid of a Suzuki stack or other conversion circuitry, which may be included in conversion circuitry 1714, according to one or more embodiments. By directly interfacing with (Bi)CMOS write address decoder 1712 (and / or (Bi)CMOS row write circuitry 1804, to be discussed with reference to FIG. 18), the (Bi)CMOS signal so converted may be, for example, (i) a write row line current I WRL (ii) other signals (e.g., write column line current I WCL_1 and I WCL_M (pulse associated with the write row line current I WRL and (iii) address signals for selecting particular rows within the storage circuit. Optionally, the address signals may be "encoded," as shown in FIG. 17A, to reduce the size of the conversion circuit 1714.

[0108] Addresses and time triggers (clock signals) associated with write operations may be communicated through conversion circuitry 1714, which, in one or more embodiments, may provide bit conversion ranging from substantially serial to substantially parallel conversion. Substantially serial bit conversion may reduce the area of ​​the superconducting die, particularly associated with Suzuki stacks, whereas substantially parallel bit conversion may be employed in applications where increased conversion speed is preferred.

[0109] The current reversal control circuit 1710 may include, for each bit (1 to N, where N is an integer greater than or equal to 2) of the decoded write address, at least one first-second current direction flip-flop 1702, at least one NAND gate 1704, at least one inverter gate 1706, and at least one AND gate 1708, such that the flow of current in the first or second direction through a selected row may be determined by the logic state stored in the first-second current direction flip-flop 1702 corresponding to each row of the storage circuit.

[0110] Each bit 1 through N of at least a subset of bits in the decoded address signal is provided to an input of a corresponding flip-flop (first and second current direction flip-flops) 1702 and to a first input of a corresponding NAND gate 1704 and AND gate 1708. The output of the first and second current direction flip-flops 1702 may be connected to a second input of the AND gate 1708 and an input of an inverter 1706. The output of the inverter 1706 may be provided to a second input of the NAND gate 1704. The output of the NAND gate 1704 is configured to generate a complement direction address signal, and the output of the AND gate 1708 is configured to generate a true direction address signal. While the current reversal control circuit 1710 may be described with reference to specific logic gates (e.g., AND 1708, NAND 1704), it should be appreciated that other configurations using circuit elements implementing equivalent logical functions are also contemplated.

[0111] FIG. 17B is a schematic diagram illustrating at least a portion of an example first-second current direction flip-flop 1702 that may be used within the superconducting and (Bi)CMOS write address decoder 1700 shown in FIG. 17A , according to one or more embodiments. The first-second current direction flip-flop 1702 preferably supports a row write circuit of an MJJ-based superconducting RAM. Referring to FIG. 17B , the first-second current direction flip-flop 1702 may include a first delay element (Inv_Delay_1) 1752, a falling (or, in an alternative design, rising) edge-sensitive clock chopper 1758, and a flip-flop 1760 (a pulsed / SCAN / shift-initialized flip-flop or other latch circuit).

[0112] More specifically, referring to FIG. 17B , a first-second current direction flip-flop 1702 is adapted to receive as an input at least a portion of a decoded address, which is provided to an input of a first delay element 1752. An output generated by the first delay element 1752 at node 1, which is an inverted and delayed version of a portion of the decoded address input signal In, is provided to a clock chopper 1758, which in some embodiments may be implemented using a second delay element 1754 and a NOR gate 1756. Specifically, the output of the first delay element 1752 may be provided as an input to the second delay element 1754 and a first input of the NOR gate 1756. The output generated by the second delay element 1754 may be provided to a second input of the NOR gate 1756 (the second input is essentially a delayed version of the first input). The output of the NOR gate 1756 may be provided as a clock signal to trigger the flip-flop 1760. The output of the flip-flop 1760 may form the output (Out) of the first-second current direction flip-flop 1702 .

[0113] The state of flip-flop 1760 may be flipped after each write operation (described in further detail in conjunction with FIG. 18) targeting its corresponding row, such that the output (Out) of flip-flop 1760 drives the logic of current reversal control circuit 1710 in the selected row to reverse current flow for subsequent write operations to that row. First delay circuit 1752 and clock chopper 1758 may be configured to create a trigger (clock) to ensure the current reversal signal is applied at the appropriate time only after the write operation is completed.

[0114] 17C is an example timing diagram 1770 depicting at least some of the signals generated within the example first-second current direction flip-flop 1702 shown in FIG. 17B, which may be useful in explaining the internal operation and external function of the first-second current direction flip-flop 1702, according to one or more embodiments. Timing diagram 1770 shows a row select pulse presented at the input (“In”) of first-second current direction flip-flop 1702, which may be used to configure first-second current direction flip-flop 1702 for the next row operation by flipping its internal state. A trigger pulse on the clock node (input of flip-flop 1706) ensures proper timing of the event, preferably flip-flop 1760 being flipped only after a write operation. The two possibilities for flip-flop state reversal are as follows: (i) dashed line 1782 (waveform) indicates the transition of flip-flop 1760 (or first-second current direction flip-flop 1702) from the 1 state to the 0 state; (ii) solid line 1780 (waveform) indicates the transition of flip-flop 1760 (or first-second current direction flip-flop 1702) from the 0 state to the 1 state.

[0115] More generally, a write address decoder for an MJJ featuring current reversal control (e.g., circuit 1700 shown in FIG. 17A) can include a write address decoder (e.g., 1712 in FIG. 17A) and a current reversal control circuit (e.g., 1710 in FIG. 17A). Additionally, as an alternative to forming a more localized clock (e.g., via first delay element 1752 and clock chopper 1758 shown in FIG. 17B), it is contemplated that the clock for triggering flip-flop 1760 to reverse its state by itself can be formed by logically ANDing a global clock with the decoded address (associated with each row).

[0116] FIG. 18 is a schematic diagram depicting at least a portion of an example write circuit 1800 for writing MJJs in accordance with one or more embodiments of the present disclosure. Using a mixed superconducting and (Bi)CMOS write circuit, the example write circuit 1800 can be embedded in a superconducting memory cell. To aid in understanding this example embodiment, the conductor currents and gate voltages of example n-channel field-effect transistors (NFETs) and p-channel field-effect transistors (PFETs) (i.e., FETs) associated with the active mode of the write circuit 1800 are shown in FIG. 18 by way of example, but not limitation, and without loss of generality. The column write line current generated within the write circuit 1800 can be positive (i.e., a first direction) or negative (i.e., a second direction), according to one or more embodiments, depending on which state is being written to each memory cell in a selected set of memory cells. However, it should be understood that embodiments of the present invention are not limited to any particular assignment of current direction and / or current polarity.

[0117] Furthermore, the underlying technology used to implement the write circuitry itself can be either (Bi)CMOS technology, superconducting technology, or a hybrid (combination) of both (Bi)CMOS technology and superconducting technology to achieve the desired application of magnetic field and magnetic flux to write the superconducting memory cell 1802 having at least one MJJ.

[0118] As will be explained in more detail below, the write circuit 1800 advantageously enables the application of a π-phase setting seed current in either a clockwise or counterclockwise direction to the superconducting loop of the storage circuit through the MJJ stack of material via a transformer (e.g., transformer 106 of FIG. 1 ) (according to which the column line connections are formed) or via another coupling element associated with the storage circuit. The write circuit 1800 can be used to “write” or “program” MJJs, which can function as memory elements in JMRAM or JMPLA, as known in the art. A further requirement for the write operation is that the write circuit 1800 generates a bidirectional easy axis field component in the plane of the MJJ.

[0119] Continuing with reference to FIG. 18, write circuitry 1800 preferably includes a plurality of memory cells 1802 (memory cells <1> <1> From memory cells <n> <n>(N and M are integers (N and M may or may not be equal)), at least one (Bi)CMOS row write circuit 1804, a column write circuit 1806 (which in the illustrated embodiment includes first and second elements), and a plurality of write row lines WRL1 to WRL2 connected to the row write circuit 1804 and preferably arranged in a row orientation (or horizontal orientation). M and a plurality of write column lines WCL1 to WCL2 connected to column write circuitry 1806 and preferably arranged in a column orientation perpendicular to the write line rows (e.g., vertical orientation). M In this configuration, where each memory cell 1802 to be written can have at least one MJJ, the (Bi)CMOS row write circuit 1804 supplies a write row line current I WRL and a write row line current I WRL Write row lines WRL1 to WRL N The column write circuitry 1806 is carried by a selected one of the write row lines. While the column write circuitry 1806 may preferably be superconducting, which would provide significant power savings, it should be understood that the column write circuitry 1806 need not be superconducting; that is, the column write circuitry 1806 may be implemented using non-superconducting elements or a hybrid of superconducting and non-superconducting elements (depending on the desired tradeoff between chip area and power consumption).

[0120] Each write column line WCL1 to WCL M A first element of column write circuitry 1806 (preferably, but not necessarily, superconducting to achieve significant power savings) that may be connected to the bottom end of each write column line, and a second element of column write circuitry 1806 (preferably, but not necessarily, superconducting) that may be connected to the top end of each write column line, collectively provide a supercurrent I WCL_1 From I WCL_M and a plurality of write column lines configured to generate a superconducting current I WCL_1 From I WCL_M are the write column lines WCL1 to WCL M 18. It is contemplated that more than one write column line may be associated with each column of memory cells 1802, i.e., that memory cells 1802 may require more than one column input to complete a write operation, either for selection or for defining a state. Similarly, it is contemplated that more than one write row line may be associated with each row of memory cells 1802, i.e., that memory cells 1802 may require more than one row input to complete a write operation, either for selection or for defining a state.

[0121] Write column lines 1 to M (WCL1 to WCL M ) are the write column line currents I WCL_1 From I WCL_M into the memory cells 1802, and in some embodiments, may be arranged to pass through a transformer in at least each subset of the memory cells 1802. As previously described in connection with the example storage circuit 100 of FIG. 1, the transformer 106 of the example storage circuit 100 can receive a clockwise or counterclockwise π-phase setting seed current, which induces a proportional secondary current for setting a clockwise or counterclockwise π-phase current in the superconducting loop of the storage circuit 100. In the example write circuit 1800 of FIG. 18, at least each subset of the memory cells 1802 is connected to the example memory write circuit of FIG. The memory cell 100 may comprise a memory write circuit 1800, which are connected in series along a given write column line WCL, for example by connecting the second terminals "In_Out_2_π phase setting" of each of the memory cells 100 (FIG. 1) to the first terminals "In_Out_1_π phase ground" of the memory cells 100, except at the ends of the write column line WCL, where the column line thus formed of the memory cells 1802 is connected at a first end to a second element of a column write circuit 1806 (preferably, but not necessarily, superconducting) and at a second end to a first element of the column write circuit 1806, along the given write column line WCL, for setting a clockwise or counterclockwise π-phase current in the superconducting loop of each memory cell, and in particular of a "selected" one of the memory cells 1802.

[0122] The first and second elements of the column write circuit 1806 are configured to control the write column line current I as described in U.S. Patent Application No. 17 / 993,586 to Reohr, which is incorporated herein by reference in its entirety. WCL_1 From I WCL_M , and can adapt each column line current as a negative or positive current. Each of these data preferably defines the sign (i.e., direction) of the current flowing in the corresponding column. The data is provided to both the first and second elements of the column write circuit 1806, where it can be used to trigger portions of the superconducting circuit into voltage states, thereby applying the voltages to the respective write column lines WCL1 through WCL2. M Note that the current is redirected and guided along a particular path that defines the sign of the current carried in each of the electrodes.

[0123] In one or more embodiments, the column current can induce a π-phase setting seed current in either a clockwise or counterclockwise direction in the superconducting loop of the memory cell 1802. While not equivalent to a (Bi)CMOS push-pull circuit in terms of its internal functionality, the superconducting bidirectional driver described in U.S. Patent Application No. 17 / 993,586 to Reohr performs a similar global function as a push-pull circuit, i.e., to drive a positive or negative current (i.e., a first direction or a second direction) based on an input data signal.

[0124] Alternative (Bi)CMOS and superconducting column write circuits (to 1806) are known in the art and may be configured for use with at least some aspects of the inventive concepts. Some of these alternative (Bi)CMOS and superconducting column write circuits may have a write column line current I that can be sourced from and returned to the same superconducting column write circuit. WCL This capability is made possible by the use of wrap-around connections in the write-column lines, each of which is configured to connect a pair of adjacent even and odd write-column lines.

[0125] The (Bi)CMOS row write circuit 1804, in one or more embodiments, writes the memory cells 1802 <1> <1> from <n> <m>Write row lines WRL1 to WRL M Which of the write row lines is the write row line current I WRL and a write row line current I in the row selected for the write operation. WRL 17A) for selectively controlling the direction (in other words, negative or positive current) that the write row lines WRL1 to WRL2 will take. Corresponding pairs of FETs (NFET 1812 and PFET 1813) in first and second (Bi)CMOS row write circuits 1804, 1805, working together, can be configured to selectively control the direction (in other words, negative or positive current) that the write row lines WRL1 to WRL2 will take for the purpose of writing the memory cell 1802. M Write row line current I WRL , and to control the direction of the write row line current.

[0126] More specifically, each of the FETs (NFET 1812 and PFET 1813) in the first and second (Bi)CMOS row write circuits 1804, 1805 preferably connects to the write row lines WRL1 to WRL N 18. The write address decoder 1700 includes a first source / drain connected to a corresponding one of the write row lines, a second source / drain connected to a voltage source, which may be programmable, and a gate adapted to receive a corresponding one of the control signals generated by a superconducting and (Bi)CMOS write address decoder 1700 featuring current reversal control (first decoder 1700 configured to generate a first subset of control signals to be supplied to a first row write circuit 1804 and a second decoder 1700 configured to generate a second subset of control signals to be supplied to a second row write circuit). The first and second subsets of control signals can function in conjunction with each other to enable or disable a pair of FETs (NFET 1812 and PFET 1813) in the first and second row write circuits 1804 and 1805 associated with the same write row line. In one or more embodiments, a voltage supplied to the second source / drain of each of NFETs 1812, 1813 results in a write row line current I WRL can be independently controlled so that the magnitude and direction can be optimized according to the characteristics of the individual MJJ within each memory cell 1802 to be written.

[0127] By way of example only and not limitation, when two corresponding pairs of FETs 1812, 1813 (a first NFET 1812 and a first PFET 1813; and a second NFET and a second PFET) connected to the same write row line, such as WRL1, are configured such that the source / drain of the FETs 1812, 1813 in the second row write circuit 1805 are connected to ground and VDD, respectively, and the source / drain of the FETs 1812, 1813 in the first row write circuit 1804 are connected to ground and VDD, respectively, the write row line current I WRL will flow in one of two directions depending on the first and second subsets of control signals. Figure 18 shows, for example, (i) the write row line current I as it flows from the first row write circuit 1804 to the second row write circuit 1805 when carried through write row line 1; WRL and (ii) the voltage that can be induced on the write row line N(WRL N ) through the first row write circuit 1804. Similarly, (i) the first write row line current I from the second write row circuit 1805 to the first row write circuit 1804 is shown. WRL and (ii) voltages that can disable all other current paths between write row circuits 1804 and 1805. The current flow can be governed by control signals (which can be driven to ground or VDD) to the gates of the corresponding FETs. Thus, as is known in the art, the write row circuits 1804, 1805 and the write row lines WRL1 to WRL N In one or more embodiments, a push-pull circuit configuration for each write row line WRL can be enabled to drive a write row line current I in a specified direction through the selected write row line. WRI Only one pair of FET switches is enabled during a given write cycle to guide the . A regulated voltage can be induced at a point labeled "VDD" to control the magnitude of the write row lines in this circuit.

[0128] In Figure 18, write row lines WRL1 through WRL N Segments of an exemplary MJJ 1822 and WRL 1824 are included near memory write circuit 1800 to illustrate a preferred relative orientation of all MJJs corresponding to memory cell 1802 with respect to π. Such a preferred orientation, particularly less than 90 degrees, reduces the magnetic field requirements in driving the magnetic layer of each MJJ in memory cell 1802 from a first π state, through a zero state, and into a second π state, thereby reducing the magnitude of the write row line current required to generate the magnetic field. This minimum write margin for the MJJs is shown in FIG. 4 and is labeled "(iv) New π State."

[0129] Overview for programming PLA and FPGA By way of example only and without loss of generality, Figures 19, 20, and 21 depict exemplary schematic diagrams useful for describing techniques for programming memory circuits, such as PLAs, ROMs, and / or FPGAs, according to one or more embodiments of the present invention. The exemplary methodologies for programming circuits shown in Figures 19-21 can be distinguished from conventional / known approaches by virtue of at least their additional ability to provide the alternating, reversing applied easy-axis magnetic field components necessary to achieve an easy-axis-based π-0-π state transition on at least one MJJ selected from a set of MJJs. As previously noted for all astroid-based diagrams, such as Figures 4 and 5, the applied magnetic field can include a hard-axis field component in addition to the easy-axis field component to reduce the total field strength required to overcome the magnetic switching threshold of the free and pinned layers of the MJJ.

[0130] We now describe the application of FIGS. 19, 20, and 21 to the preferred write methodology previously described with reference to FIGS. 2, 3, 4, 6, 10, 11, and 12. The underlying (Bi)CMOS circuitry may be capable of current carrying. The advancement over known circuits and methodologies for writing MJJ-based memory circuits taught in this particular embodiment of the present disclosure may involve the inclusion of at least one MJJ domain orientation attribute that serves a role similar to that of the first-second current direction flip-flop 1702 in FIG. 17A for the (Bi)CMOS write address decoder 1700 featuring current reversal control. The MJJ domain orientation attribute coordinates the current reversal between a current write operation and the next write operation targeting at least one particular MJJ, so that an easy-axis-based π-0-π state transition can be achieved in both writes. In other words, the magnetic field applied to the MJJ should be opposite its soft and hard layer domain orientations.

[0131] 19 is a conceptual diagram conceptually illustrating the magnetic field application portion of an exemplary MJJ write circuit 1900, in accordance with one or more embodiments of the present invention. The MJJ write circuit 1900 advantageously provides a highly reliable, process variation resistant mechanism for programming (i.e., writing) the phase (e.g., state) of MJJs in MJ-based circuits. Referring to FIG. 19, the MJJ write circuit 1900 writes multiple MJJs 19021 to 19022. N Each MJJ has a unique corresponding write line segment (WLS) line WLS1 to WLS N where N is an integer greater than or equal to 2. The WLS associated with a given MJJ is preferably oriented at an angle to the major axis of the MJJ as the WLS passes near and over the free (soft) layer of the MJJ, rather than being positioned perpendicular to the major axis. As previously mentioned, positioning the WLS at an angle to the major axis of the MJJ can reduce the required magnetic field needed to write the MJJ. As known to those skilled in the art, MJJs are typically formed in the shape of an ellipse having a major axis and a minor axis, the major axis of the ellipse being longer than and perpendicular to the minor axis.

[0132] Each MJJ-based storage circuit 1908 preferably includes at least one MJJ (MJJ_1 to MJJ_N) and at least one WLS (WLS1 to WLS_N). N ) and n-channel FET (NFET) devices (e.g., n-channel metal-oxide semiconductor field-effect transistors (MOSFETs)) (NFETs 19041 through 19044) each connected in series with a corresponding WLS to selectively connect the WLS to a current source 1906. N In one or more embodiments, the lamp source 1906 may provide positive and negative currents (i.e., bidirectional) I of predetermined magnitudes for successive write cycles to the memory cell. WLS and vice versa), thereby controlling the selected WLS and correspondingly selected FETs 19041, 19042. N , and drives easy-axis-based π-0-π state transitions through the wires into and out of the buses or other interconnects (e.g., In_Out_1, In_Out_2).

[0133] In one or more alternative embodiments, the current source 1906 may be configured to generate current in only one direction, and a control circuit such as an H-bridge may control the current I flowing through the WLS, as will be apparent to those skilled in the art. W In some embodiments, an H-bridge circuit may be incorporated into current source 1906, thereby forming a bidirectional current source. Additionally, transistors 19041 through 19044 may be used to selectively connect the WLS lines to interconnects In_Out_1 and / or In_Out_2. N 1904 , each of which connects a first one of the interconnects In_Out_1 to a corresponding WLS. N ) and a second subset of bottom transistors (e.g., 19041), each connecting a second one of the interconnects In_Out_2 to a corresponding WLS. In other embodiments, a given WLS may include both top and bottom transistors, only top transistors, or only bottom transistors. Dashed lines 19051 to 1905 are used to indicate a generalized current switch that may be implemented with (Bi)CMOS circuit elements, such as BJTs, or a combination of FETs and BJTs, and that may include the first and second subsets of transistors along with corresponding WLS lines in an MJJ-based storage circuit described with reference to FIG. 20. N 19. For clarity, only one MJJ write circuit is shown in FIG. 19, but it will be appreciated that embodiments of the present invention are not limited to only the particular configuration shown. When one of the transistors, such as transistor 19041, is in an activated state (i.e., turned on or enabled), transistors 19042 through 19044 are in an activated state (i.e., turned on or enabled). N The remaining N-1 transistors, etc., are preferably inactive (ie, turned off or disabled).

[0134] 20 is a schematic diagram illustrating an example MJJ-based storage circuit 2000 in accordance with one or more embodiments of the present invention. The MJJ-based storage circuit 2000 includes the MJJ-based storage circuit 100 (of FIG. 1), at least one integrated write switch FET 1904, and an MJJ domain orientation attribute (1910 of FIG. 19) associated with the MJJ 110, where the MJJ domain orientation attribute is configured to generate an easy axis field component that opposes the parallel domain orientation of the soft and hard layers of the MJJ 1910 to enable easy axis-based π-0-π state transitions for both even and odd write selections. WLS is used to guide the

[0135] 21 is a schematic diagram depicting at least a portion of an example write circuit 2100 for writing MJJs, including at least one MJJ domain orientation attribute for each MJJ, in accordance with one or more alternative embodiments of the present invention. As will be described in further detail below, the write circuit 2100 advantageously provides a π-phase setting seed current in either a clockwise or counterclockwise direction through the MJJ stack of material and into the superconducting loop of the memory circuit via an inductor associated with the memory cell (example details of the memory cell are clearly shown in FIG. 20, according to some embodiments). The write circuit 2100 can be used to "program" MJJs, which can function, for example, as memory elements that act as programmable switches in a Josephson magnetic programmable logic array (JMPLA), and which can function as memory elements for other programmable circuit functions in a superconducting FPGA, among other uses, as described, for example, in U.S. Pat. No. 9,595,970 to W. Reohr et al., the disclosure of which is incorporated herein by reference in its entirety.

[0136] Write circuit 2100 includes multiple storage circuits 2102 (e.g., 2000 in FIG. 20) arranged in multiple write columns A through Z, although embodiments of the present invention are not limited to any particular number of write columns. The storage circuits 2102 in each write column A through Z may be further divided into one or more write columns 1 through M, where M is an integer greater than or equal to 2, and each write column line includes multiple storage circuits 1 through N, where N is an integer greater than or equal to 2. Each storage circuit 2102 may be referred to according to the unique row and write column line with which it is associated. Thus, for example, storage circuit 2102 in write column A, row 1, write column line 1 may be referred to as storage circuit A. <1> <1> and the storage circuit in write column A, row N, write column line M may be designated as storage circuit A <n> <m>Similarly, the storage circuit 2102 in write column Z, row 1, write column line 1 may be designated as storage circuit Z <1> <1> and the storage circuit in write column Z, row N, and write column line M is storage circuit Z <n> <m>can be specified as:

[0137] The write circuit 2100 further includes a plurality of (Bi)CMOS switches, which in one or more embodiments include NFETs 2114 and 2116. A From 2114 Z , each NFET connected to a corresponding one of write columns A to Z. More specifically, NFET2114 A From 2114 Z Each of the write columns preferably includes a first source / drain connected to a first terminal of the write current source 2120 via a first interconnect In_Out1, a second source / drain connected to first ends of a plurality of column lines 1 to M associated with a corresponding one of the write columns, and a plurality of control signals 2116 provided thereto. A From 2116 Z and a gate configured to receive a control signal from a corresponding one of the write column lines A through Z. A second end of each write column line in a respective write column A through Z is connected through a series connected resistor 2118 or other resistive element (e.g., wire) to a second terminal of a write current source 2120 via a second interconnect In_Out2. In one or more embodiments, the write current source 2120 generates a bidirectional write current I for writing states into the plurality of storage circuits 2102. Column_Source The power supply may be configured to provide:

[0138] 21, write circuit 2100 is configured to write only one storage circuit 2102 at a time. By way of example only, and without loss of generality, storage circuit A is selected to illustrate the operation of write circuit 2100. <1> <1> A write operation for this is shown using a dashed box that surrounds this storage circuit. Also shown within the dashed box is the write line segment current I WLS and the write line segment magnetic field H generated by the write line segment current WLS is shown, the write line segment magnetic field H WLS passes through the write line segment WLS2 124 and acts on the MJJ2 122 of the "selected" memory cell (thereby generating a magnetic field having, specifically, an easy axis field component). <1> <1> NFET2114 is used to provide a positive or negative π phase setting current (Boolean state) for writing A A high voltage (e.g., VDD) control signal 2116 is applied to the gate of A By applying A is activated (i.e., turned on). <1> <1> The write line segment current I can only be applied to WLS However, preferably, it generates at least an easy axis magnetic field component that can select a memory cell for a write operation consistent with (i) the relative orientation of WLS2124 and MJJ2122 and (ii) FIG. 20 (including FET1904 disclosed herein for selectively writing the memory cell).

[0139] Each write column line 1 through M in each write column A through Z is preferably configured to carry a write current for writing a state into the storage circuit 2102, and in some embodiments may be arranged to pass through a transformer in each of at least a subset of the memory cells 2102. As previously described in connection with the example storage circuit 2000 shown in FIG. 20 , the transformer 106 of the example storage circuit 2000 can receive a positive or negative π phase setting current to induce a proportional secondary seed current for setting a clockwise or counterclockwise π state current in the superconducting loop of the storage circuit 2000. In the example write circuit 2100 of FIG. 21, at least a subset of the storage circuits 2102 may each comprise the example storage circuits 2000 of FIG. 20 connected in series along the write column line of the write circuit 2100 by connecting the second terminal “In_Out_2_π phase setting” of each of the storage circuits 2000 to the first terminal “In_Out_1_π phase setting” of each of the storage circuits 2000, except at the ends of the write column line, and the column of storage circuits 2102 is connected to a FET 2114 at a first end of the write column line WCL and to a resistor 2118 at a second end within the write column line WCL, thereby setting a clockwise or counterclockwise π state current in the superconducting loop of each storage circuit 2102, and in particular of a “selected” one of the storage circuits 2102.

[0140] It should be understood that this array-like embodiment, and other exemplary embodiments, do not require that a storage circuit 2102 be located at the intersection of each unique row and column pair. Furthermore, the terms "row" and "column" lines are used to imply at least intersecting lines, which may or may not be orthogonal at any location. It will also be recognized that the terms "row" and "column" are intended merely to convey relative position. For example, by rotating a circuit 90 degrees, a "row" can become a "column."

[0141] 21, each of at least a subset of storage circuits 2102 in storage circuit 2100 may, in one or more embodiments, control a write line segment current I carried by a corresponding write line segment WLS 2124 for the purposes of writing (and, in a preferred embodiment, more specifically, for the purposes of selecting a write) at least one corresponding MJJ 2122 (e.g., MJJ 2010 of FIG. 20). WLS Each storage circuit may further include at least one NFET switch 1904 for controlling the write line segment current I WLS 20 or 21, but is shown as current source 1906 in FIG. 19) is connected to a first terminal of the storage circuit Z <n> <m>Through WLS for 2102, memory circuit A <1> <1> 19 to a first end of a respective write line segment (e.g., WLS 2024) associated with 2102, e.g., via In_Out_1 in FIG. 19. A second current source (e.g., current source 1906 in FIG. 19), which may comprise a single current source or multiple current sources, preferably generates a current I WLS and / or the current I generated by the second current source WLS 19 for controlling the magnitude, sign, and duration of WLS Each of the NFET switches associated with the write line segments in each storage circuit 2102 has a first source / drain connected to the second end of a corresponding one of the write line segments, a second source / drain connected to a second terminal of the second current source (e.g., terminal In_Out_2 in FIG. 19 ), and a gate adapted to receive one or more control signals.

[0142] When the second (write line segment) current source (e.g., current source 1906 in FIG. 19, and therefore not shown) is enabled for a write operation (e.g., control signal Control_I WLS (by setting CLK to a "1" (i.e., active) state), write line segment WLS (storage circuit A <1> <1> WLS to Storage Circuit Z for 2102 <n> <m>A write line segment current I of a predetermined magnitude flows through a selected write line segment (WLS for 2102). WLS is enabled by activating a corresponding one of the write segment line circuits, for example, by turning on a corresponding NFET switch (1904 in FIG. 19) in storage circuit 2102.

[0143] (For example, the control signal Control_I Column_Source When the (global write column line) current source 2120 is enabled for a write operation by setting WLS ) (which provides WCL_T However, an enabled (Bi)CMOS switch / NFET circuit (e.g., NFET2114 as seen in Figure 21) A ) are split into substantially equal positive currents (or substantially equal negative currents) within each write column line associated with the first and second current sources 2120. In this regard, it is important to note that the magnitudes of the positive and negative currents may differ (because each storage circuit 2102 may be written using different currents supplied by the first and second current sources, preferably when written independently of the other storage circuits 2102), which is beneficial for reliable writing of the MJJs within the memory cells 2000 / 2102 in light of their actual non-ideal magnetic switching characteristics. When the first source 2120 is enabled, the current I Column<1> From I Column <m>< / m> However, (Bi)CMOS switch / NFET circuit 2114 A From 2114 Z Control signal 2116 A From 2116 Z The multiple associated column lines are adjusted by <1> From column line <m>, which allows the current to flow through the dashed box (i.e., the memory circuit <1> <1> 2102) is surrounded by a magnetic field (H WLS ) to manage the current to write.

[0144] Total column line current I WCL_T can be determined using the following formula: I WCL_T =WCLN×I Column Here, WCLN is the flowing positive (or negative) write column line current (I) associated with each write column (e.g., A to Z). Column ) and I Column represents the positive (or negative) π-phase setting current flowing in the write column line (denoted as "Column_line" in FIG. 21). The total row line current I WCL_T are substantially equal column currents I due to the presence of resistor 2118 (which functions to "divide" the current equally, as is known in the art of superconducting electronics). Column (i.e., I Column<1> From I Column <m>< / m> Furthermore, these column currents induce a π phase setting current through the transformer action (induction) in each storage circuit 2102.

[0145] 19, one MJJ associated with a corresponding storage circuit 2102 (e.g., storage circuit 2000) can be selected from the entire set of MJJs at a time for a write operation. In the write circuit 2100 shown in FIG. 21, each NFET 1904 of each storage circuit 2000 of FIG. 20 and each NFET 2114 of FIG. 21 A From 2114 Z The gate voltages of the gates of the MOS transistors can be controlled by a shift register. These gate voltages are then applied to the memory cells required for the write operation (I WLS via), and to deliver that state (I Column (via) to guide the current.

[0146] By driving its gate high while all other gates of the NFETs in storage circuit 2102 are held low, <1> <1> 19 and 20. <1> <1> is selected to be written, and the write circuit 1900 of FIG. 19 reads the entire array of storage circuits 2102 (here, storage circuits A <1> <1> From memory circuit Z <n> <m>) to the memory circuit 2102 (here, memory circuit A <1> <1> The write line segment current I WLS (H WLS (generating the column current I Column write selection memory circuit 2102 (for example, memory circuit A <1> <1> ) to (correctly) induce a clockwise or counterclockwise π-state current in the I Column However, other storage circuits 2102 (e.g., storage circuit A) <1> <1> From memory circuit A <n> <m>) flows through

[0147] Use of MJJs in analog circuits to support three-state (three-phase) MJJ superconducting loops Although method and circuit embodiments have been described herein in connection with exemplary memory cell topologies and methods (e.g., 100 of FIG. 1 and 200 of FIG. 2), these exemplary memory cell topologies and methods should be understood as examples and are not intended to impose limitations on the scope or spirit of the present disclosure.

[0148] Not only Boolean circuits, but analog circuits are also contemplated. These analog circuits may be advantageously configured to utilize the full set of three-phase circulating currents available in the superconducting loop comprising the MJJ. The three-phase currents may include: (i) a clockwise circulating current enabled by the π-state of the MJJ; (ii) the absence of circulating current (i.e., zero circulating current or zero current) as a characteristic of the zero-state of the MJJ; and (iii) a counterclockwise circulating current also enabled by the π-state of the MJJ. As depicted in FIG. 22A , the write circuitry may have domain tracking memory elements (e.g., MJJ domain orientation attribute and MJJ zero-state / zero circulating current attribute) that can be used to identify all domain orientations and thus monitor / drive the writing transitions between three-phase current levels within the superconducting loop.

[0149] FIG. 22A is a schematic diagram depicting at least a portion of an example MJJ-based storage circuit 2200 including at least one integrated write switch, as well as MJJ domain orientation and MJJ zero-state / zero circulating current attributes, in accordance with one or more embodiments of the present invention. The MJJ-based storage circuit 2200 is similar to the example MJJ-based storage circuit 2000 shown in FIG. 20, but modified only to support three-phase state operation. The three-phase state operation of the storage circuit 2200 can take advantage of the fact that an MJJ-based memory cell can contain at least one superconducting loop with an MJJ that supports three stable states of circulating current at any given time (i.e., counterclockwise circulating current driven by the MJJ in the π state, clockwise circulating current driven by the MJJ in the π state, and no circulating state when the MJJ is in the zero state), and that each of these circulating current states can be assigned a unique three-phase logic state that can be detected during a read operation of the storage circuit / memory cell.

[0150] Note that in all figures, the list of "MJJ write attributes" can include the write current direction, the write current magnitude, the duration of their application, and the write current ramp rate, as corresponding to the transition from a first circulating current and associated configuration to a second circulating current and associated configuration.

[0151] Specifically, the MJJ-based storage circuit 2200 is modified to have at least one additional write attribute. In particular, the storage circuit 2200 includes an MJJ domain orientation attribute that identifies the π-state configuration of the MJJ, similar to the storage circuit 2000 shown in FIG. 20, and further includes an MJJ zero-state (i.e., zero circulating current) attribute that identifies the MJJ in its zero state.

[0152] The read row line RRL supplies a first read row line current I to perform first and second binary read operations (described in more detail below), respectively. RRL_first and a second read row line current I opposite to the first read row line current. RRL_Second is used to apply

[0153] 22A also shows a circulating current loop comprising Josephson junctions 102 and 104, MJJ1910, and secondary inductor / coil L4 of transformer 108. During a read operation, the current circulating in this loop is a clockwise circulating current (- / +)I circ +(- / +)I T , counterclockwise circulating current (+ / -) I circ +(+ / -)I T , or zero circulating current (- / +) I T where I circ is the current circulating in the superconducting loop during standby, and I T is the current component coupled in through the transformer 108 during the read operation. CB is the non-circulating DC column bias current component. The three-phase state of the memory cell is related to the circulating current in the memory cell 2200 (i.e., clockwise circulating current, counterclockwise circulating current, or zero circulating current), and the circulating current in the memory cell 2200 can be detected by a read operation of the memory cell 2200.

[0154] Analog circuits utilizing three-phase persistent currents (e.g., clockwise current, counterclockwise current, and zero current) in the manner described above according to one or more embodiments of the present invention can be employed in any case where persistent energization is useful. While other methods of coupling (e.g., galvanic coupling) are also contemplated and within the scope of embodiments of the present invention, a common case may be coupling persistent currents stored in a superconducting loop including a MJJ and at least one inductor to another superconducting loop in a superconducting circuit through mutual inductance. By way of example only and not limitation, one such application is to provide a magnetic flux bias to a superconducting quantum interference device (SQIUD) loop for the purpose of energizing the loop with either positive magnetic flux, negative magnetic flux, or zero magnetic flux, corresponding to clockwise circulating current, counterclockwise circulating current, or zero circulating current (emphasis is three-phase). SQUIDs are often used as detectors, and the resulting flux differential between states can vary the operating threshold of the SQUID as desired. Analog control can make SQUIDs sensitive, insensitive, or partially sensitive to signals, as desired.

[0155] 22B is a schematic diagram depicting at least a portion of an exemplary MJJ-based memory circuit 2250 in accordance with one or more embodiments of the present invention, in which a three-phase persistent current stored in one superconducting loop is used to control a persistent current circulating in another superconducting loop. Referring to FIG. 22B, the MJJ-based memory circuit 2250 can include a first superconducting loop comprising at least one MJJ 2254 and at least one first inductor L1 coupled to the at least one MJJ 2254. The MJJ-based memory circuit 2250 can further include a second superconducting loop comprising at least one Josephson junction (or a superconducting circuit including at least one Josephson junction) 2252 and at least one second inductor L2 coupled to the at least one Josephson junction 2252. In one or more embodiments, the first inductor L1 and the second inductor L2 are included in and form components of a transformer 2256 configured to result in a mutual inductance between the first inductor and the second inductor.

[0156] A stored persistent current (e.g., clockwise current, counterclockwise current, and zero current) circulating in the first superconducting loop can be set by applying a magnetic field to MJJ2254 using a write row current carried by a write row line passing between terminals “In_Out_2_Magnetic Field” and “In_Out_1_Magnetic Field” of the storage circuit near MJJ2254. At least one of the clockwise, counterclockwise, or zero current circulating in the first superconducting loop can be configured to control the current in the second superconducting loop comprising second inductor L2 and Josephson junction 2252. The use of three current states (i.e., three phases): clockwise current, counterclockwise current, and zero current represents a significant advantage over conventional binary current states in which there are only two distinguishable currents.

[0157] FIG. 23 is a multi-element diagram that can be used to conceptually explain an example three-phase write operation within a corresponding storage circuit (e.g., the example storage circuits 2200, 2250 shown in FIGS. 22A and 22B, respectively) in accordance with one or more embodiments of the present invention. Referring to FIG. 23, three different configuration transitions of an MJJ are shown that support writing three-phase state memory persistent current within a superconducting loop for use in analog or digital circuits. The configuration transitions of the MJJ include: (i) a π-0-π configuration transition 2302 to establish a clockwise or counterclockwise π-state current within the superconducting loop; (ii) a π-0 configuration transition 2304 from a clockwise or counterclockwise π state to establish a zero-state current (i.e., no circulating current) within the superconducting loop; and (iii) a 0-π configuration transition 2306 to establish a clockwise or counterclockwise π-state current within the superconducting loop from the zero state. The π-0-π configuration transition 2302 has already been described in sufficient detail with reference to the example write method 200 of FIG. 2 and therefore will not be described further herein.

[0158] FIG. 23, like FIG. 2, illustrates an example time progression of the layers and their orientations of an example spin valve MJJ, with the soft (easy) layer progressing from 204 to 212 and the hard (pinned) layer progressing from 206 to 214, as well as the applied magnetic field (H) direction 210, which may increase in strength (i.e., magnitude) with time. In FIG. 23, time progresses from left to right. In the example write process shown in FIG. 23, it should be understood that each diagram of the two / multilayer MJJ follows the following convention: the top layer (e.g., 204) is the soft (easy) layer and the bottom layer (e.g., 206) is the hard (pinned) layer, with a separation layer 208 between them.

[0159] Below each magnetic field layer configuration is shown its corresponding associated minimum energy state of the inductive loop containing the MJJ. In the left diagram showing the initial MJJ orientation 202, both layers 204, 206 have magnetic orientations pointing to the left, and a magnetic field 210 begins to be applied that is opposite to the initial MJJ orientation 202. In the steady state, the inductive loop can have two potential wells 220, only one of which can be occupied by a circulating current. When the top layer switches, a critical current I C decreases, resulting in a less localized minimum 222 indicated by a single black dot. In the center diagram, the soft layer 212 has a magnetic orientation pointing to the right, while the pinned layer 206 does not change its magnetic orientation, indicating that the magnitude of the applied magnetic field 210 is sufficient to switch the soft layer 212 but not the hard layer 206. As shown between the left and center diagrams, the energy levels 220, 222, and 224 of the inductive loop flatten out. When the MJJ is in its zero state (energy diagram 224), there is no circulating current and only one minimum exists.

[0160] A π-0 configuration transition 2304 to establish a zero-state current (i.e., no circulating current) in the superconducting loop can be implemented using the following example method. Referring to FIG. 23 , where the MJJ is initially in a clockwise or counterclockwise π state, writing the MJJ can be achieved by: (1) applying a right-handed (easy axis) magnetic field 210 when the junction is initially in a left-left (LL) π state (as shown in FIG. 23 ), or applying a left-handed (easy axis) magnetic field when the junction is in a right-right (RR) π state; and (2) increasing the magnetic field, resulting in the easy and hard layers switching to a right-left (RL) or left-right (LR) configuration (i.e., an antiparallel configuration) corresponding to a second three-phase state, the zero state. In FIG. 23 , only the soft layer switches from the 204 orientation to the 212 orientation.

[0161] Next, we describe a 0-π configuration transition 2306 for establishing a clockwise or counterclockwise π-state current in the superconducting loop. As with the π-0-π configuration transition 2302 (previously described in connection with FIG. 2), an applied easy axis field 210, in combination with an applied seed current (driven through the transformer 106 and present in the transformer 106 and the loop-containing inductor L2 of the MJJ 1910 (an element of the memory cell 2200 of FIG. 22A )), can generate a 0-π configuration transition 2306 corresponding to two of the three phase states of the MJJ. Specifically, assuming that the MJJ is initially in a null state where the soft and hard layers may be antiparallel (i.e., the soft layer 212 is oriented to the right and the hard layer 206 is oriented to the left, or vice versa, as shown in FIG. 23), the MJJ can be configured to have clockwise or counterclockwise circulating currents within its superconducting loops by: (1) changing the orientation of the hard layers to right-to-right (RR) when the junction (MJJ) is initially in a right-to-left (RL) null state (as shown in FIG. 23) while coupling in a clockwise or counterclockwise (positive or negative) seed current. (1) applying an increased magnetic field oriented in the right direction to switch the hard layer orientation to the π-state or, when the junction is in the left-right (LR) zero state, applying an increased magnetic field oriented in the left direction to switch the hard layer orientation to the left-left (LL) configuration; (2) removing the magnetic field while leaving the junction in the π-state; and (3) trapping a circulating current in parallel with step (2), corresponding to a three-phase state (either clockwise or counterclockwise), as set by a “seed” current applied by transformer 106 of FIG. 22A (which effectively forms the write bit line) to the superconducting loop containing the MJJ.

[0162] Furthermore, for a 0-π configuration transition to establish a clockwise or counterclockwise π-state current in the superconducting loop, it is also contemplated that the MJJ can initially be in the zero state, such that the soft and hard layers can be parallel to one another (i.e., the soft layer 212 and hard layer 206 are oriented to the right, or the soft layer 212 and hard layer 206 are oriented to the left, as shown in FIG. 8 ). In this scenario, the methodology for generating a 0-π configuration transition would be similar to that already described above, but derived from FIG. 8 rather than FIG. 2 . Specifically, when the MJJ is in the zero state, no circulating current energy state can exist in the absence of an externally applied field. The applied magnetic field is reversed in a direction opposite to the magnetic orientations of the soft and hard layers, causing the soft layer to switch direction (e.g., from 814 to 804, as shown in FIG. 8 ) and become antiparallel to the hard layer, thereby establishing the MJJ in the π state.

[0163] It will be appreciated that the three-phase write operation is limited. In one or more embodiments, due to the fact that the IWLS writes a zero state into any superconducting loop containing an associated (i.e., magnetically coupled) MJJ, only one memory cell at a time can be independently written to the three-phase state. If two or more memory cells are selected at once for a write operation and one of the memory cells is written to the zero state (i.e., with no circulating current), all of the other memory cells will also be written to the zero state. In other words, easy-axis field-driven zero-state writing allows only one MJJ at a time, thereby utilizing the fundamental writing selectively enabled by NFET 1904 of FIG. 19 . If the WLS is common to the cells in a row, all of the memory cells in the row will be written to the zero-state current.

[0164] Three-phase read operation example At the heart of an exemplary three-phase read operation of a storage circuit, according to one or more embodiments, are two binary read operations, which are described with reference to the exemplary storage circuit 2200 of FIG. 22A. The first binary read operation reads the circulating current I circ is either (i) a current in a clockwise direction or (ii) a current in either a zero current (i.e., no circulating current) or a current in a counterclockwise direction. The second binary read operation is configured to determine whether the circulating current I circ is a clockwise current, or either zero current or a counterclockwise current. As is known in the art, during a binary read operation, the measurement (i.e., determination) is made by detecting or not detecting a transition of a Josephson junction (e.g., either JJ102 or JJ104 in FIG. 22A) to one voltage state when (or if) its critical current is exceeded.

[0165] To perform the first and second binary read operations, an external read circuit, such as the example read or write enable circuit 1670 of FIG. 16C (particularly for achieving energy efficiency, as previously described in connection with write operations) is required. Referring to FIG. 22A, the write row line 1672 shown in FIG. 16C may be configured as a read row line RRL within the storage circuit 2200, and a first read row line current I RRL_First and the second read row line current I RRL_Second can be used to apply

[0166] A counterclockwise circulating current (I) in a memory cell (e.g., included in storage circuit 2200 of FIG. 22A) during a first binary read operation via forcing a Josephson junction (e.g., JJ102) to its voltage state (which may be arbitrarily associated with a logic “1” state) circ ) detection, a positive current through JJ102 is calculated as the critical current I of JJ102 according to the following equation: C It will be designed to exceed: (JJ102)I C <|I circ |+|I T |+|I CB / 2| Here, I circ is the circulating current in the superconducting loop, and I CB is the DC column bias current component, and I T is the first read row line current I RRL_First , where the magnitude symbol "|" denotes the sign / direction of the constituent currents in the storage circuit 2200, along with the reference to a positive current through the JJ 102.

[0167] In the first binary read operation, if it is determined that the JJ 102 is not driven to one voltage state, then there is either no current in the memory cell (zero state) or there is clockwise current in the memory cell (due to the JJ being in the π state).

[0168] A clockwise circulating current (I) in the memory cell during a second binary read operation via forcing the Josephson junction (e.g., JJ104) to its voltage state (which may be associated with a logic "1" state) circ ) detection, a positive current through JJ104 is calculated as the critical current I of JJ104 according to the following equation: C It will be designed to exceed: (JJ104)I C <|I circ |+|I T |+|I CB / 2| Here, to match the illustrative case for detecting counterclockwise circulating currents described above, I circ is the circulating current in the superconducting loop, and I CB is the DC column bias current component, and I T is the second read row line current I RRL_Second , where the magnitude symbol "|" denotes the sign / direction of the constituent currents in the storage circuit 2200, along with the reference to a positive current through the JJ 104.

[0169] In the second binary read operation, if it is determined that the JJ 104 is not driven to one voltage state, then there is either no current in the memory cell (zero state) or there is a counterclockwise current in the memory cell (π state).

[0170] After both read operations, simple Boolean logic can be utilized to determine the three-phase state of the memory cell from the binary read operations as corresponding to counterclockwise current, clockwise current, and zero current, in accordance with one or more embodiments of the inventive concepts.

[0171] Given the prior art, only illustrative embodiments of the inventive concepts have been described herein that demonstrate certain novel aspects of the circuits and / or methods. With the superconducting and hybrid superconducting and (Bi)CMOS circuit embodiments described in this disclosure, the fundamental novelty of these embodiments, which represent a departure from conventional approaches, can be related to the reversal of current direction / polarity to facilitate an easy-axis-based π-0-π state transition during a cycle or every other cycle, as exhibited in the exemplary circuits and methods. Thus, specifically, we have introduced a tracking mechanism for reversing current direction / polarity used to induce a π-0-π state transition by generating at least an easy-axis field component for at least one MJJ. As will be apparent to those skilled in the art having the benefit of the teachings herein, write circuits, such as circuits having an external current source directing current to the MJJ memory cell, can be devised. These circuits may require additional memory allocated to tracking the current direction / polarity reversals necessary to implement the write method according to embodiments of the present invention for any type of memory array (e.g., RAM, CAM, PLA, ROM, and FPGA).

[0172] In this disclosure, the term "exemplary" is used herein to mean serving as an example, instance, or illustration. Any example or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other examples or implementations.

[0173] Terms such as "at least one" and "one or more" may be used interchangeably or in combination throughout this description. The term "and / or" as used herein is intended to include any and all combinations of one or more of the associated listed items.

[0174] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context specifically indicates otherwise. Furthermore, it will be understood that the terms "comprise" and / or "comprising," as used herein, specify the presence of a referenced feature, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. Spatial descriptors such as "above," "below," "up," "below," "upper," and "lower" may be used herein to denote the location of elements, structures, or features relative to one another as illustrated in the figures, rather than absolute locations. Accordingly, a semiconductor device or semiconductor die according to embodiments of the present invention may be otherwise oriented (e.g., rotated 90 degrees or otherwise oriented), and the spatially relative descriptions used herein may be interpreted accordingly.

[0175] Furthermore, when an element, such as a layer, region, or substrate, is referred to as being "on top of," "above," "in contact with," or "on" another element, it is understood that this is broadly intended to mean that the element is in direct contact with the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly on" another element, it is intended that no intervening elements are present. Similarly, when an element is referred to as being "connected" or "coupled" to another element, it will be recognized that the element may be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0176] Although order terms such as "first," "second," etc. may be used herein to describe various elements, it will be understood that these elements are not limited by such terms. These terms are merely used to distinguish one element from another and should not be construed as conveying any particular order of elements relative to one another. For example, a first element could also be referred to as a second element, and similarly, a second element could also be referred to as a first element, without departing from the scope of the present disclosure. As may be used herein, the term "and / or" when used in conjunction with a list of associated elements is intended to include any and all combinations of one or more of the associated listed elements. For example, the phrase "A, B, and / or C" is intended to include element A only, element B only, element C only, or all combinations and permutations of elements A, B, and C.

[0177] The terminology used herein is for the purpose of describing particular embodiments of the inventive concepts only and is not intended to limit the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Furthermore, it will be understood that the terms "comprise," "comprising," "include," and / or "including," as used herein, are intended to specify the presence of referenced features, integers, steps, operations, elements, and / or components, but do not necessarily exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0178] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Furthermore, it will be understood that terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and in the related art, and should not be interpreted in an idealized or overly formal sense unless specifically defined herein.

[0179] While the concepts of the present invention have been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.< / m> < / n> < / m> < / n> < / m> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / n> < / n>

Claims

1. 1. A write circuit for writing a state into at least one memory cell in a magnetic Josephson junction (MJJ) based storage circuit, comprising: a first current source configured to generate a first current for applying an easy axis magnetic field component to a MJJ in at least one selected memory cell among a plurality of memory cells in the storage circuit during a write operation; a second current source configured to generate a second current in the at least one selected memory cell to induce a third current passing through the MJJ in the at least one selected memory cell during the write operation, the third current being a seed current for setting a π-state current of the MJJ in at least one superconducting loop of the at least one selected memory cell for a subsequent read operation; a write circuit, wherein at least the first current source is configured such that during the write operation, the MJJ in the at least one selected memory cell transitions (i) from a pi (π) state, in which a clockwise or counterclockwise current circulates in a superconducting loop in the at least one memory cell, to a zero state, in which no current circulates in the superconducting loop, and back to the π state, or (ii) from the zero state to the π state, or (iii) from the π state to the zero state.

2. 2. The write circuit of claim 1, further comprising a control circuit coupled to at least the first current source, the control circuit configured to control a direction of the first current to control a direction of the easy axis magnetic field component applied to the MJJ in the at least one selected memory cell.

3. 3. The write circuit of claim 2, wherein the control circuit comprises one or more flip-flop circuits, each of which is associated with at least one memory cell of the plurality of memory cells in the storage circuit and configured to receive at least a portion of a decoded write address provided to the flip-flop circuit, and to generate an output control signal provided to the control circuit, the output control signal being configured to result in a change in direction of the easy axis magnetic field component being triggered after completion of a write cycle or during a write cycle.

4. Each of at least a subset of the flip-flop circuits: a first delay element configured to receive the portion of the decoded write address provided to the first delay element and to generate a first output signal that is an inverted and delayed version of the portion of the decoded write address; a second delay element configured to receive the first output signal and to generate a second output signal that is a delayed version of the first output signal; a NOR gate configured to receive the first output signal at a first input, to receive the second output signal at a second input, and to generate a third output signal; a flip-flop configured to receive the third output signal and to generate the output control signal; The write circuit of claim 3 , comprising:

5. 4. The write circuit of claim 3, wherein each of at least a subset of the flip-flop circuits comprises at least one of a CMOS circuit and a superconducting circuit.

6. The write circuit of claim 2 , wherein the control circuit is configured to alternate the direction of the first current in alternating write cycles.

7. The write circuit of claim 2 , wherein the control circuit is configured to alternate the direction of the first current in the same write operation.

8. The write circuit of claim 2 , wherein the control circuit is configured to alternate the direction of the first current in every other write operation.

9. The control circuit to receive at least one of: (i) a first attribute indicative of a domain orientation of the MJJ in the at least one memory cell when the MJJ is in the π state; and (ii) a second attribute indicative of the absence of a circulating current when the MJJ is in the zero state; controlling the direction of the easy axis magnetic field component applied to the MJJ in the at least one selected memory cell as a function of at least one of the first and second attributes; 3. The write circuit of claim 2, configured to:

10. 3. The write circuit of claim 2, wherein the control circuit is configured to control the second current source to control the third current, which is a seed current for setting the π-state current, during the transition of the MJJ from at least one of (i) the zero state to the π-state and (ii) from the π-state via the 0 state to the π-state.

11. During the write operation, the control circuitry: controlling the first current source to apply the first current in a first direction to apply the easy axis magnetic field component to the MJJ in the selected memory cell, the MJJ comprising a soft layer and a hard layer arranged in a stacked structure, the MJJ configured to be in the π state before the write operation, and magnetic domain orientations of the soft layer and the hard layer being parallel to each other; increasing the magnitude of the applied first current in the first direction resulting in the MJJ transitioning to the zero state, wherein the magnetic domain orientation of the soft layer switches direction from its orientation in the π state prior to the write operation of the MJJ; controlling the second current source to couple a clockwise or counterclockwise seed current into the superconducting loop containing the MJJ while concurrently increasing the magnitude of the applied first current in the first direction, such that the MJJ transitions back to the π state and the magnetic domain orientation of the hard layer switches direction from its original orientation before the write operation; controlling the first and second current sources to remove the easy axis magnetic field component applied to the MJJ in the selected memory cell and to remove the seed current coupled into the superconducting loop, respectively, so that the MJJ remains configured in the π state, the magnetic domain orientations of the soft and hard layers are aligned with each other, and a circulating current is trapped within the superconducting loop comprising the MJJ, the direction of the circulating current being a function of the direction of the seed current coupled into the superconducting loop; The write circuit of claim 2 configured to:

12. A write circuit as described in claim 2, wherein the MJJ has hard and soft layers in a stack structure, and during the write operation, the control circuit is configured to control the first current source so that, as a result, the magnetic domain orientations of the soft and hard layers of the MJJ in the π state after the write operation are opposite to the magnetic domain orientations of the soft and hard layers of the MJJ in the π state before the write operation.

13. during the write operation, the control circuitry is further configured to control the first and second current sources so as to result in the magnetic domain orientations of the soft and hard layers of the MJJ in the π state before the write operation being opposite to the first direction of the applied easy axis magnetic field component; The control circuit switching a direction of the applied easy axis magnetic field component generated by the first current source to a second direction opposite to the first direction after the MJJ transitions to the null state; increasing the magnitude of the applied easy axis magnetic field component in the second direction while coupling the clockwise or counterclockwise seed current in parallel into the superconducting loop until the MJJ transitions back to the π state, where the magnetic domain orientations of each of the soft and hard layers are in the same direction as their respective magnetic domain orientations before the write operation; The write circuit of claim 11 further configured to:

14. 10. The write circuit of claim 1, further comprising at least one non-superconducting decoder circuit configured to receive at least a portion of the encoded non-superconducting write address signal and to generate a decoded address signal.

15. 15. The write circuit of claim 14, further comprising a conversion circuit configured to receive at least a portion of an encoded superconducting write address signal and to generate the encoded non-superconducting write address that is provided to the non-superconducting decoder circuit.

16. Further comprising a control circuit, 2. The write circuit of claim 1, wherein the control circuit is configured to control the first and second current sources to apply the easy axis magnetic field component and the seed current, respectively, to the MJJ in the selected memory cell, such that a domain orientation of the MJJ in the π state before the write operation is the same as a domain orientation of the MJJ in the π state after completion of the write operation.

17. Further comprising a control circuit, 2. The write circuit of claim 1, wherein the control circuit is configured to control the first and second current sources to apply the easy axis magnetic field component and the seed current, respectively, to the MJJ in the selected memory cell, such that a domain orientation of the MJJ in the π state before the write operation is different from a domain orientation of the MJJ in the π state after completion of the write operation.

18. The write circuit of claim 1 , wherein all components within the write circuit are superconducting elements.

19. The write circuit of claim 1 , wherein components in the write circuit are a hybrid combination of superconducting and non-superconducting elements.

20. 1. A method for writing a state into at least one selected magnetic Josephson junction (MJJ) in a memory cell of an MJJ-based storage circuit, comprising: applying an easy axis magnetic field oriented in a first direction to the selected MJJ, the selected MJJ comprising soft and hard layers arranged in a stacked structure, the selected MJJ being configured to be in a π state in which a clockwise or counterclockwise current circulates in a superconducting loop containing the selected MJJ, and the magnetic domain orientations of the soft and hard layers are parallel to each other; increasing the magnitude of the applied easy axis magnetic field in the first direction to result in the selected MJJ transitioning to a null state where no current circulates in the superconducting loop, and the magnetic domain orientations of the soft and hard layers are antiparallel to each other; further increasing the magnitude of the applied easy axis magnetic field in the first direction while coupling a clockwise or counterclockwise seed current in parallel into the superconducting loop containing the selected MJJ, so that the selected MJJ transitions back to the π state and the magnetic domain orientations of the soft and hard layers are parallel to each other; removing the applied easy axis magnetic field so that the selected MJJ remains configured in the π state, with the magnetic domain orientations of the soft and hard layers aligned with each other; Including, A method wherein a circulating current is trapped within the superconducting loop containing the selected MJJ, the direction of the circulating current being a function of the direction of the seed current coupled into the superconducting loop.

21. The method described in claim 20, wherein the magnetic domain orientation of each of the soft layer and the hard layer of the selected MJJ in the π state after the write operation is configured to be opposite to the magnetic domain orientation of each of the soft layer and the hard layer of the selected MJJ in the π state before the write operation.

22. The method described in claim 20, wherein the magnetic domain orientation of each of the soft layer and the hard layer of the selected MJJ in the π state after the write operation is configured to be the same as the magnetic domain orientation of each of the soft layer and the hard layer of the selected MJJ in the π state before the write operation.

23. The method according to claim 22, wherein the magnetic domain orientation of each of the soft and hard layers of the selected magneto-judge in the π state before a write operation is opposite to the first direction of the applied easy axis magnetic field, and the method further comprises: after the selected MJJ transitions to the null state, switching the direction of the applied easy axis magnetic field to a second direction opposite to the first direction; increasing the magnitude of the applied easy axis magnetic field in the second direction while coupling the clockwise or counterclockwise seed current in parallel into the superconducting loop containing the selected MJJ until the selected MJJ transitions back to the π state, wherein the magnetic domain orientations of each of the soft and hard layers are in the same direction as their respective magnetic domain orientations before the write operation; 21. The method of claim 20, further comprising:

24. The method according to claim 24, wherein the magnetic domain orientations of the soft and hard layers of the selected magneto-judge in the π state before a write operation are antiparallel to each other, increasing the magnitude of the applied easy axis magnetic field in the first direction until the selected MJJ transitions to a null state, the magnetic domain orientation of the soft layer switching direction such that the magnetic domain orientations of the soft and hard layers of the selected MJJ are parallel to each other; after the selected MJJ transitions to the null state, switching the direction of the applied easy axis magnetic field to a second direction opposite to the first direction; increasing the magnitude of the applied easy axis magnetic field in the second direction while coupling the clockwise or counterclockwise seed current in parallel into the superconducting loop containing the selected MJJ until the selected MJJ transitions back to the π state, wherein the magnetic domain orientations of each of the soft and hard layers are in the same direction as their respective initial magnetic domain orientations before the write operation; 21. The method of claim 20, further comprising:

25. 1. A method for writing a state into at least one selected magnetic Josephson junction (MJJ) in a memory cell of an MJJ-based storage circuit, comprising: applying an easy axis magnetic field oriented in a first direction to the selected MJJ, the selected MJJ comprising soft and hard layers arranged in a stacked structure, and configured to be in one of a π state, in which a clockwise or counterclockwise current circulates in a superconducting loop in the memory cell containing the selected MJJ, and a zero state, in which no current circulates in the superconducting loop; When the selected MJJ is in the π state, increasing the magnitude of the applied easy axis magnetic field in the first direction, resulting in the selected MJJ transitioning from the π state to a zero state, and removing the applied easy axis magnetic field, resulting in the selected MJJ remaining configured in the zero state; If the selected MJJ is in the zero state, increasing the magnitude of the applied easy axis magnetic field in the first direction while concurrently coupling a clockwise or counterclockwise seed current into the superconducting loop until the selected MJJ transitions to the π state, thereby removing the applied easy axis magnetic field so that the selected MJJ remains configured in the π state; When the selected MJJ is in the π state, increasing the magnitude of the applied easy axis magnetic field in the first direction, resulting in the selected MJJ transitioning from the π state to a zero state, and with the selected MJJ in the zero state, further increasing the magnitude of the applied easy axis magnetic field in the first direction while coupling a clockwise or counterclockwise seed current into the superconducting loop in parallel until the selected MJJ transitions back to the π state, thereby removing the applied easy axis magnetic field, resulting in the selected MJJ remaining configured in the π state; and at least one of the steps of When the selected MJJ is in the π state, a circulating current is trapped in the superconducting loop containing the selected MJJ, the direction of the circulating current being a function of the direction of the seed current.

26. 1. A magnetic Josephson junction (MJJ) circuit with three-phase circulating current for controlling a circuit function of an analog circuit and / or a digital circuit, comprising: at least one MJJ, and at least a first inductor; a first superconducting loop comprising: at least one Josephson junction; and at least a second inductor; a second superconducting loop comprising: Equipped with 1. A magnetic Josephson junction (MJJ) circuit configured such that at least one of a clockwise current, a counterclockwise current, and zero current in the first superconducting loop controls a circulating current in the second superconducting loop.

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