Semiconductor equipment

Abstract

To suppress hot carrier deterioration without reducing an operation speed, in a semiconductor device that generates an output voltage having a voltage amplitude higher than a withstanding voltage of a transistor.SOLUTION: A P-type transistor MP0 and a P-type transistor MP2 are connected in series between a power supply terminal 11 and an output terminal 13. An N-type transistor MN0 and an N-type transistor MN2 are connected between a ground terminal 12 and a power supply terminal 13. The N-type transistor MN2 and the P-type transistor MP2 are on / off-controlled in a complementary manner in response to an input signal VIN. A gate voltage control circuit 110 changes at least one of gate voltages of the P-type transistor MP0 and the N-type transistor MN0 whose drains are electrically connected with the output terminal 13 so as to follow an output voltage VOUT at the output terminal 13 while maintaining an ON state of the P-type transistor MP0 or the N-type transistor MN0.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device for outputting a signal having a voltage amplitude higher than the breakdown voltage of a transistor.

Background Art

[0002] In a semiconductor device including a level shift circuit, an example is known in which a circuit that outputs a high-amplitude logic signal using an input low-amplitude logic signal is configured using a transistor having a breakdown voltage corresponding to the low amplitude. For example, a semiconductor device that generates an output signal set to 0 [V] (GND) or 3.3 [V] in response to an input signal set to 0 [V] (GND) or 1.8 [V] is configured by a transistor with a breakdown voltage of 1.8 [V].

[0003] In Japanese Unexamined Patent Application Publication No. 2017-175288 (Patent Document 1), in the output stage, a circuit configuration is shown in which two low-breakdown-voltage transistors are connected in series between a high-voltage power supply terminal and an output terminal where an output signal is generated, and between the output terminal and a ground terminal to ensure the breakdown voltage. Further, in Patent Document 1, a voltage at the time of turning on is supplied to the gate of the low-breakdown-voltage transistor constituting the output stage via a potential conversion circuit. Thereby, the gate-source voltage applied when the low-breakdown-voltage transistor is turned on is kept low.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the semiconductor device described in Patent Document 1, hot carrier degradation can be suppressed by suppressing the transient drain-source voltage during the turn-on of a low-voltage transistor.

[0006] However, in the technology described in Patent Document 1, the operating speed of the transistor during turn-on decreases by keeping the gate-source voltage low. In other words, it is understood that there is a trade-off between suppressing hot carrier degradation and improving operating speed.

[0007] Therefore, when the technology described in Patent Document 1 is applied to semiconductor devices manufactured using advanced processes that result in significant hot carrier degradation, adjusting the gate voltage to suppress hot carrier degradation leads to a significant decrease in the transistor's operating speed, raising concerns that this may cause problems in applications to circuits requiring high-speed response.

[0008] This disclosure aims to solve the above problems and provides a semiconductor memory device that can suppress hot carrier degradation without reducing the operating speed when generating an output voltage with a voltage amplitude higher than the breakdown voltage of the transistor.

[0009] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0010] A semiconductor device according to one embodiment generates an output signal with a voltage amplitude greater than that of an input signal, and comprises a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, and a gate voltage control circuit. The first P-type transistor and the second P-type transistor are connected in series between a power line supplying a first power supply potential and an output terminal where the output signal is generated. The first N-type transistor and the second N-type transistor are connected in series between a reference potential line supplying a reference potential and an output terminal. The first N-type transistor and the first P-type transistor have drains electrically connected to the output terminal. Signals are input to the gates of the second N-type transistor and the second P-type transistor, respectively, to switch them on and off complementaryly according to the input signal. The gate voltage control circuit changes the gate voltages of the first P-type transistor and the first N-type transistor according to the voltage at the output terminal. The gate voltage control circuit is configured to maintain the ON state of either the first P-type transistor or the first N-type transistor when the output signal voltage changes in response to a change in the logic level of the input signal, and to change at least one of the gate voltages of the first N-type transistor and the first P-type transistor in accordance with the change in the output terminal voltage. [Effects of the Invention]

[0011] According to the above embodiment, in a semiconductor device that generates an output voltage with a voltage amplitude higher than the breakdown voltage of the transistor, hot carrier degradation can be suppressed without reducing the operating speed. [Brief explanation of the drawing]

[0012] [Figure 1] This is a circuit diagram illustrating the configuration of the semiconductor device relating to the first comparative example. [Figure 2] Figure 1 shows the transient waveform diagram of the semiconductor device. [Figure 3] Figure 1 shows a transient waveform diagram of a modified example of the semiconductor device. [Figure 4]It is a circuit diagram for explaining the configuration of a semiconductor device according to a second comparative example. [Figure 5] It is a circuit diagram for explaining the configuration of a semiconductor device according to Embodiment 1. [Figure 6] It is a circuit diagram for explaining a configuration example of an intermediate potential generation circuit. [Figure 7] It is a transient operation waveform diagram of a semiconductor device according to Embodiment 1. [Figure 8] It is a circuit diagram for explaining the configuration of a semiconductor device according to Embodiment 2. [Figure 9] ​​​​​​​​​​​​​​​​​​​​​​​​​On the one hand, the output signal is set to the ground potential GND at the L level, and is set to the high power supply potential VCCQH higher than the low power supply potential VCCQ at the H level. That is, the amplitude of the output signal is larger than the amplitude of the input signal VIN. As an example, the low power supply potential VCCQ is 1.8 [V], and the high power supply potential VCCQH is 3.3 [V].

[0017] In addition, hereinafter, the voltage value of the output terminal 13 is referred to as the output voltage VOUT. Therefore, when the output signal is at the H level, VOUT = VCCQH (3.3 [V]), and when the output signal is at the L level, VOUT = GND (0 [V]). Also, when the output signal changes from the H level to the L level or from the L level to the H level, the output voltage VOUT transiently changes between the ground potential GND (0 [V]) and the high power supply potential VCCQH (3.3 [V]).

[0018] The semiconductor device 100A is configured in the same manner as in Patent Document 1, and includes an inverter 15, a level shift circuit 20, potential conversion circuits 21 and 22, and P-type transistors MP1 and MP2 and N-type transistors MN1 and MN2 that constitute an output stage. The transistors MP1, MP2, MN1, and MN2 have a breakdown voltage equivalent to the low power supply potential VCCQ (here, 1.8 [V]). That is, the breakdown voltage of the transistors MP1, MP2, MN1, and MN2 is lower than the potential difference between the high power supply potential VCCQH and the ground potential GND.

[0019] The inverter 15 operates by receiving the low power supply potential VCCQ and outputs an inverter output signal VINV obtained by inverting the input signal VIN. When the input signal VIN is at the logical low level (hereinafter, "L level"), VINV = VCCQ, and when the input signal VIN is at the logical high level (hereinafter, "H level"), VINV = GND.

[0020] The level shift circuit 20 outputs a level shift signal VLFP obtained by inverting the input signal VIN. The level shift circuit 20 sets VLFP = VCCQH when the input signal VIN is at the L level, while setting VLFP = (1 / 2)·VCCQH when the input signal VIN is at the H level.

[0021] The potential conversion circuit 21 outputs a gate voltage signal VNG2, obtained by converting the potential of the inverter output signal VINV from the inverter 15, to the gate of transistor MN2. The potential conversion circuit 21 has an N-type transistor MN5 that functions as an NMOS transfer gate when the low power supply potential VCCQ is input to its gate. While the amplitude of the inverter output signal VINV is GND to VCCQ, the amplitude of the gate voltage signal VNG2 output from the potential conversion circuit 21 is GVD to VCCQ - Vtn. Here, Vtn is the threshold voltage of transistor MN5.

[0022] Similarly, the potential conversion circuit 22 outputs a gate voltage signal VPG2, obtained by converting the potential of the level shift signal VLFP from the level shift circuit 20, to the gate of transistor MP2. The potential conversion circuit 22 has a P-type transistor MP5 that functions as a PMOS transfer gate when the low power supply potential VCCQ is input to its gate. While the transient amplitude of the level shift signal VLFP is (1 / 2)·VCCQH~VCCQH, the amplitude of the gate voltage signal VPG2 output from the potential conversion circuit 22 is (1 / 2)·VCCQH+Vtp~VCCQH. Here, Vtp is the threshold voltage of transistor MP5.

[0023] In the output stage, P-type transistors MP1 and MP2 are connected in series via node NP1 between output node No, which is connected to output terminal 13, and power line PL, which is connected to power terminal 11. That is, the source of transistor MP2 is connected to power line PL, and its drain is connected to node NP1. The source of transistor MP1 is connected to node NP1, and its drain is connected to output node No.

[0024] Similarly, the N-type transistors MN1 and MN2 are connected in series via node NN1 between output node No and the ground line GL connected to ground terminal 12. That is, the source of transistor MN2 is connected to the ground line GL and its drain is connected to node NN1. The source of transistor MN1 is connected to node NN1 and its drain is connected to output node No.

[0025] A bias voltage VREFP is input to the gate of transistor MP1, and a bias voltage VREFN is input to the gate of transistor MN1. The bias voltages VREFP and VREFN are set to an intermediate potential between the ground potential GND and the high power potential VCCQH, which allows transistors MP1 and MN1 to be turned on. For example, VREFN = VCCQ and VREFP = (1 / 2)·VCCQH.

[0026] The gate of transistor MP2 receives the gate voltage signal VPG2 from the potential conversion circuit 21. The gate of transistor MN2 receives the gate voltage signal VNG2 from the potential conversion circuit 22.

[0027] When the input signal VIN is at a low level (GND), inverter 15 outputs a high level (VINV=VCCVQ), and level shift circuit 20 also outputs a high level (VLFP=VCCQH). As a result, VPG2=VCCQH is input to the gate of transistor MP2, and VNG2=VCCQ-Vtn is input to the gate of transistor MN2. Consequently, transistor MP2 is turned off while transistor MN2 is turned on, so ground potential GND is transmitted to output node No, and the output signal becomes low level (VOUT=GND).

[0028] Conversely, when the input signal VIN is at a high level (VCCQ), the inverter 15 outputs a low level (VINV=GND), and the level shift circuit 20 outputs a low level (VLFP=(1 / 2)·VCCQH). As a result, VPG2=(1 / 2)·VCCQH+Vtp is input to the gate of transistor MP2, and VNG2=GND is input to the gate of transistor MN2. Consequently, transistor MN2 is turned off while transistor MP2 is turned on, so the high power supply potential VCCQH is transmitted to output node No, and the output signal becomes high level (VOUT=VCCQH).

[0029] In this way, the semiconductor device 100A can take a low-amplitude logic signal (input signal VIN) as input and output a high-amplitude logic signal (output voltage VOUT) (GND to VCCQH).

[0030] Figure 2 shows the transient operation waveform of the semiconductor device 100A shown in Figure 1, specifically, the transient operation waveform when the input signal VIN changes from a high level to a low level.

[0031] Referring to Figure 2, when the input signal VIN changes from a high level (VCCQ = 1.8[V]) to a low level (GND = 0[V]), as described above, the gate voltage signal VPG2 changes from a low level ((1 / 2)·VCCQH + Vtp ≈ 2.0[V]) to a high level (VCCQH = 3.3[V]). Also, the gate voltage signal VNG2 rises from a low level (GND = 0[V]) to a high level (VCCQ - Vtn ≈ 1.0[V]).

[0032] In response to changes in the gate voltage signals VNG2 and VPG2, transistor MP2 in the output stage turns off while transistor MN2 turns on. Accordingly, the output voltage VOUT at output terminal 13 changes from a high level (VCCQH = 3.3[V]) to a low level (GND = 0[V]).

[0033] When the output voltage VOUT decreases, there is concern that the drain-source voltages Vds1n and Vds2n of the turned-on transistors MN1 and MN2 will transiently increase. The potential VNN1 of node NN1, which corresponds to the connection node of transistors MN1 and MN2, is equivalent to the bias voltage VREFN input to the gate of transistor MN1 when the output signal is at a high level (VOUT = VCCQH). Assuming VREFN = VCCQ = 1.8[V], for transistor MN1, Vds1n = VCCQH - VCCQ = approximately 1.5[V], and for transistor MN2, Vds1n = VREFN = approximately 1.8[V]. At this time, both Vds1n and Vds2n are below the breakdown voltage level of transistors MN1 and MN2 (1.8[V]).

[0034] In contrast, as shown in Figure 2, during the process in which the gate voltage signal VNG2 rises, the potential VNN1 of node NN1 decreases before the output voltage VOUT, causing the Vds1n of transistor MN1 to transiently increase. In semiconductor device 100A, the transient increase in the Vds1n of transistor MN1 is suppressed by generating the gate voltage signal VNG2 of transistor MN2 using the potential conversion circuit 21.

[0035] Figure 3 shows an operation waveform diagram similar to that in Figure 2, but with the arrangement of the potential conversion circuits 21 and 22 omitted from the semiconductor device 100A.

[0036] As shown in Figure 3, when the potential conversion circuits 21 and 22 are not provided, the gate voltage signal VPG2 rises from 1.8[V] (L level: (1 / 2)·VCCQH) to 3.3[V] (H level: VCCQH) faster than in Figure 2. Similarly, the gate voltage signal VNG2 rises from 0[V] (L level: GND) to 1.8[V] (H level: VCCQ) faster than in Figure 2.

[0037] Accordingly, in Figure 3, the turn-on operation of transistor MN2 is faster, so the decrease in the potential VNN1 of node NN1 is larger compared to Figure 2. As a result, in Figure 3, compared to Figure 2, the transient Vds1n of transistor MN1 becomes excessively large, exceeding the breakdown voltage level (1.8[V]) and rising to about 2.5[V]. As a result, there is concern about hot carrier degradation in transistor MN1.

[0038] In other words, in the semiconductor device 100A of the first comparative example, by providing potential conversion circuits 21 and 22, the gate-source voltage of transistor MN1 during turn-on (Vga2n in Figure 1) can be lowered, thereby slowing down the change in the potential VNN1 of node NN1. As a result, the transient Vds1n of transistor MN1 is reduced compared to Figure 3, and consequently, hot carrier degradation can be suppressed.

[0039] On the other hand, as can be seen from the comparison between Figure 3 and Figure 2, suppressing the gate-source voltage reduces the transistor's turn-on speed, so the time required for the output voltage VOUT level transition (from H level to L level in Figures 2 and 3) increases in Figure 2. In other words, it can be seen that the operating speed of semiconductor device 100A is reduced in exchange for suppressing hot carrier degradation.

[0040] Figure 4 shows a circuit diagram illustrating the configuration of a semiconductor device relating to the second comparative example. In Figure 2, in order to avoid a decrease in operating speed, the potential conversion circuits 21 and 22 shown in Figure 2 are not included, and the drain-source voltage per transistor is reduced by increasing the number of transistors connected in series in the output stage.

[0041] Referring to Figure 4, the semiconductor device 100B relating to the second comparative example includes P-type transistors MP0 to MP2 and N-type transistors MN0 to MN2 that constitute the output stage. In Figure 4, the low power supply potential VCCQ and the high power supply potential VCCQH are at the same levels as in Figure 2. As described above, the breakdown voltage of each of the transistors MN0 to MN2 and MP0 to MP2 that constitute the output stage is equivalent to the low power supply potential VCCQ (1.8 [V]), which is lower than the potential difference between the high power supply potential VCCQH and the ground potential GND.

[0042] The P-type transistors MP0 to MP2 are connected in series between output node No and power line PL via nodes NP1 and NP2. Specifically, the drain of transistor MP0 is connected to output node No (output terminal 13), and its source is connected to node NP1. The source of transistor MP1 is connected to node NP2, and its drain is also connected to node NP1. The source of transistor MP2 is connected to power line PL, and its drain is also connected to node NP2.

[0043] The N-type transistors MN0 to MN2 are connected in series between output node No and ground line GL via nodes NN1 and NN2. Specifically, the drain of transistor MN0 is connected to output node No, and its source is connected to node NN1. The drain of transistor MN1 is connected to node NN1, and its source is connected to node NN2. Also, the source of transistor MP2 is connected to ground line GL, and its drain is connected to node NN2.

[0044] A fixed bias voltage VREFP0 is input to the gate of transistor MP0, and a fixed bias voltage VREFP1 is input to the gate of transistor MP1. For example, VREFP0 = VREFP1 = 0.5·VCCQH. The output signal (VLFP) of the level shift circuit 20 in Figure 1 is input to the gate of transistor MP2 without passing through the potential conversion circuit 22 (Figure 1). That is, the gate voltage signal VPG2 of transistor MP2 has an amplitude of (1 / 2)·VCCQH to VCCQH, i.e., an amplitude of (1 / 2)·3.3[V] to 3.3[V].

[0045] A fixed bias voltage VREFN0 is input to the gate of transistor MN0, and a fixed bias voltage VREFN1 is input to the gate of transistor MN1. For example, VREFN0 = VREFN1 = VCCQ. The output signal (VINV) of the inverter 15 in Figure 1 is input to the gate of transistor MN2 without passing through the potential conversion circuit 21 (Figure 1). That is, the gate voltage signal VNG2 of transistor MN2 has an amplitude from GND to VCCQ, i.e., an amplitude from 0[V] to 1.8[V].

[0046] This study examines the operation of transistors MN0 to MN2 in semiconductor device 100B when the gate voltage signal VNG2 changes from 0[V] to 1.8[V] (low power supply potential VCCQ) in response to a change in the logic level of the input signal VIN, and the output voltage VOUT drops from 3.3[V] to 0[V] (VCCQH).

[0047] First, let's consider the first case where VREFN0 = VREFN1, for example, when both are 1.8[V]. In the first case, when the output voltage VOUT changes from a high level to a low level in response to the rise in the output voltage (VNG2) of the inverter 15, transistors MN2 and MN1 turn on in that order. As a result, the potential drop at node NN1 increases the drain-source voltage Vds0n of transistor MN0 on the output terminal 13 side, leading to increased hot carrier degradation of transistor MN0.

[0048] Next, consider a second case where VREFN0 > VREFN1, for example, VREFN0 = 2.2[V] and VREFN1 = 1.8[V]. In the second case, VREFN0 increases the gate-source voltage Vgs0n of transistor MN0, which is input to the gate, causing the potential of node NN1 to be higher than in the first case described above. As a result, the drain-source voltage Vds0n of transistor MN0, i.e., hot carrier degradation, is suppressed more than in the first case. However, in the second case, there is a concern that when the output voltage VOUT at output terminal 13 drops to 0[V], an overvoltage of 2.2[V] is applied between the drain and gate of transistor MN0, which has a voltage rating of 1.8[V]. Conversely, in the first case, the gate voltage (VREFN0) of transistor MN0 is set so that no overvoltage is applied between the drain and gate of transistor MN0 even when the output voltage VOUT drops to 0[V].

[0049] As described above, in the semiconductor device 100B relating to the second comparative example, the inventors have found that a new challenge is to set the gate voltage of transistors MN0 and NP0, whose drains are connected to the output terminal 13, in a way that does not exceed the breakdown voltage and suppresses hot carrier degradation.

[0050] <First Embodiment> Figure 5 is a circuit diagram illustrating the configuration of the semiconductor device 101A according to Embodiment 1.

[0051] As shown in Figure 5, the semiconductor device 101A includes a level shift circuit 20, a gate voltage control circuit 110, and N-type transistors MN0 to MN2 and P-type transistors MP0 to MP0.

[0052] Transistors MN0~MN2 and MP0~MP0 constitute the same output stage as semiconductor device 100B according to the second comparative example. That is, among the N-type transistors MN0~MN2 connected in series between output terminal 13 and ground line GL, transistor MN0 is positioned closest to output terminal 13 and has a drain electrically connected to output terminal 13. The breakdown voltages of transistors MN0~MN2 and MP0~MP2 are the same as those explained in Figure 4.

[0053] Similarly, among the P-type transistors MP0 to MP2 connected in series between the output terminal 13 and the power line PL, transistor MP0 is positioned closest to the output terminal 13 and has a drain that is electrically connected to the output terminal 13.

[0054] The gate of transistor MP2 receives the output voltage of the level shift circuit 20, similar to that in Figure 1, as the gate voltage signal VPG2. Therefore, when the input signal VIN is at a low level (GND=0[V]), VCCQH (3.3[V]) is input to the gate of transistor MP2, and when the input signal VIN is at a high level (VCCQ=1.8[V]), (1 / 2)·VCCQH (1.65[V]) is input.

[0055] The gate of transistor MN2 receives the output signal (VINV) of inverter 15, as shown in Figure 1, as the gate voltage signal VGN0. Specifically, when the input signal VIN is at a low level, the low power supply potential VCCQ is input to the gate of transistor MN2, and when the input signal VIN is at a high level, the ground potential GND is input. In this way, the gates of transistors MN2 and MP2 receive signals to switch them on and off complementaryly according to the input signal VIN.

[0056] In Figure 5, transistor MP0 corresponds to one embodiment of the "first P-type transistor," transistor MP2 to one embodiment of the "second P-type transistor," and transistor MP1 to one embodiment of the "third P-type transistor." Similarly, transistor MN0 corresponds to one embodiment of the "first N-type transistor," transistor MN2 to one embodiment of the "second N-type transistor," and transistor MN1 to one embodiment of the "third N-type transistor." Furthermore, the ground potential GND corresponds to one embodiment of the "reference potential," the high power supply potential VCCQH to one embodiment of the "first power supply potential," the low power supply potential VCCQ to one embodiment of the "second power supply potential," and the ground line GL corresponds to one embodiment of the "reference potential line."

[0057] In semiconductor device 101A, when the input signal VIN is at a high level (VCCQ = 1.8[V]), the output terminal 13 is electrically connected to the power supply terminal 11 by the activation of transistors MP0 to MP2, and the output voltage VOUT = VCCQH (3.3[V]). On the other hand, when the input signal VIN is at a low level (GND = 0[V]), the output terminal 13 is electrically connected to the ground terminal 12 by the activation of transistors MN0 to MN2, and the output voltage VOUT = GND (0[V]).

[0058] A bias voltage VREFP is input to the gate of transistor MP1 to turn it on, and a bias voltage VREFN is input to the gate of transistor MN1 to turn it on. For example, the bias voltages VREFP and VREFN are set to correspond to the intermediate potential between the high power supply potential VCCQH and the ground potential GND. For example, the bias voltages VREFP and VREFN can be generated by the intermediate potential generation circuit 120 shown in Figure 6. The bias voltage VREFP corresponds to one embodiment of the "first bias voltage," and the bias voltage VREFN corresponds to one embodiment of the "second bias voltage."

[0059] Referring to FIG. 6, the intermediate potential generation circuit 120 has resistor elements R2 and R3 connected in series between the power line PL and the ground line GL via intermediate potential nodes NRFP and NRFN. As a result, an intermediate potential obtained by dividing the high power supply potential VCCQH by the resistor elements R2 and R3 is generated at the intermediate potential nodes NRFP and NRFN.

[0060] The potential of the intermediate potential node NRFP is input as a bias voltage VREFP to the gate of the transistor MP1 and to the gate voltage control circuit 110. Similarly, the potential of the intermediate potential node NRFN is input as a bias voltage VREFN to the gate of the transistor MN1 and to the gate voltage control circuit 110. Therefore, 0 < VREFN, VREFP < VCCQH (3.3 [V]), and VREFN and VREFP are determined by the voltage division ratio of the resistor elements R2 and R3.

[0061] Incidentally, the bias voltages VREFN and VREFP may be set to the same potential by a common intermediate potential generation circuit 120, or may be set to different potentials by individual intermediate potential generation circuits 120 having different voltage division ratios.

[0062] Referring to FIG. 5 again, the gate voltage control circuit 110 includes N-type transistors MN11 and MN12 and P-type transistors MP11 and MP12. The gate voltage control circuit 110 controls the gate voltage signal VPG0 of the transistor MP0 and the gate voltage signal VNG0 of the transistor MN0 according to the output voltage VOUT of the output terminal 13.

[0063] The sources of the transistors MN11 and MN12 are electrically connected to a node NPG0 that transmits the gate voltage signal VPG0 to the transistor MP0. The drain of the transistor MN11 is electrically connected to the output terminal 13 via the resistor element R1, and the drain of the transistor MN12 is electrically connected to the intermediate potential node NRFP of the intermediate potential generation circuit 120. [[ID=*17]]

[0064] A bias voltage VREFP from the intermediate potential generation circuit 120 is input to the gate of the transistor MN11, and the gate of the transistor MN12 is electrically connected to the output terminal 13 via the resistor element R1. The transistor MN11 corresponds to an embodiment of the "fourth N-type transistor", and the transistor MN12 corresponds to an embodiment of the "fifth N-type transistor", respectively.

[0065] The sources of the transistors MP11 and MP12 are electrically connected to a node NNG0 that transmits the gate voltage signal VNG0 to the transistor MN0. The drain of the transistor MP11 is electrically connected to the output terminal 13 via the resistor element R1, and the drain of the transistor MP12 is electrically connected to the intermediate potential node NRFN of the intermediate potential generation circuit 120.

[0066] A bias voltage VREFN from the intermediate potential generation circuit 120 is input to the gate of the transistor MP11, and the gate of the transistor MP12 is electrically connected to the output terminal 13 via the resistor element R1. That is, the transistor MP11 corresponds to an embodiment of the "fourth P-type transistor", and the transistor MP12 corresponds to an embodiment of the "fifth P-type transistor", respectively.

[0067] Thereby, the gate voltage signal VNG0 of the transistor MN0 is controlled according to the high and low relationship between the output voltage VOUT of the output terminal 13 and the bias voltage VREFN according to the on / off states of the transistors MP11 and MP12. Specifically, when VOUT < VREFN, the gate voltage signal VNG0 is set to the bias voltage VREFN by turning on the transistor MP - 12. On the other hand, when VOUT > VREFN, the gate voltage signal VNG0 is set to change following the output voltage VOUT by turning on the transistor MP11.

[0068] Similarly, the gate voltage signal VPG0 of transistor MP0 is controlled according to the high and low relationship between the output voltage VOUT of output terminal 13 and the bias voltage VREFP in response to the on / off states of transistors MN11 and MN12. Specifically, when VOUT > VREFP, the gate voltage signal VPG0 is fixed to the bias voltage VREFP due to the on state of transistor MN12. On the other hand, when VOUT < VREFP, the gate voltage signal VPG0 is set to change following the output voltage VOUT due to the on state of transistor MN11.

[0069] In this way, the gate voltage control circuit 110 operates such that at least one of the gate voltage signals VNG0 and VPG0 changes following the output voltage VOUT in the transient state where the output voltage VOUT changes between GND and VCCQH while maintaining transistor MP0 or MN0 in the on state.

[0070] Next, in semiconductor device 101A, a transient operation in which the output voltage VOUT changes from the state of VOUT = VCCQH (H level) to VOUT = GND (L level) due to the turn-on of transistors MN0 to MN2 will be described.

[0071] In this transient operation, the gate voltage signal VNG0 of transistor MN0 decreases after starting from a voltage higher than the bias voltage VREFN (VOUT = VCCGH) following the output voltage VOUT. Thus, similar to the second case described for semiconductor device 100B according to the second comparative example, the drain-source voltage Vds0n of transistor MN0 generated in response to the turn-on of transistors MN2 and MN1 can be suppressed.

[0072] In the process where the output voltage VOUT further decreases in response to the turn-on of transistors MN0 to MN2, when VOUT < VREFN, the gate voltage signal VNG0 is set equal to the bias voltage VREFN. Therefore, by setting the bias voltage VREFN below the breakdown voltage of transistor MN0, transistor MN0 can be prevented from being applied with an overvoltage between the drain and the gate in the same manner as in the first case described for the semiconductor device 100B according to the second comparative example while maintaining the on state.

[0073] Next, in the semiconductor device 101A, a transient operation in which the output voltage VOUT changes from the state of VOUT = GND (L level) to VOUT = VCCQH (H level) due to the turn-on of transistors MP0 to MP2 will be described.

[0074] In this transient operation, the gate voltage signal VPG0 of transistor MP0 rises after starting from a voltage lower than the bias voltage VREFP (VOUT = GND) following the output voltage VOUT. Thereby, the drain-source voltage Vds0p of transistor MP0 generated in response to the turn-on of transistors MP2 and MP1 can be suppressed.

[0075] [[ID=I2]]In the process where the output voltage VOUT further increases in response to the turn-on of transistors MP0 to MP2, when VOUT > VREFP, the gate voltage signal VNG0 is fixed to the bias voltage VREFP. Therefore, by setting the bias voltage VREFP below the breakdown voltage of transistor MP0, transistor MN0 can be prevented from being applied with an overvoltage between the drain and the gate while maintaining the on state.

[0076] In this way, due to the arrangement of the gate voltage control circuit 110, for transistors MN0 and NP0 whose drains are electrically connected to the output terminal 13, the gate voltage can be controlled so as to suppress hot carrier degradation without exceeding the breakdown voltage in a manner that enjoys both advantages of the first and second cases in the semiconductor device 100B according to the second comparative example.

[0077] In the semiconductor device 101A according to Embodiment 1, the gate voltage signals VPG2 and VNG2 of transistors MN2 and MP2 are generated without the need for the potential conversion circuits 21 and 22 found in the semiconductor device 100A according to the first comparative example. That is, by suppressing the gate-source voltage of transistors MN2 and MP2 during turn-on, it is possible to suppress both hot carrier degradation and maintain operating speed.

[0078] Figure 7 shows the transient operation waveform of semiconductor device 101A shown in Figure 5, specifically the transient operation waveform when the input signal VIN changes from a high level to a low level. Figure 7(a) shows the transient operation waveform of semiconductor device 101A, while Figure 7(b) shows the transient operation waveform of semiconductor device 100A (the first comparative example). Figure 7(b) is a reproduction of the waveform diagram from Figure 2 on the same time axis as Figure 7(a).

[0079] As shown in Figure 7(a), the gate voltage signal VPG2 rises from 1.8[V] (L level: (1 / 2)·VCCQH) to 3.3[V] (H level: VCCQH), similar to Figure 3, and is faster than in Figure 2 (Figure 7(b)). Similarly, the gate voltage signal VNG2 rises from 0[V] (L level: GND) to 1.8[V] (H level: VCCQ), which is faster than in Figure 7(b). Therefore, in Figure 7(a), it can be seen that the turn-on operation of transistor MN2 is faster and the rate of change of the output voltage VOUT is also higher compared to Figure 7(b).

[0080] Furthermore, in Figure 7(a), when the gate voltage signal VNG2 rises, the gate voltage control circuit 110 sets the gate voltage signal VNG0 higher than VREFN (1.8[V]) in accordance with the output voltage VOUT. As a result, by reducing the on-resistance of transistor MN0, the decrease in the potential of node NN1 (VNN1) is suppressed, and the transient drain-source voltage Vds0n of transistor MN0 can be reduced to the same level as or lower than Vds1n in Figure 7(b). This makes it possible to suppress hot carrier degradation, similar to the first comparative example.

[0081] Thus, according to the semiconductor device 101A of Embodiment 1, when generating an output voltage with a voltage amplitude (here, 3.3[V]) higher than the transistor's breakdown voltage (here, 1.8[V]), hot carrier degradation can be suppressed in the same way as the first comparative example (semiconductor device 100A) without reducing the operating speed, as in the first comparative example (semiconductor device 100A).

[0082] <Second Embodiment> Figure 8 is a circuit diagram illustrating the configuration of the semiconductor device 101B according to Embodiment 2.

[0083] Referring to Figures 8 and 5, the semiconductor device 101B differs from the semiconductor device 100A (Figure 5) according to Embodiment 1 in that the gate voltage control circuit 110 has different gate connections for transistors MN12 and MP12. Specifically, the gate of transistor MN12 is electrically connected to node NP1, which corresponds to the source of transistor MP0, rather than to output terminal 13. Similarly, the gate of transistor MP12 is electrically connected to node NN1, which corresponds to the source of transistor MN0, rather than to output terminal 13. The other configurations of semiconductor device 101B are the same as those of semiconductor device 101A, so a detailed explanation will not be repeated.

[0084] In semiconductor device 101B, during the transient operation in which the output voltage VOUT changes from a high level to a low level in response to the turn-on of transistors MN0 to MN2, the potential of node NN1, which is closer to the ground terminal 12, drops before the potential of output terminal 13. As a result, the gate voltage control circuit 110 can turn on transistor MP12 before transistor MP11 turns off.

[0085] Similarly, in the transient operation where the output voltage VOUT changes from a low level to a high level in response to the turn-on of transistors MN0 to MN2, the potential of node NP1, which is closer to the power supply terminal 11, rises before the potential of output terminal 13. As a result, the gate voltage control circuit 110 can turn on transistor MN12 before transistor MN11 turns off.

[0086] In contrast, in the semiconductor device 101A shown in Figure 5, the gates of transistors MN12 and MP12 are electrically connected to the output terminal 13. Therefore, during the period when the output voltage VOUT transiently becomes equal to the bias voltages VREFN and VREFP, both transistors MP11 and MP12, or both transistors MN11 and MN12, may be turned off. Specifically, during the period when the voltage difference between the bias voltage VREFN or VREFP and the output voltage VOUT is smaller than the threshold voltage of transistors MN11 and MN12 or the threshold voltage of transistors MP11 and MP12, both transistors MP11 and MP12, or both transistors MN11 and MN12, will be turned off.

[0087] Thus, when both transistors MP11 and MP12, or both transistors MN11 and MN12, are turned off, node NNG0 or NPG0 becomes floating, raising concerns that the gate voltage signals VNG0 and VPG0 may become transiently unstable. For example, during the period when node NNG0 or NPG0 is floating, the gate voltage signals VNG0 and VPG0 change due to the influence of voltage changes at output terminal 13 via capacitive coupling, raising concerns that the on-current of transistors MN0 and MP0 may decrease. In particular, under high-speed operation, the decrease in on-current may reduce the operating speed, potentially destabilizing the operation of semiconductor device 101A.

[0088] In the semiconductor device 101B according to Embodiment 2, the gate voltage signals VNG0 and VPG0 can be stabilized by changing the gate connection destination of transistors MN12 and MP12 in the gate voltage control circuit 110 from Embodiment 1. As a result, the semiconductor device 101B can be operated stably even under high-speed conditions.

[0089] <Third Embodiment> In the third embodiment, a configuration will be described that allows the semiconductor device according to Embodiment 1 or 2 to be switchable between a low-voltage operating mode in which the amplitude of the output signal corresponds to a low power supply potential VCCQ, and a high-voltage operating mode in which the amplitude corresponds to a high power supply potential VCCQH.

[0090] Figure 9 is a circuit diagram illustrating the configuration of the semiconductor device 101C according to Embodiment 3. The semiconductor device 101C is configured to be able to select and operate between a high-voltage operation mode in which VCCQH = 3.3[V] is supplied to the power terminal 11 and power line PL, and a low-voltage operation mode in which VCCQH = 1.8[V], according to the power mode signal POC*. Here, the power mode signal POC* is set to an L level in the high-voltage operation mode and to an H level in the low-voltage operation mode. The high-voltage operation mode corresponds to one embodiment of the "first operation mode," and the low-voltage operation mode corresponds to one embodiment of the "second operation mode."

[0091] Referring to Figures 9 and 5, the semiconductor device 101C differs from the semiconductor device 100A according to Embodiment 1 (Figure 5) in that it includes a gate voltage control circuit 111 instead of a gate voltage control circuit 110. The gate voltage control circuit 111 further includes connection selection circuits 115 and 116 in addition to the configuration of the gate voltage control circuit 110 shown in Figure 8. The other configurations of the semiconductor device 101C are the same as those of the semiconductor device 101A, so a detailed explanation will not be repeated.

[0092] The connection selection circuit 115 has N-type transistors MN13 and MN14. Transistors MN13 and MN14 are connected in series between node NPG0 (the gate of transistor MP0) and the ground line GL. A bias voltage VREFN is input to the gate of transistor MN13, and a power mode signal POC* is input to the gate of transistor MN14. The connection selection circuit 115 corresponds to the "first connection selection circuit" provided for the gate of transistor MP0.

[0093] The connection selection circuit 116 has N-type transistors MN15 and MN16 and P-type transistors MP13 and MP14. Transistor MP14 is connected between node NNG0 (the gate of transistor MN0) and the intermediate potential node NRFN. The gate of transistor MP14 is connected to node Nx. Transistor MP13 is connected between the power line PL and node Nx. The gate of transistor MP13 is input to the bias voltage VREFN.

[0094] Transistors MN15 and MN16 are connected in series between node Nx and the ground line GL. A bias voltage VREFN is input to the gate of transistor MN15. A power mode signal POC* is input to the gate of transistor MN16. The connection selection circuit 116 corresponds to the "second connection selection circuit" provided for the gate of transistor MN0.

[0095] In low-voltage operation mode, the power mode signal POC* is set to high level, VCCQH = 1.8[V], and the bias voltages VREFN and VREFP are set to approximately 0.8[V] to 1.0[V].

[0096] When transistor MN14 is turned on in response to POC*=H, the source of transistor MN13, which receives a bias voltage VREFN at its gate, becomes ground potential GND, and so transistor MN13 also turns on. The connection selection circuit 115 electrically connects node NPG0, which transmits the gate voltage signal VPG0, to the ground line GL when transistors MN13 and MN14 are turned on.

[0097] Similarly, in low-voltage operation mode, when transistor MN16, which receives the power mode signal POC* at its gate, is turned on, transistor MN15, which receives the bias voltage VREFN at its gate, is also turned on. As transistors MN15 and MN16 are turned on, node Nx becomes ground potential GND, which turns off transistor MP13, which receives the bias voltage VREFN at its gate, while transistor MP14, which has a gate connected to node Nx, is turned on. As a result, the connection selection circuit 116 electrically connects node NNG0, which transmits the gate voltage signal VNG0, to the intermediate potential node NRFN, which supplies the bias voltage VREFN.

[0098] As a result, in low-voltage operation mode (POC*=H level), the gate voltage control circuit 111 fixes the gate voltage signal VPG0 to ground potential GND and the gate voltage signal VNG0 to bias voltage VREFN, regardless of the operation of the gate voltage control circuit 110, that is, regardless of the output voltage VOUT.

[0099] Therefore, in low-voltage operation mode, transistors MN0 and MP0 in semiconductor device 101C remain ON regardless of the output voltage VOUT. Also, in low-voltage operation mode, the voltage conversion function by the level shift circuit 20 is disabled, and a signal equivalent to the inverter output signal VINV (0~1.8[V]) from inverter 15 is input to the gate of transistor MP2. As a result, semiconductor device 101C operates to output an output voltage VOUT corresponding to the input signal VIN (0~1.8[V]) with an amplitude of 0[V](GND) to 1.8[V](VCCQH).

[0100] In contrast, in the high-voltage operation mode where the power mode signal POC* is set to L level, the additionally placed transistors MN13~MN16 are turned off in the gate voltage control circuit 111. Furthermore, when VCCQH=3.3[V] and VREFN=1.8[V], transistor MP13 is turned on, and the high power supply potential VCCQH(3.3.3[V]) is transmitted to node Nx. As a result, transistor MP14 is kept off.

[0101] As a result, the connection selection circuit 115 electrically disconnects node NPG0 from the ground line GL. Similarly, the connection selection circuit 116 electrically disconnects node NNG0 from the intermediate potential node NRFN. Therefore, in the high-voltage operation mode (POC*=L level), the gate voltage control circuit 111 controls the potentials of the gate voltage signals VNG0 and VPG0 using the gate voltage control circuit 110, similar to that in Figure 5. That is, the gate voltage signals VNG0 and VPG0 are controlled in the same manner as in Embodiment 1. As a result, the semiconductor device 101C operates in the same manner as the semiconductor device 101A, outputting an output voltage VOUT corresponding to the input signal VIN (0~1.8[V]) with an amplitude of 0[V](GND)~3.3[V](VCCQH).

[0102] As described above, in the semiconductor device 101A according to Embodiment 1, when the difference between the output voltage VOUT and the bias voltages VREFN and VREFP is smaller than the threshold voltage of the transistor, a period occurs in the gate voltage control circuit 110 in which both transistors MN11 and MN12 are off, or both transistors MP11 and MP12 are off. This raises concerns that the potential of the gate voltage signals VNG0 and VPG0 may become unstable. Therefore, when the semiconductor device 101A is operated in low-voltage operation mode (VCCQH = 1.8[V]), there are concerns that the ratio of the period in which the potential of the gate voltage signals VNG0 and VPG0 becomes unstable to the total period of the transient state in which the output voltage VOUT changes between GND (0[V]) and VCCQH (1.8[V]) will increase.

[0103] In contrast, according to the semiconductor device 101C of Embodiment 3, in low-voltage operation mode, the gate voltage signals VNG0 and VPG0 can be controlled to fix transistors MN0 and MP0 in the ON position. As a result, instability in operation due to changes in the ON current of transistors MN0 and MP0 can be prevented in low-voltage operation mode.

[0104] Furthermore, in the semiconductor device 101C according to Embodiment 3, the gate destinations of transistors MN12 and MP12 included in the gate voltage control circuit 110 can be changed to nodes NN1 and NP1, respectively, as in Figure 7. That is, by combining the semiconductor device 101B according to Embodiment 2 (Figure 8) with Embodiment 3, it is possible to operate the semiconductor device 101C in the same way as the semiconductor device 101B in high-voltage operation mode.

[0105] Furthermore, in embodiments 1 to 3, it is also possible to swap the positions of transistors MN1 and MN2 and place transistor MN2 on the ground terminal 12 side. Similarly, it is also possible to swap the positions of transistors MP1 and MP2 and place transistor MP2 on the power terminal 11 side.

[0106] In embodiments 1 to 3, an example was assumed in which 1.8[V] rated transistors were connected in series to achieve an output voltage VOUT amplitude of 3.3[V]. For this reason, an example configuration in which three transistors are connected in series between the power line PL and the ground line GL and the output node No (output terminal 13) was described. However, it should be noted for clarification that the number of transistors connected in series to constitute the output stage is not limited to the examples given above.

[0107] Embodiments 1 to 3 describe a configuration in which one MN2, MP2 (first transistor) has a voltage input to its gate corresponding to the input signal VIN, one MN0, MP0 (second transistor) has a gate voltage controlled by gate voltage control circuits 110, 111, and one MN1, MP1 (third transistor) has a gate voltage input to its gate corresponding to bias voltages VREFP, VREFN. However, in order to ensure the breakdown voltage between the drain and source, it is also possible to add any number of transistors of the same conductivity type between transistors MN2, MP2 and transistors MN1, MP1, and / or between transistors MN0, MP0 and transistors MN1, MP1. In this case, the gate voltage of the added transistors can be controlled in the same way as that of transistors MN2, MP2 (first transistor), transistors MN0, MP0 (second transistor), or transistors MN1, MP1 (third transistor).

[0108] Alternatively, the semiconductor device according to this embodiment can be configured by omitting the arrangement of transistors MN1 and MP1, to which bias voltages VREFP and VREFN are input to the gate.

[0109] Figure 10 shows a circuit diagram illustrating the configuration of a modified example of the semiconductor device according to this embodiment.

[0110] Referring to Figures 10 and 5, the modified semiconductor device 101D differs from the semiconductor device 100A (Figure 5) according to Embodiment 1 in that the arrangement of transistor MN1, to which the bias voltage VREFP is input to the gate, and transistor MP1, to which the bias voltage VREFP is input to the gate, is omitted. Accordingly, the output stage is composed of P-type transistors MP0 and MP2 connected in series between the power line PL and output node No via node NP1, and N-type transistors MN0 and MN2 connected in series between the ground line GL and output node No via node NN1.

[0111] The gate voltages of transistors MN2 and MP2 are controlled to switch them on and off complementaryly according to the input signal VIN, similar to Embodiment 1. The gates of transistors MN0 and MP0 are input to gate voltage signals VNG0 and VPG0 generated by a gate voltage control circuit 110 similar to that in Figure 5 or Figure 8. Alternatively, the gates of transistors MN0 and MP0 may be input to gate voltage signals VNG0 and VPG0 generated by a gate voltage control circuit 111 shown in Figure 9.

[0112] Furthermore, in the semiconductor device 101D shown in Figure 10, it is possible to add any number of transistors of the same conductivity type between transistors MN0, MP0 and transistors MP2, MN2. In this case, the gate voltage of the added transistors can be controlled in the same way as that of transistors MN2, MP2 (first transistors) or transistors MN0, MP0 (second transistors).

[0113] Regarding the multiple embodiments described above, it is also stated for confirmation that it was intended from the outset of filing that the configurations described in each embodiment could be appropriately combined, including combinations not mentioned in the specification, to the extent that no inconsistencies or contradictions would arise.

[0114] Although the present disclosure has been described in detail based on embodiments, it goes without saying that the present disclosure is not limited to these embodiments and can be modified in various ways without departing from its essence. [Explanation of symbols]

[0115] 11 Power terminal, 12 Ground terminal, 13 Output terminal, 15 Inverter, 20 Level shift circuit, 21, 22 Potential conversion circuit, 100A, 100B, 101A~101D Semiconductor equipment, 110, 111 Gate voltage control circuit, 115, 116 Connection selection circuit, 120 Intermediate potential generation circuit, GL Ground line, GND Ground potential, NRFN, NRFP Intermediate potential node, Ni Input node, No Output node, PL Power line, POC* Power mode signal, R1~R3 ​​Resistor element, VCCQ Low power supply potential, VCCQH High power supply potential, VIN Input signal, VINV Inverter output signal, VLFP Level shift signal, VNG0, VNG2, VPG0, VPG2 Gate voltage signal, VOUT Output voltage, VREFN, VREFN0, VREFN1, VREFP, VREFP0, VREFP1 Bias voltage.

Claims

1. A semiconductor device that generates an output signal at an output terminal with a voltage amplitude larger than that of an input signal, A first and second P-type transistor are connected in series between the power supply line that supplies the first power supply potential and the output terminal, The system comprises a reference potential line that supplies a reference potential and first and second N-type transistors connected in series between the reference potential line and the output terminal, The first N-type and P-type transistors have drains electrically connected to the output terminals. The gates of the second N-type and P-type transistors are respectively input to the second N-type and P-type transistors, in accordance with the input signal, to switch them on and off in a complementary manner. The aforementioned semiconductor device is The system further includes a gate voltage control circuit for changing the gate voltages of the first P-type and N-type transistors in accordance with the voltage of the output terminal, The gate voltage control circuit is configured to keep the first P-type or N-type transistor ON when the voltage of the output signal changes in response to a change in the logic level of the input signal, and to change the gate voltage of at least one of the first N-type and P-type transistors in accordance with the change in the voltage of the output terminal. The gate voltage control circuit is configured such that when the voltage at the output terminal is higher than a predetermined first bias voltage, it inputs the first bias voltage to the gate of the first P-type transistor, while when the voltage at the output terminal is lower than the first bias voltage, it inputs a voltage corresponding to the voltage at the output terminal to the gate of the first P-type transistor. A semiconductor device wherein the first bias voltage is less than or equal to the breakdown voltage of the first P-type transistor.

2. The aforementioned semiconductor device is The system further comprises a third P-type transistor connected in series with the second P-type transistor between the first P-type transistor and the power supply line, The semiconductor device according to claim 1, wherein the first bias voltage is input to the gate of the third P-type transistor.

3. A semiconductor device that generates an output signal at an output terminal with a voltage amplitude greater than that of an input signal, A first and second P-type transistor are connected in series between the power supply line that supplies the first power supply potential and the output terminal, The system comprises a reference potential line that supplies a reference potential and first and second N-type transistors connected in series between the reference potential line and the output terminal, The first N-type and P-type transistors have drains electrically connected to the output terminals. The gates of the second N-type and P-type transistors are respectively input to the second N-type and P-type transistors, in accordance with the input signal, to switch them on and off in a complementary manner. The aforementioned semiconductor device is The system further includes a gate voltage control circuit for changing the gate voltages of the first P-type and N-type transistors in accordance with the voltage of the output terminal, The gate voltage control circuit is configured to keep the first P-type or N-type transistor ON when the voltage of the output signal changes in response to a change in the logic level of the input signal, and to change the gate voltage of at least one of the first N-type and P-type transistors in accordance with the change in the voltage of the output terminal. The gate voltage control circuit is configured such that when the voltage at the output terminal is lower than a predetermined second bias voltage, it inputs the second bias voltage to the gate of the first N-type transistor, while when the voltage at the output terminal is higher than the second bias voltage, it inputs a voltage corresponding to the voltage at the output terminal to the gate of the first N-type transistor. A semiconductor device wherein the second bias voltage is less than or equal to the breakdown voltage of the first N-type transistor.

4. The aforementioned semiconductor device is The system further comprises a third N-type transistor connected in series with the second N-type transistor between the first N-type transistor and the reference potential line, The semiconductor device according to claim 3, wherein the gate of the third N-type transistor is input to the second bias voltage.

5. The gate voltage control circuit is, A fourth N-type transistor having a source connected to the gate of the first P-type transistor and a drain electrically connected to the output terminal, The present invention includes a fifth N-type transistor having a source connected to the gate of the first P-type transistor and a drain electrically connected to a node that supplies the first bias voltage, The gate of the fourth N-type transistor is input to the first bias voltage. The semiconductor device according to claim 1, wherein the gate of the fifth N-type transistor is electrically connected to the output terminal.

6. The semiconductor device operates by selectively applying a first operating mode in which the first power supply potential is set to a first potential, and a second operating mode in which the first power supply potential is set to a second potential lower than the first potential. The semiconductor device according to claim 5, wherein the gate voltage control circuit further includes a first connection selection circuit configured to electrically connect the gate of the first P-type transistor to the reference potential line in the second operating mode, and electrically disconnect the gate of the first P-type transistor from the reference potential line in the first operating mode.

7. The gate voltage control circuit is, A fourth N-type transistor having a source connected to the gate of the first P-type transistor and a drain electrically connected to the output terminal, The present invention includes a fifth N-type transistor having a source connected to the gate of the first P-type transistor and a drain electrically connected to a node that supplies the first bias voltage, The gate of the fourth N-type transistor is input to the first bias voltage. The semiconductor device according to claim 1, wherein the gate of the fifth N-type transistor is electrically connected to the source of the first P-type transistor.

8. The gate voltage control circuit is, A fourth P-type transistor having a source connected to the gate of the first N-type transistor and a drain electrically connected to the output terminal, The system includes a fifth P-type transistor having a source connected to the gate of the first N-type transistor and a drain electrically connected to a node that supplies the second bias voltage. The gate of the fourth P-type transistor is input to the second bias voltage. The semiconductor device according to claim 3, wherein the gate of the fifth P-type transistor is electrically connected to the output terminal.

9. The semiconductor device operates by selectively applying a first operating mode in which the first power supply potential is set to a first potential, and a second operating mode in which the first power supply potential is set to a second potential lower than the first potential. The semiconductor device according to claim 8, wherein the gate voltage control circuit further includes a second connection selection circuit configured to electrically connect the gate of the first N-type transistor to a node supplying the second bias voltage in the second operating mode, while electrically disconnecting the gate of the first N-type transistor from the node in the first operating mode.

10. The gate voltage control circuit is, A fourth P-type transistor having a source connected to the gate of the first N-type transistor and a drain electrically connected to the output terminal, The system includes a fifth P-type transistor having a source connected to the gate of the first N-type transistor and a drain electrically connected to a node that supplies the second bias voltage. The gate of the fourth P-type transistor is input to the second bias voltage. The semiconductor device according to claim 3, wherein the gate of the fifth P-type transistor is electrically connected to the source of the first N-type transistor and electrically connected to the output terminal.

11. The semiconductor device operates by selectively applying a first operating mode in which the first power supply potential is set to a first potential, and a second operating mode in which the first power supply potential is set to a second potential lower than the first potential. The semiconductor device according to claim 1, wherein the gate voltage control circuit operates such that, when the voltage of the output signal changes in response to a change in the logic level of the input signal, in the first operating mode, it changes the gate voltage of the first P-type transistor in accordance with the change in the voltage of the output terminal, and in the second operating mode, it fixes the gate voltage of the first P-type transistor regardless of the voltage of the output terminal.

12. The semiconductor device operates by selectively applying a first operating mode in which the first power supply potential is set to a first potential, and a second operating mode in which the first power supply potential is set to a second potential lower than the first potential. The semiconductor device according to claim 3, wherein the gate voltage control circuit operates such that, when the voltage of the output signal changes in response to a change in the logic level of the input signal, in the first operating mode, it changes the gate voltage of the first N-type transistor in accordance with the change in the voltage of the output terminal, while in the second operating mode, it fixes the gate voltage of the first N-type transistor regardless of the voltage of the output terminal.

13. The aforementioned semiconductor device is A third P-type transistor is connected in series with the second P-type transistor between the first P-type transistor and the power supply line, The system further comprises a third N-type transistor connected in series with the second N-type transistor between the first N-type transistor and the reference potential line, The semiconductor device according to claim 1 or 3, wherein a bias voltage lower than the potential difference between the reference potential and the first power supply potential for turning on the third P-type transistor and the third N-type transistor is input to the gates of the third P-type transistor and the third N-type transistor.

14. The input signal is set to a second power supply potential lower than the reference potential or the first power supply potential. The semiconductor device according to claim 1 or 3, wherein the breakdown voltage of each of the first and second P-type transistors and the first and second N-type transistors is greater than or equal to the potential difference between the second power supply potential and the reference potential.

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