Semiconductor structure and manufacturing method thereof

Abstract

This disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a first wafer. The first wafer includes a first interconnect layer, a first conductive layer disposed on the first interconnect layer, a first dielectric layer covering the first conductive layer, and a first bonding pad embedded in the first dielectric layer and extending into the first conductive layer. The method for manufacturing the semiconductor structure includes the following operations: forming a first conductive layer on the first interconnect layer; forming a first dielectric layer on the first conductive layer and the first interconnect layer; etching the first dielectric layer to form a first trench on the first conductive layer; etching a portion of the first conductive layer to form a second trench; and forming a first bonding pad in the second trench.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure and a method for manufacturing the semiconductor structure. Prior Technology

[0002] In pursuit of smaller semiconductor device sizes and smaller semiconductor structure footprints, chip-on-chip and chip-on-wafer technologies are widely used in the manufacture of semiconductor packaging structures.

[0003] Chip-to-chip and chip-to-wafer stacking not only reduce the footprint of semiconductor packaging structures but also increase memory capacity and integration density. Increased memory capacity and integration density lead to faster speeds and greater bandwidth. However, chip-to-chip and chip-to-wafer stacking still present some challenges. Summary of the Invention

[0004] This disclosure provides a semiconductor structure. The semiconductor structure includes a first wafer. The first wafer includes a first interconnect layer, a first conductive layer disposed on the first interconnect layer, a first dielectric layer covering the first conductive layer, and a first bonding pad embedded in the first dielectric layer and extending into the first conductive layer.

[0005] In some embodiments, the first wafer further includes an anti-reflective layer disposed between the first conductive layer and the first dielectric layer and on the first conductive layer.

[0006] In some embodiments, the first bonding pad includes a first metal layer and a second metal layer, with the first metal layer surrounding the second metal layer.

[0007] In some embodiments, the cross-section of the first bonding pad includes a top width, a bottom width, and an intermediate width that is less than or equal to the top width and the bottom width.

[0008] In some implementations, the top width is greater than the bottom width.

[0009] In some embodiments, the semiconductor structure further includes a second wafer disposed on the first wafer, wherein the second wafer includes a second dielectric layer, a substrate disposed on the second dielectric layer, a second bonding pad embedded in the second dielectric layer and bonded to the first bonding pad, and a silicon through-hole embedded in the second dielectric layer and the substrate and in contact with the second bonding pad.

[0010] In some embodiments, the interface between the first and second mating pads is substantially flat.

[0011] In some embodiments, the second bonding pad includes a first metal layer and a second metal layer, with the first metal layer surrounding the second metal layer.

[0012] In some embodiments, the cross-section of the second bonding pad includes a top width and a bottom width that is greater than or equal to the top width.

[0013] This disclosure provides a method for manufacturing a semiconductor structure. This method includes the following operations: forming a first conductive layer on a first interconnect layer; forming a first dielectric layer on the first conductive layer and the first interconnect layer; etching the first dielectric layer to form a first trench on the first conductive layer; etching a portion of the first conductive layer to form a second trench; and forming a first bonding pad in the second trench.

[0014] In some embodiments, this method further includes the following operations: An anti-reflective layer is formed on the first conductive layer before forming the first dielectric layer on the first conductive layer and the first interconnect layer. A portion of the anti-reflective layer is etched before etching a portion of the first conductive layer to form the second trench.

[0015] In some embodiments, forming the first bonding pad in the second trench includes sequentially depositing a first metal layer and a second metal layer in the second trench.

[0016] In some embodiments, the grain size of the first metal layer is larger than the grain size of the second metal layer.

[0017] In some embodiments, the method further includes the following operations: receiving a first substrate and a silicon through-hole embedded in the first substrate; etching the first substrate to expose the silicon through-hole; forming a second dielectric layer to cover the first substrate and the silicon through-hole; etching the second dielectric layer to form a third trench and expose the silicon through-hole; forming a second bonding pad in the third trench; and bonding the first bonding pad to the second bonding pad.

[0018] In some embodiments, forming the second bonding pad in the third trench includes sequentially forming a first metal layer and a second metal layer in the third trench.

[0019] In some embodiments, the grain size of the first metal layer is larger than the grain size of the second metal layer.

[0020] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are intended to provide further explanation of the claimed content of this disclosure. Simple Explanation of the Diagram

[0021] This disclosure can be more fully understood by reading the following detailed description of the embodiments and referring to the accompanying drawings. Figure 1A is a cross-sectional view of a semiconductor structure according to some embodiments. Figure 1B is an enlarged view of part A in Figure 1A. Figure 1C is a cross-sectional view of a semiconductor structure according to some embodiments. Figure 1D is an enlarged view of part B in Figure 1C. Figures 2A and 2B are flowcharts of methods for manufacturing semiconductor structures according to some embodiments. Figure 3 is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor structure according to various embodiments of this disclosure. Figure 4A is an enlarged view of part C in Figure 3. Figures 4B through 4F illustrate intermediate stages in the fabrication of semiconductor structures, continuing from Figure 4A. Figures 5, 6, and 7 are cross-sectional views illustrating intermediate stages of manufacturing a semiconductor structure according to various embodiments of this disclosure. Figure 8A is an enlarged view of part D in Figure 7. Figures 8B through 8G illustrate intermediate stages in the fabrication of semiconductor structures, continuing from Figure 8A. Figures 9 and 10A are cross-sectional views illustrating intermediate stages of manufacturing a semiconductor structure according to various embodiments of this disclosure. Figure 10B is an enlarged view of part E in Figure 10A. Figure 11A is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor structure according to various embodiments of this disclosure. Figure 11B is an enlarged view of part F in Figure 11A. Figures 12A to 13 are cross-sectional views illustrating intermediate stages of manufacturing a semiconductor package structure according to various embodiments of this disclosure. Implementation

[0022] Embodiments of the present disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0023] It should be understood that while the terms "first," "second," "third," etc., may be used in this document to describe different elements, parts, regions, layers, and / or components, such elements, parts, regions, layers, and / or components should not be limited by these terms. These terms are used only to distinguish an element, part, region, layer, or component from another element, part, region, layer, or component. Therefore, without departing from the teachings of this document, "first element," "element," "region," "layer," or "part" discussed below may be referred to as a second element, element, region, layer, or component.

[0024] This disclosure relates to structures composed of different layers. When the terms "on," "above," or "over" are used to refer to two different layers (including a substrate), they simply mean that one layer is on top of or on top of another. These terms do not require that the two layers be in direct contact and allow other layers to be located between them. For example, all layers of a structure can be considered to be "on" the substrate, even if they are not all in direct contact with the substrate. The term "direct" can be used to indicate that two layers are in direct contact with each other and there is no layer between them.

[0025] This disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure. In the semiconductor structure, a bonding pad extends into the conductive layer, which increases the contact area between the conductive layer and the bonding pad, thereby reducing the resistance between the conductive layer and the bonding pad.

[0026] Figure 1A is a cross-sectional view of a semiconductor structure 100A according to some embodiments. Figure 1B is an enlarged view of part A in Figure 1A. To simplify the diagrams in Figure 1A, some semiconductor elements are shown only in Figure 1B but not in Figure 1A. Referring to Figures 1A to 1B, the semiconductor structure 100A includes a first wafer 110. The first wafer 110 includes a substrate 111, a first interconnect layer 112, a first conductive layer 113, a first dielectric layer 114, an inorganic barrier layer 115, an anti-reflective layer 116, and a first bonding pad 117. In some embodiments, the substrate 111 includes a silicon (Si) substrate, a substrate formed of a material including Si, a silicon-on-insulator (SOI) substrate, or a substrate formed of other types of semiconductor materials.

[0027] As shown in Figures 1A and 1B, a first interconnect layer 112 is disposed on a substrate 111. The first interconnect layer 112 includes a plurality of conductive wires 112L, a plurality of conductive vias 112V, and a dielectric layer 112D. The conductive wires 112L and conductive vias 112V are disposed in the dielectric layer 112D. The conductive wires 112L and conductive vias 112V are embedded in the dielectric layer 112D, wherein the conductive wires 112L and conductive vias 112V are interconnected. In some embodiments, the conductive wires 112L and conductive vias 112V respectively comprise conductive materials, such as aluminum (Al), copper (Cu), titanium (Ti), ruthenium (Ru), or tungsten (W), but the present disclosure is not limited thereto. In some embodiments, dielectric layer 112D includes, for example, but not limited to, silicon dioxide (SiO2), boron-containing silicate glass (BSG), fluorine-containing silicate glass (FSG), silicon nitride (Si3N4), silicon carbide (SiC), borophosphosilicate glass (BPSG), silicon oxynitride (SiON), or combinations thereof. In some embodiments, a diffusion barrier layer (not shown) is disposed between conductor 112L / conductive via 112V and dielectric layer 112D. In some embodiments, diffusion barrier layer includes, for example, but not limited to, titanium nitride (TiN) or tantalum nitride (TaN). The first interconnect layer 112 can be electrically connected to other elements in the first wafer 110, which will be described below.

[0028] As shown in Figures 1A and 1B, a first conductive layer 113 is disposed on the first interconnect layer 112. In some embodiments, the first conductive layer 113 comprises a metal, such as Al, W, Cu, Ti, or Ru, but this disclosure is not limited thereto. In some embodiments, the top surface of the first conductive layer 113 is concave, but the shape of the concave surface is not limited to that shown in Figure 1B. The first conductive layer 113 can be electrically connected to the first interconnect layer 112. The semiconductor structure 100A can implement any number of first conductive layers 113, such as one, two, three, four, five, etc.

[0029] As shown in Figures 1A and 1B, a first dielectric layer 114 covers a first conductive layer 113. In some embodiments, the first dielectric layer 114 includes, for example, but not limited to, SiO2, BSG, FSG, Si3N4, SiC, BPSG, SiON, or combinations thereof. As shown in Figures 1A and 1B, an inorganic barrier layer 115 is disposed on the first dielectric layer 114. In some embodiments, the inorganic barrier layer 115 includes, for example, but not limited to, SiO2, silicon carbon nitride (SiCN), SiN, SiON, SiC, or combinations thereof.

[0030] As shown in Figures 1A and 1B, an anti-reflective layer 116 is disposed between the first conductive layer 113 and the first dielectric layer 114, and on the first conductive layer 113. In some embodiments, the anti-reflective layer 116 comprises TiN, Ti, or a combination thereof, but this disclosure is not limited thereto. The anti-reflective layer 116 prevents the first conductive layer 113 from being etched into unintended patterns after subsequent exposure and development.

[0031] As shown in Figures 1A and 1B, a first bonding pad 117 is embedded in a first dielectric layer 114 and an inorganic barrier layer 115, and extends into a first conductive layer 113. In some embodiments, the top surface of the first bonding pad 117 is substantially coplanar with the top surface of the inorganic barrier layer 115. In some embodiments, the first bonding pad 117 includes a first metal layer 118 and a second metal layer 119, with the first metal layer 118 surrounding the second metal layer 119. In some embodiments, the first metal layer 118 extends into the first conductive layer 113. In some embodiments, the first metal layer 118 and the second metal layer 119 each comprise TaN, Ta, TiN, Ti, Cu, or combinations thereof. In some embodiments, the first metal layer 118 and the second metal layer 119 comprise the same material. In some embodiments, the first metal layer 118 and the second metal layer 119 comprise different materials. In some embodiments, the first bonding pad 117 is a columnar structure. In some embodiments, the cross-section of the first bonding pad 117 includes a top width d1, a bottom width d3, and an intermediate width d2 that is less than or equal to the top width d1 and the bottom width d3. In some embodiments, the top width d1 is greater than the bottom width d3. The first bonding pad 117 provides a larger surface area for electrical connection with other components. Compared to a semiconductor structure where the bonding pad does not extend into the conductive layer, extending the first bonding pad 117 into the first conductive layer 113 increases the contact area between the first conductive layer 113 and the first bonding pad 117, resulting in a lower resistance between the first conductive layer 113 and the first bonding pad 117. The semiconductor structure 100A can implement any number of first bonding pads 117, such as one, two, three, four, five, etc.

[0032] As shown in Figures 1A and 1B, the semiconductor structure 100A further includes a second wafer 120 disposed on the first wafer 110, wherein the second wafer 120 includes an inorganic barrier layer 121, a second dielectric layer 122, a first substrate 123, a second bonding pad 124, a silicon through-hole 125, a second interconnect layer 126, a third dielectric layer 127, and a second conductive layer 128. In some embodiments, the inorganic barrier layer 121 includes, for example, but not limited to, SiO2, SiCN, SiN, SiON, or SiC. In some embodiments, the inorganic barrier layer 121 is bonded to the inorganic barrier layer 115. In some embodiments, the bonding interface 129 between the inorganic barrier layer 121 and the inorganic barrier layer 115 is substantially planar. As shown in Figures 1A and 1B, the second dielectric layer 122 is disposed on the inorganic barrier layer 121. In some embodiments, the second dielectric layer 122 includes, for example, but not limited to, SiO2, BSG, FSG, Si3N4, SiC, BPSG, SiON, or combinations thereof. As shown in Figures 1A to 1B, a first substrate 123 is disposed on the second dielectric layer 122. In some embodiments, the first substrate 123 includes a Si substrate, a substrate formed of a material including Si, an SOI substrate, or a substrate formed of other types of semiconductor materials.

[0033] As shown in Figures 1A and 1B, the second bonding pad 124 is embedded in the second dielectric layer 122 and the inorganic barrier layer 121, and bonded to the first bonding pad 117. In some embodiments, the bottom surface of the second bonding pad 124 is substantially coplanar with the bottom surface of the inorganic barrier layer 121. In some embodiments, the bonding interface 129 between the first bonding pad 117 and the second bonding pad 124 is substantially flat. In some embodiments, the second bonding pad 124 includes a first metal layer 130 and a second metal layer 131, with the first metal layer 130 surrounding the second metal layer 131. In some embodiments, the first metal layer 130 and the second metal layer 131 each comprise TaN, Ta, TiN, Ti, Cu, or combinations thereof. In some embodiments, the first metal layer 130 and the second metal layer 131 comprise the same material. In some embodiments, the first metal layer 130 and the second metal layer 131 comprise different materials. In some embodiments, the second bonding pad 124 is a tubular structure. In some embodiments, the cross-section of the second bonding pad 124 includes a top width d4 and a bottom width d5 ​​greater than or equal to the top width d4. The second bonding pad 124 provides a larger surface area for electrical connection with other components. The semiconductor structure 100A can implement any number of second bonding pads 124, such as one, two, three, four, five, etc.

[0034] As shown in Figures 1A and 1B, a silicon through-hole 125 is embedded in the second dielectric layer 122 and the first substrate 123, and contacts the second bonding pad 124. In some embodiments, the top surface of the silicon through-hole 125 is substantially coplanar with the top surface of the first substrate 123. The semiconductor structure 100A can implement any number of silicon through-holes 125, such as one, two, three, four, five, etc. As shown in Figures 1A and 1B, a second interconnect layer 126 is disposed on the first substrate 123 and the silicon through-hole 125. The second interconnect layer 126 includes a plurality of wires 126L, a plurality of conductive vias 126V, and a dielectric layer 126D. The wires 126L and conductive vias 126V are disposed in the dielectric layer 126D. The wires 126L and conductive vias 126V are embedded in the dielectric layer 126D, wherein the wires 126L and conductive vias 126V are interconnected. For embodiments of the conductor 126L, conductive via 126V, and dielectric layer 126D, please refer to the aforementioned embodiments of the conductor 112L, conductive via 112V, and dielectric layer 112D. The second interconnect layer 126 can be electrically connected to the silicon through-hole 125 and other components in the second wafer 120, which will be described below.

[0035] As shown in Figure 1A, a third dielectric layer 127 is disposed on the second interconnect layer 126. In some embodiments, the third dielectric layer 127 includes, for example, but not limited to, SiO2, BSG, FSG, Si3N4, SiC, BPSG, SiON, or combinations thereof. As shown in Figure 1A, a second conductive layer 128 is embedded in the third dielectric layer 127. In some embodiments, the top surface of the second conductive layer 128 is substantially coplanar with the top surface of the third dielectric layer 127. In some embodiments, the second conductive layer 128 includes a metal, such as Al, W, Cu, Ti, or Ru, but this disclosure is not limited thereto. In some embodiments, the cross-section of the second conductive layer 128 is rectangular or trapezoidal, but this disclosure is not limited thereto. The second conductive layer 128 can be electrically connected to the second interconnect layer 126. The semiconductor structure 100A can implement any number of second conductive layers 128, for example, one, two, three, four, five, etc.

[0036] Figure 1C is a cross-sectional view of a semiconductor structure 100B according to some embodiments. Figure 1D is an enlarged view of part B in Figure 1C. To simplify the diagrams in Figure 1C, some semiconductor elements are shown only in Figure 1D but not in Figure 1C. Referring also to Figures 1C to 1D, the semiconductor structure 100B further includes a first wafer 140 disposed between a first wafer 110 and a second wafer 120. The first wafer 140 includes an inorganic barrier layer 141, a second dielectric layer 142, a second bonding pad 143, a substrate 144, a silicon through-hole 145, a first interconnect layer 146, a first conductive layer 147, a first dielectric layer 148, an anti-reflective layer 149, a first bonding pad 150, and an inorganic barrier layer 151. The inorganic barrier layer 141 is bonded to the inorganic barrier layer 115 (not shown). For embodiments of the inorganic barrier layer 141, please refer to the aforementioned embodiments of the inorganic barrier layer 121. As shown in Figures 1C to 1D, a second dielectric layer 142 is disposed on an inorganic barrier layer 141. For an embodiment of the second dielectric layer 142, please refer to the previously described embodiment of the second dielectric layer 122. A second bonding pad 143 is embedded in the second dielectric layer 142 and the inorganic barrier layer 141, and is bonded to a first bonding pad 117. In some embodiments, the second bonding pad 143 includes a first metal layer 152 and a second metal layer 153, with the first metal layer 152 surrounding the second metal layer 153. For an embodiment of the second bonding pad 143, the first metal layer 152, and the second metal layer 153, please refer to the previously described embodiments of the second bonding pad 124, the first metal layer 130, and the second metal layer 131. A substrate 144 is disposed on the second dielectric layer 142. For an embodiment of the substrate 144, please refer to the previously described embodiment of the first substrate 123. A silicon through-hole 145 is embedded in the substrate 144 and the second dielectric layer 142 and contacts the second bonding pad 143. For an embodiment of silicon through-hole 145, please refer to the aforementioned embodiment of silicon through-hole 125. A first interconnect layer 146 is disposed on the substrate 144 and the silicon through-hole 145. The first interconnect layer 146 includes a plurality of conductive lines 146L, a plurality of conductive vias 146V, and a dielectric layer 112D. For an embodiment of the first interconnect layer 146, conductive lines 146L, conductive vias 146V, and dielectric layer 146D, please refer to the aforementioned embodiment of the first interconnect layer 112, conductive lines 112L, conductive vias 112V, and dielectric layer 112D. For an embodiment of the first conductive layer 147, first dielectric layer 148, anti-reflective layer 149, first bonding pad 150, and inorganic barrier layer 151, please refer to the aforementioned embodiment of the first conductive layer 113, first dielectric layer 114, anti-reflective layer 116, first bonding pad 117, and inorganic barrier layer 115. The first bonding pad 150 and the inorganic barrier layer 151 are respectively bonded to the second bonding pad 124 and the inorganic barrier layer 121 (not shown).In some embodiments, the first bonding pad 150 includes a first metal layer 154 and a second metal layer 155, with the first metal layer 154 surrounding the second metal layer 155. For embodiments of the first metal layer 154 and the second metal layer 155, please refer to the previously described embodiments of the first metal layer 118 and the second metal layer 119.

[0037] Figures 2A and 2B are flowcharts of a method 200 for manufacturing a semiconductor structure 100A according to some embodiments. Method 200 includes operations 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, and 226. Figures 3, 5, 6, 7, 9, 10A, and 11A are cross-sectional views showing intermediate stages of manufacturing the semiconductor structure 100A according to various embodiments of this disclosure. Although the methods disclosed herein are described using a series of operations or steps, the order in which these operations or steps are shown should not be construed as a limitation of this disclosure. For example, some operations may be performed in a different order and / or simultaneously with other steps. Furthermore, it is not necessary to perform all the shown operations and / or features to implement the embodiments of this disclosure. Additionally, each operation described herein may comprise several sub-steps or actions. It is worth noting that the number of semiconductor elements in Figures 3 to 11B is not limited to this; in other words, the number of semiconductor elements can be 1, 2, 3, 4, 5, etc.

[0038] Figure 3 is a cross-sectional view of semiconductor structure 300. Figure 4A is an enlarged view of portion C in Figure 3. To simplify the diagram in Figure 3, some semiconductor elements are shown only in Figure 4A but not in Figure 3. Referring to Figures 2A, 3, and 4A, method 200 begins with operation 202, receiving substrate 111. In operation 204, a first interconnect layer 112 is formed on substrate 111. The first interconnect layer 112 can be formed by the following operations: forming a plurality of conductive lines 112L and a plurality of conductive vias 112V, followed by depositing a dielectric layer 112D to cover the conductive lines 112L and conductive vias 112V. In some embodiments, the conductor 112L, the conductive via 112V, and the dielectric layer 112D are formed by a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low-pressure CVD (LPCVD), another deposition process, or any suitable combination thereof. In operation 206, one or more first conductive layers 304 are formed on the first interconnect layer 112. In some embodiments, the first conductive layer 304 is formed by a deposition process such as CVD, PVD, ALD, LPCVD, another deposition process, or any suitable combination thereof. In operation 208, a first dielectric layer 306 is formed on the first conductive layer 304 and the first interconnect layer 112. In some embodiments, the first dielectric layer 306 is formed by a deposition process such as CVD, PVD, ALD, LPCVD, another deposition process, or any suitable combination thereof. Before forming the first dielectric layer 306 on the first conductive layer 304 and the first interconnect layer 112, one or more anti-reflection layers 308 are formed on the first conductive layer 304. In some embodiments, the anti-reflection layer 308 is formed by a deposition process such as CVD, PVD, ALD, LPCVD, another deposition process, or any suitable combination thereof. After operation 208, an inorganic barrier layer 310 is deposited on the first dielectric layer 306 to form the semiconductor structure 300. In some embodiments, the inorganic barrier layer 310 is formed by a deposition process such as CVD, PVD, ALD, LPCVD, another deposition process, or any suitable combination thereof.

[0039] Referring to Figures 2A, 4A, and 4B, in operation 210, a first dielectric layer 306 is etched to form one or more first trenches 312 and a first dielectric layer 114 on a first conductive layer 304. Prior to etching the first dielectric layer 306, an inorganic barrier layer 310 is etched to form an inorganic barrier layer 115. In some embodiments, the first dielectric layer 306 and the inorganic barrier layer 310 are etched using a dry etching process. In some embodiments, the first trench 312 includes a top width d6 and a neck width d7. In some embodiments, the top width d6 is greater than or equal to the neck width d7.

[0040] Referring to Figures 2A, 4B, and 4C, in operation 212, a portion of the first conductive layer 304 is etched to form one or more second trenches 314 and the first conductive layer 113. Prior to etching a portion of the first conductive layer 304 to form the second trenches 314, a portion of the anti-reflective layer 308 is etched to form an anti-reflective layer 116. In some embodiments, the first conductive layer 304 and the anti-reflective layer 308 are etched using a dry etching process. In some embodiments, the second trench 314 is a tubular structure. In some embodiments, the second trench 314 includes a top width d6, a neck width d7, and a bottom width d8, wherein the neck width d7 is less than or equal to the top width d6 and the bottom width d8. In some embodiments, the top width d6 is greater than the bottom width d8. Compared to semiconductor structures where the elements deposited in the trench do not extend into the conductive layer, etching a portion of the first conductive layer 304 to form the second trench 314 can increase the contact area between the first conductive layer 113 and the elements deposited in the second trench 314, thereby reducing the resistance between the first conductive layer 113 and the elements deposited in the second trench 314.

[0041] Referring to Figures 2A and 4C through 4F, in operation 214, one or more first bonding pads 117 are formed in a second trench 314. In some embodiments, forming the first bonding pads 117 in the second trench 314 includes sequentially depositing a first metal layer 316 and a second metal layer 318 in the second trench 314. Specifically, the first metal layer 316 is deposited substantially co-located in the second trench 314 and fills a recess in the first conductive layer 113, and the second metal layer 318 fills the remaining portion of the second trench 314. In some embodiments, after the first metal layer 316 and the second metal layer 318 are sequentially deposited in the second trench 314, the first metal layer 316 and the second metal layer 318 are planarized to form a first bonding pad 117 comprising a first metal layer 118 and a second metal layer 119. In some embodiments, the first metal layer 316 and the second metal layer 318 are deposited by a deposition process such as PVD, sputtering, electroplating, another deposition process, or any suitable combination thereof. In some embodiments, the first metal layer 316 and the second metal layer 318 are planarized by chemical mechanical polishing (CMP). In some embodiments, the first metal layer 316 and the second metal layer 318 are planarized until the top surfaces of the first metal layer 316 and the second metal layer 318 are aligned with the top surface of the inorganic barrier layer 115. In some embodiments, the first metal layer 316 and the second metal layer 318 comprise the same material. In some embodiments, the first metal layer 316 and the second metal layer 318 comprise different materials. In some embodiments, the first metal layer 316 and the second metal layer 318 each comprise TaN, Ta, TiN, Ti, Cu, or a combination thereof. In some embodiments, the grain size of the first metal layer 316 is larger than the grain size of the second metal layer 318. In some embodiments, the grain size of the first metal layer 316 is greater than 100 nm. In some embodiments, the grain size of the first metal layer 316 is between 100 nm and 5000 nm, for example, 100, 200, 400, 600, 800, 1000, 1200, 1400, 1600, 1800, 2000, 2200, 2400, 2600, 2800, 3000, 3200, 3400, 3600, 3800, 4000, 4200, 4400, 4600, 4800, or 5000 nm. In some embodiments, the grain size of the second metal layer 318 is less than 100 nm, for example, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, or 100 nm.Compared to bonding pads consisting only of metal layers with a grain size less than 100 nm, the larger grain size of the first metal layer 316 compared to the second metal layer 318 (less than 100 nm) increases the formation rate of the first bonding pad 117. Compared to semiconductor structures where bonding pads deposited in trenches do not extend into the conductive layer, forming the first bonding pad 117 in the second trench 314 and contacting the first conductive layer 113 increases the contact area between the first conductive layer 113 and the first bonding pad 117, thereby reducing the resistance between the first conductive layer 113 and the first bonding pad 117.

[0042] Figure 5 is a cross-sectional view of the semiconductor structure 400 after operations 202 to 214 are completed. As shown in Figures 5 and 6, the first wafer 110 is formed after the singulation process of the semiconductor structure 400 is performed.

[0043] Figure 7 is a cross-sectional view of the semiconductor structure 500. As shown in Figure 7, in some embodiments, the semiconductor structure 550 is bonded to a carrier 502 via an adhesive layer (not shown) to form the semiconductor structure 500. In some embodiments, the carrier 502 includes Si, ceramic, metal, or the like. In some embodiments, the adhesive layer includes a peelable or easily removable material, such as epoxy resin or other suitable adhesive. Figure 8A is an enlarged view of portion D in Figure 7. Referring to Figures 2B, 7, and 8A, in operation 216, a third dielectric layer 127, one or more second conductive layers 128, a second interconnect layer 126, a first substrate 504, and one or more silicon through-holes 125 are received to form the semiconductor structure 550. The first substrate 504 is formed on the second interconnect layer 126. Silicon through-holes 125 are embedded in the first substrate 504.

[0044] As shown in Figures 2B, 8A, and 8B, in operation 218, the first substrate 504 is etched and polished to expose one or more silicon through-holes 125 to form the first substrate 123. In some embodiments, the first substrate 504 is etched by a dry etching process. In some embodiments, the protrusion height H1 of the silicon through-holes 125 is between 3 micrometers (μm) and 8 μm, for example, 3, 4, 5, 6, 7, or 8 μm.

[0045] Referring to Figures 2B, 8B, and 8C, in operation 220, a second dielectric layer 506 is formed to cover the first substrate 123 and the silicon through-hole 125. In some embodiments, after forming the second dielectric layer 506 to cover the first substrate 123 and the silicon through-hole 125, an inorganic barrier layer 508 is formed on the second dielectric layer 506. In some embodiments, the second dielectric layer 506 and the inorganic barrier layer 508 are formed by a deposition process, such as, but not limited to, CVD, PVD, ALD, LPCVD, another deposition process, or any suitable combination thereof.

[0046] Referring to Figures 2B, 8C, and 8D, in operation 222, the second dielectric layer 506 is etched to form one or more third trenches 510 and a second dielectric layer 122, exposing the silicon through-hole 125. In some embodiments, an inorganic barrier layer 508 is etched to form an inorganic barrier layer 121 before etching the second dielectric layer 506. In some embodiments, the second dielectric layer 506 and the inorganic barrier layer 508 are etched by a dry etching process. In some embodiments, the cross-sectional view of the third trench 510 includes a top width d9 and a bottom width d10. In some embodiments, the top width d9 is greater than or equal to the bottom width d10. In some embodiments, the cross-sectional view of the third trench 510 is trapezoidal or rectangular, but this disclosure is not limited thereto.

[0047] Referring to Figures 2B and 8D through 8G, in operation 224, one or more second bonding pads 124 are formed in the third trench 510. In some embodiments, forming the second bonding pads 124 in the third trench 510 includes sequentially forming a first metal layer 512 and a second metal layer 514 in the third trench 510. Specifically, the first metal layer 512 is deposited co-located in the third trench 510, and the second metal layer 514 fills the remaining portion of the third trench 510. In some embodiments, after sequentially forming the first metal layer 512 and the second metal layer 514 in the third trench 510, the first metal layer 512 and the second metal layer 514 are planarized to form a second bonding pad 124 comprising a first metal layer 130 and a second metal layer 131. In some embodiments, the first metal layer 512 and the second metal layer 514 are formed by a deposition process such as PVD, sputtering, electroplating, another deposition process, or any suitable combination thereof. In some embodiments, the first metal layer 512 and the second metal layer 514 are planarized using CMP. In some embodiments, the first metal layer 512 and the second metal layer 514 are planarized until their top surfaces are aligned with the top surface of the inorganic barrier layer 121. In some embodiments, the first metal layer 512 and the second metal layer 514 comprise the same material. In some embodiments, the first metal layer 512 and the second metal layer 514 comprise different materials. In some embodiments, the first metal layer 512 and the second metal layer 514 each comprise TaN, Ta, TiN, Ti, Cu, or a combination thereof. In some embodiments, the grain size of the first metal layer 512 is larger than the grain size of the second metal layer 514. In some embodiments, the grain size of the first metal layer 512 is greater than 100 nm. In some embodiments, the grain size of the first metal layer 512 is between 100 nm and 5000 nm, for example, 100, 200, 400, 600, 800, 1000, 1200, 1400, 1600, 1800, 2000, 2200, 2400, 2600, 2800, 3000, 3200, 3400, 3600, 3800, 4000, 4200, 4400, 4600, 4800, or 5000 nm. In some embodiments, the grain size of the second metal layer 514 is less than 100 nm, for example, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, or 100 nm. Compared to bonding pads that only include metal layers with a grain size of less than 100 nm, the grain size of the first metal layer 512 is larger than that of the second metal layer 514 (less than 100 nm), which increases the formation speed of the second bonding pad 124.

[0048] As shown in Figure 9, after completing operations 216 to 224, a semiconductor structure 600 is formed. The semiconductor structure 600 includes a semiconductor structure 610 and a carrier 502. The semiconductor structure 610 includes an inorganic barrier layer 121, a second dielectric layer 122, a first substrate 123, a second bonding pad 124, a silicon through-hole 125, a second interconnect layer 126, a third dielectric layer 127, and a second conductive layer 128.

[0049] Figure 10A is a cross-sectional view of semiconductor structure 700. Figure 10B is an enlarged view of portion E in Figure 10A. To simplify the diagram in Figure 10A, some semiconductor elements are shown only in Figure 10B but not in Figure 10A. Referring to Figures 2B, 10A, and 10B, in operation 226, first bonding pads 117 to second bonding pads 124 are bonded. First wafer 110 is also inverted and stacked on semiconductor structure 610 to form semiconductor structure 700. Semiconductor structure 700 includes semiconductor structure 710 and carrier 502. Semiconductor structure 710 includes first wafer 110 and semiconductor structure 610. The bonding temperature of first bonding pad 117 to second bonding pad 124 is between 150°C and 250°C, for example, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, or 250°C. As described above, the first bonding pad 117 and the second bonding pad 124 each include a second metal layer 119 and a second metal layer 131, respectively. Because the grain size of the second metal layer 119 and the second metal layer 131 is small (less than 100 nm), the bonding temperature at which the first bonding pad 117 bonds to the second bonding pad 124 is reduced. Furthermore, when the first bonding pad 117 and the second bonding pad 124 are bonded, the second metal layer 119 of the first bonding pad 117 and the second metal layer 131 of the second bonding pad 124 are fused together. Additionally, the bottom width d5 ​​of the second bonding pad 124 is greater than the bottom width d11 of the first bonding pad 117, which eliminates the need for precise alignment between the first bonding pad 117 and the second bonding pad 124.

[0050] Figure 11A is a cross-sectional view of semiconductor structure 800. Figure 11B is an enlarged view of portion F in Figure 11A. To simplify the diagram in Figure 11A, some semiconductor elements are shown only in Figure 11B but not in Figure 11A. In another embodiment, a first wafer 140 is stacked on semiconductor structure 610 and a first wafer 110 is stacked on the first wafer 140 to form semiconductor structure 800. Semiconductor structure 800 includes semiconductor structure 810 and carrier 502. Semiconductor structure 810 includes first wafer 110, first wafer 140, and semiconductor structure 610. That is, in operation 226, first bonding pads 150 and 117 are bonded to second bonding pads 124 and 143, respectively. The formation of the first wafer 140 includes the following processes. The substrate 111, first interconnect layer 146, first conductive layer 147, first dielectric layer 148, anti-reflective layer 149, first bonding pad 150, and inorganic barrier layer 151 are formed with reference to the aforementioned operations 202 to 214. After performing operation 202, the substrate 111 is etched to form one or more trenches (not shown), and silicon through-holes 145 are subsequently formed in the trenches. Next, after performing operation 214, the formed semiconductor structure is inverted to facilitate subsequent operations. Subsequently, the inorganic barrier layer 141, second dielectric layer 142, second bonding pad 143, and substrate 144 are formed with reference to the aforementioned operations 218 to 224. For embodiments of the inorganic barrier layer 141, second dielectric layer 142, second bonding pad 143, substrate 144, silicon through-hole 145, first interconnect layer 146, first conductive layer 147, first dielectric layer 148, anti-reflection layer 149, first bonding pad 150, and inorganic barrier layer 151, please refer to the aforementioned embodiments of the inorganic barrier layer 121, second dielectric layer 122, second bonding pad 124, first substrate 123, silicon through-hole 125, second interconnect layer 126, first conductive layer 113, first dielectric layer 114, anti-reflection layer 116, first bonding pad 117, and inorganic barrier layer 115. For embodiments of the semiconductor structure 800, please refer to the aforementioned embodiments of the semiconductor structure 700. It is worth noting that any number of first wafers 140 can be stacked between the semiconductor structure 610 and the first wafers 110, for example, two, three, four, five, etc. Furthermore, semiconductor structure 800 includes all the advantages described in the aforementioned semiconductor structure 700.

[0051] Figures 12A to 13 are cross-sectional views illustrating intermediate stages of manufacturing a semiconductor package structure 1000 according to various embodiments of this disclosure. Referring to Figures 10A, 11A, 12A, and 12B, after operations 202 to 226 are completed, the outer surfaces of the first wafer 110 / first wafer 140 and the top surface of the second wafer 120 are surrounded by molding materials 904 and 906. In some embodiments, molding materials 904 and 906 comprise polymers, epoxy resins, resins, or other suitable materials. Semiconductor structures 710 and 810 are then debonded from the carrier 502, and one or more conductive members 902 are subsequently disposed on the bottom of the second conductive layer 128 in the second wafer 120. Subsequently, a dicing process is performed on semiconductor structures 710 and 810 to form semiconductor structures 900A and 900B. In some embodiments, the conductive component 902 comprises a metallic material, such as tin (Sn), Cu, nickel (Ni), gold (Au), or other suitable metallic materials.

[0052] Figure 13 illustrates an embodiment of the semiconductor package structure 1000. Referring to Figure 13, after forming the semiconductor structure 900B, the semiconductor structure 900B is disposed on and connected to the interposer 1002, and a logic die 1004 is disposed on the interposer 1002 and connected to the interposer 1002 via one or more conductive members 1006 at the bottom of the logic die 1004. Subsequently, the interposer 1002 is disposed on a substrate (not shown) and connected to the substrate via silicon vias 1012 in the interposer 1002 and one or more conductive members 1008 at the bottom of the interposer 1002 to form the semiconductor package structure 1000. In some embodiments, the semiconductor structure 900B in the semiconductor package structure 1000 may be replaced by a semiconductor structure 900A or other semiconductor structures. In some embodiments, the semiconductor structure 900A / semiconductor structure 900B is a high bandwidth memory (HBM). In some embodiments, the logic die 1004 includes, for example, but not limited to, an application-specific integrated circuit (ASIC), a central processing unit (CPU), or a graphics processing unit (GPU). In some embodiments, the interposer 1002 includes a substrate 1010, silicon through-holes 1012 embedded in the substrate 1010, and an interconnect layer 1014 disposed on the silicon through-holes 1012, with a conductive member 1008 disposed below the silicon through-holes 1012. For embodiments of the conductive member 1008, the substrate 1010, and the interconnect layer 1014, please refer to the aforementioned embodiments of the conductive member 902, the substrate (substrate 111 / first substrate 123 / substrate 144), and the interconnect layer (first interconnect layer 112 / second interconnect layer 126 / first interconnect layer 146).

[0053] In summary, this disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure. In the semiconductor structure, the bonding pad extends into the conductive layer, increasing the contact area between them and thereby reducing the resistance between the conductive layer and the bonding pad. In some embodiments, compared to bonding pads that only include a metal layer with a grain size of less than 100 nm, the larger grain size of the first metal layer compared to the larger grain size of the second metal layer (less than 100 nm) increases the bonding pad formation speed. Furthermore, the grain size of the second metal layer of both the first and second bonding pads is less than 100 nm, which reduces the bonding temperature at which the first bonding pad bonds to the second bonding pad.

[0054] Although this disclosure has been described in considerable detail with reference to certain embodiments, other embodiments may also be possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments included herein.

[0055] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from its scope or spirit. In view of the foregoing, this disclosure is intended to cover modifications and variations of this disclosure that fall within the scope of the appended patent applications.

[0056] 100A, 100B, 300, 400, 500, 550, 600, 610, 700, 710, 800, 810, 900A, 900B: Semiconductor Structure 110, 140: First chip 111, 144, 1010: Substrate 112, 146: First interconnection layer 112D, 126D, 146D: Dielectric layer 112V, 126V, 146V: Conductive vias 112L, 126L, 146L: Conductors 113, 147, 304: First conductive layer 114, 148, 306: First dielectric layer 115, 121, 141, 151, 310, 508: Inorganic barrier layer 116, 149, 308: Anti-reflective layer 117, 150: First joint pad 118, 130, 152, 154, 316, 512: First metal layer 119, 131, 153, 155, 318, 514: Second metal layer 120: Second chip 122, 142, 506: Second dielectric layer 123, 504: First substrate 124, 143: Second joint pad 125, 145, 1012: Silicon perforation 126: Second Interconnect Layer 127: Third dielectric layer 128: Second conductive layer 129: Interface 200: Method 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, 226: Operations 312: First trench 314: Second trench 502: Carrier 510: Third trench 902, 1006, 1008: Conductive components 904, 906: Molding materials 1000: Semiconductor Packaging Structure 1002: Intermediary Layer 1004: Logic die 1014: Interconnection Layer A, B, C, D, E, F: Part d1, d4, d6, d9: Top width d2: Middle width d3, d5, d8, d10: Bottom width d7: Neck width d11: Width H1: Highlight

[0057] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor structure, comprising: A first chip includes: a first interconnect layer; a first conductive layer disposed on the first interconnect layer; a first dielectric layer covering the first conductive layer; a first bonding pad embedded in the first dielectric layer and extending into the first conductive layer; and an anti-reflective layer disposed between the first conductive layer and the first dielectric layer and on the first conductive layer.

2. The semiconductor structure as claimed in claim 1, wherein the first bonding pad includes a first metal layer and a second metal layer, and the first metal layer surrounds the second metal layer.

3. The semiconductor structure as described in claim 1, wherein a cross-section of the first bonding pad includes: One top width; A bottom width, wherein the top width is greater than the bottom width; And a middle width, which is smaller than the top width and the bottom width.

4. The semiconductor structure as described in claim 1, further comprising: A second wafer is disposed on the first wafer, wherein the second wafer includes: a second dielectric layer; a substrate disposed on the second dielectric layer; a second bonding pad embedded in the second dielectric layer and bonded to the first bonding pad; and a silicon via embedded in the second dielectric layer and the substrate and in contact with the second bonding pad.

5. The semiconductor structure as claimed in claim 4, wherein a bonding interface between the first bonding pad and the second bonding pad is substantially flat.

6. The semiconductor structure as claimed in claim 4, wherein the second bonding pad includes a first metal layer and a second metal layer, and the first metal layer surrounds the second metal layer.

7. The semiconductor structure as described in claim 4, wherein a cross-section of the second bonding pad includes: One top width; And a bottom width that is greater than or equal to the top width.

8. A method for manufacturing a semiconductor structure, comprising: A first conductive layer is formed on a first interconnect layer; An anti-reflective layer is formed on the first conductive layer; A first dielectric layer is formed on the first conductive layer and the first interconnect layer; the first dielectric layer is etched to form a first trench on the first conductive layer; a portion of the anti-reflective layer is etched; a portion of the first conductive layer is etched to form a second trench; And to form a first bonding pad in the second groove.

9. The method of manufacturing a semiconductor structure as claimed in claim 8, wherein forming the first bonding pad in the second trench includes sequentially depositing a first metal layer and a second metal layer in the second trench.

10. The method of manufacturing a semiconductor structure as claimed in claim 9, wherein a grain size of the first metal layer is larger than a grain size of the second metal layer.

11. The method of manufacturing a semiconductor structure as described in claim 8, further comprising: Receives a first substrate and a silicon through-hole embedded in the first substrate; The first substrate is etched to expose the silicon via; A second dielectric layer is formed to cover the first substrate and the silicon via; the second dielectric layer is etched to form a third trench to expose the silicon via; a second bonding pad is formed in the third trench; and the first bonding pad is bonded to the second bonding pad.

12. The method of manufacturing a semiconductor structure as claimed in claim 11, wherein forming the second bonding pad in the third trench includes sequentially forming a first metal layer and a second metal layer in the third trench.

13. The method of manufacturing a semiconductor structure as described in claim 12, wherein a grain size of the first metal layer is larger than a grain size of the second metal layer.

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