Semiconductor device

Abstract

A channel stopper electrode (52) and an n+-type channel stopper region (53) are respectively provided spaced apart from an outermost peripheral FLR (41) and an outermost peripheral FLR (41) outside a voltage-withstand structure (40). The n+-type channel stopper region (53) faces an inner end part (52a) of the channel stopper electrode (52) in a depth direction Z with an interlayer insulating film (21) therebetween. The width (L2) of an inner portion (53-1) of the n+-type channel stopper region (53) further inward than the inner end part (52a) of the channel stopper electrode (52) is less than or equal to half the distance (L1) between the channel stopper electrode (52) and one of the outermost peripheral FP (42) and the outermost peripheral FLR (41) of the voltage-withstand structure (40). The depth (d2) of the n+-type channel stopper region (53) is shallower than the depth (d1) of the FLR (41). Thus, a predetermined breakdown voltage of the semiconductor device (10) can be stably secured.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] In conventional semiconductor devices, a predetermined breakdown voltage is ensured by providing a predetermined breakdown voltage structure in an edge termination region surrounding the periphery of the active region and alleviating the electric field applied to the main junction (pn junction) of the active region when reverse bias is applied. Also, a channel stopper structure is provided at the outermost periphery of the semiconductor substrate to prevent the generation of a parasitic channel due to the wiring potential on the front surface of the semiconductor substrate, thereby improving the reliability of the semiconductor device (see, for example, Patent Documents 1 to 5 listed below).

[0003] International Publication No. 2013 / 132568 Patent No. 6668687 International Publication No. 2014 / 155565 JP 2019-087730 A JP 2016-134411 A

[0004] Conventionally, a breakdown voltage structure and a channel stopper structure are designed based on the allowable limit values ​​of the amount of positive charge and negative charge accumulated in the protective insulating film on the semiconductor substrate in the edge termination region, but in the above-mentioned Patent Documents 1 to 4, there is a risk that the breakdown voltage of the edge termination region will be significantly reduced due to the adverse effects of negative charge. Patent Document 5 does not disclose a channel stopper structure equipped with a channel stopper electrode.

[0005] SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, an object of the present invention is to provide a semiconductor device that can stably ensure a predetermined breakdown voltage.

[0006] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features: A semiconductor substrate is provided with an active region and a termination region surrounding the periphery of the active region. A first semiconductor region of a first conductivity type is provided within the semiconductor substrate, extending from the active region to the termination region. A second semiconductor region of a second conductivity type is provided in the active region between the front surface of the semiconductor substrate and the first semiconductor region. A vertical element structure is provided in the active region, in which current flows between both main surfaces of the semiconductor substrate through a pn junction between the second semiconductor region and the first semiconductor region. An insulating layer covers the front surface of the semiconductor substrate in the termination region. A third semiconductor region of a second conductivity type is provided in the termination region between the front surface of the semiconductor substrate and the first semiconductor region. A breakdown voltage structure includes the third semiconductor region and surrounds the periphery of the active region. A channel stopper electrode is provided on the insulating layer, outside the breakdown voltage structure. The channel stopper electrode contacts the front surface of the semiconductor substrate through a contact hole in the insulating layer. A fourth semiconductor region of the first conductivity type is provided between the first semiconductor region and the front surface of the semiconductor substrate, between the contact hole and the third semiconductor region, and spaced apart from the third semiconductor region. The fourth semiconductor region faces an inner end of the channel stopper electrode via the insulating layer. The fourth semiconductor region has a higher impurity concentration than the first semiconductor region.

[0007] Furthermore, in the semiconductor device according to the present invention, in the above-described invention, the impurity concentration distribution of the fourth semiconductor region is a Gaussian distribution in which the impurity concentration decreases from the depth position of the peak concentration toward the front surface side and the back surface side of the semiconductor substrate.

[0008] In addition, in the semiconductor device according to the present invention, in the above-mentioned invention, the distance from the depth position of the peak concentration in the fourth semiconductor region to the front surface of the semiconductor substrate is not more than half width at half maximum of the impurity concentration distribution.

[0009] In addition, in the semiconductor device according to the present invention, in the above-described invention, a first depth position that is deeper on the back surface side of the semiconductor substrate from the depth position of the peak concentration of the fourth semiconductor region by half width at half maximum of the impurity concentration distribution is shallower than the depth of the third semiconductor region.

[0010] In addition, in the semiconductor device according to the present invention, the first depth position of the fourth semiconductor region is 10% to 60% of the depth of the third semiconductor region.

[0011] Furthermore, in the semiconductor device according to the present invention, in the above-described invention, the fourth semiconductor region has a first portion that is located inside an inner end of the channel stopper electrode, and a second portion that faces the channel stopper electrode via the insulating layer, excluding the first portion.

[0012] Furthermore, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the width of the first portion of the fourth semiconductor region is equal to or less than half the distance from the channel stopper electrode to the third semiconductor region in a direction parallel to the front surface of the semiconductor substrate.

[0013] In the semiconductor device according to the present invention, in the above-described invention, the breakdown voltage structure includes a plurality of the third semiconductor regions floating in potential, and metal electrodes, the same number as the third semiconductor regions, provided on the front surface of the semiconductor substrate and each of which is floating in potential, and the width of the first portion of the fourth semiconductor region is equal to or less than half the distance from the channel stopper electrode to the outermost terminal of the outermost third semiconductor region and the outermost terminal of the outermost metal electrode in a direction parallel to the front surface of the semiconductor substrate.

[0014] In addition, in the semiconductor device according to the present invention, the width of the second portion of the fourth semiconductor region is 40% to 60% of the width of the fourth semiconductor region.

[0015] In addition, the semiconductor device according to the present invention is characterized in that it further includes a fifth semiconductor region provided between the front surface of the semiconductor substrate and the first semiconductor region outside the fourth semiconductor region, the fifth semiconductor region being in contact with the channel stopper electrode via the contact hole, and the first depth position of the fourth semiconductor region being shallower than a depth of the fifth semiconductor region.

[0016] The semiconductor device according to the present invention is the above-described one, further comprising a fifth semiconductor region provided between the front surface of the semiconductor substrate and the first semiconductor region outside the fourth semiconductor region, the fifth semiconductor region being in contact with the channel stopper electrode via the contact hole, the fourth semiconductor region being located closer to the fifth semiconductor region than the third semiconductor region.

[0017] In addition, in the semiconductor device according to the present invention, the fifth semiconductor region is of the second conductivity type.

[0018] In addition, the semiconductor device according to the present invention further includes a sixth semiconductor region of the first conductivity type provided between the second semiconductor region and the first semiconductor region, the sixth semiconductor region having a higher impurity concentration than the first semiconductor region, and the impurity concentration distribution of the fourth semiconductor region is the same as the impurity concentration distribution of the sixth semiconductor region.

[0019] According to the above-described invention, the outward extension of the depletion layer directly below the inner end of the channel stopper electrode is suppressed, and electric field concentration in that portion is suppressed, thereby improving the breakdown voltage of the termination region even when negative charges are accumulated in the insulating layer.

[0020] The semiconductor device according to the present invention has the effect of stably ensuring a predetermined breakdown voltage.

[0021] FIG. 1 is a plan view showing the layout of a semiconductor device according to an embodiment as viewed from the front surface side of a semiconductor substrate. FIG. 2 is a plan view showing an enlarged view of a portion surrounded by a rectangular frame A in FIG. 1. FIG. 3 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment. FIG. 4 is a cross-sectional view showing another example of the structure of a semiconductor device according to an embodiment. FIG. 5 is a cross-sectional view showing another example of the structure of a semiconductor device according to an embodiment. FIG. 6 is a cross-sectional view showing an enlarged view of the active region of FIGS. 3 to 5. FIG. 7 is a cross-sectional view showing an enlarged view of the active region of FIGS. 3 to 5. FIG. 8 is a cross-sectional view showing the structure of an edge termination region of a semiconductor device according to a reference example.

[0022] Preferred embodiments of a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0023] (Summary) As a result of extensive research, the inventors have discovered the following. Figure 8 is a cross-sectional view showing the structure of an edge termination region of a semiconductor device according to a reference example. The semiconductor device 110 according to the reference example shown in Figure 8 is a vertical IGBT (Insulated Gate Bipolar Transistor) having an active region 101 and an edge termination region 102 surrounding the active region 101 in a semiconductor substrate 106 made of silicon (Si) as a semiconductor material. A MOS gate (insulated gate made of metal-oxide-semiconductor) 120 having a trench gate structure typical of IGBTs is disposed in the active region 101.

[0024] In the edge termination region 102, a gate runner portion 103, a breakdown voltage structure portion 104, and a channel stopper portion 105 are arranged concentrically from the inside to surround the periphery of the active region 101. In the gate runner portion 103, a gate runner 130 (a gate polysilicon wiring layer 134 and a gate metal wiring layer 135) is provided on the front surface of the semiconductor substrate 106 via an insulating layer 133. Directly below the gate runner 130, a gate metal wiring layer 135 is formed on the front surface of the semiconductor substrate 106. - A p-type well region 131 is provided across the entire area of ​​the gate runner portion 103 between the gate runner portion 103 and the p-type drift region 111 .

[0025] Breakdown withstanding structure section 104 is provided with a field limiting ring (FLR) 141 and a field plate (FP) 142 as breakdown withstanding structure 140. Breakdown withstanding structure 140 is designed in consideration of variations in the manufacturing process for each allowable limit value (allowable range of surface charge amount) of the amount of positive charge and the amount of negative charge that accumulates over time due to high-temperature, high-voltage stress in the insulating layers (insulating layer 133, interlayer insulating film 121, and surface protective film 123) on the front surface of semiconductor substrate 106 in edge termination region 102 and on FP 142.

[0026] The FLR 141 is a p-type region at a floating potential (potentially floating), and is connected to the front surface of the semiconductor substrate 106 and the n-type region. - A plurality of FLRs 141 are provided between the gate runner portion 103 and the gate metal wiring layer 135, spaced apart from the p-type well region 131. The plurality of FLRs 141 are provided spaced apart from one another and concentrically surround the periphery of the p-type well region 131. The FPs 142 are metal electrodes at floating potential that contact the FLRs 141, and are provided on the front surface of the semiconductor substrate 106, spaced apart from the gate metal wiring layer 135, in the same number as the FLRs 141. The plurality of FPs 142 are provided spaced apart from one another and concentrically surround the periphery of the gate runner portion 103.

[0027] The channel stopper section 105 is provided with a p-type channel stopper region 151 and a channel stopper electrode 152 as a channel stopper structure 150. The p-type channel stopper region 151 is in contact with the front surface of the semiconductor substrate 106 and the n-type- The FP 142 is provided between the semiconductor substrate 106 and the p-type drift region 111, at a distance from the FLR 141, and surrounds the periphery of the FLR 141. The channel stopper electrode 152 is provided at a distance from the FP 142, and surrounds the periphery of the breakdown withstanding structure 104. The channel stopper electrode 152 is a metal electrode on the outermost periphery on the front surface of the semiconductor substrate 106, and is in contact with the p-type channel stopper region 151 directly below.

[0028] Generally, n - By ion implanting n-type impurities such as phosphorus (P) into the front surface of n-type semiconductor substrate 106, p-type regions such as FLR 141 and p-type channel stopper region 151 are formed in edge termination region 102, thereby controlling the electric field distribution in edge termination region 102. - n-type impurity concentration (n - Since the n-type impurity concentration of the n-type drift region 111 is not adjusted, the allowable range of the surface charge amount is determined according to the resistivity of the silicon single crystal of the semiconductor substrate 106, and the breakdown voltage structure 104 is designed with the allowable range of the surface charge amount in mind, taking into account variations in the manufacturing process.

[0029] The inventors have confirmed that, when a simulation is performed under predetermined conditions for this reference structure (semiconductor device 110), an electric field concentrates directly below inner end 152a of channel stopper electrode 152, resulting in a significant reduction in the breakdown voltage of edge termination region 102. The predetermined conditions under which the breakdown voltage of edge termination region 102 is significantly reduced are when breakdown withstand structure 140 is set to a condition in which the depletion layer is likely to extend outward when the main junction of active region 101 is reverse biased with the IGBT in the off state, and negative charges are accumulated in the insulating layer on the front surface of semiconductor substrate 106 in edge termination region 102 and on FP 142.

[0030] For example, the wider the width of the outermost (outermost) FLR 141, the more easily the depletion layer extends outward. Furthermore, the depletion layer also extends outward due to the adverse effects of negative charge. As a result of simulating the breakdown voltage of the edge termination region 102 under conditions where it is adversely affected by negative charge, the inventors have confirmed that as the width of the outermost FLR 141 is increased, a change point occurs where the breakdown point (the point where reach-through occurs due to impact ionization) moves from the active region 101 to directly below the inner end 152 a of the channel stopper electrode 152, and that the wider the width of the outermost FLR 141, the more the breakdown voltage of the edge termination region 102 decreases.

[0031] Furthermore, since the design conditions for being less susceptible to the adverse effects of positive charges and the design conditions for being less susceptible to the adverse effects of negative charges are contradictory, it is difficult to design the breakdown voltage structure 140 so that it is not adversely affected by both positive and negative charges. Therefore, the problem to be solved in this embodiment is to provide a semiconductor device with high long-term reliability by suppressing a decrease in breakdown voltage caused by surface charges that accumulate over time in the insulating layer on the front surface of the semiconductor substrate in the edge termination region and on the FP due to high-temperature, high-voltage stress caused by long-term operation of the semiconductor device, thereby stably ensuring a predetermined breakdown voltage.

[0032] (Embodiment) The structure of a semiconductor device according to an embodiment will be described. Fig. 1 is a plan view showing the layout of a semiconductor device according to an embodiment as viewed from the front surface side of a semiconductor substrate. In Fig. 1, the boundary between an active region 1 and an edge termination region 2 (gate runner portion 3) and the boundary between the gate runner portion 3 and a breakdown voltage structure portion 4 are indicated by relatively fine dashed lines, and the inner end portion 52a of a channel stopper electrode 52 is indicated by relatively coarse dashed lines. + The mold channel stopper region 53 is hatched.

[0033] 2 is an enlarged plan view of the area enclosed by the rectangular frame A in FIG. 1. FIG. 2 shows the layout of the gate runner portion 3, the breakdown voltage structure portion 4, and the channel stopper portion 5. In FIG. 2, the p-type well region 31 and the n-type well region 32 are +The end of the p-type channel stopper region 53 is indicated by a relatively coarse dashed line, the inner end of the p-type channel stopper region 51 is indicated by a relatively fine dashed line, the FLR 41 is indicated by a thick line, and the emitter electrode 22, the gate metal wiring layer 35, the FP 42, and the channel stopper electrode 52 are all hatched in the same manner.

[0034] FIG. 3 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment. FIGS. 4 and 5 are cross-sectional views showing another example of the structure of a semiconductor device according to an embodiment. FIGS. 6 and 7 are cross-sectional views showing enlarged views of the active region structures of FIGS. 3 to 5. FIGS. 3 to 5 each show a different structural example of the edge termination region 2, and the MOS gate 20 is simplified. The cross-sectional structure of the MOS gate 20 is shown enlarged in FIGS. 6 and 7. Also, in FIGS. 3 to 5, some FLRs 41 and FPs 42 are omitted, and fewer are shown than in FIG. 2.

[0035] A semiconductor device 10 according to an embodiment shown in FIGS. 1 to 7 is a vertical IGBT having an active region 1 and an edge termination region 2 surrounding the active region 1 in a semiconductor substrate (semiconductor chip) 6 made of Si as a semiconductor material. The active region 1 is a region through which a main current (drift current) flows when the IGBT is in an on-state. The active region 1 occupies most of the area (surface area) of the semiconductor substrate 6. The active region 1 has a substantially rectangular planar shape that is substantially the same as the semiconductor substrate 6, and is located approximately in the center of the semiconductor substrate 6.

[0036] A plurality of unit cells (functional units of an element) of the IGBT having the same structure (element structure) are arranged adjacent to each other in the active region 1. Each unit cell of the IGBT has a p-type base region (second semiconductor region) 12, an n-type base region (second semiconductor region) 13, and a n-type base region (second semiconductor region) 14 on the front surface side of the semiconductor substrate 6. + type emitter region 13, p + The MOS gate 20 has a general trench gate structure consisting of a contact region 14, a trench 15, a gate insulating film 16, and a gate electrode 17. The MOS gate 20 is connected to the front surface of the semiconductor substrate 6 and the n-type contact region 14. - It is provided between the first semiconductor region 11 and the second semiconductor region 12 .

[0037] n -In the semiconductor substrate 6, diffusion regions (p-type base region 12, n-type base region 13) formed by ion implantation into the semiconductor substrate 6 are + type emitter region 13, p + type contact region 14, n-type FS region 18, p + collector region 19, p-type well region 31, and outer peripheral p + the p-type contact region 32, the FLR 41, the p-type channel stopper region 51, and the n + The part excluding the type channel stopper region 53) is n - n-type drift region 11. - The impurity concentration of the type drift region 11 is approximately the same from the active region 1 to the edge of the semiconductor substrate 6 (chip edge).

[0038] The p-type base region 12 is connected to the front surface of the semiconductor substrate 6 over the entire active region 1. - Between the n-type drift region 11, - The n-type drift region 11 is provided in contact with the n-type drift region 11. + type emitter region 13 and p + The n-type contact regions 14 are selectively provided between the front surface of the semiconductor substrate 6 and the p-type base region 12. - The p-type drift region 11 (or the CS region 11a, which will be described further below), the p-type base region 12, and the n-type + The emitter region 13 contacts the gate insulating film 16 on the sidewall of the trench 15 .

[0039] n + type emitter region 13 and p + The contact region 14 is in ohmic contact with the emitter electrode 22 on the front surface of the semiconductor substrate 6 and is in ohmic contact with the emitter electrode 22 on the bottom surface (p + The n-type collector region 19 (the end face on the side of the n-type collector region 19) contacts the p-type base region 12. + type emitter region 13 and p + The mold contact regions 14 are provided alternately and repeatedly adjacent to each other in the longitudinal direction (first direction X described later) of the trenches 15 between adjacent trenches 15. That is, the cross-sectional structure shown in FIG. 6 and the cross-sectional structure shown in FIG. 7 are alternately and repeatedly arranged in the first direction X.

[0040] p +The contact region 14 may contact the gate insulating film 16 on the sidewall of the trench 15. The outer periphery of the active region 1 (near the boundary with the edge termination region 2) is provided with a p + Only the n-type contact region 14 is provided. + The active region 1 is located inside the longitudinal ends of the trench 15 (toward the center of the semiconductor substrate 6) and inside the outermost trench 15 (toward the end of the semiconductor substrate 6) in the lateral direction of the trench 15 (in a second direction Y that is parallel to the front surface of the semiconductor substrate 6 and perpendicular to the first direction X).

[0041] That is, between several (for example, two or three) adjacent trenches 15 from the outside in the lateral direction of the trenches 15, p + Only the contact region 14 is disposed between the remaining adjacent trenches 15. + The n-type contact region 14 is disposed in the longitudinal direction of the trench 15. + type emitter region 13 and p + The mold contact regions 14 are alternately and repeatedly arranged.

[0042] The outer periphery of the active region 1 is + By providing only the contact region 14, the outer periphery p of the edge termination region 2 + Similarly to the contact between the type contact region 32 and the emitter electrode 22, the p + The hole current generated in the edge termination region 2 when the IGBT is turned off can be extracted from the contact between the type contact region 14 and the emitter electrode 22. + The p-type contact region 14 may not be provided. + Instead of the p-type contact region 14 , the p-type base region 12 reaches the front surface of the semiconductor substrate 6 .

[0043] p-type base region 12 and n - Between the n-type drift region 11 and the n-type drift region 12, - The same conductivity type as the n-type drift region 11 and -A carrier storage (CS) region (sixth semiconductor region) 11a having a higher impurity concentration than the n-type drift region 11 may be provided. This n-type CS region 11a acts as a barrier to minority carriers (positive holes), and the n-type CS region 11a directly below the p-type base region 12 (p + Since minority carriers are accumulated in the collector region 19 side, the current density between the collector and the emitter is increased, and the conductivity modulation effect is enhanced.

[0044] The trench 15 is + type emitter region 13 (or even p + through the p-type contact region 14), the p-type base region 12 and the CS region 11a; - The trench 15 extends in a stripe shape in a first direction X parallel to the front surface of the semiconductor substrate 6. A gate electrode 17 made of polysilicon (poly-Si) is provided inside the trench 15 via a gate insulating film 16. An interlayer insulating film (insulating layer) 21 is provided on the entire front surface of the semiconductor substrate 6 so as to cover the gate electrode 17. The trench 15 does not have to penetrate the CS region 11a. In this case, the trench 15 reaches the CS region 11a.

[0045] The gate insulating film 16 may extend from the inner wall of the trench 15 between the interlayer insulating film 21 and the front surface of the semiconductor substrate 6. The emitter electrode 22 is provided on the interlayer insulating film 21 over substantially the entire active region 1, and is connected to the n-type semiconductor substrate 6 via a contact hole 21 a in the interlayer insulating film 21. + type emitter region 13 and p + The emitter electrode 22 is in ohmic contact with the p-type contact region 14 and is electrically connected to these regions and the p-type base region 12. The portion of the emitter electrode 22 exposed in the opening of the surface protection film (insulating layer) 23 such as a passivation film functions as an emitter pad (electrode pad).

[0046] The back surface of the semiconductor substrate 6 and the n - Between the n-type drift region 11 and the n-type field stop (FS) region 18 common to a plurality of unit cells of the IGBT, and the p-type field stop (FS) region 18 and the p-type drift region 11 are formed over the entire area of ​​the semiconductor substrate 6. + A collector region 19 is provided.+ The p-type collector region 19 is provided between the rear surface of the semiconductor substrate 6 and the n-type FS region 18. The n-type FS region 18 may not be provided. The collector electrode 24 is provided on the entire rear surface of the semiconductor substrate 6. + ohmic contact with the p-type collector region 19, + The collector region 19 is electrically connected to the collector region 19 .

[0047] The edge termination region 2 is a region between the active region 1 and the edge (chip edge) of the semiconductor substrate 6, and surrounds the periphery of the active region 1 in a substantially rectangular shape. In the edge termination region 2, a gate runner portion 3, a breakdown voltage structure portion 4, and a channel stopper portion 5 are arranged concentrically from the inside to surround the periphery of the active region 1. The gate runner portion 3 is adjacent to the outside of the active region 1. In the gate runner portion 3, the front surface of the semiconductor substrate 6 and the n - A p-type well region 31 is provided across the entire area of ​​the gate runner portion 3 between the gate runner portion 3 and the p-type drift region 11 .

[0048] The p-type well region 31 surrounds the periphery of the active region 1 in a substantially rectangular shape, extends inward to reach the longitudinal ends of the trenches 15, and reaches the outer sidewalls of the outermost trenches 15 in the lateral direction of the trenches 15. The p-type well region 31 is directly connected or electrically connected to the p-type base region 12 of the active region 1. The depth of the p-type well region 31 may be deeper than the depth of the p-type base region 12 and the depth of the trenches 15, for example. A peripheral p + A mold contact region 32 may be provided.

[0049] In the gate runner portion 3, the emitter electrode 22 is connected to the outer periphery p through a contact hole 21b in the interlayer insulating film 21. + The emitter electrode 22 is in ohmic contact with the p-type contact region 32 and is electrically connected to this region and the p-type well region 31. + The contact with the n-type contact region 32 is made by the n-type contact region 32 of the edge termination region 2 when the IGBT is turned off. -The contact hole 21b functions to extract minority carriers (holes) generated in the type drift region 11 to the emitter electrode 22. The contact hole 21b surrounds the periphery of the active region 1 in a substantially rectangular shape.

[0050] Furthermore, in the gate runner portion 3, a gate polysilicon wiring layer 34 and a gate metal wiring layer 35 constituting a gate runner 30 are provided outside the contact hole 21b. The gate runner 30 (the gate polysilicon wiring layer 34 and the gate metal wiring layer 35) surrounds the periphery of the active region 1 in a substantially rectangular shape. The gate polysilicon wiring layer 34 is provided on the front surface of the semiconductor substrate 6 via an insulating layer 33. The gate polysilicon wiring layer 34 faces the p-type well region 31 via the insulating layer 33.

[0051] The insulating layer 33 is provided between the front surface of the semiconductor substrate 6 and the interlayer insulating film 21. The insulating layer 33 is a field oxide film or a stacked film of the gate insulating film 16 and a field oxide film, and extends, for example, to the edge of the chip. The gate polysilicon wiring layer 34 is covered with the interlayer insulating film 21. The inner end (inner peripheral end) of the gate polysilicon wiring layer 34 may face the emitter electrode 22 in the depth direction Z via the interlayer insulating film 21. The gate electrodes 17 of all MOS gates 20 are connected to the gate polysilicon wiring layer 34.

[0052] The gate polysilicon wiring layer 34 is electrically connected to a gate pad (electrode pad: not shown) in a portion not shown. The gate pad is provided on the interlayer insulating film 21 on the front surface of the semiconductor substrate 6 in the active region 1 or the gate runner portion 3, away from the emitter electrode 22. The gate metal wiring layer 35 is in contact with the gate polysilicon wiring layer 34 via a contact hole 21c in the interlayer insulating film 21. The contact hole 21c surrounds the periphery of the active region 1 in a substantially rectangular shape.

[0053] The breakdown voltage structure 4 is adjacent to the outside of the gate runner 3. The breakdown voltage structure 4 extends from the outer edge (peripheral edge) of the p-type well region 31 to the n-type well region 32 (described later). +The edge termination region 2 extends to the inner edge (inner peripheral edge) 53 a of the active region 1 main junction. The breakdown voltage structure 4 is provided with a predetermined breakdown voltage structure 40. The breakdown voltage structure 40 adjusts the electric field distribution in the edge termination region 2 by facilitating the outward extension of the depletion layer that extends outward from the main junction of the active region 1 when the main junction of the active region 1 is reverse biased.

[0054] Breakdown voltage structure 40 may be set under conditions (design conditions susceptible to the adverse effects of negative charges) that make edge termination region 2 susceptible to a decrease in breakdown voltage due to negative charges that accumulate in the insulating layers (insulating layer 33, interlayer insulating film 21, and surface protective film 23) on the front surface of semiconductor substrate 6 in edge termination region 2 and on FP 42 due to high-temperature, high-voltage stress caused by long-term operation of semiconductor device 10. The design conditions susceptible to the adverse effects of negative charges are conditions that make it easy for a depletion layer to extend outward from active region 1 when the main junction of active region 1 is reverse-biased.

[0055] An example of a design condition that is susceptible to the adverse effects of negative charge is when the width (width from the inside to the outside) of the FLR 41 is set to be wide (e.g., greater than approximately 3.0 μm). The design condition that is susceptible to the adverse effects of negative charge contradicts the design condition that is susceptible to the adverse effects of positive charge. Therefore, by making the breakdown voltage structure 40 susceptible to the adverse effects of negative charge, it is possible to reduce the adverse effects of positive charge accumulated in the insulating layer on the front surface of the semiconductor substrate 6 in the edge termination region 2 and on the FP 42.

[0056] The main junction of the active region 1 is a p-type region (p-type base region 12) fixed to the potential of the emitter electrode 22 and an n-type - The active region 1 has a pn junction with the emitter electrode 22 drift region 11. The main junction edge of the active region 1 (a pn junction fixed to the potential of the emitter electrode 22) is extended to the boundary between the gate runner 3 and the breakdown voltage structure 4 by the p-type well region 31 of the gate runner 3. The breakdown voltage is the limit voltage at which the drain-source voltage does not increase any further even if the drain-source current increases due to an avalanche breakdown at the pn junction.

[0057] The breakdown voltage structure 40 includes, for example, a field limiting ring (FLR: third semiconductor region) 41, which is a p-type region with a floating potential, and a field plate (FP) 42, which is a metal electrode with a floating potential. The FLR 41 is connected to the front surface of the semiconductor substrate 6 in the breakdown voltage structure 4 and the n-type region. - A plurality of FLRs 41 are provided between the first and second drift regions 11 and at a distance from the p-type well region 31. The plurality of FLRs 41 are provided at a distance from each other and concentrically surround the periphery of the p-type well region 31. The FLRs 41 have the function of reducing the electric field applied to the Si interface (the interface between the interlayer insulating film 21 and the front surface of the semiconductor substrate 6).

[0058] The plurality of FLRs 41 are in contact with the interlayer insulating film 21 on the front surface of the semiconductor substrate 6, and each - The FLRs 41 are surrounded by the n-type drift region 11. The n-type well region 31 is formed between the adjacent FLRs 41 and between the innermost FLR 41 and the p-type well region 31. - The type drift region 11 reaches the front surface of the semiconductor substrate 6. For example, the widths (widths from the inside to the outside) of the FLRs 41 are all substantially the same, and the spacing between adjacent FLRs 41 becomes wider toward the outside. The impurity concentrations of the FLRs 41 are all substantially the same. The impurity concentration of the FLRs 41 is, for example, substantially the same as the impurity concentration of the p-type well region 31.

[0059] On the front surface of the semiconductor substrate 6 in the breakdown voltage structure 4, FPs 42, the same number as the FLRs 41, are provided, spaced apart from the gate metal wiring layer 35. The multiple FPs 42 are provided spaced apart from one another and concentrically surround the periphery of the gate runner portion 3. Each FP 42 contacts a different FLR 41 via a contact hole 21d in the interlayer insulating film 21. The FPs 42 have the function of discharging and reducing fixed charges at the Si interface. The FPs 42 can control the extension of a depletion layer that spreads outward from the active region 1 when the main junction of the active region 1 is reverse biased.

[0060] The FP42 extends from within the contact hole 21d onto the interlayer insulating film 21. The portion of the FP42 extending onto the interlayer insulating film 21 may extend inward and outward from the FLR41 directly below (the FLR41 it contacts). By extending the FP42 inward from the FLR41 directly below, the outward extension of the depletion layer directly below the inner end (inner peripheral end) of the FP42 is suppressed. By extending the FP42 outward from the FLR41 directly below, the depletion layer is more likely to extend outward from the outer end (outer peripheral end) of the FP42.

[0061] The width by which the FP 42 extends inward and outward from the FLR 41 directly below is set appropriately according to the required breakdown voltage of the edge termination region 2 and may be different for each FP 42. The inner end or outer end or both ends of the FP 42 may terminate on the FLR 41 directly below via the interlayer insulating film 21. Figures 3 and 4 show examples in which the outer end 42b of the outermost (outermost) FP 42 extends in different ways. The width of the FP 42 (width from the inner side to the outer side) may be wider, for example, as it extends outward.

[0062] The channel stopper portion 5 is adjacent to the outside of the breakdown voltage structure portion 4. The channel stopper portion 5 has n + The channel stopper section 5 is a region from an inner end 53a of the p-type channel stopper region 53 to the chip end. The channel stopper section 5 is provided with a channel stopper structure 50. The channel stopper structure 50 includes a p-type channel stopper region (fifth semiconductor region) 51, a channel stopper electrode 52, and an n-type channel stopper region (fifth semiconductor region) 53a. + The p-type channel stopper region 51 is formed between the front surface of the semiconductor substrate 6 and the n-type channel stopper region (fourth semiconductor region) 53. - It is provided between the mold drift region 11 and the substrate.

[0063] The p-type channel stopper region 51 is provided apart from the outermost FLR 41 and surrounds the periphery of the FLR 41. The p-type channel stopper region 51 is in contact with the interlayer insulating film 21 on the front surface of the semiconductor substrate 6, is exposed at the chip edge, and is n -The p-type channel stopper region 51 is surrounded by the n-type drift region 11. The depth of the p-type channel stopper region 51 (depth position of the lower surface) may be shallower than the depth of the FLR 41, for example, about 4 μm to 6 μm. Instead of the p-type channel stopper region 51, an n-type channel stopper region (not shown) exposed at the chip edge may be provided.

[0064] A channel stopper electrode 52 fixed to the same potential as the collector electrode 24 is provided on the front surface of the semiconductor substrate 6 in the channel stopper portion 5. The channel stopper electrode 52 is provided away from the FP 42 and surrounds the periphery of the breakdown voltage structure portion 4. The channel stopper electrode 52 is the outermost metal electrode on the front surface of the semiconductor substrate 6 and faces the entire p-type channel stopper region 51 in the depth direction Z. The channel stopper electrode 52 contacts the p-type channel stopper region 51 via a contact hole 21e in the interlayer insulating film 21.

[0065] The p-type channel stopper region 51 and the channel stopper electrode 52 have the function of preventing the occurrence of a parasitic channel due to the wiring potential (the potential of the wiring layer drawn from the chip center to the chip edge) on the front surface of the semiconductor substrate 6. The channel stopper electrode 52 extends inward from within the contact hole 21e onto the interlayer insulating film 21, and protrudes further inward than the p-type channel stopper region 51. An inner end (inner peripheral end) 52a of the channel stopper electrode 52 is connected to the n-type semiconductor substrate 6 via the interlayer insulating film 21. + The molded channel terminates on the channel stopper region 53 .

[0066] n + The n-type channel stopper region 53 is connected to the front surface of the semiconductor substrate 6. - The n-type drift region 11 is provided between the p-type channel stopper region 51 and the outermost FLR 41. + The mold channel stopper region 53 is provided apart from the FLR 41 and surrounds the periphery of the outermost FLR 41. + Between the mold channel stopper region 53 and the outermost FLR 41, n - The type drift region 11 reaches the front surface of the semiconductor substrate 6. +The entire upper surface of the mold channel stopper region 53 is covered with the interlayer insulating film 21 .

[0067] n + The n-type channel stopper region 53 is disposed at a position closer to the p-type channel stopper region 51 than the outermost FLR 41. + The n-type channel stopper region 53 may be in contact with the p-type channel stopper region 51 or may be spaced apart from the p-type channel stopper region 51. + When the n-type channel stopper region 53 and the p-type channel stopper region 51 are in contact with each other, the p-type channel stopper region 51 + There is a risk that the contact points with the mold channel stopper region 53 may become partially low in impurity concentration or disappear.

[0068] n + When the n-type channel stopper region 53 and the p-type channel stopper region 51 are disposed apart from each other, + Between the n-type channel stopper region 53 and the p-type channel stopper region 51, - The type drift region 11 reaches the front surface of the semiconductor substrate 6. + The upper surface of the type channel stopper region 53 is p-type + In this case, the front surface of the semiconductor substrate 6 and the n-type collector region 19 side + Between the n-type channel stopper region 53 - A type drift region 11 is interposed.

[0069] n + The n-type channel stopper region 53 faces the channel stopper electrode 52 in the depth direction Z via the interlayer insulating film 21, and extends further inward than the channel stopper electrode 52. + The channel stopper region 53 has a depth of n in the depth direction Z. + The n-type channel stopper region 53 has an inner portion (first portion) 53-1 that does not face the n-type channel stopper region 53, and an outer portion (second portion) 53-2 that is located directly below the n-type channel stopper electrode 52. + The width of the outer portion 53-2 of the channel stopper region 53 is n +The width is about 40% to 60% of the entire width of the mold channel stopper region 53 .

[0070] That is, n + The channel stopper region 53 faces the inner end 52 a of the channel stopper electrode 52 in the depth direction Z, and is disposed between the channel stopper electrode 52 and the outermost FP 42. + The resistivity of the semiconductor substrate 6 is locally reduced (the dose is increased) in the portion where the type channel stopper region 53 is provided, and the outward extension of the depletion layer immediately below the inner end 52 a of the channel stopper electrode 52 is suppressed, thereby suppressing the electric field concentration immediately below the inner end 52 a of the channel stopper electrode 52.

[0071] n + The mold channel stopper region 53 does not face the FP 42 in the depth direction Z. + The inner end (inner peripheral end) 53a of the channel stopper region 53 is located between the channel stopper electrode 52 and the outermost FP 42 and the outermost FLR 41. + The width L2 of the inner portion 53-1 of the channel stopper region 53 is preferably about half or less of the distance L1 (the distance in the direction parallel to the front surface of the semiconductor substrate 6) between the channel stopper electrode 52 and the outermost terminating one of the outermost FP 42 and the outermost terminating one of the outermost FLR 41 (L2≦L1 / 2).

[0072] For example, when the outermost FP 42 protrudes outward from the FLR 41 (the outermost FLR 41) directly below (FIG. 3), + The width L2 of the inner portion 53-1 of the channel stopper region 53 is about half or less of the distance L1 between the channel stopper electrode 52 and the outermost FP 42. When the outer end 42b of the outermost FP 42 terminates on the FLR 41 directly below, + The width L2 of the inner portion 53-1 of the channel stopper region 53 is less than the distance L1 between the channel stopper electrode 52 and the outermost FLR 41. +The width L2 of the inner portion 53-1 of the channel stopper region 53 may be approximately half or less of the distance L1 between the channel stopper electrode 52 and the outermost FLR 41 (FIG. 4). By doing so, the shape of the outermost FLR 41 can be maintained, and a decrease in breakdown voltage can be prevented.

[0073] When the outer end 42 b of the outermost FP 42 terminates on the FLR 41 directly below, the extension of the depletion layer toward the channel stopper electrode 52 is suppressed, thereby enhancing the effect of suppressing the electric field concentration directly below the inner end 52 a of the channel stopper electrode 52. Furthermore, by extending the outermost FP 42 inward beyond the FLR 41 directly below, the extension of the depletion layer toward the channel stopper electrode 52 is also suppressed, thereby enhancing the effect of suppressing the electric field concentration directly below the inner end 52 a of the channel stopper electrode 52.

[0074] Even when the outermost FP 42 and the outermost FLR 41 terminate at the same position on the outside, n + The width L2 of the inner portion 53-1 of the channel stopper region 53 may be set to about half or less of the distance L1 between the channel stopper electrode 52 and the outermost FP 42 (the outermost FLR 41). + The inner end 53a of the mold channel stopper region 53 is preferably located approximately midway between the channel stopper electrode 52 and the outermost FP 42 or the outermost FLR 41, or outside thereof.

[0075] n + The depth d2 of the mold channel stopper region 53 (depth position of the lower surface) is shallower than the depth d1 of the FLR 41 (depth position of the lower surface). + The depth d2 of the mold channel stopper region 53 is preferably about 10% to 60% of the depth d1 of the FLR 41 (0.1×d1≦d2≦0.6×d1). + When the type channel stopper region 53 is spaced apart from the front surface of the semiconductor substrate 6, n + It is only necessary that the depth position of the lower surface of the mold channel stopper region 53 satisfies the above condition with respect to the depth d1 of the FLR 41.

[0076] n+ Simulations by the present inventors have confirmed that the deeper the depth d2 of the channel stopper region 53, the lower the breakdown voltage of the edge termination region 2. For example, when the drift region has a super junction (SJ) structure as in Patent Document 2, depletion progresses outward in the lateral direction (direction parallel to the front surface of the semiconductor substrate) from the pn junction between the n-type region and the p-type region that make up the SJ structure. Therefore, even if a relatively deep n-type region is provided near the edge of the semiconductor substrate, the outward extension of the depletion layer is not hindered.

[0077] On the other hand, in the case of a normal n-type semiconductor device that does not have an SJ structure as in the present embodiment, - In the case of the p-type drift region 11, the p-type drift region 11 is located below the main junction of the active region 1. + The depletion proceeds from the main junction edge of the active region 1 to the edge of the n-type FS region 18 (i.e., the p-type collector region 19 side of the semiconductor substrate 6). + Depletion progresses in an oblique direction toward the n-type collector region 19. + It is presumed that if the depth d2 of the channel stopper region 53 is large, depletion in the oblique direction near the edge of the semiconductor substrate 6 is hindered.

[0078] Therefore, n + When the depth d2 of the type channel stopper region 53 exceeds the upper limit, n + The extension of the depletion layer is inhibited by the n-type channel stopper region 53, and the breakdown voltage of the edge termination region 2 is reduced. + When the depth d2 of the mold channel stopper region 53 is less than the above-mentioned lower limit, n + The effect of providing the type channel stopper region 53 cannot be obtained. Although not particularly limited, for example, the depth d1 of the FLR 41 is about 5 μm or more and 10 μm or less, and + The depth d2 of the mold channel stopper region 53 may be approximately 1 μm or more and 3 μm or less.

[0079] n + The impurity concentration of the n-type channel stopper region 53 is uniquely determined, and the impurity concentration of the n-type channel stopper region 53 is uniquely determined. - It does not depend on the impurity concentration of the n-type drift region 11.+ The impurity concentration of the channel stopper region 53 is, for example, 1×10 18 / cm 3 It is about less than 1×10 16 / cm 3 5x10 or more 17 / cm 3 It is within the range of about n + The impurity concentration of the channel stopper region 53 is 1×10 18 / cm 3 Above this, the depletion layer no longer extends outward, and n + This is not preferable because the electric field is concentrated in the channel stopper region 53 .

[0080] n + The n-type channel stopper region 53 is a diffusion region formed by ion implantation of n-type impurities into the front surface of the semiconductor substrate 6. + The impurity concentration distribution of the type channel stopper region 53 is determined by the following equation: + The impurity concentration has a peak concentration (maximum value of impurity concentration) at a relatively shallow depth position on the collector region 19 side, and the impurity concentration decreases from the depth position of the peak concentration toward the front surface side and the back surface side of the semiconductor substrate 6, respectively.

[0081] n + The channel stopper region 53 is formed by a p + The first depth position, which is deeper on the collector region 19 side, is defined as the bottom surface, and the second depth position, which is shallower on the front surface side of the semiconductor substrate 6 by the half width at half maximum of the impurity concentration distribution from the depth position of the peak concentration, is defined as the top surface. + When the distance from the depth position of the peak concentration to the front surface of the semiconductor substrate 6 is equal to or less than the half width at half maximum of the impurity concentration distribution, the front surface of the semiconductor substrate 6 is the upper surface of the type channel stopper region 53 .

[0082] For example, n +The type channel stopper region 53 preferably has substantially the same impurity concentration distribution (particularly, peak concentration) as the CS region 11a. By opening predetermined locations of the ion implantation mask for forming the CS region 11a, the n-type channel stopper region 53 can be implanted simultaneously with the CS region 11a. + The acceleration voltage of the ion implantation for forming the CS region 11a is relatively high, for example, 2 MeV to 3 MeV, so that even if the ion implantation is performed through the initial insulating film onto the semiconductor substrate 6, the n-type channel stopper region 53 can be formed with an impurity concentration distribution that is almost the same as that when the ions are implanted directly into the semiconductor substrate 6. + A mold channel stopper region 53 can be formed.

[0083] The channel stopper structure 50 does not include a p-type channel stopper region 51, but includes a channel stopper electrode 52 and an n-type + Alternatively, the channel stopper electrode 52 may be formed only from the n-type channel stopper region 53 (FIG. 5). In this case, the channel stopper electrode 52 is connected to the front surface of the semiconductor substrate 6 through the contact hole 21e of the interlayer insulating film 21. - It contacts the drift region 11. + An outer end (outer peripheral end) 53b of the mold channel stopper region 53 may extend outward to the chip edge and be exposed at the chip edge. Although Fig. 5 shows the FLR 41 and FP2 having the same configuration as Fig. 3, the FLR 41 and FP2 may also be arranged in the same configuration as Fig. 4.

[0084] The breakdown voltage structure 40 has at least n - It is sufficient to provide a p-type region that forms a pn junction with the p-type drift region 11, and a junction termination extension (JTE) structure (not shown) may be provided instead of the plurality of FLRs 41. The JTE structure is a structure in which the impurity concentration decreases (or the depth decreases) from the inside to the outside. - The p-type regions are arranged adjacent to each other so as to overlap each other concentrically around the periphery of the active region. - This structure has a type electric field relaxation layer.

[0085] p -The effective impurity concentration of the p-type electric field buffer layer decreases from the inside to the outside. - The n-type electric field relaxation layer is - The p-type well region 31 is provided between the p-type drift region 11 and the p-type well region 31. - The entire upper surface of the electric field relaxation layer is covered with the interlayer insulating film 21. When the breakdown voltage structure 40 has a JTE structure, the FP 42 is not provided. + The channel stopper region 53 and the p - The positional relationship with the n-type electric field relaxation layer is + This is the same as the positional relationship between the mold channel stopper region 53 and the outermost FLR 41 .

[0086] The operation of the semiconductor device 10 according to the embodiment will be described. Normally, the emitter electrode 22 is grounded or has a negative voltage applied thereto. The collector electrode 24 has a positive voltage applied thereto relative to the emitter electrode 22. Even in this state, if the voltage applied to the gate electrode 17 is less than the gate threshold voltage, the p-type base region 12 and the n-type base region 13 are connected to each other. - Since the pn junction (main junction of the active region 1) between the IGBT and the type drift region 11 (or the CS region 11a) is reverse biased, no main current flows between the emitter and collector. In other words, the IGBT (semiconductor device 10) remains in the off state.

[0087] On the other hand, when a voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 17 while a positive voltage relative to the emitter electrode 22 is applied to the collector electrode 24, a channel (n-type inversion layer) is formed in the p-type base region 12 along the trench 15. + through the n-type emitter region 13 and the channel - Electrons are injected into the p-type drift region 11, + collector region 19 and n - The pn junction between the collector electrode 24 and the n-type drift region 11 is forward biased. - Since holes are injected into the type drift region 11, a main current flows between the emitter and the collector (between both main surfaces of the semiconductor substrate 6), and the IGBT transitions to the ON state.

[0088] By reducing the voltage applied to the gate electrode 17 to less than the gate threshold voltage again, the channel disappears and n - Since the supply of electrons to the n-type drift region 11 is stopped, - The supply of holes to the n-type drift region 11 is also stopped. - The electrons and holes accumulated in the n-type drift region 11 are discharged to the collector electrode 24 and the emitter electrode 22, respectively, or - The electrons are annihilated by recombination in the type drift region 11, and no current flows between the emitter and collector. The IGBT transitions from the on state to the off state.

[0089] When the IGBT is turned off, the reverse-biased active region 1 is connected to the main junction of the n - The breakdown voltage of edge termination region 2 can be improved by the amount that the depletion layer extends outward within type drift region 11. At this time, even if positive charges are accumulated in the insulating layers (insulating layer 33, interlayer insulating film 21, and surface protective film 23) on the front surface of semiconductor substrate 6 in edge termination region 2 or on FP 42, the provision of breakdown voltage structure 40 makes the breakdown voltage of edge termination region 2 less susceptible to adverse effects of the positive charges. Furthermore, the more conditions are set for breakdown voltage structure 40 that make it easier for the depletion layer to extend outward from active region 1, the more resistant to adverse effects of the positive charges can be made.

[0090] Furthermore, even if negative charges are accumulated in the insulating layer on the front surface of the semiconductor substrate 6 in the edge termination region 2 or on the FP 42, n + Type channel stopper region 53 suppresses the outward extension of the depletion layer directly below inner end 52 a of channel stopper electrode 52, thereby suppressing electric field concentration in that portion, thereby improving the breakdown voltage of edge termination region 2. Therefore, even if positive or negative charges accumulate over time in the insulating layer on the front surface of semiconductor substrate 6 or on FP 42 in edge termination region 2 due to high-temperature, high-voltage stress caused by long-term operation of semiconductor device 10, the specified breakdown voltage of edge termination region 2 can be stably ensured.

[0091] n + By providing the type channel stopper region 53, the n-type - Simulations by the present inventors have confirmed that a high electric field is uniformly applied to almost the entire region of the type drift region 11. It is presumed that the high electric field uniformly applied to the inner portion of the breakdown voltage structure 4 shifts the breakdown point inward from directly below the inner end 52a of the channel stopper electrode 52, thereby improving the breakdown voltage of the edge termination region 2 when negative charge is accumulated. The stable breakdown voltage of the edge termination region 2 means that the breakdown voltage of the edge termination region 2 does not fluctuate in response to negative and positive charges and is maintained at or above the breakdown voltage of the edge termination region 2 under normal conditions (zero charge).

[0092] As described above, according to the embodiment, n + The n-type channel stopper region is provided outside the outermost FLR and spaced apart from the FLR, and faces the inner end of the channel stopper electrode in the depth direction. Even if negative charges are accumulated over time in the insulating layer on the front surface of the semiconductor substrate in the edge termination region or on the FP due to high temperature and high voltage stress caused by long-term operation of the semiconductor device, the n-type channel stopper region + The channel stopper region prevents the depletion layer from extending outward just below the inner edge of the channel stopper electrode, thereby preventing electric field concentration in that area. This improves the breakdown voltage of the edge termination region, ensuring a stable, predetermined breakdown voltage for the edge termination region. This improves the long-term reliability of the edge termination region against negative charges.

[0093] Furthermore, according to the embodiment, by increasing the breakdown voltage of the edge termination region by applying a negative charge, the tolerance range of the manufacturing process variation of the FLR can be widened or the number of FLRs can be reduced, thereby enabling miniaturization.

[0094] The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention is not limited to IGBTs, but can be applied to vertical semiconductor devices, such as vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS field effect transistors with an insulated gate made of a three-layer structure of metal-oxide film-semiconductor) and vertical diodes. In this case, p + Instead of the collector region, + By providing the n-type drain region, a MOSFET is formed. In the MOSFET, the n-type drain region serves as a carrier spread (CS) region that reduces the spreading resistance of carriers. + Without providing a type emitter region, + Instead of the collector region, + By providing a cathode region, a diode is formed.

[0095] The present invention is also applicable to RC-IGBTs (Reverse Conducting IGBTs) and RB-IGBTs (Reverse Blocking IGBTs) in which a diode is built into the same semiconductor substrate as the IGBT. + A part of the collector region is n + An RC-IGBT is formed by replacing the n-type cathode region with a p-type cathode region, and an RB-IGBT is formed by forming a p-type channel stopper region deep enough to penetrate from the front surface to the back surface of the semiconductor substrate and exposing it on the entire chip edge. The present invention is also applicable to semiconductors with a wider band gap than silicon (hereinafter referred to as wide band gap semiconductors), such as silicon carbide (SiC). In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type.

[0096] As described above, the semiconductor device according to the present invention is useful as a power semiconductor device used in power conversion devices and power supply devices for various industrial machines.

[0097] 1, 101 active region 2, 102 edge termination region 3, 103 gate runner portion 4, 104 breakdown voltage structure portion 5, 105 channel stopper portion 6, 106 semiconductor substrate 10, 110 semiconductor device 11, 111 n - n-type drift region 11a CS region 12 p-type base region 13 + Type emitter region 14p + Type contact region 15 Trench 16 Gate insulating film 17 Gate electrode 18 n-type FS region 19 n + 20 MOS gate 21, 121 interlayer insulating film 21a to 21e, 121a to 121e contact hole 22 emitter electrode 23, 123 surface protection film 24 collector electrode 30, 130 gate runner 31, 131 p-type well region 32 outer peripheral p + 1. Type contact region 33, 133 Insulating layer 34, 134 Gate polysilicon wiring layer 35, 135 Gate metal wiring layer 40, 140 Breakdown resistance structure 41, 141 FLR 42, 142 FP 42b Outer end of outermost FP 50, 150 Channel stopper structure 51, 151 P-type channel stopper region 52, 152 Channel stopper electrode 52a, 152a Inner end of channel stopper electrode 53 n + Mold channel stopper region 53-1 n + Inner portion of mold channel stopper region 53-2 n + Outer portion of mold channel stopper region 53a n + Inner end of mold channel stopper region d1 FLR depth (depth position of bottom surface) d2 n + L1: Depth of the mold channel stopper region (depth position of the bottom surface) L2: Distance between the channel stopper electrode and the outermost terminating one of the outermost FP and the outermost FLR + Width of inner portion 53-1 of mold channel stopper region X: First direction parallel to the front surface of the semiconductor substrate Y: Second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction Z: Depth direction

Claims

a first semiconductor region of a first conductivity type provided within the semiconductor substrate spanning from the active region to the termination region; a second semiconductor region of a second conductivity type provided in the active region between a front surface of the semiconductor substrate and the first semiconductor region; a vertical element structure provided in the active region in which a current flows between both main surfaces of the semiconductor substrate through a pn junction between the second semiconductor region and the first semiconductor region; an insulating layer covering the front surface of the semiconductor substrate in the termination region; a voltage-withstanding structure having a third semiconductor region of a second conductivity type provided between the front surface of the semiconductor substrate and the first semiconductor region in the termination region and surrounding the active region; and a channel stopper electrode provided on the insulating layer outside the voltage-withstanding structure and in contact with the front surface of the semiconductor substrate via a contact hole in the insulating layer. a fourth semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor region, the fourth semiconductor region being provided between the front surface of the semiconductor substrate and the first semiconductor region, between the contact hole and the third semiconductor region, and spaced apart from the third semiconductor region, and facing an inner end of the channel stopper electrode via the insulating layer.

2. The semiconductor device according to claim 1, characterized in that the impurity concentration distribution of the fourth semiconductor region is a Gaussian distribution in which the impurity concentration decreases from the depth position of the peak concentration toward the front surface side and the back surface side of the semiconductor substrate, respectively.

3. The semiconductor device according to claim 2, wherein the distance from the depth position of the peak concentration in the fourth semiconductor region to the front surface of the semiconductor substrate is equal to or less than the half-width at half maximum of the impurity concentration distribution.

4. The semiconductor device described in claim 2, characterized in that a first depth position that is deeper than the depth position of the peak concentration of the fourth semiconductor region on the back side of the semiconductor substrate by half the half-width at half maximum of the impurity concentration distribution is shallower than the depth of the third semiconductor region.

5. A semiconductor device according to claim 4, characterized in that the first depth position of the fourth semiconductor region is 10% to 60% of the depth of the third semiconductor region.

6. The semiconductor device according to claim 1, characterized in that the fourth semiconductor region has a first portion located inside an inner end of the channel stopper electrode, and a second portion excluding the first portion and facing the channel stopper electrode via the insulating layer.

7. The semiconductor device according to claim 6, wherein the width of the first portion of the fourth semiconductor region is less than half the distance from the channel stopper electrode to the third semiconductor region in a direction parallel to the front surface of the semiconductor substrate.

8. The semiconductor device according to claim 6, wherein the breakdown voltage structure comprises: a plurality of third semiconductor regions floating in potential; and metal electrodes, the same number as the third semiconductor regions, provided on the front surface of the semiconductor substrate and each of which is floating in potential and in contact with a different third semiconductor region; and the width of the first portion of the fourth semiconductor region is less than half the distance from the channel stopper electrode to the outermost terminal of the outermost third semiconductor region and the outermost metal electrode in a direction parallel to the front surface of the semiconductor substrate.

9. The semiconductor device according to claim 6, wherein the width of said second portion of said fourth semiconductor region is not less than 40% and not more than 60% of the width of said fourth semiconductor region.

10. The semiconductor device described in claim 4, further comprising a fifth semiconductor region provided between the front surface of the semiconductor substrate and the first semiconductor region outside the fourth semiconductor region and in contact with the channel stopper electrode via the contact hole, wherein the first depth position of the fourth semiconductor region is shallower than the depth of the fifth semiconductor region.

11. The semiconductor device described in claim 1, further comprising a fifth semiconductor region provided between the front surface of the semiconductor substrate and the first semiconductor region outside the fourth semiconductor region and in contact with the channel stopper electrode via the contact hole, wherein the fourth semiconductor region is disposed closer to the fifth semiconductor region than the third semiconductor region.

12. The semiconductor device according to claim 10 or 11, wherein the fifth semiconductor region is of the second conductivity type.

13. The semiconductor device according to claim 2, further comprising a sixth semiconductor region of a first conductivity type provided between the second semiconductor region and the first semiconductor region and having a higher impurity concentration than the first semiconductor region, wherein the impurity concentration distribution of the fourth semiconductor region is the same as the impurity concentration distribution of the sixth semiconductor region.

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