Server system and communication method therefor

Abstract

The present application relates to the technical field of servers. Disclosed are a server system and a communication method therefor. The server system comprises: at least one first processor board and a host server, wherein the at least one first processor board is in communication connection with the host server by means of a switching network; the first processor board comprises a first field programmable gate array chip and a first processor chip; the first field programmable gate array chip and the first processor chip are packaged and interconnected; the host server is configured to transmit host data to the first field programmable gate array chip by means of the switching network; and the first field programmable gate array chip is configured to process the host data, receive request data which is sent by means of the first processor chip, generate a communication protocol message on the basis of the processed host data and the request data, and transmit the communication protocol message to a destination processor board by means of the switching network. By means of the present application, pooling acceleration of a server system is realized, thereby realizing efficient layout of computing power resources.

Description

A server system and communication method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on June 25, 2023, with application number 202310752395.X, and application name “A Server System and Its Communication Method”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of server technology, and in particular to a server system and a communication method thereof. Background Art

[0004] Artificial intelligence (AI) is currently being widely applied in a wide variety of applications. The three main pillars of AI are hardware, algorithms, and data. Hardware refers to the chips that run AI algorithms and the corresponding computing platforms, primarily including graphics processing units (GPUs), neural processor units (NPUs), ASICs (Application Specific Integrated Circuits), and field programmable gate arrays (FPGAs). As the demand for AI computing power continues to increase, AI processor clusters are often used to perform computations on large-scale, complex models.

[0005] The communication performance between AI nodes in a distributed AI processor cluster is a key part of the overall system performance. However, no effective solutions have yet been proposed to address the problem in related technologies where the layout of computing resources is difficult to match with AI computing power.

[0006] Summary of the Invention

[0007] In view of this, the present application provides a server system and a communication method thereof to solve the problem of efficient layout of computing resources in a distributed AI processor cluster.

[0008] According to a first aspect, the present application provides a server system, comprising: at least one first processor board and a host server, wherein the at least one first processor board is communicatively connected to the host server via a switching network; wherein the first processor board comprises a first field programmable gate array chip and a first processor chip; the first field programmable gate array chip and the first processor chip are packaged and interconnected;

[0009] a host server configured to transmit host data to the first field programmable gate array chip via a switching network;

[0010] The first field programmable gate array chip is configured to process host data and receive request data sent by the first processor chip, generate a communication protocol message based on the processed host data and the request data, and transmit the communication protocol message to the destination processor board through the switching network.

[0011] The present application provides a server system that sets at least one first processor board without changing the original data center topology. Pooled acceleration of the server system can be achieved through the first processor board without the need for a CPU (Central Processing Unit) server, greatly reducing the consumption of multiple devices, improving acceleration efficiency, and achieving efficient layout of computing resources. In addition, the first field programmable gate array chip and the first processor chip are packaged and interconnected, which can give full play to their respective acceleration performance and ensure the lowest communication delay between the two.

[0012] In an optional embodiment, the invention further comprises: at least one second processor board, the second processor board being connected to the host server, and the second processor board being connected to the at least one first processor board via a switching network; wherein the second processor board comprises a second field programmable gate array chip and a second processor chip, and the second field programmable gate array chip and the second processor chip are packaged and interconnected;

[0013] The second field programmable gate array chip is configured to obtain host data and receive request data sent by the second processor chip, generate a communication protocol message based on the processed host data and request data, and transmit the communication protocol message to the destination processor board through the switching network.

[0014] The present application provides a server system in which a second processor board is connected to a host server, which can achieve local acceleration and reduce data transmission on the network.

[0015] In an optional embodiment, the first field programmable gate array chip and the first processor chip are connected through a chip packaging method, and the second field programmable gate array chip and the second processor chip are connected through a chip packaging method.

[0016] The present application provides a server system in which a first field programmable gate array chip and a first processor chip, a second field programmable gate array chip and a second processor chip are respectively connected to different processor boards through chip packaging, thereby minimizing the communication delay between the processor chip and the field programmable gate array chip.

[0017] In an optional embodiment, the chip packaging method includes UCIe or ACC.

[0018] In an optional embodiment, the first processor chip includes a storage module; the first field programmable gate array chip includes: a bus interface module, a protocol processing module, a resource detection engine module, a resource transmission module, a memory controller, a memory mapping module and an interface module; wherein,

[0019] The bus interface module is connected to the protocol processing module and is configured to transmit the data to be processed to the protocol processing module;

[0020] The protocol processing module is connected to the resource detection engine module, the memory mapping module and the resource transmission module, and is configured to parse the data to be processed, generate configuration data, and transmit the configuration data to the resource detection engine module;

[0021] a resource detection engine module configured to determine a network address of a destination processor board based on the configuration data and transmit the network address of the destination processor board to the protocol processing module;

[0022] a memory mapping module configured to obtain request data from the processor chip, determine a memory address of a destination processor board based on the request data from the processor chip, and transmit the memory address of the destination processor board to the protocol processing module;

[0023] The storage module is configured to transmit the virtual memory address to the protocol processing module through the interface module, the memory controller and the resource transmission module in sequence;

[0024] The protocol processing module is also configured to encapsulate the network address, memory address and virtual memory address of the destination processor board, generate a communication protocol message, and transmit the communication protocol message to the destination processor board via the bus interface module and the switching network in turn.

[0025] The present application provides a server system that utilizes a resource detection engine module, a memory mapping module, and a storage module to accurately acquire information about a target processor board. The protocol processing module encapsulates the target processor board information into a communication protocol message, and realizes communication interaction between server systems through a bus interface module and a switching network, thereby ensuring efficient interconnection of the server systems.

[0026] In an optional embodiment, the first processor chip further includes: an acceleration processing module;

[0027] The acceleration processing module is connected to the interface module and is configured to obtain acceleration data and accelerate the processor operation speed based on the acceleration data; wherein the acceleration data is generated by the protocol processing module by parsing the data to be processed and transmitted to the interface module through the memory controller and the resource transmission module.

[0028] The server system provided in the present application improves the operating speed of the processor through an acceleration processing module, thereby improving the computing power acceleration efficiency. In addition, the acceleration data is transmitted to the interface module through a memory controller and a resource transmission module, ensuring that the storage rate of the interface module is consistent with the storage rate of the bus interface module.

[0029] In an optional embodiment, the first field programmable gate array chip further includes: a field programmable gate array acceleration engine;

[0030] The field programmable gate array acceleration engine is connected to the protocol processing module and the memory controller, and is configured to pre-process the data to be processed and transmit the pre-processed data to the processor chip through the memory controller.

[0031] The present application provides a server system that dynamically reconfigures a field programmable gate array acceleration engine according to application requirements, thereby improving application flexibility and scalability and enhancing computing power acceleration efficiency.

[0032] In an optional implementation, the resource detection engine module includes:

[0033] The lookup table storage unit is configured to match the configuration data with the configuration information table to determine the current processor board, and to match the current processor board with the network address table to determine the network address of the destination processor board.

[0034] The present application provides a server system in which a lookup table storage unit sets a configuration information table and a network address table, thereby ensuring accurate judgment of the destination processor board and improving application flexibility and scalability.

[0035] In an optional embodiment, the lookup table storage unit is further configured to broadcast status information of the current first processor board and receive status messages of other first processor boards, and update the configuration information table and the network address table based on the status messages of other first processor boards.

[0036] The present application provides a server system that dynamically monitors resource usage of the server system through a lookup table storage unit, and can then bypass faulty processor boards based on the resource usage of the server system, thereby improving the reliability of the server system.

[0037] In an optional embodiment, the interface module includes: an initialization configuration unit;

[0038] The initialization configuration unit is configured to obtain initialization configuration information and perform link initialization configuration, space initialization configuration and internal register configuration based on the initialization configuration information.

[0039] The present application provides a server system in which an initialization configuration unit performs link initialization configuration, space initialization configuration, and internal register configuration, thereby ensuring normal data transmission between a first field programmable gate array chip and a first processor chip, and ensuring normal calculation and processing of data by the first field programmable gate array chip.

[0040] In an optional embodiment, the bus interface module is also configured to obtain custom configuration information and transmit the custom configuration information to the resource detection engine module and the memory mapping module; wherein the resource detection engine module initializes the configuration information table and the network address table based on the custom configuration information, and the memory mapping module initializes the configuration memory queue.

[0041] The present application provides a server system that uses custom configuration information to configure relevant data, laying the foundation for subsequent data processing and communication interaction in the first field programmable gate array chip, thereby improving application flexibility and scalability.

[0042] In an optional embodiment, the bus interface module includes a MAC interface and a PCIE interface; wherein,

[0043] The MAC interface is connected to the switching network and is configured to transmit the communication protocol message to the first processor card or the second processor card through the switching network;

[0044] The PCIE interfaces are connected to the host server and the switching network respectively, and are configured to transmit host data to the second processor board.

[0045] The present application provides a server system that connects a bus interface module with different devices, differentiates transmission modes, ensures efficient data transmission, and avoids congestion of transmission queues.

[0046] According to a second aspect, the present application provides a communication method of a server system, which is applied to the server system of the first aspect, and the method includes:

[0047] The host server transmits the host data to the first field programmable gate array chip through the switching network;

[0048] The first field programmable gate array chip processes the host data and receives the request data sent by the first processor chip, generates a communication protocol message based on the processed host data and the request data, and transmits the communication protocol message to the destination processor board through the switching network.

[0049] In an optional embodiment, the first field programmable gate array chip processes host data and receives request data sent by the first processor chip, generates a communication protocol message based on the processed host data and the request data, and transmits the communication protocol message to a destination processor board through a switching network, including:

[0050] The bus interface module transmits the data to be processed to the protocol processing module;

[0051] The protocol processing module parses the data to be processed, generates configuration data, and transmits the configuration data to the resource detection engine module;

[0052] The resource detection engine module determines the network address of the destination processor board based on the configuration data, and transmits the network address of the destination processor board to the protocol processing module;

[0053] The memory mapping module obtains the request data of the processor chip, determines the memory address of the destination processor board based on the request data of the processor chip, and transmits the memory address of the destination processor board to the protocol processing module;

[0054] The storage module transmits the virtual memory address to the protocol processing module through the interface module, the memory controller and the resource transmission module in sequence;

[0055] The protocol processing module encapsulates the network address of the destination processor board, the memory address and the virtual memory address of the destination processor board, generates a communication protocol message, and transmits the communication protocol message to the switching network through the bus interface module.

[0056] In an optional embodiment, the method further includes:

[0057] The protocol processing module parses the data to be processed to generate acceleration data, and transmits the acceleration data to the acceleration processing module through the resource transmission module, memory controller and interface module in sequence;

[0058] The acceleration processing module accelerates the operating speed of the processor based on the acceleration data.

[0059] In an optional embodiment, the method further includes:

[0060] The field programmable gate array acceleration engine pre-processes the data to be processed and transmits the pre-processed data to the processor chip through the memory controller.

[0061] In an optional embodiment, the resource detection engine module determines the network address of the destination processor board based on the configuration data, including:

[0062] The lookup table storage unit matches the configuration data with the configuration information table to determine the current processor board, and matches the current processor board with the network address table to determine the network address of the destination processor board.

[0063] In an optional embodiment, the method further includes:

[0064] The lookup table storage unit broadcasts the status information of the current first processor board, receives status messages of other first processor boards, and updates the configuration information table and the network address table based on the status messages of other first processor boards.

[0065] In an optional embodiment, the method further includes:

[0066] The initialization configuration unit obtains initialization configuration information, and performs link initialization configuration, space initialization configuration, and internal register configuration based on the initialization configuration information.

[0067] In an optional embodiment, the method further includes:

[0068] The bus interface module obtains the custom configuration information and transmits the custom configuration information to the resource detection engine module and the memory mapping module; wherein the resource detection engine module initializes the configuration information table and the network address table based on the custom configuration information, and the memory mapping module initializes the configuration memory queue.

[0069] In an optional embodiment, the method further includes:

[0070] The MAC interface transmits the communication protocol message to the first processor board or the second processor board through the switching network;

[0071] The PCIE interface transmits the host data to the second processor board.

[0072] According to a third aspect, the present application further provides a non-volatile readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0074] FIG1 is a schematic diagram of the structure of GPU Direct RDMA according to the related art;

[0075] FIG2 is a structural block diagram of a server system according to an embodiment of the present application;

[0076] FIG3 is a structural block diagram of a first processor board according to an embodiment of the present application;

[0077] FIG4 is a schematic diagram of a communication protocol message according to an embodiment of the present application;

[0078] FIG5 is a schematic diagram of communication interaction of a server system according to an embodiment of the present application;

[0079] FIG6 is a schematic diagram of communication interaction of another server system according to an embodiment of the present application;

[0080] FIG7 is a schematic diagram of communication interaction of another server system according to an embodiment of the present application;

[0081] FIG8 is a schematic diagram of a server system performing neural network model training according to an embodiment of the present application;

[0082] FIG9 is a flow chart of a communication method of a server system according to an embodiment of the present application. DETAILED DESCRIPTION

[0083] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, other embodiments obtained by those skilled in the art without making creative efforts are all within the scope of protection of this application.

[0084] As the demand for AI computing power continues to increase, AI processor clusters are often used to complete the calculation of large-scale complex models. For example, Chat GPT (Chat Generative Pre-trained Transformer, based on natural language processing technology and neural network models) uses tens of thousands of GPUs to complete calculations.

[0085] RDMA (Remote Direct Memory Access) transfers data directly from the memory of one computer to another without requiring the operating systems of both computers to be connected, making it suitable for use in large-scale parallel computer clusters. GPU Direct RDMA refers to RDMA transmission between GPUs (GPU memory on one host is directly transferred to the memory of GPUs on another host). The CPU participates in control but not in data transmission. As shown in Figure 1, "GPU Memory" refers to GPU memory, often also called device memory, and "System Memory" refers to host memory. InfiniBand (wireless broadband) is a network communication protocol and the most common protocol specification for implementing RDMA technology. Chip set refers to the chipset, which primarily implements PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) switching functions. InfiniBand network cards and GPU accelerators are interconnected with the chip set through the PCIE interface. The chip set implements PCIE switching functions, and PCIE switching chips or switching cards can also be used.

[0086] Related technologies propose the use of FPGA clusters to expand the functions of the original computing center. FPGA nodes (host servers + FPGA accelerator cards) are connected to the original computing center through a network switch, and the FPGAs in the cluster are connected to form a cluster through a ring network.

[0087] The current communication solution for GPUs between multiple machines is GPU Direct RDMA (a technology supported by NVIDIA GPUs that allows the GPU of a local computer to directly access the memory of a remote GPU). As shown in Figure 1, the GPU board itself does not support network functions. To communicate with a remote GPU, a network card is required. Therefore, the GPU, network card, chip set (chipset) or PCIe switch (PCIe switching chip or PCIe switching card, which implements PCIe switching and forwarding functions), and CPU (Central Processing Unit) are usually bound together to form a GPU node. At the same time, due to technical limitations, the GPU and network card need to be under the same RC (Root Complex).

[0088] Related technologies propose a large-scale inference system based on a hybrid GPU-FPGA cluster. This system adds FPGA acceleration nodes (host servers with FPGA acceleration cards) to the multi-machine GPU pooling solution. By distributing computing and memory to GPU nodes and FPGA nodes respectively, each node is connected through a high-speed network.

[0089] Related technologies propose to reduce the tight coupling between the GPU card and the server by introducing an FPGA-based adapter card with data processing capabilities between the original GPU card and the server motherboard. This is similar to the network card function in the GPU Direct RDMA solution, but adds the function of receiving and processing network configuration signals.

[0090] However, in the above-mentioned GPU Direct RDMA pooling solution, the GPU nodes in the distributed GPU pooling platform need to include network cards, PCIE switches, and CPUs during deployment, which makes deployment difficult, consumes high energy, and has large transmission delays. In addition, the GPU pooling platform only has GPU accelerator cards, and all acceleration functions are implemented by the GPU. GPUs are suitable for computing acceleration, but not for network acceleration and storage acceleration, and their applicable scenarios are limited. Related technologies use FPGA adapter cards instead of network cards, which can receive some configuration management information through the network to reduce coupling with the CPU. However, it is still a network card in essence, but it adds the processing of network control data, and the management and allocation of pooled resources are still on the server. The solution proposed in the above-mentioned related technologies adds FPGA acceleration nodes (CPU+FPGA) to the GPU pooling nodes, which are set to look up embedded tables or perform functional expansion. However, the FPGA acceleration nodes and GPU acceleration nodes are deployed in different servers and connected through the network, resulting in large transmission delays and high energy consumption.

[0091] Therefore, how to achieve more efficient communication between AI nodes and how to better allocate computing resources are the keys to system design.

[0092] In this embodiment, a server system is provided, as shown in Figure 2, including: at least one first processor board 1 and a host server 2, wherein the at least one first processor board 1 (i.e., xPU board) is communicatively connected to the host server 2 via a switching network 3; wherein the first processor board 1 includes a first field programmable gate array chip (FPGA) 4 and a first processor chip 5; the first field programmable gate array chip 4 and the first processor chip 5 are packaged and interconnected.

[0093] The host server 2 is configured to transmit host data to the first field programmable gate array chip 4 through the switching network 3 .

[0094] The first field programmable gate array chip 4 is configured to process host data and receive request data sent by the first processor chip 5, generate a communication protocol message based on the processed host data and request data, and transmit the communication protocol message to the destination processor board through the switching network 3.

[0095] The server system is a system composed of a host server 2, at least one first processor board 1 and a switching network.

[0096] Optionally, the destination processor board is a first processor board 1 other than the current processor board.

[0097] Optionally, the request information may include the virtual memory address of the first processor chip 5, data after accelerated processing, and the like.

[0098] Optionally, the first processor chip 5 includes an AI chip such as GPU / NPU (Neural Processor Unit) / TPU (Tensor Processing Unit).

[0099] Optionally, the number of first processor boards 1 is generally controlled within 16K boards, and the actual number of deployed first processor boards 1 can be set according to computing power requirements.

[0100] The present application provides a server system in which a first field programmable gate array chip and a first processor chip are packaged and interconnected, so as to give full play to their respective acceleration performance, and the communication delay between the two is minimized. For example, AI training and AI reasoning are usually completed in two systems, but the present application can be completed through the first processor board. The GPU / DPU / TPU realizes training acceleration, and the FPGA realizes reasoning acceleration, which greatly improves the acceleration efficiency. In addition, at least one first processor board is set without changing the original data center topology, which can greatly simplify the deployment in the data center, greatly reduce costs, reduce power consumption, make a reasonable layout of application computing power, and improve acceleration efficiency.

[0101] In some optional embodiments, the further comprising: at least one second processor board 6, the second processor board 6 being connected to the host server 2, and the second processor board 6 being connected to the at least one first processor board 1 via the switching network 3; wherein the second processor board 6 comprises a second field programmable gate array chip 7 and a second processor chip 8, and the second field programmable gate array chip 7 and the second processor chip 8 are packaged and interconnected;

[0102] The second field programmable gate array chip 7 is configured to obtain host data and receive request data sent by the second processor chip 8, generate a communication protocol message based on the processed host data and request data, and transmit the communication protocol message to the destination processor board through the switching network.

[0103] Optionally, a pooled resource pool has a host server 2 set as the pooled management of the resource pool. The acceleration card on the host server 2 can be the second processor board 6 connected through the PCIE interface on the second field programmable gate array chip 7, or an FPGA acceleration card or an ordinary network card can be used. Then, according to the application acceleration scenario, FPGA acceleration nodes, GPU acceleration nodes, etc. can also be added to the acceleration resource pool.

[0104] Optionally, if the original data center topology can be changed, the second processor board 6 can also be connected to the host server 2. If the original data center topology cannot be changed, only the first processor board 1 can be connected.

[0105] Optionally, the destination processor board may be the first processor board 1 or the second processor board 6 .

[0106] Optionally, the second field programmable gate array chip 7 and the second processor chip 8 have the same structures and data processing steps as the first field programmable gate array chip 4 and the first processor chip 5 .

[0107] The present application provides a server system in which a second processor board is connected to a host server, which can achieve local acceleration and reduce data transmission on the network.

[0108] In some optional implementations, the first field programmable gate array chip 4 and the first processor chip 5 are connected via a chip packaging method, and the second field programmable gate array chip 7 and the second processor chip 8 are connected via a chip packaging method.

[0109] Optionally, the core particle packaging method adopts chiplet (chiplet packaging technology, integrating multiple chips using advanced packaging technology) packaging technology, including UCIe (Universal Chiplet Interconnect Express, a universal chiplet packaging technology) or ACC (domestic chiplet packaging technology).

[0110] Optionally, FPGA and AI chips such as GPU / NPU / TPU (i.e., the first processor chip 5) are interconnected and integrated on a first processor chip 5 through chiplet technology.

[0111] The present application provides a server system in which a first field programmable gate array chip and a first processor chip, a second field programmable gate array chip and a second processor chip are respectively connected to different processor boards through chip packaging, thereby minimizing the communication delay between the processor chip and the field programmable gate array chip.

[0112] In some optional embodiments, as shown in FIG3 , the first processor chip 5 includes a storage module 9; the first field programmable gate array chip 4 includes: a bus interface module 10, a protocol processing module 11, a resource detection engine module 12, a resource transmission module 13, a memory controller 14, a memory mapping module 15 and an interface module 16; wherein,

[0113] The bus interface module 10 is connected to the protocol processing module 11 and is configured to transmit data to be processed to the protocol processing module 11 .

[0114] Optionally, the bus interface module 10 uses a MAC interface and / or a PCIE interface.

[0115] The protocol processing module 11 is connected to the resource detection engine module 12 , the memory mapping module 15 and the resource transmission module 13 , and is configured to parse the data to be processed, generate configuration data, and transmit the configuration data to the resource detection engine module 12 .

[0116] Optionally, the protocol processing module 11 adopts protocol_proc (a protocol program); the resource detection engine module 12 adopts a Sniffer (sniffer, also called data packet capture software); and the resource transmission module 13 adopts a DMA (Direct Memory Access) controller.

[0117] The resource detection engine module 12 is configured to determine the network address of the destination processor board based on the configuration data, and transmit the network address of the destination processor board to the protocol processing module 11 .

[0118] The memory mapping module 15 is configured to obtain request data from the processor chip, determine the memory address of the destination processor board based on the request data from the processor chip, and transmit the memory address of the destination processor board to the protocol processing module 11 .

[0119] Optionally, the memory mapping module 15 uses a lookup table stored in the FPGA.

[0120] The storage module 9 is configured to transmit the virtual memory address to the protocol processing module 11 through the interface module 16 , the memory controller 14 and the resource transmission module 13 in sequence.

[0121] Optionally, the storage module 9 adopts HBM (High Bandwidth Memory), DDR (Double Data Rate), GDDR (Graphics Double Data Rate); the interface module 16 adopts UCIe interface.

[0122] The protocol processing module 11 is also configured to encapsulate the network address (MAC / IP address) of the destination processor board, the memory address and the virtual memory address of the destination processor board, generate a communication protocol message, and transmit the communication protocol message to the switching network 3 through the bus interface module 10.

[0123] Optionally, as shown in Figure 4, the communication protocol message adopts the UDP (User Datagram Protocol, Ethernet message protocol) message format, wherein, in the Ethernet frame header, the IP header and the UDP header are the protocol fields specified by the UDP protocol message, generally the MAC address, and the IP address is used for routing forwarding; wherein, the destination xPU address is a virtual memory address, through which the GPU physical memory address is obtained (the internal memory mapping module 15 module also implements the conversion from virtual address to physical address) and is stored in the GPU memory, and the memory address of the destination processor board is also encapsulated in the communication protocol message.

[0124] Optionally, the destination MAC address, destination IP address, length / type, and IP header field are all obtained by the resource detection engine module 12 according to the table lookup method; the source MAC address and source IP address are generated by the data to be processed input by the bus interface module 10; the destination ID number and destination xPU address are both custom-generated by the first processor chip 5; the accelerated application data is generated by the first processor chip 5 after processing the data input by the field programmable gate array acceleration engine; when encapsulating the communication protocol message, the protocol processing module 11 adds a check bit at the end of the message to verify whether the current board is the destination processor board.

[0125] Optionally, the switching network determines the destination processor card by identifying the Ethernet frame header and / or IP header, and then transmits the communication protocol message to the destination processor card via the bus interface module 10 and the switching network 3 in sequence.

[0126] The present application provides a server system that implements memory mapping and memory management, data transmission between first processor boards, network communication protocol processing, and pooled resource management in a distributed system through a first field programmable gate array chip, thereby achieving efficient communication of the server system. The resource detection engine module, memory mapping module, and storage module are used to accurately obtain the destination processor board information. The protocol processing module encapsulates the destination processor board information into communication protocol messages. Communication interaction between server systems is achieved through a bus interface module and a switching network, ensuring efficient interconnection of the server systems.

[0127] In some optional implementations, the first processor chip 5 further includes: an acceleration processing module 17;

[0128] The acceleration processing module 17 is connected to the interface module 16 and is configured to obtain acceleration data and accelerate the processor running speed based on the acceleration data; wherein, the acceleration data is generated by parsing the data to be processed by the protocol processing module 11 and transmitted to the interface module 16 through the memory controller 14 and the resource transmission module 13.

[0129] Optionally, the acceleration processing module 17 is implemented using the functions of the GPU / DPU / TPU itself.

[0130] The server system provided in the present application improves the operating speed of the processor through an acceleration processing module, thereby improving the computing power acceleration efficiency. In addition, the acceleration data is transmitted to the interface module through a memory controller and a resource transmission module, ensuring that the storage rate of the interface module is consistent with the storage rate of the bus interface module.

[0131] In some optional implementations, the first field programmable gate array chip 4 further includes: a field programmable gate array acceleration engine 18;

[0132] The field programmable gate array acceleration engine 18 is connected to the protocol processing module 11 and the memory controller 14 , and is configured to pre-process the data to be processed and transmit the pre-processed data to the processor chip through the memory controller 14 .

[0133] Optionally, the field programmable gate array acceleration engine 18 is a user-reconfigurable acceleration engine that can be set to network acceleration, storage acceleration, and computing acceleration.

[0134] Optionally, the field programmable gate array acceleration engine 18 may also be a DPU (Data Processing Unit) or an IPU (Infrastructure Processing Unit).

[0135] The present application provides a server system that dynamically reconfigures a field programmable gate array acceleration engine according to application requirements, thereby improving application flexibility and scalability and enhancing computing power acceleration efficiency.

[0136] In some optional implementations, the resource detection engine module 12 includes:

[0137] The lookup table storage unit 19 is configured to match the configuration data with the configuration information table to determine the current processor board, and to match the current processor board with the network address table to determine the network address of the destination processor board.

[0138] Optionally, the network address table adopts a MAC (Media Access Control Address) / IP (Internet Protocol) table.

[0139] The present application provides a server system in which a lookup table storage unit sets a configuration information table and a network address table, thereby ensuring accurate judgment of the destination processor board and improving application flexibility and scalability.

[0140] In some optional embodiments, the lookup table storage unit 19 is also configured to broadcast the status information of the current first processor board 1, and receive status messages of other first processor boards 1, and update the configuration information table and the network address table based on the status messages of other first processor boards 1.

[0141] Optionally, the lookup table storage unit 19 broadcasts the current status information of the first processor board 1, such as interface status, memory resource usage, board temperature, board abnormal status and other information; at the same time, it receives the status message broadcast by the first processor board 1, parses it and updates its own routing table (including configuration information table and network address table), and for a faulty board, deletes the ID of the faulty board in the routing table to ensure that the communication protocol message will not be sent to the faulty board.

[0142] The present application provides a server system that dynamically monitors resource usage of the server system through a lookup table storage unit, effectively utilizes GPU resources, and improves the reliability of the server system by bypassing faulty processor boards.

[0143] In some optional implementations, the interface module 16 includes: an initialization configuration unit 20;

[0144] The initialization configuration unit 20 is configured to obtain initialization configuration information and perform link initialization configuration, space initialization configuration and internal register configuration based on the initialization configuration information.

[0145] Optionally, the initialization configuration unit 20 performs initialization training of the UCIe link, initialization configuration of the space, and initialization configuration of the internal register according to pre-stored initialization configuration data.

[0146] The present application provides a server system in which an initialization configuration unit performs link initialization configuration, space initialization configuration, and internal register configuration, thereby ensuring normal data transmission between the first field programmable gate array chip and the first processor chip 5, and ensuring normal calculation and processing of data by the first field programmable gate array chip.

[0147] In some optional embodiments, the bus interface module 10 is also configured to obtain custom configuration information and transmit the custom configuration information to the resource detection engine module 12 and the memory mapping module 15; wherein the resource detection engine module 12 initializes the configuration information table and the network address table based on the custom configuration information, and the memory mapping module 15 initializes the configuration memory queue.

[0148] Optionally, the host server 2 transmits the custom configuration information to the bus interface module 10, and a unique ID number is assigned to the first processor board 1 based on the custom configuration information. The resource detection engine module 12 defines the initialization configuration of the lookup table, and the memory mapping module 15 initializes the configuration memory queue.

[0149] The present application provides a server system that uses custom configuration information to configure relevant data, laying the foundation for subsequent data processing and communication interaction in the first field programmable gate array chip, thereby improving application flexibility and scalability.

[0150] In some optional implementations, the bus interface module 10 includes a MAC interface 21 and a PCIE interface 22; wherein,

[0151] The MAC interface 21 is connected to the switching network 3 and is configured to transmit the communication protocol message to the first processor board 1 or the second processor board 6 through the switching network 3 .

[0152] The PCIE interface 22 is connected to the host server 2 and the switching network 3 respectively, and is configured to transmit host data to the second processor board 6 .

[0153] Optionally, the PCIE interface of the first field programmable gate array chip 4 (the PCIE interface 22 in this topology only has a power supply function) is deployed on the first processor board 1 without a CPU, and is connected to the switching network 3 through the network interface (i.e., the PCIE interface 22) to form an acceleration resource pool.

[0154] Optionally, the second field programmable gate array chip 7 is plugged into the host server 2 through a PCIE interface (the PCIE interface 22 in this topology has an interface communication function).

[0155] Optionally, the PCIE interface function in the first processor board 1 is in a power down state in the BOX deployment mode, and the PCIE interface function inside the first field programmable gate array chip 4 and the second field programmable gate array chip 7 is turned off to save power consumption. When deployed in the server system, the PCIE interface 22 and the MAC interface 21 are effective at the same time. The host data passes through the PCIE interface 22, and the network data (i.e., the communication protocol message) passes through the MAC interface 21, thereby realizing the communication between the second processor board 6 or the first processor board 1 and the host or the network.

[0156] The present application provides a server system that connects a bus interface module with different devices, differentiates transmission modes, ensures efficient data transmission, and avoids congestion of transmission queues.

[0157] The communication method of the server system is described through the following optional embodiments.

[0158] Example 1:

[0159] As shown in FIG5 , the first processor chip includes an acceleration processing module and a storage module; the first field programmable gate array chip includes: a bus interface module, a protocol processing module, a resource detection engine module, a resource transmission module, a memory controller, a memory mapping module, and an interface module;

[0160] The protocol_proc module (protocol processing module) parses or encapsulates network transmission protocol messages, sends configuration data to the Sniffer module, and sends acceleration data to the FPGA's memory controller (memory controller) through DMA.

[0161] The Memory Controller stores the acceleration data and transmits it to the processor chip (i.e., GPU / DPU / TPU) through the UCIe Root Port module (interface module).

[0162] The Sniffer module (resource detection engine module) stores each processor board's unique ID number (identity document) and multiple software-definable lookup tables through a LUT (Look-Up-Table). The lookup table contents can be retrieved based on the ID number, such as searching the configuration table to obtain pooling configuration information, searching the MAC (Media Access Control Address) / IP (Internet Protocol) table to obtain the MAC and IP addresses of the target processor board, and searching the memory address table to obtain the DMA (Direct Memory Access) address.

[0163] At the same time, the Sniffer module collects memory information from each processor chip in the server system and automatically encapsulates local data into network protocol messages based on the usage of each processor chip. The messages are then routed to the destination processor card via the switching network, thus achieving active management of the pooled platform resources that decouples the CPU during operation.

[0164] The Sniffer module also broadcasts local memory information and configuration information;

[0165] The memory map module manages DMA queue information for DMA operations. DMA operations include DMA writes and DMA reads. DMA writes send xPU memory data to the network interface via DMA writes, and then to the remote xPU. DMA reads transfer data obtained from the remote xPU to the FPGA via the network interface and write it back to the xPU memory via DMA reads.

[0166] The data after DMA operation is used by xPU to apply accelerated processing.

[0167] The UCIe Root Port module receives the configuration information from the Sniffer module to complete the initial configuration of the processor board and obtains the DMA queue information from the Memory Map module for DMA operations.

[0168] The FPGA acceleration engine module is a user-reconfigurable acceleration engine that can be set as network acceleration, storage acceleration, and computing acceleration.

[0169] Example 2:

[0170] As shown in FIG6 , the first processor chip includes an acceleration processing module and a storage module; the first field programmable gate array chip includes a bus interface module, a protocol processing module, a resource detection engine module, a resource transmission module, a memory controller, a memory mapping module, and an interface module; the memory controller is connected to the external storage module, and the external storage module uses DDR memory (double data rate synchronous dynamic random access memory);

[0171] The protocol_proc module (protocol processing module) parses or encapsulates network transmission protocol messages, sends configuration data to the Sniffer module, and sends acceleration data to the FPGA's memory controller (memory controller) through DMA.

[0172] The Memory Controller transfers the accelerated data to the DDR Memory (Double Data Rate Memory) for storage, and transmits the accelerated data to the processor chip (i.e., GPU / DPU / TPU) through the UCIe Root Port module (interface module).

[0173] The Sniffer module (resource detection engine module) stores each processor board's unique ID number (identity document) and multiple software-definable lookup tables. Based on the ID number, the Sniffer module retrieves the table contents, such as pooling configuration information from the configuration table, MAC (Media Access Control Address) / IP (Internet Protocol) table for the target processor board's MAC and IP addresses, and memory address table for DMA (Direct Memory Access) addresses.

[0174] At the same time, the Sniffer module collects memory information from each processor chip in the server system and automatically encapsulates local data into network protocol messages based on the usage of each processor chip. The messages are then routed to the destination processor card via the switching network, thus achieving active management of the pooled platform resources that decouples the CPU during operation.

[0175] The Sniffer module also broadcasts local memory information and configuration information;

[0176] The memory map module manages DMA queue information for DMA operations;

[0177] The UCIe Root Port module (interface module) receives the configuration information from the Sniffer module to complete the initial configuration of the processor board and obtains the DMA queue information from the Memory Map module for DMA operations.

[0178] The FPGA acceleration engine module is a user-reconfigurable acceleration engine that can be set as network acceleration, storage acceleration, and computing acceleration.

[0179] Example 3:

[0180] As shown in FIG7 , the first processor chip includes an acceleration processing module and a storage module; the first field programmable gate array chip includes a bus interface module, a protocol processing module, a resource detection engine module, a resource transmission module, a memory controller, a memory mapping module, and an interface module; the memory controller is connected to the external storage module, and the external storage module uses FPGA memory; the storage module uses GPU memory;

[0181] The protocol_proc module (protocol processing module) parses or encapsulates network transmission protocol messages, sends configuration data to the Sniffer module, and sends acceleration data to the FPGA's memory controller (memory controller) through DMA.

[0182] The Memory Controller transfers the accelerated data to the FPGA Memory for storage, and then transfers the accelerated data to the GPU Memory in the processor chip through the UCIe Root Port module (interface module) for storage.

[0183] GPU Memory transfers the virtual memory address to the protocol_proc module through the UCIe Root Port module, Memory Controller, and DMA (Direct Memory Access, data transfer module);

[0184] The Sniffer module (resource detection engine module) stores each processor board's unique ID number (identity document) and multiple software-definable lookup tables. Based on the ID number, the Sniffer module retrieves the table contents, such as pooling configuration information from the configuration table, MAC (Media Access Control Address) / IP (Internet Protocol) table for the target processor board's MAC and IP addresses, and memory address table for DMA (Direct Memory Access) addresses.

[0185] At the same time, the Sniffer module collects memory information from each processor chip in the server system and automatically encapsulates local data into network protocol messages based on the usage of each processor chip. The messages are then routed to the destination processor card via the switching network, thus achieving active management of the pooled platform resources that decouples the CPU during operation.

[0186] The Sniffer module also broadcasts local memory information and configuration information;

[0187] The memory map module manages DMA queue information for DMA operations;

[0188] The UCIe Root Port module receives the configuration information from the Sniffer module to complete the initial configuration of the processor board and obtains the DMA queue information from the Memory Map module for DMA operations.

[0189] The FPGA acceleration engine module is a user-reconfigurable acceleration engine that can be set as network acceleration, storage acceleration, and computing acceleration.

[0190] Example 4:

[0191] As shown in Figure 8, taking neural network model training as an example, assuming that this neural network model training requires three xPU boards (i.e., the first processor board and the second processor board), the number of xPU boards in the pooling platform can be flexibly expanded according to the model size; xPU board-1 is inserted into the host server and also serves as the management node, and the other two xPU boards (i.e., xPU board-2 and xPU board-3) are in the BOX (machine-card decoupling) server. The three xPU boards accelerate the neural network model training through pipeline parallelization;

[0192] The bus interface module, protocol processing module, resource detection engine module, resource transmission module, memory controller, memory mapping module and interface module are used to implement static logic, and the FPGA acceleration engine is used to implement training data preprocessing. Among them, the FPGA static logic includes xPU initialization configuration (firmware burning, configuration space initialization, etc.), xPU memory address mapping management, xPU DMA data transmission, network protocol message processing, pooling function management and network card function. The training data preprocessing and data synchronization processing modules are user-reconfigurable acceleration engines used to implement model training preprocessing and result synchronization.

[0193] The communication process of the xPU pooling platform to accelerate model training is as follows:

[0194] 1. Initialization process:

[0195] 1. The host server initializes and configures the FPGAs of the three xPU boards, assigns unique ID numbers to each of them, initializes and configures the three software-defined lookup tables within the Sniffer module, and initializes and configures the xPU DMA queues in the Memory Map module. The initialization configuration of xPU Board-1 is completed through the PCIE interface, and the initialization configuration of the other two xPU boards is completed through a custom network protocol. Specifically, the initialization configuration of xPU Board-2 and xPU Board-3 is completed through the init (initialization process) in the UCIe Root Port module.

[0196] 2. The FPGAs of the three xPU boards, combined with the configuration information of the Sniffer module, complete the initialization configuration of the xPU through the UCIe Root Port module, including loading the xPU firmware and configuring the xPU configuration space;

[0197] 3. The Sniffer module periodically broadcasts the real-time memory status information of the local xPU and receives the xPU memory information of the remote xPU board of the pooling platform. It independently selects the target xPU based on the xPU resource status of the pooling platform.

[0198] 2. Data processing process:

[0199] 4. The host server sends the data to be processed to the FPGA acceleration engine - training data preprocessing module of xPU board-1 through the PCIE interface for preprocessing of the training data, such as data modification and data analysis;

[0200] 5. After completing preprocessing, FPGA-1's acceleration engine sends the data to the xPU through its DMA engine for Model-1 calculation. After the calculation is complete, xPU-1 sends the data to FPGA-1 through its DMA engine. The Sniffer module and memory-map module obtain the memory address and board MAC / IP address of the destination xPU through a table lookup, encapsulate the data into a custom protocol message format, and send it to the switching network.

[0201] 6. The switching network routes the data to the destination xPU board-2 based on the MAC address.

[0202] 7. xPU-2 parses the network message data and sends it to the acceleration engine of FPGA-2 for training data preprocessing. After processing, it is sent to xPU-2 via the xPU DMA engine for model-2 calculation.

[0203] 8. After xPU-2 completes the calculation, it sends the data back to FPGA-2 via DMA. After being processed by the internal processing module, it is encapsulated into a network protocol message and sent to the switching network.

[0204] 9. The switching network routes the data to the xPU-3 based on the destination MAC address. FPGA-3 parses the network message data and sends it to the FPGA acceleration engine for data synchronization processing. After processing, it is sent to the xPU-3 for final calculation.

[0205] 10. After xPU-3 completes the final calculation, the data is encapsulated in a network protocol message by FPGA-3 and sent to the switching network. The switching network routes it to xPU board-1 based on the destination MAC address.

[0206] 11. After parsing, the FPGA of xPU board-1 directly sends the data to the host through the PCIE interface, completing the accelerated calculation of the entire training model.

[0207] In the above embodiment 4, the training model data is processed by three xPU boards, including FPGA acceleration processing and xPU acceleration processing, maximizing the use of the acceleration processor. The FPGA and xPU are on the same board and interconnected through the chiplet low-latency interface bus, which has very low latency, efficiently completes the acceleration processing, and is easy to deploy. In addition, the real-time resources of the pooled platform can be obtained through the xPU Sniffer module, improving the reliability of the pooled platform by bypassing the faulty board.

[0208] This embodiment further provides a communication method for a server system, which is applied to the server system provided in the above embodiment, as shown in FIG9 , and includes:

[0209] Step S901: The host server transmits host data to the first field programmable gate array chip through the switching network;

[0210] Step S902: The first field programmable gate array chip processes the host data and receives the request data sent by the first processor chip, generates a communication protocol message based on the processed host data and the request data, and transmits the communication protocol message to the destination processor board through the switching network.

[0211] In some optional implementations, step S902 includes:

[0212] The bus interface module transmits the data to be processed to the protocol processing module;

[0213] The protocol processing module parses the data to be processed, generates configuration data, and transmits the configuration data to the resource detection engine module;

[0214] The resource detection engine module determines the network address of the destination processor board based on the configuration data, and transmits the network address of the destination processor board to the protocol processing module;

[0215] The memory mapping module obtains the request data of the processor chip, determines the memory address of the destination processor board based on the request data of the processor chip, and transmits the memory address of the destination processor board to the protocol processing module;

[0216] The storage module transmits the virtual memory address to the protocol processing module through the interface module, the memory controller and the resource transmission module in sequence;

[0217] The protocol processing module encapsulates the network address of the destination processor board, the memory address and the virtual memory address of the destination processor board, generates a communication protocol message, and transmits the communication protocol message to the switching network through the bus interface module.

[0218] Optionally, the communication protocol message adopts the UDP message format, wherein the IP header and UDP header in the Ethernet frame header are the protocol fields specified by the UDP protocol message, generally the MAC address, and the IP address is used for routing forwarding; wherein, the destination xPU address is the virtual memory address, through which the GPU physical memory address is obtained (the internal memory mapping module also implements the conversion from virtual address to physical address) and stored in the GPU memory, and the memory address of the destination processor board is also encapsulated in the communication protocol message.

[0219] The present application provides a communication method for a server system, which utilizes a resource detection engine module, a memory mapping module, and a storage module to accurately obtain the information of a destination processor board. The protocol processing module encapsulates the information of the destination processor board into a communication protocol message, and realizes communication interaction between server systems through a bus interface module and a switching network, thereby ensuring efficient interconnection of the server systems.

[0220] In some optional embodiments, the method further includes:

[0221] The protocol processing module parses the data to be processed to generate acceleration data, and transmits the acceleration data to the acceleration processing module through the resource transmission module, memory controller and interface module in sequence;

[0222] The acceleration processing module accelerates the operating speed of the processor based on the acceleration data.

[0223] In some optional embodiments, the method further includes:

[0224] The field programmable gate array acceleration engine pre-processes the data to be processed and transmits the pre-processed data to the processor chip through the memory controller.

[0225] Optionally, the field programmable gate array acceleration engine is a user-reconfigurable acceleration engine that can be set to network acceleration, storage acceleration, and computing acceleration.

[0226] In some optional implementations, the resource detection engine module determines the network address of the destination processor board based on the configuration data, including:

[0227] The lookup table storage unit matches the configuration data with the configuration information table to determine the current processor board, and matches the current processor board with the network address table to determine the network address of the destination processor board.

[0228] Optionally, the network address table adopts a MAC (Media Access Control Address) / IP (Internet Protocol) table.

[0229] In some optional embodiments, the method further includes:

[0230] The lookup table storage unit broadcasts the status information of the current first processor board, receives status messages of other first processor boards, and updates the configuration information table and the network address table based on the status messages of other first processor boards.

[0231] In some optional embodiments, the method further includes:

[0232] The initialization configuration unit obtains initialization configuration information, and performs link initialization configuration, space initialization configuration, and internal register configuration based on the initialization configuration information.

[0233] Optionally, the initialization configuration unit performs initialization training of the UCIe link, initialization configuration of the space, and initialization configuration of the internal register according to pre-stored initialization configuration data.

[0234] In some optional embodiments, the method further includes:

[0235] The bus interface module obtains the custom configuration information and transmits the custom configuration information to the resource detection engine module and the memory mapping module; wherein the resource detection engine module initializes the configuration information table and the network address table based on the custom configuration information, and the memory mapping module initializes the configuration memory queue.

[0236] Optionally, the custom configuration information is transmitted from the host server to the bus interface module, a unique ID number is assigned to the first processor board based on the custom configuration information, the resource detection engine module defines the initialization configuration of the lookup table, and the memory mapping module initializes the configuration memory queue.

[0237] In some optional embodiments, the method further includes:

[0238] The MAC interface transmits the communication protocol message to the first processor board or the second processor board through the switching network;

[0239] The PCIE interface transmits the host data to the second processor board.

[0240] Optionally, the PCIE interface function in the first processor board is in a power down state in BOX deployment mode, shutting down the PCIE interface function inside the first field programmable gate array chip and the second field programmable gate array chip to save power consumption. When deployed in a server system, the PCIE interface and the MAC interface are effective at the same time, the host data passes through the PCIE interface, and the network data (i.e., the communication protocol message) passes through the MAC interface, thereby realizing communication between the second processor board or the first processor board and the host or the network.

[0241] The communication method of a server system in this embodiment is applied to a server system in the embodiment shown in FIG2 , so the implementation of step S901 and step S903 can refer to the corresponding description of the embodiment shown in FIG2 in the previous text, and will not be repeated here.

[0242] It can be understood that the functions and beneficial effects of the method of this embodiment correspond to the functions and beneficial effects of a server system in the embodiment shown in FIG2 , and will not be described in detail here.

[0243] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of this application.

[0244] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the working processes of the above-described systems, devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0245] In the several embodiments provided in the embodiments of the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0246] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0247] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0248] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the relevant technology or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a non-volatile readable storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned non-volatile readable storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc., various non-volatile readable storage media that can store program code.

[0249] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A server system, characterized in that: include: At least one first processor board and a host server, wherein the at least one first processor board is communicatively connected to the host server via a switching network; wherein the first processor board comprises a first field programmable gate array chip and a first processor chip; the first field programmable gate array chip and the first processor chip are packaged and interconnected; The host server is configured to transmit host data to the first field programmable gate array chip through the switching network; The first field programmable gate array chip is configured to process the host data and receive request data sent by the first processor chip, generate a communication protocol message based on the processed host data and the request data, and transmit the communication protocol message to the destination processor board through the switching network.

2. The server system according to claim 1, characterized in that: Also includes: At least one second processor board, the second processor board is connected to the host server, and the second processor board is connected to the at least one first processor board through the switching network; wherein the second processor board includes a second field programmable gate array chip and a second processor chip, and the second field programmable gate array chip and the second processor chip are packaged and interconnected; The second field programmable gate array chip is configured to obtain the host data and receive the request data sent by the second processor chip, generate a communication protocol message based on the processed host data and the request data, and transmit the communication protocol message to the destination processor board through the switching network.

3. The server system according to claim 2, characterized in that: The first field programmable gate array chip and the first processor chip are connected via a chip packaging method, and the second field programmable gate array chip and the second processor chip are connected via a chip packaging method.

4. The server system according to claim 3, characterized in that: The chip packaging method includes UCIe or ACC.

5. The server system according to claim 2, characterized in that: The first processor chip includes a storage module; the first field programmable gate array chip includes: a bus interface module, a protocol processing module, a resource detection engine module, a resource transmission module, a memory controller, a memory mapping module and an interface module; wherein, The bus interface module is connected to the protocol processing module and is configured to transmit the data to be processed to the protocol processing module; The protocol processing module is connected to the resource detection engine module, the memory mapping module and the resource transmission module, and is configured to parse the data to be processed, generate configuration data, and transmit the configuration data to the resource detection engine module; The resource detection engine module is configured to determine the network address of the destination processor board based on the configuration data, and transmit the network address of the destination processor board to the protocol processing module; The memory mapping module is configured to obtain request data of the processor chip, determine the memory address of the destination processor board based on the request data of the processor chip, and transmit the memory address of the destination processor board to the protocol processing module; The storage module is configured to transmit the virtual memory address to the protocol processing module in sequence through the interface module, the memory controller and the resource transmission module; The protocol processing module is also configured to encapsulate the network address of the destination processor board, the memory address of the destination processor board and the virtual memory address, generate a communication protocol message, and transmit the communication protocol message to the destination processor board via the bus interface module and the switching network in sequence.

6. The server system according to claim 5, characterized in that: The first processor chip further includes: an acceleration processing module; The acceleration processing module is connected to the interface module and is configured to obtain acceleration data and accelerate the processor running speed based on the acceleration data; wherein the acceleration data is generated by the protocol processing module by parsing the data to be processed, and is transmitted to the interface module through the memory controller and the resource transmission module.

7. The server system according to claim 5, characterized in that: The first field programmable gate array chip further includes: a field programmable gate array acceleration engine; The field programmable gate array acceleration engine is connected to the protocol processing module and the memory controller, and is configured to pre-process the data to be processed and transmit the pre-processed data to be processed to the processor chip through the memory controller.

8. The server system according to claim 5, characterized in that: The resource detection engine module includes: The lookup table storage unit is configured to match the configuration data with the configuration information table to determine the current processor board, and to match the current processor board with the network address table to determine the network address of the destination processor board.

9. The server system according to claim 8, characterized in that: The lookup table storage unit is also configured to broadcast the status information of the current first processor board, receive status messages of other first processor boards, and update the configuration information table and the network address table based on the status messages of other first processor boards.

10. The server system according to claim 5, characterized in that: The interface module includes: an initialization configuration unit; The initialization configuration unit is configured to obtain initialization configuration information, and perform link initialization configuration, space initialization configuration and internal register configuration based on the initialization configuration information.

11. The server system according to claim 8, characterized in that: The bus interface module is also configured to obtain custom configuration information and transmit the custom configuration information to the resource detection engine module and the memory mapping module; wherein the resource detection engine module initializes the configuration information table and the network address table based on the custom configuration information, and the memory mapping module initializes the configuration memory queue.

12. The server system according to claim 5, characterized in that: The bus interface module includes a MAC interface and a PCIE interface; wherein, The MAC interface is connected to the switching network and is configured to transmit the communication protocol message to the first processor card or the second processor card through the switching network; The PCIE interface is connected to the host server and the switching network respectively, and is configured to transmit the host data to the second processor board.

13. A communication method of a server system, characterized in that: Applied to the server system according to any one of claims 1 to 12, the method comprises: The host server transmits the host data to the first field programmable gate array chip through the switching network; The first field programmable gate array chip processes the host data and receives request data sent by the first processor chip, generates a communication protocol message based on the processed host data and the request data, and transmits the communication protocol message to the destination processor board through the switching network.

14. The method according to claim 13, characterized in that The first field programmable gate array chip processes the host data, receives request data sent by the first processor chip, generates a communication protocol message based on the processed host data and the request data, and transmits the communication protocol message to the destination processor board through the switching network, including: The bus interface module transmits the data to be processed to the protocol processing module; The protocol processing module parses the data to be processed, generates configuration data, and transmits the configuration data to the resource detection engine module; The resource detection engine module determines the network address of the destination processor board based on the configuration data, and transmits the network address of the destination processor board to the protocol processing module; The memory mapping module obtains the request data of the processor chip, determines the memory address of the destination processor board based on the request data of the processor chip, and transmits the memory address of the destination processor board to the protocol processing module; The storage module transmits the virtual memory address to the protocol processing module through the interface module, the memory controller and the resource transmission module in sequence; The protocol processing module encapsulates the network address of the destination processor board, the memory address of the destination processor board and the virtual memory address, generates a communication protocol message, and transmits the communication protocol message to the switching network through the bus interface module.

15. The method according to claim 14, characterized in that Also includes: The protocol processing module parses the data to be processed to generate acceleration data, and transmits the acceleration data to the acceleration processing module through the resource transmission module, the memory controller and the interface module in sequence; The acceleration processing module accelerates the processor operation speed based on the acceleration data.

16. The method according to claim 14, characterized in that Also includes: The field programmable gate array acceleration engine pre-processes the data to be processed, and transmits the pre-processed data to be processed to the processor chip through the memory controller.

17. The method according to claim 14, characterized in that The resource detection engine module determines the network address of the destination processor board based on the configuration data, including: The lookup table storage unit matches the configuration data with the configuration information table to determine the current processor board, and matches the current processor board with the network address table to determine the network address of the destination processor board.

18. The method according to claim 17, characterized in that Also includes: The lookup table storage unit broadcasts the status information of the current first processor board, receives status messages of other first processor boards, and updates the configuration information table and the network address table based on the status messages of the other first processor boards.

19. The method according to claim 14, characterized in that Also includes: The initialization configuration unit obtains initialization configuration information, and performs link initialization configuration, space initialization configuration and internal register configuration based on the initialization configuration information.

20. The method according to claim 17, characterized in that Also includes: The bus interface module obtains custom configuration information and transmits the custom configuration information to the resource detection engine module and the memory mapping module; wherein the resource detection engine module initializes the configuration information table and the network address table based on the custom configuration information, and the memory mapping module initializes the configuration memory queue.

21. The method according to claim 14, characterized in that Also includes: The MAC interface transmits the communication protocol message to the first processor card or the second processor card through the switching network; The PCIE interface transmits the host data to the second processor board.

22. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 13 to 21 when executed by a processor.

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