Combined passivation back contact solar cell having front wide band gap doping, and preparation method therefor

Abstract

The present disclosure relates to the technical field of back contact solar cells, and in particular relates to a combined passivation back contact solar cell having front wide band gap doping, and a preparation method therefor. The solar cell comprises a silicon wafer, and a first semiconductor layer, a second semiconductor layer and a third semiconductor layer arranged on the front face of the silicon wafer. The third semiconductor layer comprises a second tunneling oxide layer and a third doped polycrystalline silicon layer, provided in sequence from inside to outside. The third doped polycrystalline silicon layer is a doped polycrystalline silicon layer containing a first doping element and a second doping element, the first doping element being phosphorus, and the second doping element comprising any one of carbon and oxygen. Furthermore, the band gap width of the third doped polycrystalline silicon layer is ≥1.6eV. The present disclosure, while ensuring a passivation effect, can greatly decrease device investment costs, greatly reduce parasitic absorption of a third semiconductor layer on the front surface of a cell, and increase short-circuit current of the cell, thereby increasing cell conversion efficiency.

Description

Front wide bandgap doped combined passivated back contact solar cell and preparation method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to Chinese patent application No. 2023108148190 filed with the Patent Office of China on July 5, 2023, entitled “Front-side wide bandgap doped jointly passivated back contact solar cell and its preparation method,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0003] The present disclosure belongs to the technical field of back-contact solar cells, and in particular relates to a front-side wide-bandgap-doped combined passivation back-contact solar cell and a preparation method thereof. Background Art

[0004] Currently, back-contact heterojunction solar cells generally require the preparation of a silicon wafer with a polished backside and textured frontside. A first semiconductor layer and a second semiconductor layer are then formed on the backside of the wafer, and a third semiconductor layer is formed on the frontside. The third semiconductor layer comprises a front-side passivation layer and an anti-reflection layer. The front-side passivation layer comprises an intrinsic amorphous silicon layer and an N-type doped amorphous or microcrystalline silicon layer. The preparation process is relatively long, and the first semiconductor layer on the backside and the third semiconductor layer on the frontside are composed of an intrinsic amorphous silicon layer and an N-type doped amorphous or microcrystalline silicon layer.

[0005] However, since the third semiconductor layer consists of an intrinsic amorphous silicon layer and an N-type doped amorphous / microcrystalline silicon layer, good passivation is achieved primarily through a large amount of hydrogen. When the temperature exceeds 250°C, hydrogen will outgas significantly, thus affecting the passivation effect. Therefore, the intrinsic amorphous silicon layer and the N-type doped amorphous / microcrystalline silicon layer are generally formed separately using plate-type PECVD coating. Plate-type PECVD uses radio frequency power ignition and deposition at low temperatures (≈200°C). The radio frequency power supply has strict requirements for cavity shielding and grounding, making plate-type PECVD equipment very expensive. Therefore, current back-contact cells suffer from long process flows and high equipment investment. Furthermore, the bandgap width of the amorphous silicon on the front side of the cell is generally between 1.5 and 1.7 eV, but the absorption coefficient is very large, approximately 10 times that of single-crystal or multicrystalline silicon. This results in significant parasitic absorption, which reduces the silicon wafer's light absorption efficiency, thereby reducing the cell's short-circuit current and, in turn, the cell's conversion efficiency.

[0006] Summary of the Invention

[0007] The purpose of the present disclosure is to overcome the defects of conventional battery structures in the prior art, such as the need for multiple plate-type PECVD coatings on the semiconductor layer, which results in high equipment investment, very large parasitic absorption of amorphous silicon on the front side of the battery, and reduced battery conversion efficiency, and to provide a front-side wide-bandgap-doped combined passivated back-contact solar cell and a preparation method thereof. The present disclosure can significantly reduce the equipment investment cost while ensuring the passivation effect, significantly reduce the parasitic absorption of the third semiconductor layer on the front side of the battery, increase the short-circuit current of the battery, and thus improve the battery conversion efficiency.

[0008] To achieve the above objectives, in a first aspect, the present disclosure provides a front-side wide-bandgap doped combined passivated back-contact solar cell, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer arranged on the back side of the silicon wafer, and a third semiconductor layer arranged on the front side of the silicon wafer; the first semiconductor layer comprises a first tunneling oxide layer and a first doped polysilicon layer arranged in sequence from the inside to the outside, the second semiconductor layer comprises an intrinsic amorphous silicon layer and a second doped silicon layer arranged in sequence from the inside to the outside, the third semiconductor layer comprises a second tunneling oxide layer and a third doped polysilicon layer arranged in sequence from the inside to the outside, the third doped polysilicon layer is a doped polysilicon layer containing a first doping element and a second doping element, the first doping element is phosphorus, the second doping element comprises any one of carbon and oxygen, and the bandgap width of the third doped polysilicon layer is ≥1.6 eV, the thickness ratio of the third doped polysilicon layer to the first doped polysilicon layer is 2%-10%, and the thickness of the third doped polysilicon layer is 4-15 nm.

[0009] In some optional embodiments of the present disclosure, the bandgap width of the third doped polysilicon layer is 1.6-2.2 eV.

[0010] In some optional embodiments of the present disclosure, the thickness of the third doped polysilicon layer is 5-15 nm.

[0011] In some optional embodiments of the present disclosure, the effective doping concentration of the second doping element in the third doped polysilicon layer is 1e19-4e21 cm-3, and the effective doping concentration of the first doping element is 1e19-9e20 cm-3.

[0012] In some optional embodiments of the present disclosure, the first doped polysilicon layer and the third doped polysilicon layer are both N-type, and the second doped silicon layer is P-type.

[0013] In some more optional embodiments of the present disclosure, the third doped polysilicon layer is a carbon-doped N-type doped polysilicon layer.

[0014] In some optional embodiments of the present disclosure, a second semiconductor opening region is opened on the first semiconductor layer, the back side of the silicon wafer where the second semiconductor opening region is located is a textured surface, and the front side of the silicon wafer is a textured surface.

[0015] In the present disclosure, a first semiconductor opening region is opened on the second semiconductor layer, and the first semiconductor opening region and the second semiconductor opening region are arranged at intervals.

[0016] In some optional embodiments of the present disclosure, the thickness of the first tunneling oxide layer and the second tunneling oxide layer is 0.5-1.25:1, and the thickness of the second tunneling oxide layer is 1-3 nm.

[0017] In some optional embodiments of the present disclosure, the effective doping concentration of the first doped polysilicon layer is 1e19-9e20 cm-3.

[0018] In some optional embodiments of the present disclosure, the back side of the silicon wafer is divided into a first emitter region where the first semiconductor layer contacts the silicon wafer, a second emitter region where the second semiconductor layer contacts the silicon wafer, and a transition region between the first emitter region and the second emitter region. The first semiconductor layer and the second semiconductor layer are sequentially arranged in the transition region from the inside out. More optionally, the first semiconductor layer and the second semiconductor layer are in direct contact with each other.

[0019] In some embodiments of the present disclosure, the combined passivated back contact solar cell further includes: a transparent conductive film, which is arranged on the outer surface of the first semiconductor layer or the second semiconductor layer located in the outermost layer in the first emitter region, the second emitter region and the transition region respectively, and an insulating groove is opened in the portion of the transparent conductive film in the transition region.

[0020] In some embodiments of the present disclosure, the combined passivation back contact solar cell further includes an anti-reflection layer disposed on an outer surface of the third semiconductor layer.

[0021] In some embodiments of the present disclosure, the combined passivation back contact solar cell further includes: a metal electrode, which is arranged in the first emitter region and the second emitter region and is located on the outer surface of the corresponding transparent conductive film.

[0022] In a second aspect, the present disclosure provides a method for preparing a combined passivated back contact solar cell, wherein the combined passivated back contact solar cell is the combined passivated back contact solar cell with a front wide bandgap doping as described in the first aspect.

[0023] The preparation method disclosed herein comprises the following steps:

[0024] S1, provide silicon wafers;

[0025] S2, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer;

[0026] S3, opening the back surface obtained in S2, removing the first semiconductor layer and the mask layer, and forming a second semiconductor opening region;

[0027] S4, cleaning the back surface obtained in S3 to remove the remaining first semiconductor layer and mask layer in the second semiconductor opening area;

[0028] S5. Forming a third semiconductor layer on the front side of the silicon wafer obtained in S4, and then cleaning and removing the plating on the back side of the silicon wafer; the third semiconductor layer is formed by in-situ doping deposition by tubular PECVD followed by annealing, or by doping the first doping element and the second doping element by LPCVD deposition;

[0029] S6. Depositing a second semiconductor layer on the back side of the silicon wafer obtained in S5.

[0030] In some embodiments of the present disclosure, in S5, the process of forming the third semiconductor layer by tubular PECVD in-situ doping deposition followed by annealing includes a first stage, a second stage, and annealing.

[0031] Optionally, in the first stage, a first gas comprising silane and nitrous oxide is introduced, a glow light is turned on, and a second tunneling oxide layer is formed by chemical reaction deposition. Optionally, the reaction temperature in the first stage is 400-450°C, the reaction pressure is 100-2000 mtorr, and the reaction time is 10-60 seconds.

[0032] More optionally, the process then proceeds to a second stage, in which a second gas comprising silane, a first doping element source gas, hydrogen, and a second doping element source gas is introduced, the glow light is activated, and a third doped polysilicon layer is formed by chemical reaction deposition. Optionally, the reaction temperature in the second stage is 400-450°C, the reaction pressure is 100-2000 mtorr, and the reaction time is 30-200 seconds. Optionally, the second doping element source gas comprises methane or carbon dioxide, and the first doping element source gas comprises phosphine.

[0033] More optionally, annealing is performed after the above deposition is completed, with an annealing pressure of 2000 mtorr-1 atm, an annealing temperature of 750-900° C., and an annealing time of 5-60 min.

[0034] In some embodiments of the present disclosure, in S5, the process of forming the third semiconductor layer by doping the first doping element and the second doping element after LPCVD deposition includes: first depositing the second tunneling oxide layer and the intrinsic polysilicon layer; then ion implanting the first doping element and the second doping element, or then diffusing the first doping element and the second doping element.

[0035] In some embodiments of the present disclosure, in S2, the process of forming the first semiconductor layer includes: first forming a first tunneling oxide layer by a wet or dry method, and then forming a first doped polysilicon layer by any one of the following methods: depositing an intrinsic polysilicon layer by LPCVD and then diffusing it, depositing it by in-situ doping by PECVD and then annealing it, depositing it by PVD and then in-situ doping and annealing it, or depositing it by LPCVD and then ion implanting it.

[0036] In some embodiments of the present disclosure, the deposition of the second semiconductor layer in S6 is performed by plate-type CVD.

[0037] In some embodiments of the present disclosure, the preparation method further includes a post-texturing step: providing a double-sided polished and cleaned silicon wafer in S1; and the cleaning in S4 is texturing cleaning, so that a texturing surface is simultaneously formed in the second semiconductor opening area on the front and back sides of the silicon wafer.

[0038] In some embodiments of the present disclosure, the preparation method further includes the step of removing the mask layer: after the texturing and cleaning in S4, the mask layer is removed from the area outside the second semiconductor opening area on the back side by acid cleaning.

[0039] In some embodiments of the present disclosure, the preparation method further includes: S5, after forming the third semiconductor layer, depositing an anti-reflection layer on the front side of the silicon wafer by tubular PECVD, and then performing the cleaning described in S5 to remove the plating on the back side of the silicon wafer.

[0040] In some embodiments of the present disclosure, the preparation method further includes: S7, etching an opening on the back side of the silicon wafer obtained in S6 to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then cleaning.

[0041] In some embodiments of the present disclosure, the preparation method further includes: S8, depositing a transparent conductive film on the back side of the silicon wafer obtained in S7.

[0042] In some embodiments of the present disclosure, the preparation method further includes: S9, etching an opening on the surface of the transition area between the second semiconductor opening area and the first semiconductor opening area on the back side of the silicon wafer obtained in S8 to form an insulating groove between the second semiconductor opening area and the first semiconductor opening area.

[0043] In some embodiments of the present disclosure, the preparation method further includes: S10, forming metal electrodes on the surfaces of the second semiconductor opening region and the first semiconductor opening region on the back side of the silicon wafer obtained in S9. Beneficial effects:

[0044] The present disclosure adopts a second tunneling oxide layer and a third doped polysilicon layer with a high bandgap width and an appropriate thickness as the third semiconductor layer on the front side of the silicon wafer in a combined passivated back contact battery structure. The third doped polysilicon layer is doped with a second doping element including carbon or oxygen so that the bandgap width is ≥1.6eV. At the same time, the absorption coefficient of polysilicon is only one tenth of that of conventional amorphous silicon. Therefore, the parasitic absorption of the third semiconductor layer on the front side of the battery can be greatly reduced, the short-circuit current of the battery is increased, and thus the battery conversion efficiency is improved. At the same time, the third semiconductor layer with the above-mentioned specific structure, in combination with the combined passivated first semiconductor layer and second semiconductor layer, can reduce the equipment investment cost, facilitate mass production and promotion, and improve the battery conversion efficiency. Among them, in the combined passivation structure, if the band gap width of the third doped polysilicon layer in the third semiconductor layer is too large, the front passivation effect will be reduced, thereby reducing the battery open circuit; if it is too small, the front parasitic absorption will increase, thereby reducing the battery short-circuit current; if the thickness ratio of the third doped polysilicon layer to the first doped polysilicon layer in the third semiconductor layer is too large, the front parasitic absorption will increase, thereby reducing the battery current; if it is too small, the front passivation effect will be reduced, thereby reducing the battery open circuit voltage; if the thickness of the third doped polysilicon layer in the third semiconductor layer is too large, the parasitic absorption will increase, thereby reducing the battery short-circuit current, thereby reducing the battery efficiency; if it is too small, the front passivation effect will be reduced, thereby reducing the battery open circuit voltage, thereby reducing the battery efficiency.

[0045] Furthermore, in the combined passivated back-contact solar cell disclosed herein, since the third semiconductor layer does not use amorphous silicon, both the first and third semiconductor layers can be formed using tubular PECVD, eliminating the need for plate-type PECVD. This significantly reduces equipment costs. In contrast, in the prior art, tubular PECVD generally uses a medium-frequency power supply for ignition, which cannot meet the RF power supply requirements of plate-type PECVD for cavity shielding and grounding. Therefore, in the prior art, the third semiconductor layer, consisting of an intrinsic amorphous silicon layer and an N-type doped amorphous / microcrystalline silicon layer, must be formed using plate-type PECVD.

[0046] The synergistic effect of the various steps in the disclosed preparation method significantly reduces equipment investment costs while ensuring passivation, significantly reduces parasitic absorption in the third semiconductor layer on the front side of the battery, and increases the battery's short-circuit current, thereby improving the battery's conversion efficiency. In particular, the use of tubular PECVD to prepare the third semiconductor layer significantly reduces equipment investment costs; and the preparation of the second semiconductor layer (requiring low-temperature preparation) is performed after the first and third semiconductor layers (tubular PECVD preparation requires a maximum temperature exceeding 800°C) are completed. This specific step has at least the following advantages:

[0047] First, compared with the method of first preparing the first semiconductor layer and the second semiconductor layer and then preparing the third semiconductor layer in conventional heterojunction batteries, it can avoid the technical problem that the second semiconductor layer is formed by the plate CVD method. The plate CVD deposition temperature is less than 250°C. When the temperature is greater than 250°C, a large amount of hydrogen atoms will overflow, thereby affecting the passivation effect.

[0048] Secondly, compared with the existing double-sided tunneling silicon oxide passivated back-contact solar cell (in which a tunneling oxide layer and a doped polycrystalline layer are formed on both the front and back sides), it can take advantage of the different requirements of the front and back sides for the doped polycrystalline layer, satisfying both the effect of reducing parasitic absorption and improving passivation on the front side, and also satisfying the special requirements of the interface contact (i.e., the interface contact between the transparent conductive film and the first semiconductor layer, which is conducive to current extraction) and the conductive effect on the back side. In the double-sided tunneling silicon oxide passivated back-contact solar cell of the prior art, a tunneling oxide layer and a doped polycrystalline layer are formed on both the front and back sides, i.e., the first semiconductor layer and the third semiconductor layer are formed at the same time. Excessive carbon or oxygen doping in the doped polycrystalline layer not only increases the band gap width of the film layer and affects the interface contact, but also leads to a significant increase in resistivity or even insulation, which cannot meet the special requirements of the interface contact and conductive effect on the back side.

[0049] On the third aspect, in the prior art double-sided tunneling silicon oxide passivated back-contact solar cells, the doped polycrystalline layer formed simultaneously on the front and back sides uses LPCVD to first deposit the intrinsic polycrystalline layer, and then forms the doped polycrystalline layer through phosphorus diffusion. The LPCVD deposition of the intrinsic polycrystalline layer relies entirely on the high-temperature decomposition of silane to achieve silicon atom deposition, and the deposition temperature is generally between 550-650°C. Carbon or oxygen doping requires the use of gases such as methane or carbon dioxide, and the decomposition temperature of methane or carbon dioxide is greater than 900°C, which is incompatible with the above-mentioned prior art method of simultaneously forming the first semiconductor layer and the third semiconductor layer on the front and back sides and the LPCVD process used. The present disclosure adopts the method of preparing the second semiconductor layer after the first semiconductor layer and the third semiconductor layer are prepared in sequence, so that the preparation of the third semiconductor layer is compatible with the LPCVD process, and can also be prepared using the tubular PECVD method with lower preparation cost. The tubular PECVD method mainly forms plasma under the action of power supply and then deposits, which makes it easier to achieve doping deposition of different elements, greatly reducing the equipment investment cost.

[0050] Moreover, the present invention also performs special cleaning to remove the back-side plating of the silicon wafer after forming the third semiconductor layer and before depositing the second semiconductor layer. This can avoid the technical problem that a thicker oxide layer is formed in the second semiconductor opening area on the back of the silicon wafer due to the need for high-temperature treatment of up to 800°C in the tubular PECVD process for preparing the wide-bandgap third doped polysilicon layer on the front side, thereby affecting the passivation effect of the second semiconductor layer.

[0051] In the optional post-texturing preparation method disclosed in the present invention, in the specific battery structure disclosed in the present invention, the texturing and cleaning can be performed after the second semiconductor opening area is formed, that is, the texturing surface is formed simultaneously in the second semiconductor opening area and the front side by a post-texturing method, which greatly simplifies the process flow, reduces the equipment usage of plate-type PECVD, and thus greatly reduces the equipment investment cost; it can be optionally combined with a structure without a mask layer on the back side to greatly improve the adhesion of the second semiconductor layer on the first semiconductor layer, improve the surface cleanliness of the silicon wafer substrate, improve the product yield and stability, and simplify the process flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0053] FIG1 is a schematic diagram of the structure of a conventional back-contact heterojunction solar cell;

[0054] FIG2 is a process flow chart of a combined passivated back contact solar cell prepared in Example 1 of the present disclosure;

[0055] FIG3 is a schematic diagram of the structure of the silicon wafer after polishing and cleaning in step S1 of Example 1 of the present disclosure;

[0056] FIG4 is a schematic structural diagram of forming a first semiconductor layer and a mask layer on the back side of a silicon wafer in step S2 of embodiment 1 of the present disclosure;

[0057] FIG5 is a schematic structural diagram of forming a second semiconductor opening region on the back side of a silicon wafer in step S3 of embodiment 1 of the present disclosure;

[0058] FIG6 is a schematic structural diagram of the silicon wafer after texturing and cleaning in step S4 of Example 1 of the present disclosure;

[0059] FIG7 is a schematic structural diagram of forming a third semiconductor layer and an anti-reflection layer on the front side of a silicon wafer in step S5 of Example 1 of the present disclosure;

[0060] FIG8 is a schematic structural diagram of forming a second semiconductor layer on the back side of a silicon wafer in step S6 of Example 1 of the present disclosure;

[0061] FIG9 is a schematic structural diagram of forming a first semiconductor opening region on the back side of a silicon wafer in step S7 of Example 1 of the present disclosure;

[0062] FIG10 is a schematic diagram of the structure of depositing a transparent conductive film on the back side of a silicon wafer in step S8 of Example 1 of the present disclosure;

[0063] FIG11 is a schematic structural diagram of forming an insulating trench mask pattern on the back side of a silicon wafer in step S9 of Example 1 of the present disclosure;

[0064] FIG12 is a schematic structural diagram of forming an insulating groove on the back side of a silicon wafer in step S9 of Example 1 of the present disclosure;

[0065] FIG13 is a schematic structural diagram of forming a metal electrode on the back side of a silicon wafer in step S10 of embodiment 1 of the present disclosure.

[0066] Description of Reference Numerals

[0067] 10. N-type silicon wafer, 11. First tunneling oxide layer, 12. Back N-type doped polysilicon layer, 13. Mask layer, 14. Second tunneling oxide layer, 15. Front N-type doped polysilicon layer, 16. Anti-reflection layer, 17. Intrinsic amorphous silicon layer, 18. P-type doped amorphous silicon layer, 19. Transparent conductive film, 20. Mask material, 21. Metal electrode; 01. First semiconductor film layer, 02. Second semiconductor film layer, 03. Third semiconductor film layer. DETAILED DESCRIPTION

[0068] In this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0069] In the present disclosure, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0070] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0071] In this disclosure, the area close to the silicon wafer is considered inner, and the area opposite to the silicon wafer is considered outer.

[0072] In a first aspect, the present disclosure provides a front-side wide bandgap doped jointly passivated back-contact solar cell, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer disposed on the back side of the silicon wafer, and a third semiconductor layer disposed on the front side of the silicon wafer.

[0073] The first semiconductor layer includes a first tunneling oxide layer and a first doped polysilicon layer arranged in sequence from the inside to the outside, the second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer arranged in sequence from the inside to the outside, and the third semiconductor layer includes a second tunneling oxide layer and a third doped polysilicon layer arranged in sequence from the inside to the outside.

[0074] The third doped polysilicon layer disclosed herein is a doped polysilicon layer containing a first doping element and a second doping element, wherein the first doping element is phosphorus and the second doping element is either carbon or oxygen. Furthermore, the band gap width of the third doped polysilicon layer is ≥ 1.6 eV, the thickness ratio of the third doped polysilicon layer to the first doped polysilicon layer is 2%-10%, and the thickness of the third doped polysilicon layer is 4-15 nm.

[0075] In some optional embodiments of the present disclosure, the bandgap width of the third doped polysilicon layer is 1.6-2.2 eV, specifically, for example, 1.6 eV, 1.7 eV, 1.8 eV, 1.9 eV, 2.0 eV, 2.1 eV, 2.2 eV, etc. In this optional solution, the bandgap width of the third doped polysilicon layer is appropriate, which can achieve both low parasitic absorption and passivation effects on the front side of the battery, and is more conducive to improving battery efficiency.

[0076] In some optional embodiments of the present disclosure, the thickness of the third doped polysilicon layer is 5-15 nm. In this optional solution, the thickness of the third doped polysilicon layer is appropriate, and it can also take into account the low parasitic absorption and passivation effect on the front side of the battery, which is more conducive to improving battery efficiency.

[0077] In some optional embodiments of the present disclosure, the effective doping concentration of the second doping element in the third doped polysilicon layer is between 1e19-4e21cm⁻³, and the effective doping concentration of the first doping element is between 1e19-9e20cm⁻³. In this optional solution, the doping concentrations of the doping elements in the third doped polysilicon layer are appropriate, achieving both low parasitic absorption and passivation effects on the front side of the cell, thereby further improving cell efficiency.

[0078] The third doped polysilicon layer disclosed herein can be a multi-layer structure or a single-layer structure. The multi-layer structure can be achieved by varying the doping concentration in steps. Those skilled in the art can further optimize the structure based on the present disclosure according to actual needs. When the structure is a multi-layer structure, the parameters only need to be within the above-mentioned ranges for the corresponding doping concentrations.

[0079] In some optional embodiments of the present disclosure, the silicon wafer is an N-type silicon wafer, the first doped polysilicon layer and the third doped polysilicon layer are both N-type, and the second doped silicon layer is P-type.

[0080] In some alternative embodiments of the present disclosure, the third doped polysilicon layer is a carbon-doped N-type doped polysilicon layer. This alternative solution can better control the doping concentration and band gap width, which is more conducive to improving the short-circuit current density and battery conversion efficiency.

[0081] In some optional embodiments of the present disclosure, a second semiconductor opening region is opened on the first semiconductor layer, the back side of the silicon wafer where the second semiconductor opening region is located is a textured surface, and the front side of the silicon wafer is a textured surface.

[0082] The second semiconductor layer of the present disclosure has a first semiconductor opening region, which is spaced apart from the second semiconductor opening region. The width Wp of the second semiconductor opening region of the present disclosure can be selected from 0.3 to 0.6 mm, and the width Wn of the first semiconductor opening region can be selected from 0.1 to 0.3 mm.

[0083] In some optional embodiments of the present disclosure, the thickness of the first tunneling oxide layer and the second tunneling oxide layer is 0.5-1.25:1, and the thickness of the second tunneling oxide layer is 1-3 nm. In this optional solution, the thickness ratio of the two tunneling oxide layers is appropriate in the combined passivation structure, which can achieve both the passivation effect on the front and back sides and the tunneling effect on the back side, and is more conducive to improving the battery open circuit voltage and battery efficiency.

[0084] In some optional embodiments of the present disclosure, the effective doping concentration of the first doped polysilicon layer is 1e19-9e20 cm-3.

[0085] In some optional embodiments of the present disclosure, the back side of the silicon wafer is divided into a first emitter region where the first semiconductor layer contacts the silicon wafer, a second emitter region where the second semiconductor layer contacts the silicon wafer, and a transition region between the first and second emitter regions. The first and second semiconductor layers are sequentially disposed in the transition region from the inside out. It is understood that the second semiconductor layer is not disposed in the first emitter region, and the first semiconductor layer is not disposed in the second emitter region.

[0086] A mask layer may be provided between the first semiconductor layer and the second semiconductor layer in the transition region. More optionally, the first semiconductor layer and the second semiconductor layer are in direct contact with each other in the transition region without providing a mask layer.

[0087] The silicon wafer disclosed in the present invention is a Czochralski single crystal silicon wafer or a cast single crystal silicon wafer.

[0088] In some embodiments of the present disclosure, the combined passivated back-contact solar cell further includes a transparent conductive film disposed on the outer surface of the first semiconductor layer or the second semiconductor layer located at the outermost layer in the first emitter region, the second emitter region, and the transition region, respectively. The portion of the transparent conductive film within the transition region defines an insulating trench. The insulating trench width Wi of the present disclosure can be selected to be 20-120 μm. The insulating trench ensures that the resistance between the second semiconductor opening region and the first semiconductor opening region is greater than 1 kΩ.

[0089] The second doped silicon layer in the second semiconductor layer of the present disclosure may be a doped amorphous or microcrystalline silicon layer. The thickness and doping concentration of both the intrinsic amorphous silicon layer and the second doped silicon layer may be within the ranges known in the art. Optionally, the thickness of the intrinsic amorphous silicon layer is 5-15 nm, the thickness of the second doped silicon layer is 10-35 nm, and the effective doping concentration of the second doped silicon layer is between 1e19 and 4e20 cm⁻³.

[0090] In some embodiments of the present disclosure, the combined passivated back contact solar cell further comprises an anti-reflection layer disposed on the outer surface of the third semiconductor layer. The anti-reflection layer may be, for example, silicon oxide, fluoride, or silicon nitride, and may have a thickness of 700-850 nm.

[0091] In some embodiments of the present disclosure, the combined passivation back contact solar cell further includes: a metal electrode, which is arranged in the first emitter region and the second emitter region and is located on the outer surface of the corresponding transparent conductive film.

[0092] In a second aspect, the present disclosure provides a method for preparing a combined passivated back contact solar cell, wherein the combined passivated back contact solar cell is the combined passivated back contact solar cell with a front wide bandgap doping as described in the first aspect.

[0093] The preparation method disclosed herein comprises the following steps:

[0094] S1, provide silicon wafers;

[0095] S2, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer;

[0096] S3, opening the back surface obtained in S2, removing the first semiconductor layer and the mask layer, and forming a second semiconductor opening region;

[0097] S4, cleaning the back surface obtained in S3 to remove the remaining first semiconductor layer and mask layer in the second semiconductor opening region;

[0098] S5, forming a third semiconductor layer on the front surface of the silicon wafer obtained in S4, and then cleaning and removing the plating on the back surface of the silicon wafer;

[0099] S6. Depositing a second semiconductor layer on the back side of the silicon wafer obtained in S5.

[0100] In S5, the third semiconductor layer is formed by in-situ doping deposition by tubular PECVD followed by annealing, or is formed by doping the first doping element and the second doping element after LPCVD deposition.

[0101] In some embodiments of the present disclosure, the process of forming the third semiconductor layer by tubular PECVD in-situ doping deposition followed by annealing includes a first stage, a second stage, and annealing.

[0102] Optionally, in the first stage, a first gas including laughing gas is introduced, the glow is turned on, and a second tunneling oxide layer is formed by chemical reaction deposition.

[0103] More optionally, the reaction temperature of the first stage is 350-450° C., the reaction pressure is 100-2000 mtorr, and the reaction time is 10-360 s.

[0104] After the first stage, the second stage is entered. More optionally, a second gas comprising silane, a first doping element source gas, hydrogen, argon, and a second doping element source gas is introduced in the second stage, and the glow light is turned on to form a third doped polysilicon layer by chemical reaction deposition. The volume flow ratio of the silane, the first doping element source gas, hydrogen, argon, and the second doping element source gas can be selected within a conventional range as long as the desired film layer can be formed. For example, the volume flow ratio of the silane, the first doping element source gas, the second doping element source gas, hydrogen, and argon in the second gas can be selected to be 1:0-0.5:0-1:0-5:0-5.

[0105] Optionally, the reaction temperature of the second stage is 350-450° C., the reaction pressure is 100-2000 mtorr, and the reaction time is 30-200 s.

[0106] Optionally, the second doping element gas source includes methane or carbon dioxide, and the first doping element gas source includes phosphine.

[0107] Annealing is performed after the second stage of deposition is completed. More optionally, the annealing pressure is 2000 mtorr-1 atm, the annealing temperature is 750-900° C., and the annealing time is 5-70 minutes.

[0108] In some embodiments of the present disclosure, in S5, the process of forming the third semiconductor layer by post-LPCVD doping with the first doping element and the second doping element includes: first depositing a second tunneling oxide layer and an intrinsic polysilicon layer; then ion implanting the first doping element and the second doping element, or then diffusing the first doping element and the second doping element. Those skilled in the art can select corresponding process parameters for post-LPCVD doping with the first doping element and the second doping element based on the desired third semiconductor layer to be formed.

[0109] The method for forming the first semiconductor layer and mask layer in S2 of the present disclosure can be deposited using any method known in the art. For example, in some embodiments of the present disclosure, in S2, the process of forming the first semiconductor layer includes: first forming a first tunneling oxide layer using a wet or dry method, and then forming a first doped polysilicon layer using any of the following methods: depositing an intrinsic polysilicon layer by LPCVD followed by diffusion, in-situ doping deposition by tubular PECVD followed by annealing, in-situ doping deposition by PVD followed by annealing, or depositing an intrinsic polysilicon layer by LPCVD followed by ion implantation. For example, the mask layer is formed by PECVD deposition.

[0110] The present disclosure describes the use of a wet or dry method to form the first tunnel oxide layer, wherein the wet method includes ozone oxidation, nitric acid oxidation, ozone water oxidation, etc., and the dry method includes thermal oxidation, PECVD in-situ oxidation, etc., which are all existing technologies and will not be repeated here.

[0111] In S2, the mask layer can be retained or removed, and removal is optional. The mask layer can be at least one of silicon nitride, silicon oxynitride, and silicon oxide, and can have a thickness of 50-200 nm.

[0112] In some embodiments of the present disclosure, the preparation method further includes a post-texturing step: providing a double-sided polished and cleaned silicon wafer in S1; and the cleaning in S4 is texturing cleaning, so that a texturing surface is simultaneously formed in the second semiconductor opening area on the front and back sides of the silicon wafer.

[0113] In some embodiments of the present disclosure, the preparation method further includes the step of removing the mask layer: after the texturing cleaning in S4, acid cleaning (optionally hydrofluoric acid cleaning) is performed to remove the mask layer in the area outside the second semiconductor opening area on the back side.

[0114] In S3 of the present disclosure, the opening can be formed by laser or mask etching, as long as the second semiconductor opening region can be formed. The laser can be ultraviolet or green laser with a pulse width of less than 10ns.

[0115] In some embodiments of the present disclosure, the preparation method further includes: S5, after forming the third semiconductor layer, depositing an anti-reflection layer on the front side of the silicon wafer by tubular PECVD, and then performing the cleaning described in S5 to remove the plating on the back side of the silicon wafer.

[0116] In some embodiments of the present disclosure, the deposition of the second semiconductor layer in S6 is performed by plate-type CVD.

[0117] In some embodiments of the present disclosure, the preparation method further includes: S7, etching an opening on the back side of the silicon wafer obtained in S6 to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then cleaning.

[0118] In S7, the etching opening may be performed by laser or mask etching. The laser may be an ultraviolet or green laser, and the pulse width may be less than 50 ns.

[0119] In some embodiments of the present disclosure, the preparation method further includes: S8, depositing a transparent conductive film on the back side of the silicon wafer obtained in S7. The transparent conductive film can be deposited using, for example, physical vapor deposition (PVD) or activated plasma deposition (RPD). The thickness of the transparent conductive film can be 40-80 nm. The material of the transparent conductive film can be an indium oxide film doped with tin oxide, titanium oxide, zinc oxide, or gallium oxide, or a zinc oxide film doped with aluminum oxide, gallium oxide, or boron oxide.

[0120] In some embodiments of the present disclosure, the preparation method further includes: S9, etching an opening on the surface of the transition area between the second semiconductor opening area and the first semiconductor opening area on the back side of the silicon wafer obtained in S8 to form an insulating groove between the second semiconductor opening area and the first semiconductor opening area.

[0121] The etching opening described in S9 can be carried out by mask etching. The process of mask etching includes: first printing or inkjet printing an acid-resistant mask material (such as acid-resistant ink) on the back of the silicon wafer to form an opening area of ​​the insulating groove pattern, cleaning with an acid solution to remove the transparent conductive film in the opening area of ​​the acid-resistant mask material, and then cleaning with a cleaning agent to remove the acid-resistant mask material. The acid solution can be, for example, at least one of hydrochloric acid, sulfuric acid, and nitric acid. The cleaning agent can be, for example, at least one of an alkaline cleaning agent and an oxidizing agent. The alkaline cleaning agent can be, for example, at least one of sodium hydroxide, potassium hydroxide, etc.

[0122] In some embodiments of the present disclosure, the preparation method further includes: S10, forming metal electrodes on the surfaces of the second semiconductor opening region and the first semiconductor opening region on the back side of the silicon wafer obtained in S9. The metal electrodes can be formed using screen printing or electroplating techniques. The polarity of the corresponding metal electrodes in the second semiconductor opening region and the first semiconductor opening region is different, thereby forming a second emitter and a first emitter.

[0123] The following describes embodiments of the present disclosure in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only configured to explain the present disclosure and are not to be construed as limiting the present disclosure.

[0124] Example 1

[0125] A front-side wide bandgap doped combined passivated back contact solar cell is prepared by the following steps as shown in FIG2 :

[0126] S1. As shown in FIG3 , the N-type single crystal silicon wafer 10 is double-sided polished and cleaned.

[0127] S2. As shown in FIG4 , a first semiconductor layer and a mask layer 13 are formed on the back side of the silicon wafer 10. The first semiconductor layer includes a first tunneling oxide layer 11 and a back side N-type doped polysilicon layer 12. The first tunneling oxide layer 11 is formed using a dry process, and the back side N-type doped polysilicon layer 12 is formed using LPCVD deposition of intrinsic polycrystalline followed by diffusion. The mask layer 13 is formed using PECVD deposition. The first tunneling oxide layer 11 is 1.7 nm thick, and the back side N-type doped polysilicon layer 12 is 120 nm thick. The effective doping concentration of the back side N-type doped polysilicon layer 12 is between 1e19 and 6e20 cm⁻³. The mask layer 13 is silicon nitride and is 70 nm thick.

[0128] S3. As shown in FIG5 , a laser is used to etch an opening on the back side of the silicon wafer 10 to form a second semiconductor opening region Wp. The second semiconductor opening region Wp is 0.5 mm wide. The mask layer 13, the back side N-type doped polysilicon layer 12, and the first tunneling oxide layer 11 within the second semiconductor opening region Wp are etched away. The laser has a wavelength of 532 nm and a pulse width of 1 ns.

[0129] S4. As shown in FIG6 , the mask layer 13, the back N-type doped polysilicon layer 12 and the first tunneling oxide layer 11 remaining in the second semiconductor opening area Wp are removed by texturing and cleaning. At the same time, a velvet surface is formed in the second semiconductor opening area Wp on the front and back sides of the silicon wafer. After that, the mask layer 13 outside the second semiconductor opening area Wp on the back side of the silicon wafer is removed by hydrofluoric acid cleaning.

[0130] S5. As shown in FIG7 , a third semiconductor layer and an anti-reflection layer 16 are formed on the front side of the silicon wafer 10. The third semiconductor layer includes a second tunneling oxide layer 14 and a carbon-doped front N-type doped polycrystalline layer 15. The third semiconductor layer is formed by in-situ doping deposition and subsequent annealing by tubular PECVD. The process includes: in a first stage, nitrous oxide is introduced, a glow light is turned on, and the second tunneling oxide layer 14 is formed by a chemical reaction. The reaction temperature in the first stage is 380° C., the reaction pressure is 1000 mtorr, and the reaction time is 120 s. The thickness of the second tunneling oxide layer 14 is 2 nm. Then, the process enters a second stage. In the second stage, silane, phosphine, methane, hydrogen, and argon are introduced at a volume flow ratio of 1:0.2:0.5:1:2. The glow light is turned on and a carbon-doped front N-type doped polycrystalline layer 15 is formed by a chemical reaction. The reaction temperature in the second stage is 420° C., the reaction time is 100 s, and the reaction pressure is 1000 mtorr. The thickness of the carbon-doped front N-type doped polycrystalline layer 15 is 5 nm. After deposition, the wafer is annealed in a low-pressure annealing furnace at 2000 mtorr, 850°C, and 20 minutes. The effective carbon doping concentration is 1e20 cm⁻³, the phosphorus concentration is 2e20 cm⁻³, and the band gap is 1.9 eV. A 700nm thick silicon nitride layer is then deposited on the front of the wafer using tubular PECVD. The wafer is then cleaned to remove the backside coating.

[0131] S6. As shown in FIG8 , a second semiconductor layer is deposited on the back side of silicon wafer 10 using plate-type plasma-enhanced chemical vapor deposition (PECVD) technology. The second semiconductor layer includes an intrinsic amorphous silicon layer 17 and a P-type doped amorphous silicon layer 18. Intrinsic amorphous silicon layer 17 has a thickness of 5 nm, and P-type doped amorphous silicon layer 18 has a thickness of 10 nm. The boron doping concentration in P-type doped amorphous silicon layer 18 is 5e19 cm-3.

[0132] S7. As shown in FIG9 , a laser is used to etch an opening on the back side of silicon wafer 10 to form a first semiconductor opening region Wn spaced apart from the second semiconductor opening region Wp, followed by cleaning. The first semiconductor opening region Wn is 0.3 mm wide, and the second semiconductor layer on the upper surface of the first semiconductor opening region Wn is removed by etching. The laser is ultraviolet, with a pulse width of 1 ns.

[0133] S8. As shown in FIG10 , a transparent conductive film 19 is deposited on the back of the silicon wafer 10 by physical vapor deposition (PVD). The transparent conductive film 19 has a thickness of 50 nm and is made of a tin oxide-doped indium oxide thin film.

[0134] S9. As shown in Figures 11 and 12, a mask etching method is used to etch an opening on the surface of the transition region Wg on the back of the silicon wafer 10 to form an insulating trench Wi between the first semiconductor and the second semiconductor. The width Wi is 80 μm, and the resistance between the first semiconductor and the second semiconductor after etching is greater than 1 kΩ. The conditions for forming the mask etching include: first printing an acid-resistant mask material 20 on the back of the silicon wafer 10 to form an opening area of ​​the insulating trench pattern, then cleaning with an acid solution to remove the transparent conductive film 19 in the opening area of ​​the acid-resistant ink material, and then cleaning with an ink cleaning agent to remove the acid-resistant mask material. The acid solution is hydrochloric acid and the cleaning agent is sodium hydroxide.

[0135] S10. Using screen printing technology, a metal electrode 21 is formed on the surface of the first semiconductor opening region Wn on the back side of the silicon wafer 10. A metal electrode 21 is also formed on the surface of the second semiconductor opening region Wp. The polarity of the corresponding metal electrodes in the second semiconductor opening region and the first semiconductor opening region are different. The resulting structure of the combined passivated back-contact solar cell is shown in FIG13.

[0136] Example 2

[0137] The process was carried out in accordance with Example 1, except that the front N-type doped polycrystalline layer 15 in the third semiconductor layer in S5 was an oxygen-doped N-type doped polycrystalline layer with an effective oxygen doping concentration of 1e19 cm⁻³ and a band gap of 1.7 eV. Accordingly, during the second stage of in-situ doping deposition of the third semiconductor layer using tubular PECVD, silane, phosphine, carbon dioxide, hydrogen, and argon were introduced. The volume flow ratio of silane to carbon dioxide was 1:0.2, while the flow ratios of the other gases remained unchanged.

[0138] Example 3

[0139] Refer to Example 1. The difference from Example 1 is that the S5 third semiconductor layer is formed by depositing the second tunnel oxide layer and the intrinsic polysilicon layer through LPCVD (low pressure chemical vapor deposition), and then by ion implantation of phosphorus and carbon. The thickness and doping conditions of the obtained third semiconductor layer are the same as those in Example 1.

[0140] Example 4

[0141] Refer to Example 1. The difference from Example 1 is that the S5 third semiconductor is formed by depositing a second tunnel oxide layer and an intrinsic polysilicon layer through LPCVD, and then by diffusion-doping phosphorus and carbon. The thickness and doping conditions of the obtained third semiconductor layer are the same as those in Example 1.

[0142] Example 5

[0143] The process was carried out with reference to Example 1. The difference from Example 1 was that in S5, the band gap width of the carbon-doped front N-type doped polycrystalline layer was controlled to be 2.2 eV. To meet this parameter, the process parameters were adjusted accordingly: in the second stage, silane, phosphine, methane, hydrogen, and argon were introduced, and the volume flow ratio of silane and methane was 1:1. The flow ratios of other gases remained unchanged.

[0144] Example 6

[0145] Refer to Example 1. The difference from Example 1 is that in S5, the thickness of the second tunneling oxide layer is adjusted so that the thickness of the first tunneling oxide layer and the second tunneling oxide layer is 0.57:1. To meet this parameter, the process parameters are adjusted accordingly: the reaction time of the first stage is 300s, the thickness of the second tunneling oxide layer 14 is 3nm, and the other parameters remain unchanged.

[0146] Comparative Example 1

[0147] The conventional back-contact heterojunction cell structure shown in Figure 1 is obtained by the following steps:

[0148] S101, providing a silicon wafer 10 with a single-side textured and single-side polished structure;

[0149] S102: The back of the silicon wafer is coated with a first semiconductor film layer 01 and a mask layer 13 in sequence. The first semiconductor film layer 01 is formed by plate-type PECVD. The first semiconductor film layer 01 comprises an intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer (with the same effective doping concentration as in Example 1). The thickness of both layers is the same as in Example 1. The mask layer 13 is the same as in Example 1.

[0150] S103, performing a laser opening on the back side of the silicon wafer 10, removing the mask layer 13 and a portion of the first semiconductor film layer 01, and forming a second semiconductor opening region;

[0151] S104, cleaning the silicon wafer 10 to remove the remaining first semiconductor film layer 01 in the second semiconductor opening region;

[0152] S105: forming a second semiconductor film layer 02 on the back side of the silicon wafer 10. The second semiconductor film layer 02 is formed by plate-type PECVD. The second semiconductor film layer 02 includes an intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer. The thickness of each layer of the second semiconductor film layer 02 and other structural parameters are the same as those in Example 1.

[0153] S106. Forming a third semiconductor film layer 03 on the front side. The third semiconductor film layer 03 includes a front passivation layer and an anti-reflection layer 16. The front passivation layer and the anti-reflection layer are formed by plate-type PECVD. The front passivation layer includes an intrinsic amorphous silicon layer and an N-type doped amorphous / microcrystalline silicon layer (not doped with carbon or oxygen). The intrinsic amorphous silicon layer has a thickness of 6 nm. The effective doping concentration and thickness of phosphorus in the N-type doped amorphous silicon layer are the same as those in Example 1. The anti-reflection layer 16 is the same as that in Example 1.

[0154] S107, laser opening the back side of the silicon wafer 10 to form first semiconductor opening regions alternately arranged with second semiconductor opening regions; the widths of the second semiconductor opening regions and the first semiconductor opening regions are the same as those in Example 1;

[0155] S108, cleaning the silicon wafer 10, and removing the mask layer 13 in the first semiconductor opening region;

[0156] S109, depositing a transparent conductive film 19 on the back of the silicon wafer 10; the transparent conductive film 19 is the same as that in Example 1;

[0157] S110, forming an insulating trench between the first semiconductor opening region and the second semiconductor opening region by laser or etching; the width of the insulating trench is the same as that of embodiment 1;

[0158] S111 , forming a metal electrode 21 on the first semiconductor opening region and the second semiconductor opening region of the silicon wafer 10 .

[0159] Comparative Example 2

[0160] Refer to Example 1. The difference from Example 1 is that the third semiconductor layer is formed by plate-type PECVD deposition of intrinsic amorphous silicon and N-type doped microcrystalline silicon. The thickness of the intrinsic amorphous silicon is 6 nm, and the thickness, phosphorus doping concentration, and carbon doping concentration of the N-type doped microcrystalline silicon are the same as those in Example 1.

[0161] Comparative Example 3

[0162] The process is carried out with reference to Example 1. The difference from Example 1 is that the N-type doped polysilicon layer in the third semiconductor layer is not doped with carbon, and the band gap width is 1.0-1.2 eV.

[0163] Test Case

[0164] The back contact cells of the above examples and comparative examples were tested as shown in Table 1, and the results are shown in Table 1.

[0165] Table 1

[0166] Note: The equipment investment amount is calculated based on Comparative Example 1.

[0167] The above test results show that, compared to the comparative examples, the embodiments of the present disclosure can improve both short-circuit current density and battery conversion efficiency to a higher level while reducing equipment costs. The comparative examples, on the other hand, either have high equipment costs or relatively low combined performance in short-circuit current density and battery conversion efficiency.

[0168] Optionally, it can be seen from Examples 1 and 2 that the carbon-doped optional embodiment 1 solution is more conducive to improving the short-circuit current density and battery conversion efficiency. It can be seen from Examples 1 and 3-4 that the optional embodiment 1 solution using a tubular PECVD process is more conducive to reducing equipment costs while further improving the short-circuit current density and battery conversion efficiency. It can be seen from Examples 1 and 5 that the third doped polysilicon layer adopts a suitable optional bandgap width, which is more conducive to improving the battery conversion efficiency. It can be seen from Examples 1 and 6 that the second tunneling oxide layer adopts a suitable thickness ratio, which is more conducive to improving the short-circuit current density and battery conversion efficiency.

[0169] The above describes in detail the optional embodiments of the present disclosure, but the present disclosure is not limited thereto. Within the technical concept of the present disclosure, various simple variations of the technical solution of the present disclosure can be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as the contents disclosed by the present disclosure and fall within the scope of protection of the present disclosure. Industrial Applicability

[0170] The present disclosure adopts a second tunneling oxide layer and a third doped polysilicon layer with a high bandgap width and an appropriate thickness as the third semiconductor layer on the front side of the silicon wafer in a combined passivated back contact battery structure. The third doped polysilicon layer is doped with a second doping element including carbon or oxygen so that the bandgap width is ≥1.6eV. At the same time, the absorption coefficient of polysilicon is only one tenth of that of conventional amorphous silicon. Therefore, the parasitic absorption of the third semiconductor layer on the front side of the battery can be greatly reduced, the short-circuit current of the battery is increased, and thus the battery conversion efficiency is improved. At the same time, the third semiconductor layer with the above-mentioned specific structure, in combination with the combined passivated first semiconductor layer and second semiconductor layer, can reduce the equipment investment cost, facilitate mass production and promotion, and improve the battery conversion efficiency.

Claims

1. A front-side wide bandgap doped combined passivation back contact solar cell, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer arranged on the back side of the silicon wafer, and a third semiconductor layer arranged on the front side of the silicon wafer; the first semiconductor layer comprises a first tunneling oxide layer and a first doped polysilicon layer arranged in sequence from the inside to the outside, and the second semiconductor layer comprises an intrinsic amorphous silicon layer and a second doped silicon layer arranged in sequence from the inside to the outside, characterized in that: The third semiconductor layer includes a second tunneling oxide layer and a third doped polysilicon layer arranged in sequence from the inside to the outside, the third doped polysilicon layer is a doped polysilicon layer containing a first doping element and a second doping element, the first doping element is phosphorus, the second doping element includes any one of carbon and oxygen, and the band gap width of the third doped polysilicon layer is ≥1.6eV, the thickness ratio of the third doped polysilicon layer to the first doped polysilicon layer is 2%-10%, and the thickness of the third doped polysilicon layer is 4-15nm.

2. The combined passivated back contact solar cell according to claim 1, characterized in that: The band gap width of the third doped polysilicon layer is 1.6-2.2 eV, and / or the thickness of the third doped polysilicon layer is 5-15 nm.

3. The combined passivated back contact solar cell according to claim 1 or 2, characterized in that: The effective doping concentration of the second doping element in the third doped polysilicon layer is 1e19-4e21cm-3, and the effective doping concentration of the first doping element is 1e19-9e20cm-3.

4. The combined passivated back contact solar cell according to any one of claims 1 to 3, characterized in that: The silicon wafer is an N-type silicon wafer, the first doped polysilicon layer and the third doped polysilicon layer are both N-type, and the second doped silicon layer is P-type; and / or A second semiconductor opening area is opened on the first semiconductor layer, the back side of the silicon wafer where the second semiconductor opening area is located is a textured surface, and the front side of the silicon wafer is a textured surface; a first semiconductor opening area is opened on the second semiconductor layer, and the first semiconductor opening area and the second semiconductor opening area are arranged at intervals.

5. The combined passivated back contact solar cell according to any one of claims 1 to 4, characterized in that: The third doped polysilicon layer is a carbon-doped N-type doped polysilicon layer, and / or The thickness of the first tunneling oxide layer and the second tunneling oxide layer is 0.5-1.25:1, the thickness of the second tunneling oxide layer is 1-3 nm, and the effective doping concentration of the first doped polysilicon layer is 1e19-9e20 cm-3.

6. The combined passivated back contact solar cell according to any one of claims 1 to 5, characterized in that: The back side of the silicon wafer is divided into a first emitter region where the first semiconductor layer contacts the silicon wafer, a second emitter region where the second semiconductor layer contacts the silicon wafer, and a transition region between the first emitter region and the second emitter region, wherein the first semiconductor layer and the second semiconductor layer are sequentially arranged from the inside to the outside in the transition region and are in direct contact with each other.

7. The combined passivated back contact solar cell according to claim 6, characterized in that: The combined passivated back contact solar cell also includes: The transparent conductive film is arranged on the outer surface of the first semiconductor layer or the second semiconductor layer located at the outermost layer in the first emitter region, the second emitter region and the transition region, and the transparent conductive film is partially opened in the transition region. Insulation slot; an anti-reflection layer, which is arranged on the outer surface of the third semiconductor layer; The metal electrode is arranged in the first emitter region and the second emitter region and is located on the outer surface of the corresponding transparent conductive film.

8. A method for preparing a combined passivated back contact solar cell, characterized in that: The combined passivation back contact solar cell is a front wide bandgap doped combined passivation back contact solar cell as claimed in any one of claims 1 to 7, and the preparation method comprises the following steps: S1, provide silicon wafers; S2, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer; S3, opening the back surface obtained in S2, removing the first semiconductor layer and the mask layer, and forming a second semiconductor opening area; S4, cleaning the back surface obtained in S3 to remove the remaining first semiconductor layer and mask layer in the second semiconductor opening region; S5, forming a third semiconductor layer on the front side of the silicon wafer obtained in S4, and then cleaning to remove the plating on the back side of the silicon wafer; the third semiconductor layer is formed by annealing after in-situ doping deposition by tubular PECVD, or by doping the first doping element and the second doping element after LPCVD deposition; S6. Depositing a second semiconductor layer on the back side of the silicon wafer obtained in S5.

9. The preparation method according to claim 8, characterized in that: In S5, the process of forming the third semiconductor layer by in-situ doping deposition and subsequent annealing by tubular PECVD includes a first stage, a second stage and annealing: In the first stage, a first gas including laughing gas is introduced, the glow is turned on, and a second tunneling oxide layer is formed by chemical reaction deposition. The reaction temperature of the first stage is 350-450° C., the reaction pressure is 100-2000 mtorr, and the reaction time is 10-360 s. Then enter the second stage, in which a second gas including silane, a first doping element gas source, hydrogen, argon, and a second doping element gas source is introduced, the glow is turned on, and a third doped polysilicon layer is formed by chemical reaction deposition. The reaction temperature of the second stage is 350-450° C., the reaction pressure is 100-2000 mtorr, and the reaction time is 30-200 s; the second doping element gas source includes methane or carbon dioxide, and the first doping element gas source includes phosphine; After the deposition is completed, annealing is performed, the annealing pressure is 2000mtorr-1atm, the annealing temperature is 750-900℃, and the annealing time is 5-70min.

10. The preparation method according to claim 8 or 9, characterized in that: In S5, the process of forming the third semiconductor layer by doping the first doping element and the second doping element after LPCVD deposition includes: first depositing the second tunneling oxide layer and the intrinsic polysilicon layer; then ion implanting the first doping element and the second doping element, or then diffusing the first doping element and the second doping element.

11. The preparation method according to any one of claims 8 to 10, characterized in that: In S2, the process of forming the first semiconductor layer includes: first forming a first tunneling oxide layer by a wet method or a dry method, and then forming a first doped polysilicon layer by any of the following methods: depositing an intrinsic polysilicon layer by LPCVD and then diffusing it, depositing it by tubular PECVD and then annealing it, depositing it by PVD and then annealing it, depositing it by LPCVD and then ion implanting it; and / or The second semiconductor layer is deposited in S6 by plate-type CVD.

12. The preparation method according to any one of claims 8 to 11, characterized in that: The preparation method further comprises a post-texturing step: providing a double-sided polished and cleaned silicon wafer in S1; and the cleaning in S4 is texturing cleaning, so that a velvet surface is simultaneously formed in the second semiconductor opening region on the front and back sides of the silicon wafer; and / or The preparation method further comprises the step of removing the mask layer: after the texturing and cleaning in S4, acid cleaning is performed to remove the mask layer in the area other than the second semiconductor opening area on the back side.

13. The preparation method according to any one of claims 8 to 12, characterized in that: The preparation method further comprises: S5, after forming the third semiconductor layer, depositing an anti-reflection layer on the front side of the silicon wafer by tubular PECVD, and then performing the cleaning described in S5 to remove the plating on the back side of the silicon wafer; S7, etching an opening on the back side of the silicon wafer obtained in S6 to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then cleaning; S8, depositing a transparent conductive film on the back side of the silicon wafer obtained in S7; S9, etching an opening on the surface of the transition region between the second semiconductor opening region and the first semiconductor opening region on the back side of the silicon wafer obtained in S8 to form an insulating groove between the second semiconductor opening region and the first semiconductor opening region; S10, forming metal electrodes on the surfaces of the second semiconductor opening region and the first semiconductor opening region on the back side of the silicon wafer obtained in S9.

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