Wideband frequency multiplier matching device and method

Abstract

Disclosed are a wideband frequency multiplier matching device and method. The method of matching a wideband frequency multiplier comprises the steps of: for sequential loadpull matching from an output port, setting an output port (Y) to 50 Ω and then connecting an open stub (TL4) to the output port; connecting a serial transmission line (TL3) to the output port (Y); and connecting a dual short stub (TL2) to the front end of the serial transmission line (TL3).

Description

Wideband frequency multiplier matching device and method thereof

[0001] The present invention relates to a wideband frequency multiplier matching device and method thereof.

[0002]

[0003] Modern communication and radar systems demand ultra-high-speed, high-capacity data transmission and high-precision range resolution, necessitating circuit designs with wideband capabilities. The easiest way to achieve wideband capabilities is to increase the system's operating frequency.

[0004] There are two main ways to increase the operating frequency of a system: one is to design an oscillator in a high frequency band, and the second is to supply a signal in a low frequency band and then pass it through a frequency multiplier to implement a high operating frequency signal.

[0005] High-frequency implementation using semiconductor-based frequency multipliers offers advantages over high-frequency oscillators in that it can provide highly stable signals and achieve a relatively wide bandwidth. However, it suffers from the difficulty of implementing a matching network capable of achieving wideband characteristics. Furthermore, as the operating frequency increases, parasitic components within the devices make output matching more difficult, and even when matching is achieved, it leads to losses in output power and bandwidth.

[0006]

[0007] The present invention provides a wideband frequency multiplier matching device and method thereof.

[0008] In addition, the present invention proposes a new matching method of the output portion of a frequency multiplier, thereby providing a wideband frequency multiplier matching device and method that can improve output power and bandwidth and reduce the output power and bandwidth loss mentioned above compared to existing matching methods.

[0009]

[0010] According to one aspect of the present invention, a matching method of a wideband frequency multiplier is provided.

[0011] According to one embodiment of the present invention, in a matching method of a wideband frequency multiplier, the output port (Y) is sequentially matched by loadpull from the output port by 50 A matching method of a wideband frequency multiplier can be provided, including the steps of: connecting an open stub (TL4) to the output port after setting; connecting a serial transmission line (TL3) to the output port (Y); and connecting a dual short stub (TL2) to the front end of the serial transmission line (TL3).

[0012] The above dual short stub (TL2) can be connected in a symmetrical structure based on the above serial transmission line (TL3).

[0013] A bypass capacitor can be connected to the terminal of the above short stub (TL2).

[0014] It further includes a step of connecting the serial transmission line (TL1) to the front end of the plurality of short stubs (TL2).

[0015]

[0016] According to another aspect of the present invention, a matching device of a wideband frequency multiplier is provided.

[0017] According to one embodiment of the present invention, in a matching device of a wideband frequency multiplier, the output port (Y) is sequentially connected to the output port for loadpull matching at 50 A matching device of a wideband frequency multiplier may be provided, characterized in that it comprises an open stub (TL4) connected to the output port after being set to; a serial transmission line (TL3) connected in series to the output port (Y); and a dual short stub (TL2) connected to a front end of the serial transmission line (TL3), wherein the dual short stub (TL2) is connected in a symmetrical structure.

[0018] A bypass capacitor may be connected to the terminal of the above dual short stub.

[0019]

[0020] The invention according to one embodiment of the present invention provides a wideband frequency multiplier matching device and method thereof, thereby extracting harmonic components from an output portion of a frequency multiplier using a new matching method, and thereby bringing about an increase in output power and bandwidth compared to existing matching methods.

[0021] In addition, the present invention has the advantage of being able to eliminate adverse effects in system configuration by effectively removing fundamental signal components rather than harmonic signals.

[0022]

[0023] Figure 1 is a drawing showing a conventional frequency multiplier structure.

[0024] Figure 2 is a diagram showing a circuit before output matching of a conventional push-push structure frequency multiplier.

[0025] Fig. 3 is a diagram showing the load pull simulation results in the circuit of Fig. 2.

[0026] Fig. 4 is a diagram illustrating an output matching circuit of a conventional push-push structure frequency multiplier.

[0027] Fig. 5 is a diagram showing the change in impedance according to the length of the serial transmission line in Fig. 4.

[0028] Figure 6 is a diagram showing the load-pull simulation results according to the serial transmission line in Figure 4 and the impedance according to the length of the short stub.

[0029] Fig. 7 is a flowchart showing a matching method of a wideband frequency multiplier according to one embodiment of the present invention.

[0030] FIG. 8 is a drawing showing a matching structure of a wideband frequency multiplier according to one embodiment of the present invention.

[0031] FIG. 9 is a diagram illustrating impedance changes and transmission line lengths in an output matching structure according to one embodiment of the present invention.

[0032] Figure 10 is a drawing comparing the matching results according to a conventional method and an embodiment of the present invention.

[0033] Fig. 11 is a diagram comparing the output reflection coefficient according to the output matching structure of a frequency multiplier according to a conventional embodiment and an embodiment of the present invention.

[0034] Fig. 12 is a diagram comparing output power according to the output matching structure of a frequency multiplier according to a conventional embodiment and an embodiment of the present invention.

[0035] Fig. 13 is a drawing showing a chip photo of a 300 GHz band wideband frequency multiplier implemented using the wideband output matching method of the present invention.

[0036] Fig. 14 is a drawing showing a layout photo of the output matching network of Fig. 13.

[0037] FIG. 15 is a diagram showing the measurement results of a 300 GHz frequency multiplier according to one embodiment of the present invention.

[0038]

[0039] As used herein, singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as "consist of" or "include" should not be construed to necessarily include all components or steps described in the specification, and should be construed to mean that some of the components or steps may not be included, or that additional components or steps may be included. In addition, terms such as "part" and "module" described in the specification mean a unit that processes at least one function or operation, which may be implemented by hardware or software, or by a combination of hardware and software.

[0040] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0041]

[0042] FIG. 1 is a diagram illustrating a conventional frequency multiplier structure, FIG. 2 is a diagram illustrating a circuit before output matching of a conventional push-push structure frequency multiplier, FIG. 3 is a diagram illustrating a load-pull simulation result in the circuit of FIG. 2, FIG. 4 is a diagram illustrating an output matching circuit of a conventional push-push structure frequency multiplier, FIG. 5 is a diagram illustrating an impedance change according to the length of a serial transmission line in FIG. 4, and FIG. 6 is a diagram illustrating the load-pull simulation result according to the serial transmission line in FIG. 4 and the impedance according to the length of a short stub.

[0043] Figure 2 is a circuit diagram of a frequency doubler, which is the most commonly used because it allows for an effective fundamental signal with the simplest structure. In a frequency doubler, a push-push structure with a drain-common node is most widely used to extract the second harmonic component and remove the fundamental signal, and the output matching section extracts the second harmonic component using only one transmission line in the frequency band (140 GHz).

[0044] When designing a frequency doubler in the 300 GHz band, output matching is implemented through load-pull matching. In Fig. 2, the left ( ) is the common-drain impedance (Z Drain ) and the right ( ) is the load impedance (Z Load ), the results of the load pull simulation while changing the load impedance are as shown in Fig. 3.

[0045] To achieve the highest output power in a frequency doubler, the ideal impedance point (Z) with the highest output power is shown in Fig. 3. opt ) and Z Load Design the output matching network so that it is the same.

[0046] Load pull alignment point (Z opt ) and common drain (Z Drain ) When this conjugate matching is achieved, when viewed from the output port, 50 Alignment can be achieved simultaneously.

[0047] In the conventional case, to achieve load-pull matching, a serial transmission line (TL) is used as shown in Fig. 4. s ) and short stub (TL feed ) is used. Figure 5 shows a serial transmission line (TL s ) is shown to show the change in impedance as viewed from the common-drain node depending on the length.

[0048] Figure 6 shows the load-pull simulation results (Z) according to the length of the serial transmission line. opt ) is shown. Z Load Wow Z opt TL to get closer to each other s Wow TL feed By selecting , the output network can be designed to maximize the output power. 610 in Fig. 6, TL s =0 , Z at point -2.7dBm Load You just need to configure the output network so that TL is located. feed The length is 40 am.

[0049] But 40 The short transmission line length is a short distance that can be implemented when considering the inductance components due to vias and the connection to each node of the circuit in the actual layout. In addition, due to the characteristics of the short stub, when the length is short, it exhibits narrow-band matching characteristics, so there is a problem that ideal load-pull matching cannot be performed in a frequency multiplier circuit with wide-band characteristics.

[0050] Of course, the length of the serial transmission line is 100 If the TL is long enough feed can be used, but in this case, there is a problem that the output power and bandwidth are reduced (620 in Fig. 6).

[0051]

[0052] FIG. 7 is a flowchart showing a matching method of a wideband frequency doubler according to an embodiment of the present invention, FIG. 8 is a diagram showing a matching structure of a wideband frequency doubler according to an embodiment of the present invention, FIG. 9 is a diagram showing impedance changes and transmission line lengths in an output matching structure according to an embodiment of the present invention, FIG. 10 is a diagram comparing matching results according to a conventional method and an embodiment of the present invention, FIG. 11 is a diagram comparing output reflection coefficients according to output matching structures of frequency doublers according to a conventional method and an embodiment of the present invention, FIG. 12 is a diagram comparing output power according to output matching structures of frequency doublers according to a conventional method and an embodiment of the present invention, FIG. 13 is a diagram showing a chip photo of a 300 GHz band wideband frequency doubler implemented by a wideband output matching method of the present invention, FIG. 14 is a diagram showing a layout photo of an output matching network of FIG. 13, and FIG. 15 is a diagram showing a measurement result of a 300 GHz frequency doubler according to an embodiment of the present invention.

[0053] The method described below is a loadpull matching simulation, which is a simulation that displays the output power on a Smith chart while changing the load impedance to find the ideal output impedance.

[0054] At step 710, the wideband frequency multiplier matching device (700) sets the output port (Y) to 50 Set to .

[0055] Next, in step 715, the wideband frequency multiplier matching device (700) connects an open stub (TL4) to a serial transmission line (TL5) connected to an output port.

[0056] In one embodiment of the present invention, it is assumed that the serial transmission line (TL5) is a short transmission line, and the capacitor (C1) is a DC blocking capacitor, and a sufficiently large capacitor and a sufficiently short transmission line are used so as not to affect the output matching. In one embodiment of the present invention, the length of the serial transmission line (TL5) is about 17 Let's assume that.

[0057] The impedance changes as shown in 910 of Fig. 9 by the open stub (TL4). Here, the length of the open stub (TL4) is 80 It could be.

[0058] In one embodiment of the present invention, the open stub (TL4) can be used as a capacitive load.

[0059] In step 720, the wideband frequency multiplier matching device (700) connects the serial transmission line (TL3). Here, the length of the serial transmission line (TL3) is 30 It could be.

[0060] As the serial transmission line (TL3) is connected between the serial transmission line (TL5) and the open stub (TL4) contact, the impedance changes to low as shown in 920 of FIG. 9.

[0061] In step 725, the wideband frequency multiplier matching device (700) connects a dual short stub (TL2) to the front end of the serial transmission line (TL3). Here, the length of the short stub is 40 It could be.

[0062] As shown in Fig. 8, the dual short stubs (TL2) can be connected in a symmetrical structure based on the serial transmission line (TL3).

[0063] As the dual short stub (TL2) is connected, the shape of the impedance trace according to frequency changes to a round shape as shown in 930 of Fig. 9. The round impedance trace has the characteristic of wideband matching because the impedance facing the load gets closer to the optimal impedance point (loadpull point) over a wide frequency band. To move the impedance closer to the loadpull point, the short stub (TL2) uses a transmission line with low characteristic resistance. The dual short stub (TL2) can be used as an inductive load.

[0064] The dual short stub (TL2) can serve as a DC feed to power the transistor drains. Additionally, the dual short stub (TL2) can be used as a bypass capacitor (C) for the AC ground portion. bypass ) can be added. That is, one end of the dual short stub (TL2) is connected to the front contact of the serial transmission line (TL3) in a symmetrical structure, and the other end is connected to each bypass capacitor (C bypass ) may be added.

[0065] In step 930, the wideband frequency multiplier matching device (700) connects a serial transmission line (TL1). Here, the serial transmission line (TL1) can be connected to a contact point with a drain of a transistor of the wideband frequency multiplier.

[0066] In this way, when the serial transmission line (TL1) is connected, the load pull point (Z) is as shown in 940 of Fig. 9. opt ) can be aligned with the load pull point (Z) as in 940 of Fig. 9. opt ) is wrapped around the output network, so it can be seen that it is matched over a wide frequency band and the output network exhibits broadband characteristics.

[0067] FIG. 10 and FIG. 11 are diagrams comparing the output reflection coefficient and output power according to the output matching structure of a frequency multiplier according to a conventional embodiment and an embodiment of the present invention.

[0068] As shown in Fig. 11, it can be confirmed that the bandwidth of the output reflection coefficient is about 4 times wider than that of the conventional one, from 24 GHz to 98 GHz, based on S22 = -10 dB.

[0069] In addition, as shown in Fig. 12, the conventional maximum output power is about -5 dBm, but in the output matching structure of the present invention, the maximum output power increases to about -3 dBm, and the bandwidth becomes wider from 52 GHz to 56 GHz.

[0070] In addition, in the conventional output matching structure, the length of the transmission line is 29 mm, whereas in the present invention, the length of the transmission line is 170 mm. It also has the advantage of being short and reducing chip consumption area.

[0071] Fig. 13 is a diagram showing a chip photo of a 300 GHz band wideband frequency multiplier implemented with the wideband output matching method of the present invention, and Fig. 14 is a diagram showing a layout photo of the output matching network of Fig. 13. In order to supply sufficient input power, the 300 GHz band wideband frequency multiplier is integrated with a 5-stage power amplifier, and as shown in Fig. 15, as shown in the frequency multiplier measurement results, it can be confirmed that the maximum output power is -3 dBm at 304 GHz, and the 3-dB bandwidth based on this is 272-340 GHz, implementing a wide bandwidth of approximately 68 GHz.

[0072]

[0073] The device and method according to the embodiment of the present invention may be implemented in the form of program commands that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program commands, data files, data structures, etc., alone or in combination. The program commands recorded on the computer-readable medium may be those specially designed and configured for the present invention or may be those known and usable by those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specially configured to store and execute program commands such as ROMs, RAMs, and flash memories. Examples of program commands include not only machine language codes generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter, etc.

[0074] The hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

[0075] The present invention has been described above, focusing on specific embodiments thereof. Those skilled in the art will appreciate that the present invention can be implemented in modified forms without departing from its essential characteristics. Therefore, the disclosed embodiments should be considered illustrative rather than limiting. The scope of the present invention is set forth in the claims, not the foregoing description, and all differences within the scope equivalent thereto should be construed as being encompassed by the present invention.

Claims

1. In the matching method of a wideband frequency multiplier, Output port (Y) is set to 50 for loadpull alignment sequentially from the output port. After setting to , a step of connecting an open stub (TL4) to the output port; A step of connecting a serial transmission line (TL3) to the above output port (Y); and A matching method of a wideband frequency multiplier, comprising the step of connecting a dual short stub (TL2) to the front end of the above-mentioned serial transmission line (TL3).

2. In paragraph 1, A matching method of a wideband frequency multiplier, characterized in that the above dual short stub (TL2) is connected in a symmetrical structure based on the above serial transmission line (TL3).

3. In paragraph 2, A matching method of a wideband frequency multiplier, characterized in that a bypass capacitor is connected to the terminal of the above short stub (TL2).

4. In paragraph 1, A matching method of a wideband frequency multiplier further comprising the step of connecting a serial transmission line (TL1) to the front end of the plurality of short stubs (TL2).

5. In the matching device of the wideband frequency multiplier, Output port (Y) is set to 50 for loadpull alignment sequentially from the output port. After setting to open stub (TL4) connected to the above output port; A serial transmission line (TL3) connected in series to the above output port (Y); and Including a dual short stub (TL2) connected to the front end of the above serial transmission line (TL3), A matching device of a wideband frequency multiplier, characterized in that the above dual short stubs (TL2) are connected in a symmetrical structure.

6. In paragraph 5, A matching device of a wideband frequency multiplier, characterized in that a bypass capacitor is connected to the terminal of the above dual short stub.

Images