Evaluating power dissipation

Abstract

A computer-implemented method for evaluating power dissipation of an electronic circuit design including at least one logic gate is disclosed. The method includes receiving one or more data files descriptive of the electronic circuit design, descriptive of waveform data descriptive of signal activity for logic gates used in the electronic circuit design, and descriptive of power dissipation values for internal cells of the logic gates of the electronic circuit design (701). Waveform data is extracted from the one or more data files descriptive of signal activity at primary inputs of the electronic circuit design and descriptive of outputs of registers and memories of the electronic circuit design (702). Simulation of the logic gates is performed using the extracted waveform data to generate simulated waveform data descriptive of simulated logic transitions for the internal cells of the logic gates (703), and event-based evaluation of the power dissipation of the electronic circuit design is performed based on the extracted waveform data, the simulated waveform data, and the power dissipation values (704).

Description

EVALUATING POWER DISSIPATIONFIELD

[0001] The present disclosure relates to evaluating power dissipation of an electronic circuit design.BACKGROUND

[0002] Digital electronic circuits include a chain of interconnected logic cells that together perform a logical function on one or more input signals. Such circuits experience various sources of power dissipation, such as switching power dissipation caused by the charging and discharging of capacitances at the outputs of the cells, leakage power dissipation caused by source-to-drain leakage, and internal power dissipation caused, for example, by momentary- short circuits between transistors of cells and charging and discharging of internal nets.

[0003] Power dissipation is an important consideration in the design of electronic circuits, and in particular integrated circuits (IC). which may ty pically contain millions of transistors forming the logic cells. During the IC design process, the designer may evaluate the power dissipation of the circuit repeatedly at different stages of the design process using electronic design automation software, whereby the design may be revised if the power dissipation does not meet a design specification.SUMMARY AND DESCRIPTION

[0004] Power dissipation of an integrated circuit may be evaluated based on switching activity- data recorded by a designer in a sw itching activity- file associated with an IC design, which may, for example, have been generated by the designer using switching activity- data provided by a semiconductor vendor. In the case of even moderately complex IC, how ever,reading all the recorded signals from the switching activity file into memory of a power dissipation estimator may incur substantial read time and memory resource.

[0005] A first aspect of the present disclosure, therefore, provides a computer-implemented method for evaluating power dissipation of an electronic circuit design including at least one logic gate. The method includes receiving one or more data files descriptive of the electronic circuit design, of waveform data descriptive of signal activity for logic gates used in the electronic circuit design, and of power dissipation values for internal cells of the logic gates of the electronic circuit design. The method includes extracting waveform data from the one or more data files descriptive of signal activity at primary inputs of the electronic circuit design and of outputs of registers and memories of the electronic circuit design, performing simulation of the logic gates of the electronic circuit design using the extracted waveform data to generate simulated waveform data descriptive of simulated logic transitions for the internal cells of the logic gates, and performing event-based evaluation of the power dissipation of the electronic circuit design based on the extracted waveform data, the simulated waveform data, and the power dissipation values.

[0006] Accordingly, the primary inputs to the circuit, and outputs of registers and memories of the circuit are read from the signal activity file(s), whereas the internal waveforms are simulated. As a result, the read time associated with reading all of the signals activity' waveforms from the data file(s) is reduced compared to a scenario where all of the waveform data is extracted from the signals activity file(s). Accordingly, the overhead burden for performing the power evaluation method may desirably be reduced.

[0007] In implementations, the one or more data files describe further waveform data descriptive of further signal activity of the logic gates, and the extracting waveform data from the file includes inspecting the file to distinguish the waveform data descriptive of signal activity at primary inputs of the electronic circuit design and of outputs of registers andmemories of the electronic circuit design from the further waveform data descriptive of further signal activity of the logic gates.

[0008] In implementations, the method further includes identifying simulated waveform data that is used as an input by register and / or components of the electronic circuit design, and storing that waveform data in a database, in which the waveform data is associated with the register or memory for which it is used as an input.

[0009] In implementations, the method includes retrieving the power dissipation values from the one or more data fdes and storing those power dissipation values in a local memory.

[0010] In implementations, the method includes performing the power dissipation evaluation during the simulation.

[0011] In implementations, the performing simulation includes reading the extracted waveform data with a time-based iterator.

[0012] In implementations, the method includes identifying connected logic gates and forming a connected component based on the connected logic gates. The performing simulation of the logic gates includes performing simulation of the connected components in parallel, and the performing event-based evaluation includes performing event-based evaluation of the connected components in parallel.

[0013] A second aspect of the present disclosure provides a computer system including at least one processor, and at least one memory including machine-readable instructions, where the at least one memory and the machine-readable instructions are configured to, with the at least one processor, cause the computer system to evaluate a power dissipation of an electronic circuit design including at least one logic gate by: receiving one or more data files descriptive of the electronic circuit design, of waveform data descriptive of signal activity for logic gates used in the electronic circuit design, and of power dissipation values for internal cells of the logic gates of the electronic circuit design; extracting waveform data from the oneor more data files descriptive of signal activity at primary inputs of the electronic circuit design and of outputs of registers and memories in the electronic circuit design; performing simulation of the logic gates using the extracted waveform data to generate simulated waveform data descriptive of simulated logic transitions for the internal cells of the logic gates; and performing event-based evaluation of the power dissipation of the electronic circuit design based on the extracted waveform data, the simulated waveform data, and the power dissipation values.

[0014] In implementations, the one or more data files describe further waveform data descriptive of further signal activity of the logic gates, and the at least one memory and the machine-readable instructions are configured to, with the at least one processor, cause the computer system to perform the extracting from the file by inspecting the file to distinguish the waveform data descriptive of signal activity at primary inputs of the electronic circuit design and of outputs of registers or memories in the electronic circuit design from the further waveform data descriptive of further signal activity of the logic gates.

[0015] In implementations, the at least one memory and the machine-readable instructions are configured to, with the at least one processor, cause the computer system to identify simulated waveform data that is used as an input for the event-based evaluation of power dissipation by registers and / or memories of the electronic circuit design, and store that waveform data in a database, in which the waveform data is associated with the respective register or memory for which it is used as an input.

[0016] In implementations, the at least one memory and the machine-readable instructions are configured to, with the at least one processor, cause the computer system to retrieve the power dissipation values from the one or more data files and store those power dissipation values in a local memory.

[0017] In implementations, the at least one memory and the machine-readable instructionsare configured to, with the at least one processor, cause the computer system to perform the event-based evaluation of the power-dissipation during the performing simulation.

[0018] In implementations, the at least one memory7and the machine-readable instructions are configured to, with the at least one processor, cause the computer system to perform the simulation by reading the extracted waveform data with a time-based iterator.

[0019] A third aspect of the present disclosure provides a computer program including instructions that, when executed by a computer, cause the computer to carry out the method of any of the preceding statements.

[0020] A fourth aspect of the present disclosure provides a data storage device having stored thereon the computer program of the preceding statement.

[0021] These and other aspects of the invention will be apparent from the embodiment(s) described below.BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order that the present invention may be more readily understood, embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:

[0023] Figure 1 shows schematically an example of an electronic circuit manufacturing system, including an electronic circuit evaluation system;

[0024] Figure 2 shows schematically computing hardware of the electronic circuit evaluation system;

[0025] Figure 3 shows schematically a processor of the electronic circuit evaluation system;

[0026] Figure 4 shows schematically functional modules of electronic circuit manufacturing system;

[0027] Figure 5 shows schematically combinational logic nodes of an electronic circuit design;

[0028] Figure 6 shows schematically a clock tree network of an electronic circuit design;

[0029] Figure 7 shows processes involved in evaluating power dissipation of an electronic circuit design using the electronic circuit evaluation system;

[0030] Figure 8 shows further processes involved in evaluating power dissipation of an electronic circuit design using the electronic circuit evaluation system; and

[0031] Figure 9 shows processes involved in estimating power dissipation for combinational logic nodes of the electronic circuit design using the electronic circuit evaluation system.DETAILED DESCRIPTION

[0032] Referring to Figure 1, an electronic circuit manufacturing system 101 includes an electronic circuit design system 102, an electronic circuit design evaluation system 103, and an electronic circuit fabrication system 104.

[0033] The electronic circuit design system 102 is a computer implemented system running a computer program enabling a designer to design an electronic circuit, such as an integrated circuit. The electronic circuit design system 102 receives as inputs an electronic circuit design specification and a power characterized logic cell library. The electronic circuit design specification may, for example, define specifications for computational functionality, area, circuit power consumption, etc. The standard logic cell library may describe various logic cells and their associated specifications (e.g., computational functionality, area, cell power values, behavioral models, etc.). The electronic circuit design system 102 is functional to output data describing an electronic circuit design and a data file describing switching activity in the form of waveform data for logic cells of the electronic circuit design.

[0034] The electronic circuit evaluation system 103 is a computer implemented systemrunning a computer program for evaluating operating characteristics of the electronic circuit design generated by the electronic circuit design system 102. In particular, as will be described in further detail herein, the electronic circuit evaluation system 103 is functional to estimate power dissipation for the electronic circuit design, which information may be utilized by the electronic circuit designer to revise the design of the electronic circuit, for example, to bring the electronic circuit design into compliance with power dissipation requirements defined in the circuit specification. Although the electronic circuit design system 102 and the electronic circuit evaluation system 103 are depicted in Figure 1 as being separate systems, in examples, the two systems may be implemented by a same computer program running on common computing hardw are, such as the computing system depicted in Figures 2 and 3. Thus, a designer may perform both the design and evaluation processes within a single computing environment.

[0035] The electronic circuit fabrication system 104 is a machinery-implemented system including a computer running a computer program for controlling the machinery to fabricate an electronic circuit according to the electronic circuit design generated by the electronic circuit design system 102 and evaluated by the electronic circuit evaluation system 103. For example, the electronic circuit fabrication system 104 may be configured for fabricating integrated circuits.

[0036] For the purpose of implementations of the present disclosure, the electronic circuit design system 102 and the electronic circuit fabrication system 104 may be assumed to be functionally and structurally conventional systems, and suitable system configurations would be known by the skilled person. The present disclosure is instead directed, in particular, to the functionality and structure of the electronic circuit design evaluation system 103. which will be described in further detail herein.

[0037] Referring next to Figures 2 and 3. examples of the electronic circuit evaluationsystem 103 may be implemented through the execution of machine-readable instructions contained in a computer program run by a computing system 201, such as a programmable computer. Accordingly, Figure 2 shows an illustrative example of a computing system 201 suitable for implementing the electronic circuit evaluation system. Referring firstly to Figure 2, the computing system 201 includes a computing device 202 with a processor 203 and a system memory 204. The processor 203 may be any type of programmable electronic device for executing software instructions, but will conventionally be a microprocessor. The system memory' 204 may include both a read-only memory (ROM) 205 and a random access memory' (RAM) 206. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 205 and the random access memory (RAM) 206 may store software instructions for execution by the processor 203.

[0038] The processor 203 and the system memory 204 are connected, either directly or indirectly, through a bus 207 or alternate communication structure, to one or more peripheral devices 208-212. For example, the processor 203 or the system memory 204 may be directly or indirectly connected to one or more additional memory storage devices, such as a hard disk drive 209, which may be magnetic and / or removable, a removable optical disk drive 210, and / or a flash memory card. The processor 203 and the system memory 204 also may be directly or indirectly connected to one or more input devices 211 and one or more output devices 212. The input devices 211 may include, for example, a keyboard, a pointing device (e.g., a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 212 may include, for example, a monitor display, a printer, and speakers. With various examples of the computing system 201, one or more of the peripheral devices 208-212 may be internally housed with the computing device 202.Alternately, one or more of the peripheral devices 208-212 may be external to the housing for the computing device 202 and connected to the bus 207 through, for example, a UniversalSerial Bus (USB) connection.

[0039] With some implementations, the computing device 202 may be directly or indirectly connected to a network interface 208 for communicating with other devices making up a network. The network interface 208 may translate data and control signals from the computing device 202 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface 208 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

[0040] The computing system 201 is illustrated as an example only, and it not intended to be limiting. Various embodiments may be implemented using one or more computing devices that include the components of the computing system 201, which include only a subset of those components, or which include an alternate combination of components, including components that are not shown in Figure 2. For example, various embodiments may be implemented using a multi-processor computer, a plurality of single and / or multiprocessor computers arranged into a network, or some combination of both.

[0041] In some implementations of the disclosure, the processor 203 may have more than one processor core. Accordingly, Figure 3 illustrates an example of a multi-core processor 203 that may be employed in some implementations. As seen in this figure, the processor 203 includes a plurality of processor cores 301, 302. Each processor core 301, 302 includes a computing engine 303 and 304, respectively, and a memory cache 305 and 306, respectively. As known to those of ordinary skill in the art, a computing engine 303 and 304 may include logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. Theseactions may include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR, and XOR, and retrieving data. Each computing engine 303 and 304 may then use its corresponding memory cache 305 and 306, respectively, to quickly store and retrieve data and / or instructions for execution.

[0042] Each processor core 301 and 302 is connected to an interconnect 307. The particular construction of the interconnect 307 may vary depending upon the architecture of the processor 203. With some processor cores, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect 307 may be implemented as an interconnect bus. With other processor units, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, California, the interconnect 307 may be implemented as a system request interface device. In any case, the processor cores 301 communicate through the interconnect 207 with an input / output interface 309 and a memory controller 310. The input / output interface 308 provides a communication interface to the bus 207. Similarly, the memory controller 310 controls the exchange of information to the system memory 204. With some implementations, the processor 203 may include additional components, such as a high-level cache memory accessible shared by the processor cores 301, 302. The description of the computer network illustrated in Figure 2 and Figure 3 is provided as an example only, and is not intended to suggest any limitation as to the scope of use or functionality of alternate embodiments.

[0043] Referring next to Figure 4, the electronic circuit design evaluation system 103 includes an extraction system 401, a simulation system 402, and a power estimation system 403. Data flows are depicted schematically in Figure 4 by labelled arrows.

[0044] The extraction system 401 accesses an electronic circuit design file and a switching activity data file generated by the electronic circuit design system 102. The extraction system401 may, for example, access the files stored in external storage controlled by the electronic circuit design system 102 and stream all or part of the files from the external storage when needed. Alternatively, the extraction system 401 may receive the files from the electronic circuit design system 102 and store the files internally, for example, in system memory 204 or hard disk drive 209.

[0045] The electronic circuit design may, for example, have been designed based on one or more standard cell libraries. The received circuit design may describe the electronic circuit in terms of exchange of data signals between components in the electronic circuit, such as hardware registers, flip-flops, combinational logic, etc., and in terms of logical operations that may be performed on the data signals by the electronic circuit. The circuit design may model the electronic circuit at a register transfer level (RTL), for example, with code in a hardware description language (HDL), such as SystemVerilog, Very high speed Integrated Circuit Hardware Description Language (VHDL), System C, or similar. The extraction system 401 may receive the electronic circuit design file and store the file in system memory 204.

[0046] The switching activity file, for example, in the format of Fast Signal Database (FSDB), or similar, defines waveforms of signals representing switching activity for cells of the design. The switching activity file may, for example, be generated by the electronic circuit design system 102 based on an RTL transaction simulation, using behavioral models of standard cells included in the cell library.

[0047] The extraction system 401 is functional to identify and extract waveform data in the switching activity file corresponding to the primary inputs of the design and outputs of registers and memories of the electronic circuit design. In examples to be described herein, the extraction system may further extract waveform data corresponding to outputs of hard- macros in the electronic circuit design (i. e. , components of the design for which simulation isnot possible). The extraction system 401 may then load the extracted waveforms in the system memory 204.

[0048] The simulation system 402 is functional to perform simulation of the electronic circuit design received from the design system 102. The simulation system 402 receives as inputs the electronic circuit design file output by the design system 102, the switching activity7waveform data output by the extraction system 401 corresponding to the primary' inputs and registers, memories, and hard-macros, and a technology library file.

[0049] The technology library, for example, specified in a Liberty' format, may describe the cells of the circuit design in terms of timing information, area, and power dissipation values (e.g., including leakage power and dynamic power data, etc.). In some embodiments, the technology' library may specify the internal power details for logic gates (e.g., power estimates for different arcs associated with the logic gates). For example, the technologylibrary may include a power estimate value table for each arc, which may be indexable by a combination of an input capacitance and a slew associated with the arcs of the logic gates. Each logic gate may have one or more different ty pes of arcs, such an input-output (I / O) arc or a self-arc. The I / O arc may correspond to a path between an input of the logic gate and an output of the logic gate, for example, activated when a change occurs on the output of the logic gate. The self-arc also may correspond to a path between an input a to a same input of the logic gate, for example, activated when a change occurs on the input of the logic gate, while the output remains the same.

[0050] The simulation system 402 may thereby perform simulation on the electronic circuit design, based on the primary input and register / memory / hard-macros output waveform data, and the relevant cell information in the technology library, to thereby recreate switching activity waveform information for the internal nodes of the logic gates for which switching activity waveforms were not extracted by the extraction system 401. The simulation system402 may subsequently store the simulated waveform data for clock and data inputs of the registers / memories / hard-macros in the disk 209. The simulation process performed by the simulation system 402 will be described in further detail with reference to Figures 7 and 8.

[0051] The power estimation system 403 receives as inputs the primary input and register / memory / hard-macros output waveform data generated by the extraction system 401, the internal waveform data simulated by the simulation system 402, the electronic circuit design fde, and the technology library file.

[0052] The power estimation system 403 is functional to compute power estimates for the logic cells of the electronic circuit design based on the inputs by an event-based power estimation method. The power estimation system 403 may include a waveform analysis system to read the input waveform data. In some embodiments, the waveform analysis system may implement a time-based iterator to read the waveform data for signals corresponding to all logic gates. The time-based iterator may read the waveform data according to the order of the toggle events as opposed to on a signal-by-signal basis, which allows the waveform analysis system to read the waveform data in time order for all signals, instead of once for each signal in the waveform data.

[0053] The power estimation system 403 may generate an estimate of power consumption for the circuit design based on an accumulation of the power estimates for the signals. In some embodiments, the power estimation system 403 may add the power estimates for each of the arcs and ’When’ conditions, which may correspond to a total dynamic energy estimate for the circuit design. The power estimation system may also determine a total power estimate for the circuit design by dividing the total dynamic energy estimate by the duration of the evaluation of the circuit design.

[0054] The power estimation system 403 may then output the power estimates for the cells of the electronic circuit design. For example, the power estimation system 403 may output thepower estimates to the design system 102, whereby the designer may utilize the design system 102 to assess whether the electronic circuit design meets the design specification and make revisions to the design if appropriate. And the procedures associated with creating, evaluating, and revising an electronic circuit design may be repeated during the electronic circuit design process until a final electronic circuit design is achieved. Else, when a final electronic circuit design has been reached, the evaluation system 103 may output the evaluated electronic circuit design to the circuit fabrication system 104, whereby an electronic circuit may be fabricated to the design.

[0055] Referring next to Figures 5 and 6, which depict schematically combinational logic gates and a clock network respectively, it may be seen that the present disclosure to power estimation involves a mixed mode approach for obtaining waveforms of activity in the electronic circuit design.

[0056] In Figures 5 and 6, a solid black filled node indicates waveform data extracted by the extraction system 401 from the switching activity file, whereas an empty fill node indicates a waveform simulated by the simulation system 402 that is not stored, and a grayscale node indicates a waveform simulated by the simulation system 402 that is stored. It may thus be seen that the primary inputs and register / memory / hard-macros outputs only are extracted from the switching activity file by the extraction system 401, whereas the internal waveforms are all simulated by the simulation system 402.

[0057] Because it is only the primary inputs and register / memory / hard-macros outputs that are extracted from the switching activity file, the read time associated with extracting the waveform data from the switching activity file may be reduced compared to a scenario where all of the waveform data is extracted from the switching activity file.

[0058] Referring next to Figure 7, in examples, the computer program for evaluating power dissipation of an electronic circuit design implemented by the evaluation system 103 includesfour stages.

[0059] At stage 701, the computer program causes the processor 203 of the evaluation system 103 to receive the circuit design data file descriptive of the electronic circuit design, and the switching activity7data file containing waveform data descriptive of signal activity for logic gates used in the electronic circuit design, and of power dissipation values for internal cells of the logic gates of the electronic circuit design.

[0060] At stage 702, the computer program causes the processor 203 of the evaluation system 103 to extract waveform data from the switching activity7data file descriptive of signal activity7at primary' inputs of the electronic circuit design and of outputs of registers, memories, and hard-macros of the electronic circuit design.

[0061] At stage 703, the computer program causes the processor 203 of the evaluation system 103 to perform simulation of the logic gates using the extracted waveform data to generate simulated waveform data descriptive of simulated logic transitions for the internal cells of the logic gates.

[0062] At stage 704, the computer program causes the processor 203 of the evaluation system 103 to perform event-based evaluation of the power dissipation of the electronic circuit design based on the extracted waveform data, the simulated waveform data, and the power dissipation values.

[0063] Referring next to Figure 8, in examples, the computer program for estimating power dissipation for the electronic circuit design implemented by the evaluation system 103 includes four stages.

[0064] At stage 801, the computer program causes the processor 203 of the evaluation system 103 to perform the simulation and power estimation processes for estimating power dissipation of the combinational logic gates of the electronic circuit design. At this stage, the evaluation system 103 stores in local memory 204 only the power estimates for the nodes ofthe combinational logic gates and stores in disk 209 the waveforms simulated for the combinational logic gates that are used as data inputs by the registers and memory.

[0065] At stage 802, the computer program causes the processor 203 of the evaluation system 103 to perform the simulation and power estimation processes for estimating power dissipation of the clock tree of the electronic circuit design. At this stage, the evaluation system 103 stores in local memoi 204 only the power estimates for the nodes of the clock tree and stores in disk 209 the waveforms simulated for the clock tree nodes that are used as clock inputs by the registers and memory.

[0066] At stage 803, the computer program causes the processor 203 of the evaluation system 103 to perform the power estimation processes for estimating power dissipation of the registers using the simulated waveforms stored in stages 701 and / or 702, and stores the power estimates for the registers in the local memoiy 204.

[0067] At stage 804, the computer program causes the processor 203 of the evaluation system 103 to perform the power estimation processes for estimating power dissipation of the memory / hard-macros using the simulated waveforms stored in stages 701 and 702, and stores the power estimates for the memory / hard-macros in the local memory 204.

[0068] The above order of power estimation has the advantage that the waveforms required for each stage are already available due to the simulation in the preceding steps. Further, because for each of the combinational logic gates and the clock tree, the waveform simulation and the power estimation are performed simultaneously, read and write time involved in writing the simulated waveforms to a storage disk by the simulation system and reading the waveforms back from the storage disk by a power estimation system are reduced As the waveforms are simulated, the simulated waveforms may be simultaneously used by the power estimator to generate the power estimations.

[0069] Referring next to Figure 9, the method of process 801 for estimating power for thecombinational logic nodes of the electronic circuit design performed by the evaluation system 103 includes fifteen stages.

[0070] At stage 901, the computer program causes the processor 203 of the evaluation system 103 to initiate the method. Stage 901 may, for example, involve receiving a command input by the designer via the input device 211.

[0071] At stages 902 and 903, the computer program causes the processor 203 of the evaluation system 103 to identify and collect all combinational logic nodes for the electronic circuit design, and create a model describing a connected component representing all of the combinational logic nodes, as depicted in Figure 5. The following stages are then performed in parallel for each connected component in the electronic circuit design.

[0072] At stage 904, the computer program causes the processor 203 of the evaluation system 103 to create a time-based waveform iterator using the primary input waveform of the subject connected component created at stage 903.

[0073] At stage 905, the computer program causes the processor 203 of the evaluation system 103 to determine whether a subsequent timeline is available to the waveform iterator. Where the determination is in the affirmative, indicating that further timelines are available for processing, the method proceeds to stage 906.

[0074] At stage 906, the computer program causes the processor 203 of the evaluation system 103, for each input signal, to collect value changes for the current timeline and pack it in respective timeline bit index of the 64-bit size current state integer associated with the signal.

[0075] At stage 907, the computer program causes the processor 203 of the evaluation system 103 to determine whether the 64 timeline bit-indexes has been created. Where the determination is in the affirmative, indicating that the 64 timeline bit-indexes is complete, the method proceeds to stage 808.

[0076] At stage 908, the computer program causes the processor 203 of the evaluation system 103 to perform the 64-bit state propagation for all the internal nodes in the design in topological order.

[0077] At stage 909, the computer program causes the processor 203 of the evaluation system 103 to save the current state to the previous state.

[0078] Based on stage 910, the computer program causes the processor 203 of the evaluation system 103 to perform a leakage power estimation process by identifying excited 'When’ conditions expression using signals previous state.

[0079] At stage 911, the computer program causes the processor 203 of the evaluation system 103 to store the current state if a signal is driving register / memory / hard-macros inputs.

[0080] At stage 912, the computer program causes the processor 203 of the evaluation system 103 to evaluate XOR operation of current state and previous state. The computer program further iterates all the set bits of the output of XOR operation to identify' all the toggle events.

[0081] At stage 913, the computer program causes the processor 203 of the evaluation system 103 to perform switching power estimation for all toggle events.

[0082] At stage 914, the computer program causes the processor 203 of the evaluation system 103 to identify excited arcs based on toggle events and ‘When’ condition expression based on previous state.

[0083] At stage 915, the computer program causes the processor 203 of the evaluation system 103 to perform internal power computation for every excited arc and ‘When’ condition.

[0084] The system and apparatus described above may use dedicated processor systems, micro controllers, programmable logic devices, microprocessors, or any combination thereof,to perform some or all of the operations described herein. Some of the operations described above may be implemented in software, and other operations may be implemented in hardware. Any of the operations, processes, and / or methods described herein may be performed by an apparatus, a device, and / or a system substantially similar to those as described herein and with reference to the illustrated figures.

[0085] The processing device may execute instructions or "code" stored in memory. The memory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission.

[0086] The processor memory may be integrated together with the processing device (e.g., RAM or FLASH memory disposed within an integrated circuit microprocessor or the like). In other examples, the memory may include an independent device, such as an external disk drive, a storage array, a portable FLASH key fob, or the like. The memory and processing device may be operatively coupled together, or in communication with each other, for example, by an I / O port, a network connection, or the like, and the processing device may read a file stored on the memory. Associated memory may be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which may be implemented in solid state semiconductor devices. Other memories may include moving parts, such as a known rotating disk drive. All such memories may be "machine-readable" and may be readable by a processing device.

[0087] Operating instructions or commands may be implemented or embodied in tangibleforms of stored computer software (also known as "computer program" or "code").Programs, or code, may be stored in a digital memory and may be read by the processing device. ‘‘Computer-readable storage medium" (or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory', as well as new technologies of the future, as long as the memory' may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device. The term "computer- readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, mini-computer, desktop or even laptop computer. Rather, "computer-readable" may include storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and / or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non-removable media, or any combination thereof.

[0088] A program stored in a computer-readable storage medium may include a computer program product. For example, a storage medium may be used as a convenient means to store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program, or operation with unclear boundaries.

[0089] While the application describes specific examples of carrying out embodiments of the invention, those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques that fall within the spirit and scope of the invention as set forth in the appended claims. For example, while specific terminology has been employed above to refer to electronic design automation processes, various examples of the invention may be implemented using any desired combination ofelectronic design automation processes.

[0090] One of skill in the art will also recognize that the concepts taught herein may be tailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are but one of many alternative implementations that will become apparent upon reading this disclosure.

[0091] Although the specification may refer to “an”, “one”, “another”, or “some” example(s) in a number of locations, this does not necessarily mean that each such reference is to the same example(s), or that the feature only applies to a single example.

[0092] The elements and features recited in the appended claims may be combined in different ways to produce new claims that likewise fall within the scope of the present invention. Thus, whereas the dependent claims appended below depend from only a single independent or dependent claim, it is to be understood that these dependent claims may, alternatively, be made to depend in the alternative from any preceding or following claim, whether independent or dependent. Such new combinations are to be understood as forming a part of the present specification.

[0093] While the present invention has been described above by reference to various embodiments, it should be understood that many changes and modifications can be made to the described embodiments. It is therefore intended that the foregoing description be regarded as illustrative rather than limiting, and that it be understood that all equivalents and / or combinations of embodiments are intended to be included in this description.

Claims

Claims1. A method for evaluating power dissipation of an electronic circuit design including at least one logic gate, the method being computer-implemented and comprising: receiving one or more data files descriptive of the electronic circuit design, descriptive of waveform data descriptive of signal activity for logic gates used in the electronic circuit design, and descriptive of power dissipation values for internal cells of the logic gates of the electronic circuit design; extracting waveform data from the one or more data files descriptive of signal activity at primary inputs of the electronic circuit design and descriptive of outputs of registers and memories of the electronic circuit design; performing simulation of the logic gates using the extracted waveform data, such that simulated waveform data descriptive of simulated logic transitions for the internal cells of the logic gates is generated; and performing event-based evaluation of the power dissipation of the electronic circuit design based on the extracted waveform data, the simulated waveform data, and the power dissipation values.

2. The method of claim 1, wherein the one or more data files describe further waveform data descriptive of further signal activity of the logic gates, and wherein extracting the waveform data from the one or more data files comprises inspecting the one or more data files to distinguish the waveform data descriptive of the signal activity at the primary inputs and descriptive of the outputs of the registers andmemories of the electronic circuit design from the further waveform data descriptive of the further signal activity of the logic gates.

3. The method of claim 1, further comprising: identifying simulated waveform data that is used as an input by registers or memories of the electronic circuit design; and storing the identified simulated waveform data in a database in which the identified simulated waveform data is associated with the respective register or memory for which the identified simulated waveform data is used as an input.

4. The method of claim 1, further comprising: retrieving the power dissipation values from the one or more data files; and storing the power dissipation values in a local memory.

5. The method of claim 1, further comprising performing the event-based evaluation of power-dissipation during the performing of the simulation of the logic gates.

6. The method of claim 1, wherein the performing of the simulation of the logic gates comprises reading the extracted waveform data with a time-based iterator.

7. The method of claim 1, further comprising identifying connected logic gates and forming a connected component based on the connected logic gates, wherein the performing of the simulation of the logic gates comprises performing simulation of the connected components in parallel, andwherein the performing of the event-based evaluation comprises performing eventbased evaluation of the connected components in parallel.

8. A computer system comprising: at least one processor; and at least one memory including machine-readable instructions, wherein the at least one memory and the machine-readable instructions are configured to, with the at least one processor, cause the computer system to evaluate a power dissipation of an electronic circuit design including at least one logic gate, the machine-readable instructions comprising: receiving one or more data files descriptive of the electronic circuit design, descriptive of waveform data descriptive of signal activity for logic gates used in the electronic circuit design, and descriptive of power dissipation values for internal cells of the logic gates of the electronic circuit design; extracting waveform data from the one or more data files descriptive of signal activity at primary inputs of the electronic circuit design, and descriptive of outputs of registers and memories of the electronic circuit design; performing simulation of the logic gates using the extracted waveform data, such that simulated waveform data descriptive of simulated logic transitions for the internal cells of the logic gates is generated; and performing event-based evaluation of the power dissipation of the electronic circuit design based on the extracted waveform data, the simulated waveform data, and the power dissipation values.

9. The computer system of claim 8, wherein the one or more data files describe further waveform data descriptive of further signal activity of the logic gates, and wherein the extracting of the waveform data from the one or more data files comprises inspecting the one or more files to distinguish the waveform data descriptive of the signal activity at the primary inputs of the electronic circuit design and descriptive of the outputs of the registers or memories of the electronic circuit design from the further waveform data descriptive of further signal activity of the logic gates.

10. The computer system of claim 8, wherein the at least one memory and the machine- readable instructions are further configured to, with the at least one processor, cause the computer system to: identify simulated waveform data that is used as an input by registers or memories of the electronic circuit design; and store the identified simulated waveform data in a database in which the identified simulated waveform data is associated with the respective register or memory for which the identified simulated waveform data is used as an input.

11. The computer system of claim 8, wherein the at least one memory and the machine- readable instructions are further configured to, with the at least one processor, cause the computer system to: retrieve the power dissipation values from the one or more data files; and store the power dissipation values in a local memory.

12. The computer system of claim 8, wherein the at least one memory and the machine- readable instructions are further configured to, with the at least one processor, cause the computer system to perform the event-based evaluation of the power-dissipation during the performing of the simulation of the logic gates.

13. The computer system of claim 8, wherein the performing of the simulation of the logic gates comprises reading the extracted waveform data with a time-based iterator.

14. A computer program comprising instructions, which, when executed by a computer, cause the computer to carry out the method of claims 1 to 7.

15. A data storage apparatus having stored thereon the computer program of claim 14.

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