Electrical circuit arrangement in the form of a transmission gate

Abstract

The invention relates to an electrical circuit arrangement in the form of a transmission gate, having two transistors connected in parallel, of which one transistor is designed as an NMOS transistor (MN) and another transistor is designed as a PMOS transistor (MP), the gate contacts of which can be supplied with a control voltage potential (Vc, Vc) which is inverted relative to one other, and the drain and source connections of which are each connected to one other and each constitute a connection contact (Vin, Vout) of the circuit arrangement. The invention is characterised in that 2 n NMOS transistors (MNa, MNb, MNc, MNd), where n > 2, are connected in parallel to the source-drain path of the NMOS transistor (MN) and each have source-drain paths connected in series. The NMOS transistor (MN) has a substrate connection which is connected to a voltage potential which can be tapped at a contact point between the interconnected source-drain paths of a transistor pair which is arranged centrally in the sequence along the 2 n transistors (MNa, MNb, MNc, MNd) connected in series. The contact point is connected to a source-drain path of a further NMOS transistor (MNe), which path is connected to a negative supply voltage (VSS) and to the gate contact of which transistor the inverted control voltage potential (Vc) is applied. The gate contacts of the centrally arranged transistor pair are each connected to that connection contact (Vin, Vout) which is opposite the respective transistor of the transistor pair relative to the contact point. The NMOS transistors (MNc, MNd) of the 2 n transistors (MNa, MNb, MNc, MNd) connected in series, said transistors adjoining the centrally arranged NMOS transistor pair on both sides, each have a gate contact connected to the supply voltage VC and a substrate connection connected to the negative supply voltage (VSS). Finally, the PMOS transistor (MP) is assigned an arrangement of 2 n PMOS transistors (MPa, Mpb, MPc, MPd), which is inversely symmetrical with respect to the above-mentioned transistor arrangement, and a further PMOS transistor (MPe).

Description

[0001] Electrical circuit arrangement in the form of a transmission gate

[0002] Technical area

[0003] The invention relates to an electrical circuit arrangement in the form of a transmission gate, with two transistors connected in parallel, of which one transistor is designed as an NMOS transistor and the other as a PMOS transistor, whose gate contacts can be supplied with a control voltage potential that is inverted relative to one another and whose drain and source terminals are each connected to one another and each represent a connection contact of the circuit arrangement.

[0004] State of the art

[0005] In microelectronics, a transmission gate is an integrated electronic circuit arrangement that can conduct or block currents in both directions through the circuit arrangement, similar to a control signal.

[0006] Typically, a transmission gate consists of two parallel-connected field-effect transistors, an NMOS FET and a PMOS FET, with their drain and source contacts connected to each other. The gate contacts are connected to each other via an inverter, so that control signals that are inverted relative to each other are applied to both gate contacts.

[0007] Since a transmission gate can pass current in both directions and block current, the substrate terminals are connected to the respective supply voltage potential to ensure that the substrate diodes are always operated in reverse bias. The substrate terminal of the n-channel MOSFET is therefore connected to the negative supply voltage potential, and the substrate terminal of the p-channel MOSFET is connected to the positive supply voltage potential.

[0008] Figure 1 shows a known circuit arrangement for forming a transmission gate TG, in which oppositely driven NMOS (MN) and PMOS (MP) transistors serve as switches between an input voltage 7in and an output voltage 7out. The mutually complementary control voltages Vc and Vc are applied to the gate contacts of both parallel-connected transistors MN and MP via an inverter (not shown).

[0009] If the control voltage Vc corresponds to the negative supply voltage Vss of the NMOS transistor MN, the resistance between the two voltage nodes Vin and Vout is very high, i.e., the transmission gate has a very large resistance Δfoff, so that the TG represents an open switching state. If the control voltage Vc corresponds to the positive supply voltage VDD of the NMOS transistor MP, i.e., Vc = VDD, one would therefore expect both transistors MN and MP to be turned on, i.e., to have a low on-resistance Δfon. However, especially at low supply voltages, e.g., V0D / 2~7th, a relatively large resistance Δfon of several 1 ΩkΩ is observed, which cannot be tolerated in all cases.

[0010] A simple measure would be to increase the size of the transistors. While this would further reduce Ron, it would also lead to a reduction in / ?off. In addition to the associated space constraints, it is important to consider, especially in low-power circuits, that leakage currents in the order of nanoamps should be avoided. However, this means that / ?off must be in the range of GQ.

[0011] A known measure for reducing the on-resistance Ron in a transmission gate involves voltage control of the substrates of both transistors MN and MP, i.e., bulk control. The substrate voltage of transistor MP must be kept at the highest voltage and the substrate voltage of transistor MN at the lowest voltage in the circuit to prevent conduction effects on the parasitic diodes in the transistors. However, studies on transmission gates with bulk control have shown that while the on-resistance / ?on can be significantly reduced in this way, this measure also has a detrimental effect on reducing the off-resistance Roff.

[0012] The documents US 6 020 778 A and US 5 767 733 A each disclose a transmission gate with bulk voltage control, but they have the above-mentioned disadvantages.

[0013] Description of the invention

[0014] The invention is based on the object of developing an electrical circuit arrangement in the manner of a transmission gate, with two transistors connected in parallel, of which one transistor is designed as an NMOS transistor and the other as a PMOS transistor, whose gate contacts can be supplied with a control voltage potential that is inverted relative to one another and whose drain and source connections are each connected to one another and each represent a connection contact of the circuit arrangement, in such a way that the on-resistance Ron should be as small as possible and at the same time the off-resistance Roff should be as large as possible.

[0015] The solution to the problem underlying the invention is specified in claim 1. Features that advantageously further develop the inventive concept are the subject of the subclaims and the further description, in particular with reference to the figure.

[0016] The electrical circuit arrangement according to the solution with the features of the preamble of claim 1 is characterized in that 2 n NMOS transistors, with n > 2, each with series-connected source-drain paths, are connected in parallel to the source-drain path of the NMOS transistor. The NMOS transistor has a substrate terminal connected to a voltage potential that can be tapped at a contact point between the interconnected source-drain paths of a transistor pair that is arranged centrally in the sequence along the 2 n transistors connected in series. The contact point is connected to the source-drain path of another NMOS transistor, which is connected to a negative supply voltage and to whose gate contact the inverted control voltage potential is applied.

[0017] The gate contacts of the centrally arranged transistor pair are each connected to the terminal contact that is opposite the respective transistor of the transistor pair relative to the contact point.

[0018] Furthermore, the NMOS transistors of the series-connected 2n transistors adjacent to the centrally arranged NMOS transistor pair each have a gate contact connected to the supply voltage and a substrate connection connected to the negative supply voltage. Finally, the PMOS transistor is assigned an inversely symmetrical arrangement of 2n PMOS transistors and another PMOS transistor.

[0019] For further explanation of the circuit according to the solution, reference is made to the following description with reference to Figure 1.

[0020] Brief description of the invention

[0021] The invention is described below, without limiting the general inventive concept, using an exemplary embodiment with reference to the drawing. It shows:

[0022] Fig. 1 Transmission gate according to the state of the

[0023] technology, and

[0024] Fig. 2 Circuit arrangement according to the solution. Ways of implementing the invention, industrial applicability

[0025] Figure 2 shows an electrical circuit arrangement in the form of a transmission gate, with two transistors connected in parallel, one of which is designed as an NMOS transistor MN and the other as a PMOS transistor MP, whose gate contacts can be supplied with a control voltage potential Vc, Vc that is inverted relative to one another. An inverter required for this purpose has been omitted. The drain and source terminals of the NMOS transistor MN and PMOS transistor MP are each connected to one another and each represent a connection contact in, out of the circuit arrangement, to which the input and output voltages Vin, Vout are applied.

[0026] Four NMOS transistors MNa, MNb, MNc, and MNd, each with a series-connected source-drain path, are connected in parallel to the source-drain path of the NMOS transistor MN. The NMOS transistor MN also has a substrate terminal connected to a voltage potential that can be tapped at a contact point K between the interconnected source-drain paths of a transistor pair arranged centrally in the sequence along the four series-connected transistors MNa, MNb, MNc, and MNd.

[0027] The contact point K is further connected to the source-drain path of another NMOS transistor MNe, which is connected to a negative supply voltage VSS and to whose gate contact the inverted control voltage potential (7c) is applied.

[0028] The gate contacts of the centrally arranged transistor pair MNa, MNb are each connected to the connection contact in, out that is opposite the respective transistor of the transistor pair MNa, MNb relative to the contact point K.

[0029] The NMOS transistors MNc, MNd of the four transistors MNa, MNb, MNc, MNd connected in series on both sides of the centrally arranged NMOS transistor pair MNa, MNb each have a gate contact connected to the supply voltage VC and a substrate connection connected to the negative supply voltage VSS.

[0030] The PMOS side of the electrical circuit arrangement is designed in a mirror image to the above arrangement of the explained NMOS transistors MN, MNa, MNb, MNc, MNd, MNe, that is:

[0031] Four PMOS transistors MPa, MPb, MPc, and MPd, each with a series-connected source-drain path, are connected in parallel to the source-drain path of the PMOS transistor MP. The PMOS transistor MP also has a substrate terminal connected to a voltage potential that can be tapped at a contact point K' between the interconnected source-drain paths of a transistor pair MPa, MPb, which is arranged centrally in the sequence along the four series-connected transistors MPa, MPb, MPc, and MPd.

[0032] The contact point K' is further connected to the source-drain path of another PMOS transistor MPe, which is connected to a positive supply voltage VDD and to whose gate contact the control voltage potential VC is applied.

[0033] The gate contacts of the centrally arranged transistor pair MPa, MPb are each connected to the connection contact in, out that is opposite the respective transistor of the transistor pair MPa, MPb relative to the contact point K'.

[0034] The PMOS transistors MPc, MPd of the four transistors MPa, MPb, MPc, MPd connected in series on both sides of the centrally arranged PMOS transistor pair MPa, MPb each have a gate contact connected to the inverted supply voltage Vc and a substrate connection connected to the positive supply voltage VDD.

[0035] The operation of the circuit arrangement is explained for the switched-on circuit state, ie VC = VDD, using the NMOS circuit part:

[0036] When VC = VDD, transistors MNe are "off," meaning blocked, and MNc and MNd are "on," meaning conductive. Transistors MNa and MNb are active, ensuring that the lower voltage of the input and output voltages Vin and Vout is applied to transistor MN as the bulk voltage. In the case of the PMOS circuit, it should be noted that the higher voltage is applied to PMOS transistor MP as the bulk voltage.

[0037] This type of bulk voltage control on the transistors MN and MP ensures, especially in the case of higher currents, which can lead to a considerable voltage drop between the connection contacts in and out, that specific voltages are assigned to the respective bulk potential, as explained above, which serve as quite robust and safe working potentials.

[0038] As a result, the transistor MN opens and forms a significantly lower resistance Ron.

[0039] In the off-state, i.e., Vc = VSS, transistors MNe are "on," and transistors MNc and MNd are "off." In this case, transistors MNa and MNb cannot conduct any potential because their drain contacts each represent high-impedance nodes. The bulk voltage of transistor MN is determined exclusively by transistor MNe and pulled to the supply voltage VSS. This causes resistor Roff to have a very high resistance, significantly higher than with comparable measures.

[0040] A very high resistance in the off state is essential, especially in highly sensitive applications, such as implantable electronic devices used to treat various types of neurological disorders by stimulating nerves with electrical charge. The electrical circuitry underlying these implants is multifunctional, highly integrated circuitry designed with the highest operational reliability, maximum energy efficiency, and the greatest possible miniaturization in mind. Especially in intracorporeal electrical stimulation of certain body regions, such as nerve fibers, leakage currents via electrodes that contact biological tissue areas are intolerable. Leakage currents can thus lead to permanent charge integration on electrodes, which must be prevented.

[0041] List of reference symbols in input contact out output contact

[0042] Vin input voltage

[0043] Vout output voltage

[0044] MN, MNa, NMOS transistors

[0045] MNb, MNc NMOS transistors

[0046] MNd, MNe NMOS transistors

[0047] MP, MPa, PMOS transistors

[0048] MPb, MPc PMOS transistors

[0049] MPd, MPe PMOS transistors

[0050] VDD positive supply voltage

[0051] VSS negative supply voltage

[0052] Vc control voltage

[0053] Vc inverted supply voltage

[0054] K, K' node

Claims

Patent claims 1. An electrical circuit arrangement in the form of a transmission gate, comprising two transistors connected in parallel, one of which is an NMOS transistor (MN) and the other a PMOS transistor (MP), whose gate contacts can be supplied with a control voltage potential (Vc, Vc) that is inverted relative to one another, and whose drain and source terminals are each connected to one another and each represent a connection contact (in, out) of the circuit arrangement, characterized in that 2 n NMOS transistors (MNa, MNb, MNc, MNd), with n > 2, each with series-connected source-drain paths, are connected in parallel to the source-drain path of the NMOS transistor (MN), that the NMOS transistor (MN) has a substrate terminal connected to a voltage potential that can be tapped at a contact point between the interconnected source-drain paths of a transistor pair,which is arranged centrally in the sequence along the series-connected 2 n transistors (MNa, MNb, MNc, MNd), that the contact point is connected to a source-drain path of another NMOS transistor (MNe), which is connected to a negative supply voltage (VSS) and at whose gate contact the inverted, Control voltage potential (7c) is applied, that the gate contacts of the centrally arranged transistor pair are each connected to that connection contact (in, out) which is opposite the respective transistor of the transistor pair relative to the contact point, that the NMOS transistors (MNc, MNd) of the 2 n transistors (MNa, MNb, MNc, MNd) connected in series on both sides of the centrally arranged NMOS transistor pair each have a gate contact connected to the supply voltage VC and a substrate connection connected to the negative supply voltage (VSS), and that the PMOS transistor (MP) is assigned an arrangement of 2 n PMOS transistors (MPa, Mpb, MPc, MPd) which is inversely symmetrical to the above transistor arrangement, as well as a further PMOS transistor (MPe).

2. Electrical circuit arrangement according to claim 1, characterized in that the inversely symmetrical arrangement provides 2 n connected PMOS transistors (MPa, MPb, MPc, MPd) with n > 2, each with series-connected source-drain paths, parallel to the source-drain path of the PMOS transistor (PN), that the PMOS transistor (MP) has a substrate connection which is connected to a voltage potential which can be tapped at a contact point (K') between the interconnected source-drain paths of a transistor pair (MPa, MPb) which is arranged centrally in the sequence along the series-connected 2 n transistors (MPa, MPb, MPc, MPd), that the contact point (K') is connected to a source-drain path of a further PMOS transistor (MPe), which is connected to a positive supply voltage (VDD) and at whose gate contact the Control voltage potential (Vc) is applied so that the gate contacts of the centrally arranged transistor pair (MPa,MPb) are each connected to that connection contact (in, out) which is opposite the respective transistor of the transistor pair relative to the contact point (K'), and that the PMOS transistors (MPc, MPd) of the 2 n transistors (MPa, MPb, MPc, MPd) which are adjacent to the centrally arranged PMOS transistor pair (MPa, MPb) on both sides each have an inverted, supply voltage (7c) connected to the gate contact and a substrate terminal connected to the positive supply voltage (VDD).

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