An image sensor and its fabrication method

Abstract

This invention discloses an image sensor and its fabrication method, belonging to the field of semiconductor technology. The image sensor includes at least: a substrate with a first isolation structure and a second isolation structure spaced apart within it; a photodiode, spaced apart from the first isolation structure and disposed within the substrate; a transmission gate, disposed on the substrate away from the photodiode and the first isolation structure; a floating diffusion region disposed within the substrate between the transmission gate and the second isolation structure, wherein the height of the side of the second isolation structure closest to the floating diffusion region is lower than the substrate surface, and a groove is formed therein; a source follower gate, spaced apart from the transmission gate and partially covering the second isolation structure; and a sidewall structure disposed around the transmission gate and the source follower gate, wherein the distance between the side edge of the transmission gate and the edge of the floating diffusion region is greater than the distance between the side edge of the transmission gate and the edge of the sidewall structure. The image sensor and its fabrication method provided by this invention can reduce white spot phenomena and dark current during imaging.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to an image sensor and its manufacturing method. Background Technology

[0002] CMOS image sensors (Complementary Metal Oxide Semiconductor Image Sensors, CIS) convert received photons into electrons through the photoelectric effect, and then these electrons are converted into electrical signals by circuitry, ultimately forming a digital image, thereby enabling image capture and processing. CMOS image sensors have advantages such as high integration, low power supply voltage, and low technical barriers, and are widely used in consumer electronics, autonomous driving, biometrics, and security fields.

[0003] In CMOS image sensors, the most common pixel units, such as the 4T structure, include a photodiode (PD), a floating diffusion region (FD), a transmission gate (TG), a reset transistor (RST), a source follower (SF), and a row select transistor (RS). The TG is positioned between the PD and FD. The overlap between the transmission gate and the floating diffusion region can lead to gate-induced drain leakage current (GIDL), causing abnormal changes in the FD potential. This results in white spots appearing in the image sensor during image capture. Current improvements to address the GIDL problem in the TG may severely affect the injection depth and morphology of the FD, causing plasma damage and increasing the overall sheet resistance of the FD region. Ultimately, this leads to insufficient PD reset and the formation of dark current. Summary of the Invention

[0004] The purpose of this invention is to provide an image sensor and its manufacturing method. The image sensor and its manufacturing method provided by this invention can reduce the distance from the floating diffusion region to the transmission tube, improve the GIDL problem, reduce the white spot phenomenon during imaging, and solve the problem of performance degradation caused by the increase of the overall sheet resistance of the floating diffusion region, and reduce dark current.

[0005] To address the aforementioned technical problems, the present invention provides an image sensor, comprising at least:

[0006] A substrate, wherein a first isolation structure and a second isolation structure are disposed at intervals within the substrate;

[0007] A photodiode is disposed within the substrate and spaced apart from the first isolation structure;

[0008] A transmission gate is disposed on the substrate at the end of the photodiode away from the first isolation structure;

[0009] A floating diffusion region is disposed within the substrate between the transmission gate and the second isolation structure, and the height of the side of the second isolation structure near the floating diffusion region is lower than the surface of the substrate, and a groove is provided therein;

[0010] A source follower gate is disposed on the side of the second isolation structure away from the transmission gate, and a portion of the source follower gate is disposed on the second isolation structure;

[0011] A sidewall structure is disposed around the transmission gate and the source follower gate, wherein the distance between the side of the transmission gate and the edge of the floating diffusion region is greater than the distance between the side of the transmission gate and the adjacent edge of the sidewall structure.

[0012] In one embodiment of the present invention, the image sensor includes a stepped lightly doped region disposed within the substrate between the transmission gate and the second isolation structure, the floating diffusion region being disposed within the lightly doped region, and the depth of the lightly doped region near the second isolation structure being greater than the depth of the lightly doped region near the transmission gate.

[0013] In one embodiment of the present invention, the sidewall structure includes a first sidewall and a second sidewall, wherein the first sidewall is disposed outside the transmission gate and the source follower gate, and the second sidewall is disposed outside the first sidewall.

[0014] In one embodiment of the present invention, the groove is disposed in the second isolation structure on the side close to the floating diffusion region, the width of the groove is the width of the second isolation structure minus the width of the second isolation structure covered by the source follower gate and the thickness of the first sidewall, and the depth of the groove is 90% to 95% of the groove width.

[0015] In one embodiment of the present invention, the source follower gate is disposed in the groove near the second sidewall of the groove, and the thickness of the source follower gate near the second sidewall of the groove is 50% to 75% of the thickness of the second sidewall of the transmission gate.

[0016] In one embodiment of the present invention, the second isolation structure includes a first substructure and a second substructure spaced apart. The first substructure is disposed close to the transmission gate. The sum of the widths of the first substructure and the second substructure is equal to the width of the first isolation structure. The width ratio of the second substructure to the first substructure is 2.5 to 3.5:1. The width of the active region between the first substructure and the second substructure is one-third to one-half of the width of the first substructure.

[0017] In one embodiment of the present invention, a first recess is provided on both sides of the first substructure, and a second recess is provided on both sides of the second substructure. The depth of the first recess is greater than the depth of the second recess. The edge of the source follower gate is aligned with the edge of the second recess adjacent to the first substructure. On the side of the source follower gate near the transmission gate, the sidewall structure of the source follower gate is located on the first substructure and exposes the first recess adjacent to the transmission gate.

[0018] In one embodiment of the present invention, the image sensor has a shared structure pixel layout, wherein one of the shared structure pixel layouts includes four photosensitive pixel units, two floating diffusion regions, two selection transistors, two reset transistors and one source follower transistor.

[0019] The photosensitive pixel unit includes a photodiode and a transmission tube. Two photosensitive pixel units share a floating diffusion region. The source follower tube is located at the center. The reset tube is located on the side of the floating diffusion region shared by two adjacent photosensitive pixel units away from the source follower tube. The select tube is spaced apart from the source follower tube.

[0020] The present invention also provides a method for manufacturing an image sensor, comprising at least the following steps:

[0021] A substrate is provided, wherein a first isolation structure and a second isolation structure are formed therein at intervals;

[0022] A photodiode is formed within the substrate, and the photodiode is spaced apart from the first isolation structure.

[0023] A transmission gate and a source follower gate are formed on the substrate. The transmission gate is disposed on the substrate at the end of the photodiode away from the first isolation structure. The source follower gate is disposed on the side of the second isolation structure away from the transmission gate, and a portion of the source follower gate is disposed on the second isolation structure.

[0024] A sidewall structure is formed around the transmission gate and the source follower gate.

[0025] A floating diffusion region is formed in the substrate between the transmission gate and the second isolation structure. The height of the side of the second isolation structure near the floating diffusion region is lower than the surface of the substrate, forming a groove. The distance between the side of the transmission gate and the edge of the floating diffusion region is greater than the distance between the side of the transmission gate and the edge of the adjacent sidewall structure.

[0026] In one embodiment of the present invention, the manufacturing method further includes:

[0027] After forming the transmission gate and the source follower gate, a first sidewall is formed around the transmission gate and the source follower gate;

[0028] Etch the source follower gate and the second isolation structure not covered by the first sidewall to form a groove;

[0029] A stepped lightly doped region is formed in the substrate between the transport gate and the second isolation structure by vertical ion implantation;

[0030] A second sidewall is formed outside the first sidewall, and the thickness of the second sidewall of the source-following gate on the second isolation structure is less than the thickness of the second sidewall of the transmission gate.

[0031] A full-coverage shielding layer is formed on the substrate;

[0032] Part of the masking layer at the plane is removed by vertical etching;

[0033] A floating diffusion region is formed within the lightly doped region.

[0034] In one embodiment of the present invention, the manufacturing method further includes:

[0035] A first isolation structure and a second isolation structure are formed in the substrate. The second isolation structure includes a first substructure and a second substructure that are spaced apart. The first substructure is disposed close to the transmission gate.

[0036] After forming the transmission gate and the source follower gate, a first recess is formed on both sides of the first substructure and a second recess is formed on both sides of the second substructure in the first substructure; the edge of the source follower gate is aligned with the edge of the second recess adjacent to the first substructure.

[0037] A first sidewall is formed around the transmission gate and the source follower gate;

[0038] A stepped lightly doped region is formed in the substrate between the transport gate and the second isolation structure by vertical ion implantation;

[0039] A second sidewall is formed outside the first sidewall, the sidewall structure of the source follower gate is located on the first substructure, and exposes the first recess adjacent to the transmission gate;

[0040] A full-coverage shielding layer is formed on the substrate;

[0041] Part of the masking layer at the plane is removed by vertical etching;

[0042] A floating diffusion region is formed within the lightly doped region.

[0043] In one embodiment of the present invention, the shielding layer includes a first sub-layer, a second sub-layer, and a third sub-layer, wherein the first sub-layer and the third sub-layer are silicon oxide layers, the second sub-layer is a silicon nitride layer, and a portion of the third sub-layer and the second sub-layer at the plane is removed by vertical etching; on the sidewall structure of the source follower gate near the transmission gate, the thickness of the shielding layer is 70% to 80% of the thickness of the shielding layer at the plane.

[0044] In summary, this invention provides an image sensor and its fabrication method. By improving the structure and fabrication method of the image sensor, the spacing between the side of the transmission gate and the floating diffusion region can be controlled and adjusted, thereby reducing the parasitic capacitance between the transmission gate and the floating diffusion region. This improves the GIDL effect, reduces white spot phenomena during imaging, and enhances the performance of the image sensor. It also reduces the thickness of the sidewall structure and the shielding layer near the transmission gate of the source follower gate, forming a stepped lightly doped region. This improves the electric field distribution at the interface between the lightly doped region and the second isolation structure, improving dark current without affecting the injection morphology of the floating diffusion region. It solves the problem of increased overall region resistance of the floating diffusion region caused by the distance between the injection area and the second isolation structure, avoiding dark current caused by insufficient photodiode reset. Finally, it reduces the parasitic capacitance between the floating diffusion region and the source follower gate, optimizes noise characteristics, and effectively improves conversion gain.

[0045] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0046] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1This is a planar schematic diagram of a shared structure pixel layout of an image sensor in one embodiment.

[0048] Figure 2 As in one embodiment, along Figure 1 A cross-sectional view of the gate formed in the A-A' direction.

[0049] Figure 3 As in one embodiment, along Figure 1 The A-A' direction forms the sectional view of the first side wall.

[0050] Figure 4 As in one embodiment, along Figure 1 A cross-sectional view showing a groove formed in the second isolation structure along the A-A' direction.

[0051] Figure 5 As in one embodiment, along Figure 1 A cross-sectional view of the lightly doped region formed along the A-A' direction.

[0052] Figure 6 As in one embodiment, along Figure 1 The A-A' direction forms a cross-sectional view of the sidewall medium.

[0053] Figure 7 As in one embodiment, along Figure 1 The A-A' direction forms a sectional view of the side wall structure.

[0054] Figure 8 As in one embodiment, along Figure 1 A plan view showing the shielding layer formed along the A-A' direction.

[0055] Figure 9 As in one embodiment, along Figure 1 A cross-sectional view of the masking layer after vertical etching along the A-A' direction.

[0056] Figure 10 As in one embodiment, along Figure 1 A cross-sectional view of the floating diffusion zone formed along the A-A' direction.

[0057] Figure 11 As in one embodiment, along Figure 1 A cross-sectional view of the A-A' direction after removing the masking layer.

[0058] Figure 12 In another embodiment, along Figure 1 A cross-sectional view of the isolated structure formed along the A-A' direction.

[0059] Figure 13 In another embodiment, along Figure 1 A cross-sectional view of the gate formed in the A-A' direction.

[0060] Figure 14In another embodiment, along Figure 1 The A-A' direction forms the sectional view of the first side wall.

[0061] Figure 15 In another embodiment, along Figure 1 A planar diagram showing the formation of lightly doped regions along the A-A' direction.

[0062] Figure 16 In another embodiment, along Figure 1 The A-A' direction forms a sectional view of the side wall structure.

[0063] Figure 17 In another embodiment, along Figure 1 A cross-sectional view of the shielding layer formed along the A-A' direction.

[0064] Figure 18 In another embodiment, along Figure 1 A cross-sectional view showing the floating diffusion zone formed along the A-A' direction and the removal of the masking layer.

[0065] Label Explanation:

[0066] 10. Substrate; 11. Isolation structure; 111. First isolation structure; 112. Second isolation structure; 1121. First substructure; 1122. Second substructure; 12. Active region; 13. Photodiode; 140. Transmission transistor; 150. Source follower transistor; 16. Floating diffusion region; 170. Row select transistor; 180. Reset transistor; 102. Pinning layer; 14. Transmission gate; 15. Source follower gate; 103. Gate dielectric layer; 104. First sidewall; 105. Patterned photoresist layer; 106. Groove; 107. Lightly doped region; 108. Sidewall dielectric; 1081. Second sidewall; 109. Photoresist layer; 110. Sidewall structure; 120. Masking layer; 121. First sublayer; 122. Second sublayer; 123. Third sublayer; 131. First recess; 132. Second recess. Detailed Implementation

[0067] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0068] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0069] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0070] Please see Figure 1 , Figure 11 and Figure 18 As shown, this invention provides an image sensor with a shared pixel layout. In this embodiment, a shared pixel layout is used as an example. A photodiode 13 and an adjacent transmission tube 140 constitute a photosensitive pixel unit. Four photosensitive pixel units form a shared structure, sharing a source follower transistor 150, a floating diffusion region 16, a row select transistor 170, and a reset transistor 180. All four photosensitive pixel units share the same source follower transistor 150, and two photosensitive pixel units share a floating diffusion region 16. The source follower transistor 150 is positioned centrally, and its proximity to the floating diffusion region 16 results in a small parasitic capacitance, effectively improving conversion gain. Two photosensitive pixel units share a reset transistor 180, which is located on the side of the floating diffusion region 16 shared by two adjacent photosensitive pixel units away from the source follower transistor 150, facilitating connection with the floating diffusion region. Two photosensitive pixel units share a row select transistor 170. The row select transistor 170 and the source follower transistor 150 are spaced apart on both sides of the source follower transistor 150 and are staggered with the photodiode 13. This has a smaller impact on the incident light blocking of the photodiode and can effectively improve the quantum efficiency of the pixel unit. Figure 1 The layout diagram shown is a pixel unit layout diagram in one embodiment of this application. This application also provides a method for manufacturing an image sensor; in this embodiment, for example, using... Figure 1Taking a cross-sectional view along the A-A' direction as an example, the fabrication process of the image sensor is explained. By improving the fabrication process, the distance from the floating diffusion region to the transmission tube can be optimized, the GIDL problem can be improved, the white spot phenomenon during imaging can be reduced, and the problem of performance degradation caused by the increase in the overall sheet resistance of the floating diffusion region can be solved, while reducing dark current.

[0071] Please see Figures 1 to 2 As shown, in one embodiment of the present invention, Figure 2 for Figure 1 A cross-sectional view showing the photodiode 13 and gate structure along the A-A' direction. The substrate 10 can be any suitable semiconductor material, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon-germanium (GeSi), sapphire, or silicon wafers, and may also include stacked structures composed of these semiconductors. Alternatively, it can be silicon-on-insulator, silicon-on-insulator stacked, silicon-germanium-on-insulator stacked, silicon-germanium-on-insulator, or germanium-on-insulator, depending on the requirements of the image sensor fabrication. In this embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate, or a P-type substrate. Multiple isolation structures 11 are formed within the substrate 10, dividing it into multiple active regions 12 for forming the photodiode 13, floating diffusion region 16, and multiple transistors in the image sensor.

[0072] Please see Figures 1 to 2 As shown, in one embodiment of the present invention, the isolation structure 11 is, for example, a shallow trench isolation (STI) structure. The isolation structure 11 includes, for example, a first isolation structure 111 and a second isolation structure 112, with equal depths. The first isolation structure 111 is disposed around the photodiode 13 to isolate adjacent photodiodes 13. The second isolation structure 112 is disposed between the floating diffusion region 16 and the source follower transistor 150 for isolation. The photodiode 13 is, for example, a doped region extending from the surface of the substrate 10 into the substrate 10, with one end of the photodiode 13 spaced apart from the first isolation structure 111. The impurity ions in the photodiode 13 are, for example, N-type impurities such as phosphorus or arsenic, and the depth of the photodiode 13 within the substrate 10 is, for example, less than that of the first isolation structure 111. A pinning layer 102 is formed on the surface of the photodiode 13. The doping ions of the pinning layer 102 are, for example, p-type impurities such as boron, and the doping concentration of the pinning layer 102 is, for example, greater than the doping concentration of the photodiode 13. By forming the pinning layer, the depletion region of the photodiode 13 is prevented from extending to the surface of the substrate 10, and the dark current caused by dangling bonds on the surface of the substrate 10 is reduced, thereby improving the electrical performance of the CMOS image sensor.

[0073] Please see Figure 2 As shown, in one embodiment of the present invention, a transmission gate 14 is disposed on the substrate 10 at the end of the photodiode 13 away from the first isolation structure 111, for forming a transmission tube, and the transmission gate 14 and the photodiode 13 partially overlap. A source follower gate 15 is disposed on the side of the second isolation structure 112 away from the transmission gate 14, for forming a source follower tube, and the source follower gate 15 covers a portion of the second isolation structure 112. In a specific embodiment of this application, the source follower gate 15 covers, for example, one-third to one-half of the second isolation structure 112. A gate dielectric layer 103 is disposed between the transmission gate 14 and the source follower gate 15 and the substrate 10. This application does not limit the material and thickness of the gate dielectric layer 103, the transmission gate 14, and the source follower gate 15, and selects them according to the manufacturing requirements. The gate dielectric layer 103 is, for example, silicon oxide, a high dielectric constant material, etc., and the transmission gate 14 and the source follower gate 15 are, for example, polysilicon or metal materials. In this embodiment, the gate dielectric layer 103 is, for example, silicon oxide grown by in-situ steam generation (ISSG), and the thickness of the gate dielectric layer 103 is, for example, 5nm to 10nm. The transfer gate 14 and the source follower gate 15 are, for example, polysilicon, and the thickness is, for example, 90nm to 150nm. The source follower gate 15 is, for example, N-type doped polysilicon, and the transfer gate 14 is, for example, N-type doped polysilicon. At the same time, other gates in the image sensor are formed.

[0074] Please see Figures 2 to 3 As shown, in one embodiment of the present invention, after the gate is formed, a first sidewall 104 is formed around the outer periphery of the gate. The first sidewall 104 is, for example, a stack of silicon oxide and silicon nitride, with the silicon oxide formed close to the gate sidewall. Specifically, silicon oxide and silicon nitride layers are formed on the top and sidewalls of the gate, the substrate 10, the top of the first isolation structure 111, and the second isolation structure 112 by chemical vapor deposition (CVD). Then, by dry etching, the silicon oxide and silicon nitride layers on both sides of the gate are retained, and the silicon oxide and silicon nitride layers in the remaining areas are removed to form the first sidewall 104. In this embodiment, the thickness of the first sidewall 104 is, for example, 5 nm to 10 nm, and the thickness ratio of silicon oxide to silicon nitride is, for example, 1:6 to 1:8.

[0075] Please see Figures 3 to 4As shown, in one embodiment of the present invention, after forming the first sidewall 104, a photoresist layer is formed on the substrate, and a patterned photoresist layer 105 is formed through processes such as exposure and development. The patterned photoresist layer 105 exposes a second isolation structure 112 not covered by the source follower gate 15. Using the patterned photoresist layer 105 as a mask, a groove 106 is formed on the exposed second isolation structure 112 by, for example, dry etching or wet etching. That is, the height of the side of the second isolation structure 112 closest to the subsequently formed floating diffusion region is lower than the surface of the substrate 10. The width of the groove 106 is, for example, the width of the second isolation structure 112 minus the width of the second isolation structure 112 covered by the source follower gate 15 and the thickness of the first sidewall 104, and the depth of the groove 106 is, for example, 90% to 95% of the groove width. In this embodiment, wet etching is used, for example, at room temperature for 10 to 60 seconds. The wet etching solution is, for example, dilute hydrofluoric acid (DHF), in which the volume ratio of hydrofluoric acid to water is, for example, 1:10 to 500, and the concentration of hydrofluoric acid used is, for example, 40 wt% to 55 wt%. By controlling the concentration of hydrofluoric acid and the etching time, the etching morphology and depth of the groove 106 are controlled, ensuring that the second isolation structure 112 below the first sidewall 104 is not etched. Furthermore, due to the presence of the first sidewall 104, depressions in the channel region are avoided, and there is no significant impact on the device.

[0076] Please see Figures 4 to 5 As shown, in one embodiment of the present invention, after the groove 106 is formed, the patterned photoresist layer 105 is removed, for example, by wet etching, and a lightly doped region 107 is formed in the substrate 10 between the transmission gate 14 and the second isolation structure 112. The lightly doped region 107 is formed, for example, by photolithography and ion implantation. The photolithography process includes forming a photoresist layer on the substrate 10, forming a patterned photolithography layer (not shown) by exposure, development, etc., exposing the substrate 10 between the transmission gate 14 and the second isolation structure 112 to form an ion implantation region. During ion implantation, for example, N-type ions such as phosphorus or arsenic are implanted, and the ion implantation energy is, for example, 18 keV~25 keV, and the ion implantation dose is, for example, 1×10⁻⁶. 13 atoms / cm 2 ~5×10 13 atoms / cm 2 The implantation direction is, for example, perpendicular to the surface of the substrate 10. After ion implantation, the patterned photolithography layer is removed. Due to the presence of the groove 106, the lightly doped region 107 formed is stepped, that is, the depth of the lightly doped region 107 near the groove 106 is greater than the depth of the lightly doped region 107 near the transmission gate 14. By forming the stepped lightly doped region 107, the electric field distribution at the interface between the active region and the second isolation structure 112 can be improved, and the dark current can be improved.

[0077] Please see Figures 5 to 6 As shown, in one embodiment of the present invention, after forming the lightly doped region 107, a sidewall dielectric 108 is deposited on the substrate 10. The sidewall dielectric 108 covers all structures on the substrate 10, namely, the first isolation structure 111, the second isolation structure 112, the pinning layer 102, the top and sidewalls of the transfer gate 14, the lightly doped region 107, the bottom and sidewalls of the recess 106, and the top and sidewalls of the source follower gate 15. The sidewall dielectric 108 is, for example, a stack of silicon oxide and silicon nitride. The sidewall dielectric 108 is deposited, for example, by a process such as chemical vapor deposition. The thickness of the sidewall dielectric 108 at the plane of the substrate 10 or the top of the gate is, for example, 40 nm to 60 nm. The thickness ratio of silicon oxide to silicon nitride is, for example, 1:2 to 1:5. During the deposition process, due to the influence of the deposition process, the thickness of the sidewall dielectric 108 on the first sidewall 104 is less than its thickness at the plane. In this embodiment, due to the presence of the groove 106, the sidewall height of the source follower gate 15 on the second isolation structure 112 is increased. Therefore, the thickness of the sidewall medium 108 (i.e., at point C) on the groove 106 is, for example, 50% to 75% of the thickness of the sidewall medium 108 at the plane. The thickness of the sidewall medium 108 on the sidewall of the transmission gate 14 (i.e., at point B) and the sidewall of the source follower gate 15 away from the second isolation structure 112 is, for example, 85% to 90% of the thickness of the sidewall medium 108 at the plane. Therefore, the thickness of the sidewall medium 108 on the groove 106 can be reduced.

[0078] Please see Figures 6 to 7As shown, in one embodiment of the present invention, after forming the sidewall dielectric 108, for example by dry etching, the sidewall dielectric 108 on both sides of the gate is retained, and the sidewall dielectric 108 in the remaining area is removed to form a second sidewall 1081 outside the first sidewall 104. The second sidewall 1081 is located on the side of the first sidewall 104 away from the gate, and the first sidewall 104 and the second sidewall 1081 form a sidewall structure. Since the sidewall dielectric 108 of the source follower gate 15 located on the recess 106 is relatively thin, the thickness of the sidewall structure 110 on the recess can be reduced. The thickness of the second sidewall 1081 of the source follower gate 15 near the recess 106 is, for example, 50% to 75% of the thickness of the second sidewall 1081 of the transfer gate 14. This increases the distance between the sidewall structure 110 and the lightly doped region. Since the second isolation structure 112 is located below the sidewall structure 110, it will not affect the channel region of the source follower transistor. The outer edge of the sidewall structure 110 is far enough away from the connection structure of the subsequently formed floating diffusion region 16. After the subsequent connection structure process is completed, there is sufficient isolation between the two, so the change in parasitic capacitance between them can be ignored. This reduces the parasitic capacitance between the floating diffusion region 16 and the source follower gate 15, optimizes noise characteristics, and effectively improves the conversion gain.

[0079] Please see Figures 7 to 8As shown, in one embodiment of the present invention, after forming the sidewall structure 110, a shielding layer 120 is formed on the substrate 10, and the shielding layer 120 covers all structures on the substrate 10, namely, the first isolation structure 111, the second isolation structure 112, the pinning layer 102, the transfer gate 14, the lightly doped region 107, the bottom and sidewalls of the recess 106, the source follower gate 15, and the sidewall structure 110. The shielding layer 120 includes, for example, a first sublayer 121, a second sublayer 122, and a third sublayer 123 formed sequentially. The first sublayer 121 is, for example, a silicon oxide layer with a thickness of, for example, 4nm to 8nm in the plane; the second sublayer 122 is, for example, a silicon nitride layer with a thickness of, for example, 5nm to 10nm in the plane; and the third sublayer 123 is, for example, a silicon oxide layer with a thickness of, for example, 15nm to 25nm in the plane. The shielding layer 120 is deposited, for example, by a process such as chemical vapor deposition. Due to the presence of the groove 106, the thickness of the shielding layer 120 on the sidewall structure 110 of the groove 106 is thinner than that on the plane. Furthermore, the shielding layer 120 at the groove 106 inherits the morphology of the groove 106, and the shielding layer 120 has an opening of a certain width at the groove 106, thereby avoiding interference with the subsequent injection of the floating diffusion region 16. In this embodiment, the thickness of the shielding layer 120 on the sidewall structure 110 within the groove 106 is, for example, 50% to 75% of the thickness of the shielding layer 120 on the plane. The thickness of the shielding layer 120 on the sidewall of the transmission gate 14 and the sidewall of the source following gate 15 away from the second isolation structure 112 is approximately 85% to 90% of the thickness of the shielding layer 120 on the plane.

[0080] Please see Figures 8 to 9 As shown, in one embodiment of the present invention, after forming the masking layer 120, the masking layer 120 is vertically etched by dry etching to remove a portion of the masking layer 120 at the plane, such as removing the third sub-layer 123 and the second sub-layer 122 at the plane position. When etching the third sub-layer 123, for example, carbon tetrafluoride and trifluoromethane are used as etching gases, and the second sub-layer 122 is used as an etching stop layer. When etching the second sub-layer 122, for example, sulfur hexafluoride and oxygen are used as etching gases, and the first sub-layer 121 is used as an etching stop layer, which avoids damage to the substrate 10 by the etching gases. After etching, the first sub-layer 121 remains on the substrate 10 and the gate of the masking layer 120, and the first sub-layer 121, the second sub-layer 122, and the third sub-layer 123 remain on the sidewall structure 110. By forming three sub-layers and combining vertical etching, photoresist is not required as a mask when removing the third and second sub-layers on the substrate, which reduces production costs.

[0081] Please see Figures 9 to 10As shown, in one embodiment of the present invention, after the third sub-layer 123 and the second sub-layer 122 at the etched plane, a floating diffusion region 16 is formed in the substrate 10 between the transmission gate 14 and the second isolation structure 112. The floating diffusion region 16 is formed, for example, by photolithography and ion implantation. The photolithography process includes forming a photoresist layer on the substrate 10 and forming a photoresist layer 109 by exposure, development, and other processes. The photoresist layer 109 exposes the first sub-layer 121 between the transmission gate 14 and the second isolation structure 112 to form an ion implantation region. During ion implantation, the photoresist layer 109 is used as a mask, and the first sub-layer 121 is used as an ion implantation buffer layer. For example, N-type ions such as phosphorus or arsenic are implanted, and the ion implantation energy is, for example, 18 keV~20 keV, and the ion implantation dose is, for example, 1×10⁻⁶. 15 atoms / cm 2 ~5×10 15 atoms / cm 2 The implantation direction is, for example, perpendicular to the surface of the substrate 10. After ion implantation, the photoresist layer 109 is removed.

[0082] Please see Figures 10 to 11 As shown, in one embodiment of the present invention, after the floating diffusion region 16 is formed, the masking layer 120 is removed. In this embodiment, the masking layer 120 is removed, for example, by wet etching. The wet etching solution for removing the first sub-layer 121 and the third sub-layer 123 is, for example, hydrofluoric acid or buffered oxide etch (BOE), and the wet etching solution for removing the second sub-layer 122 is, for example, a hot phosphoric acid aqueous solution. The temperature of the hot phosphoric acid is, for example, 160°C to 180°C, and the concentration of the hot phosphoric acid is, for example, 85wt% to 90wt%. In this application, since a multi-layer masking layer is formed and vertical etching is performed, the spacing X between the side of the transmission gate 14 and the edge of the floating diffusion region 16 can be controlled by controlling the thickness of the masking layer. By adjusting the spacing X, the parasitic capacitance between the transmission gate 14 and the floating diffusion region 16 can be reduced, thereby improving the GIDL effect and enhancing the performance of the image sensor. In this embodiment, the spacing X is greater than the distance between the side edge of the transmission gate 14 and the edge of the adjacent sidewall structure 110, and the difference between the spacing X and the distance is the thickness of the shielding layer 120 on the sidewall structure 110 of the transmission gate 14. Simultaneously, since a groove is formed at the second isolation structure 112 between the floating diffusion region 16 and the source follower gate 15, the thickness of the sidewall structure and the shielding layer at the groove can be reduced, forming a stepped lightly doped region. This improves the electric field distribution at the interface between the lightly doped region and the second isolation structure, thus improving dark current. Simultaneously, it does not affect the injection morphology of the floating diffusion region, solving the problem of increased overall region resistance of the floating diffusion region due to the distance between the injection region and the second isolation structure, and avoiding dark current caused by insufficient photodiode reset.

[0083] Please see Figure 11 As shown, in one embodiment of the present invention, after the floating diffusion region 16 is formed, the dielectric layer, metal wiring layer, filtering and microlens processes are performed, which will not be described in detail here.

[0084] Please see Figure 1 and Figure 12 As shown, in another embodiment of the present invention, the second isolation structure 112 includes a first substructure 1121 and a second substructure 1122. That is, when forming the isolation structure, two shallow trench isolation structures are formed between the floating diffusion region 16 and the source follower transistor 150. The shallow trench isolation structure near the floating diffusion region 16 is defined as the first substructure 1121, and the shallow trench isolation structure near the source follower transistor 150 is defined as the second substructure 1122. In this embodiment, the depths of the first isolation structure 111, the first substructure 1121, and the second substructure 1122 are equal, the sum of the widths of the first substructure 1121 and the second substructure 1122 is equal to the width of the first isolation structure 111, the width ratio of the second substructure 1122 to the first substructure 1121 is, for example, 2.5~3.5:1, and the width of the active region between the first substructure 1121 and the second substructure 1122 is, for example, one-third to one-half of the width of the first substructure 1121. The isolation structure can be formed using any method for forming shallow trench isolation structures of different widths, and this application does not impose any specific restrictions.

[0085] Please see Figure 12 and Figure 13 As shown, in another embodiment of the present invention, after the isolation structure is formed, the multiple cleaning processes during the formation of the photodiode 13, pinning layer 102, gate, etc., result in a lower height of the isolation structure and some loss of the sidewalls of the isolation structure near the active region, forming a common divot structure. The smaller the linewidth of the isolation structure, the more the isolation structure is consumed during divot formation, resulting in a larger divot size. In this embodiment, a first divot 131 is formed on both sides of the first substructure 1121, and a second divot 132 is formed on both sides of the second substructure 1122. The size of the first divot 131 is larger than the size of the second divot 132. In this embodiment, the fabrication process and structure of the photodiode 13, pinning layer 102, transmission gate 14, source follower gate 15, and gate dielectric layer 103 are the same as in the previous embodiment and will not be elaborated further. The source follower gate 15 is located on the second substructure 1122, and the edge of the source follower gate 15 is aligned with the edge of the second divot 132 adjacent to the first substructure 1121.

[0086] Please see Figures 13 to 15As shown, in another embodiment of the present invention, after the gate is formed, a first sidewall 104 is formed around the gate. The formation process, material, and thickness of the first sidewall 104 are the same as in the previous embodiment, and will not be described in detail here. Specifically, the first sidewall 104 is located within the second recess 132 on the side of the source following gate 15 near the first substructure 1121. After the first sidewall 104 is formed, a lightly doped region 107 is formed. The formation process, conditions, and type of the lightly doped region 107 are the same as in the previous embodiment, and will not be described in detail here. In this embodiment, the depth of the lightly doped region 107 near the first substructure 1121 is greater than the depth of the lightly doped region 107 near the transmission gate 14, and the overall shape is stepped, which can improve the electric field distribution at the interface and reduce dark current.

[0087] Please see Figure 15 and Figure 16 As shown, in another embodiment of the present invention, the preparation method for forming the sidewall structure 110 is the same as that in the previous embodiment. However, due to the presence of the first recess 131 and the second recess 132, the thickness of the sidewall structure 110 is less than the thickness of the sidewall structure 110 at other locations on the side of the source follower gate 15 close to the transmission gate 14. The sidewall structure 110 here is located, for example, on the first substructure 1121 and exposes the first recess 131 adjacent to the transmission gate 14.

[0088] Please see Figure 16 and Figure 17 As shown, in another embodiment of the present invention, after forming the sidewall structure, a shielding layer 120 is formed. The structure, thickness, and formation method of the shielding layer 120 are the same as in the previous embodiment, and will not be described in detail here. In this embodiment, when forming the shielding layer 120, due to the presence of the first recess 131, on the side of the source following gate 15 close to the transmission gate 14, the thickness of the shielding layer 120 on the sidewall structure 110 is, for example, 50% to 75% of the thickness at the plane. The shielding layer 120 at this location is located within the first recess 131, which can avoid affecting the injection area and morphology of the floating diffusion region 16 when the floating diffusion region 16 is subsequently formed.

[0089] Please see Figure 17 and Figure 18As shown, in another embodiment of the present invention, after forming the masking layer 120, the masking layer 120 is vertically etched to remove the third sub-layer 123 and the second sub-layer at the plane, and a floating diffusion region 16 is formed in the substrate 10 between the transmission gate 14 and the second isolation structure 112. The formation process and conditions of the floating diffusion region 16 are the same as in the previous embodiment, and will not be described in detail here. After forming the floating diffusion region 16, the masking layer 120 is removed. In this embodiment, during the formation of the masking layer 120 and the etching process, the spacing X between the side of the transmission gate 14 and the floating diffusion region 16 is controlled, and the spacing X is adjusted to reduce the parasitic capacitance between the transmission gate 14 and the floating diffusion region 16, which can improve the GIDL effect. In this embodiment, the spacing X is greater than the distance between the side of the transmission gate 14 and the edge of the adjacent sidewall structure 110, and the difference between the two is the width of the masking layer 120 on the sidewall structure 110 of the transmission gate 14. By setting the first substructure 1121 and the second substructure 1122 and controlling their width and distance, during the fabrication process, recesses are formed on both sides of the first substructure 1121 and the second substructure 1122. The bottom of the recesses is located inside the substrate 10. This can increase the vertical height of the source follower gate 15 on the side close to the transmission gate 14, and can control the shielding layer 120 on the side of the source follower gate 15 close to the transmission gate 14 to not cover the area where the floating diffusion region needs to be formed. This can ensure the injection area and injection morphology of the floating diffusion region 16 and reduce dark current.

[0090] Please see Figure 18 As shown, in one embodiment of the present invention, after the floating diffusion region 16 is formed, the process of forming a dielectric layer, a metal wiring layer, filtering and microlens is carried out, which will not be described in detail here.

[0091] In summary, this invention provides an image sensor and its fabrication method. By improving the structure and fabrication method of the image sensor, the spacing between the side of the transmission gate and the floating diffusion region can be controlled and adjusted, thereby reducing the parasitic capacitance between the transmission gate and the floating diffusion region. This improves the GIDL effect, reduces white spot phenomena during imaging, and enhances the performance of the image sensor. It also reduces the thickness of the sidewall structure and the shielding layer near the transmission gate of the source follower gate, forming a stepped lightly doped region. This improves the electric field distribution at the interface between the lightly doped region and the second isolation structure, improving dark current without affecting the injection morphology of the floating diffusion region. It solves the problem of increased overall region resistance of the floating diffusion region caused by the distance between the injection area and the second isolation structure, avoiding dark current caused by insufficient photodiode reset. Finally, it reduces the parasitic capacitance between the floating diffusion region and the source follower gate, optimizes noise characteristics, and effectively improves conversion gain.

[0092] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An image sensor, characterized in that, At least including: A substrate, wherein a first isolation structure and a second isolation structure are disposed at intervals within the substrate; A photodiode is disposed within the substrate and spaced apart from the first isolation structure; A transmission gate is disposed on the substrate at the end of the photodiode away from the first isolation structure; A floating diffusion region is disposed within the substrate between the transmission gate and the second isolation structure, and the height of the side of the second isolation structure near the floating diffusion region is lower than the surface of the substrate, and a groove is provided therein; A source follower gate is disposed on the side of the second isolation structure away from the transmission gate, and a portion of the source follower gate is disposed on the second isolation structure; A sidewall structure is disposed around the transmission gate and the source follower gate, wherein the distance between the side of the transmission gate and the edge of the floating diffusion region is greater than the distance between the side of the transmission gate and the adjacent edge of the sidewall structure. The image sensor has a shared structure pixel layout, and one of the shared structure pixel layouts includes four photosensitive pixel units, two floating diffusion regions, two selection transistors, two reset transistors and one source follower transistor. The photosensitive pixel unit includes a photodiode and a transmission tube. Two photosensitive pixel units share a floating diffusion region. The source follower tube is located at the center. The reset tube is located on the side of the floating diffusion region shared by two adjacent photosensitive pixel units away from the source follower tube. The select tube is spaced apart from the source follower tube.

2. The image sensor according to claim 1, characterized in that, The image sensor includes a stepped lightly doped region disposed within the substrate between the transmission gate and the second isolation structure. The floating diffusion region is disposed within the lightly doped region, and the depth of the lightly doped region near the second isolation structure is greater than the depth of the lightly doped region near the transmission gate.

3. The image sensor according to claim 1, characterized in that, The sidewall structure includes a first sidewall and a second sidewall, wherein the first sidewall is disposed outside the transmission gate and the source follower gate, and the second sidewall is disposed outside the first sidewall.

4. The image sensor according to claim 3, characterized in that, The groove is disposed in the second isolation structure on the side close to the floating diffusion region. The width of the groove is the width of the second isolation structure minus the width of the second isolation structure covered by the source follower gate and the thickness of the first sidewall. The depth of the groove is 90% to 95% of the groove width.

5. The image sensor according to claim 4, characterized in that, The source follower gate is disposed near the second sidewall of the groove, and the thickness of the source follower gate near the second sidewall of the groove is 50% to 75% of the thickness of the second sidewall of the transmission gate.

6. The image sensor according to claim 1, characterized in that, The second isolation structure includes a first substructure and a second substructure spaced apart. The first substructure is disposed close to the transmission gate. The sum of the widths of the first substructure and the second substructure is equal to the width of the first isolation structure. The width ratio of the second substructure to the first substructure is 2.5 to 3.5:

1. The width of the active region between the first substructure and the second substructure is one-third to one-half the width of the first substructure.

7. The image sensor according to claim 6, characterized in that, A first recess is provided on both sides of the first substructure, and a second recess is provided on both sides of the second substructure. The depth of the first recess is greater than the depth of the second recess. The edge of the source follower gate is aligned with the edge of the second recess adjacent to the first substructure. On the side of the source follower gate near the transmission gate, the sidewall structure of the source follower gate is located on the first substructure and exposes the first recess adjacent to the transmission gate.

8. A method for manufacturing an image sensor, characterized in that, At least the following steps are included: A substrate is provided, wherein a first isolation structure and a second isolation structure are formed therein at intervals; A photodiode is formed within the substrate, and the photodiode is spaced apart from the first isolation structure. A transmission gate and a source follower gate are formed on the substrate. The transmission gate is disposed on the substrate at the end of the photodiode away from the first isolation structure. The source follower gate is disposed on the side of the second isolation structure away from the transmission gate, and a portion of the source follower gate is disposed on the second isolation structure. A sidewall structure is formed around the transmission gate and the source follower gate. A floating diffusion region is formed in the substrate between the transmission gate and the second isolation structure. The height of the side of the second isolation structure near the floating diffusion region is lower than the surface of the substrate, forming a groove. The distance between the side of the transmission gate and the edge of the floating diffusion region is greater than the distance between the side of the transmission gate and the edge of the adjacent sidewall structure. The image sensor formed therein has a shared structure pixel layout, and one of the shared structure pixel layouts includes four photosensitive pixel units, two floating diffusion regions, two selection transistors, two reset transistors and one source follower transistor; The photosensitive pixel unit includes a photodiode and a transmission tube. Two photosensitive pixel units share a floating diffusion region. The source follower tube is located at the center. The reset tube is located on the side of the floating diffusion region shared by two adjacent photosensitive pixel units away from the source follower tube. The select tube is spaced apart from the source follower tube.

9. The method for manufacturing an image sensor according to claim 8, characterized in that, The manufacturing method further includes: After forming the transmission gate and the source follower gate, a first sidewall is formed around the transmission gate and the source follower gate; Etch the source follower gate and the second isolation structure not covered by the first sidewall to form a groove; A stepped lightly doped region is formed in the substrate between the transport gate and the second isolation structure by vertical ion implantation; A second sidewall is formed outside the first sidewall, and the thickness of the second sidewall of the source-following gate on the second isolation structure is less than the thickness of the second sidewall of the transmission gate. A full-coverage shielding layer is formed on the substrate; Part of the masking layer at the plane is removed by vertical etching; A floating diffusion region is formed within the lightly doped region.

10. The method for manufacturing an image sensor according to claim 8, characterized in that, The manufacturing method further includes: A first isolation structure and a second isolation structure are formed in the substrate. The second isolation structure includes a first substructure and a second substructure that are spaced apart. The first substructure is disposed close to the transmission gate. After forming the transmission gate and the source follower gate, a first recess is formed on both sides of the first substructure and a second recess is formed on both sides of the second substructure in the first substructure; the edge of the source follower gate is aligned with the edge of the second recess adjacent to the first substructure. A first sidewall is formed around the transmission gate and the source follower gate; A stepped lightly doped region is formed in the substrate between the transport gate and the second isolation structure by vertical ion implantation; A second sidewall is formed outside the first sidewall, the sidewall structure of the source follower gate is located on the first substructure, and exposes the first recess adjacent to the transmission gate; A full-coverage shielding layer is formed on the substrate; Part of the masking layer at the plane is removed by vertical etching; A floating diffusion region is formed within the lightly doped region.

11. The method for manufacturing an image sensor according to claim 9 or 10, characterized in that, The shielding layer includes a first sub-layer, a second sub-layer, and a third sub-layer. The first sub-layer and the third sub-layer are silicon oxide layers, and the second sub-layer is a silicon nitride layer. A portion of the third sub-layer and the second sub-layer at the plane is removed by vertical etching. On the sidewall structure of the source follower gate near the transmission gate, the thickness of the shielding layer is 70% to 80% of the thickness of the shielding layer at the plane.

Images