ELO-based optoelectronic device and method of manufacturing an optoelectronic device

Abstract

The invention concerns an optoelectronic device manufactured on a growth template based on an epitaxial lateral overgrowth process. Modification of existing ELO processes allow processing of optoelectronic devices exhibiting high efficiency and characterized by low defect density.

Description

[0001]2023PF01432 - 1 -ELO-BASED OPTOELECTRONIC DEVICE AND METHOD OF MANUFACTURING AN OPTOELECTRONIC DEVICE The present application claims priority from German application DE 105 2024 107 722.0 dated March 18, 2024, the disclosure of which isincorporated in its entirety herein by reference. The present invention concerns an optoelectronic device manufactured on a substrate grown by epitaxial lateral overgrowth as well as a method for processing such an optoelectronic device. 0 BACKGROUND Manufacture of optoelectronic devices has commonly been accomplished through the epitaxial growth of semiconductor material on a selected5 growth substrate. Commonly employed semiconductor materials are basedon III / V compounds, usually in the form of nitrides, phosphides and arsenides. Growth of semiconductor material on a growth substrate comprising identical material, also known as homoepitaxy, results in minimization of defects in the deposited layers due to the matching0 crystal parameters throughout the structure.Limitations related to cost and complexity of producing bulk substrates comprising III-V compounds, in particular, nitrides, have however contributed to the use of foreign substrates, in particular, sapphire5 and silicon, for commercial heteroepitaxial growth of semiconductormaterials. Thelattice mismatch between foreign substrates and III / V semiconductor layers contributes to mismatch strain, which results in crystal defects, such as crystal dislocations. Crystal dislocations may take the form of misfit dislocations along the heterointerface, or0 threading dislocations, which extend through epitaxial layers to thesurface. additionally, the difference of thermal expansion coefficients (TEC) between sapphire and silicon-based growth substrates and epitaxially grown semiconductor layers results in thermal strain in the semiconductor layers, causing cracking and bowing in the deposited5 layers.2023PF01432 - 2 -The presence of a high density of dislocation defects, particularly in µLEDs, results in a lowering of the quantum efficiency of optoelectronic devices, with threading dislocations being a major factor in lowered internal quantum efficiency. With reduction in device5 size, the statistical variation of dislocation density results in asignificant variationof the device performance. It is an object of the present application to achieve heteroepitaxial growth of high-quality semiconductor layers for manufacture of micro-0 scale optoelectronic devices with improved performance and higher yieldat lower cost. SUMMARY OF THE INVENTION5 This and other objects are addressed by the subject matter of theindependent claims. Features and further aspects of the proposed principles are outlined in the dependent claims. The inventors propose an optoelectronic device comprising epitaxial0 layers grown using a modified epitaxial lateral overgrowth processemploying commonly used bulk substrates for heteroepitaxial growth of semiconductor materials. Epitaxial lateral overgrowth (ELO) relies on selective epitaxy, in5 particular as exhibited in processes such as metalorganic vapour phaseepitaxy (MOVPE), hydride vapour phase epitaxy (HVPE) and sublimation growth. Selective epitaxy describes spatially controlled growth of an epitaxial layer through openings in a masking material. The masking material, usually a dielectric, is selected such that nucleation and0 direct growth of the semiconductor material on the surface of the maskis effectively suppressed. As a result of the selectivity of the mask, growth starts from a seed layer deposited underneath and / or within the openings in the mask and expands laterally. The choice of mask will therefore depend on the semiconductor material system used, with common5 dielectric mask materials for nitride-based epitaxy including siliconoxide (SiO2), silicon nitrides (SiNX), among others.2023PF01432 - 3 -During an ELO process, the structured mask leads to a filtering of defects, in particular, crystal defects for example threading discloations and the like, with the microstructure of the deposited epitaxial layers above the mask reproducing the underlying template5 formed by the seed layer and the openings in the dielectric mask. Inessence, the propagation of crystal defects arising from the seed layer is substantially prevented by the mask, thereby constraining dislocations to regions corresponding to the mask openings. A filtering of defects above the mask thereby results, allowing the growth of0 regions of significantly reduced density of crystal defects, with acomparative reduction in threading dislocation density in the laterally overgrown region in the order of 102to 104cm-2. In this regard the term crystal defects shall encompass several different types of defects and dislocations, including for example threading dislocations or screw5 dislocation.Variants of ELO include pendeo-epitaxy (PE), pulsed ELO and FACELO. Pendeo-epitaxy involves growth from the sidewalls of mask-capped strips of seed material, commonly resulting in formation of voids underneath0 the laterally grown layers. In pulsed ELO, the flow of at least oneprecursor is supplied intermittently, with periods of low or zero flow alternating with periods of high flow. FACELO involves control of the development of growth facets by control of specific process parameters, in particular reactor pressure and growth temperature. 5 Conventionally ELO is implemented using mask patterns comprising stripes. The resultant elongated profile is particularly suitable for long and narrow devices such as laser diodes. For devices characterized by aspect ratios close to 1, the separation of individual devices from0 the elongated layers characteristic of stripe-based ELO is associatedwith introduction of defects into the semiconductor material, particularly along the planes of separation. Additionally, an inherent low symmetry in the stripe patterns results in anisotropic stress and wafer bowing. 5 An alternative to striped patterning of the dielectric mask has been the use of circular, hexagonal or triangular dot-like openings.2023PF01432 - 4 -However, the formation of slow-growth facets limits the size of the overgrown area, thereby limiting the applications of the resultant semiconductor structures. In GaN, for example, implementation of ELO on a mask with circular or hexagonal dot-like openings results in5 hexagonal or truncated hexagonal pyramids bounded by side facets along{1101} planes, which are slow growing. The lateral expansion is slowed down by the formation of the slow-growth facets, thereby making it challenging to produce wide overgrown regions with low dislocation density. 0 To address the abovementioned challenges inherent in current ELO implementation approaches, the inventors propose a new approach to the design of the dielectric mask layer to suit the requirements of µLED fabrication. In addition, new designs of optoelectronic devices, in5 particular, µLED chips compatible with ELO processes implementedaccording to the proposed approach are disclosed. The proposed approach results in a reduced dislocation density over laterally overgrown semiconductor layers making processing of devices0 with a very narrow distribution of µLED parameters possible. As aresult, the efficiency and yield of the semiconductor fabrication process is improved. Additionally, ELO processes result in a compliance layer between the starting substrate and the epitaxial structure, said compliance layer arising either from an integrated dielectric mask5 layer or a void. The compliance layer serves to substantially eliminateor greatly reduce cracking, improving wafer yield during manufacture of optoelectronic devices. The overgrown epitaxial film is partially or fully relaxed, as thermal0 and lattice mismatch-based strains which characterize heteroepitaxialfilms directly grown on foreign substrates are avoided by growing the epitaxial film laterally from homogeneous semiconductor material. A reduction in the piezoelectric field and associated quantum confined Stark effect (QCSE) in the quantum well active region leads to improved5 efficiency of µLED devices.2023PF01432 - 5 -The proposed epitaxial structure comprises a starting substrate upon which a semiconductor seed layer, a patterned mask layer, a laterally overgrown epitaxial layer and a semiconductor stack are deposited. The deposited semiconductor stack is further processed to form5 optoelectronic devices.Common starting substrates used in manufacture of µLED devices typically comprise silicon and sapphire, with bulk substrates readily available for commercial application. Potential formation of defects due to thermal and lattice mismatch is avoided through the ELO process,0 thereby allowing great flexibility in the choice of semiconductormaterial for subsequent semiconductor layers. The semiconductor layers forming both the seed layer and the laterally overgrown epitaxial layer may comprise any suitable III / V material,5 depending on intended application. Common material systems are basedon nitrides, phosphides and arsenides, with various combinations of III-group elements resulting in binary, ternary or quaternary compounds. The nitride material system is of particular interest in manufacture of µLED devices due to the encompassed spectral range, with0 wavelengths covering the entire visible spectrum, and extending intothe infrared and deep ultraviolet ranges. Implementation of ternary and / or quaternary compounds allows achievement of a tunable bandgap, with the achievable wavelengths dependent on the proportion of specific III-group elements within the semiconductor material composition.5 While the following description primarily refers to nitride-based semiconductor materials, in particular, III-nitrides exhibiting wurtzite crystal structures, the proposed approach is not limited thereto, and may be applied to III-nitride compounds exhibiting Zinc-0 Blende crystal structure, in addition to any other semiconductormaterials and / or material systems, either singly or in combination. A method of processing an optoelectronic device according to the proposed principle involves a first step of providing a growth5 substrate. The growth substrate may comprise any suitable material,with commonly available options including but not limited to silicon and sapphire. The growth substrate may be subjected to a variety of2023PF01432 - 6 -processes to improve surface characteristics conducive to epitaxial growth. Preparatory processes employed to growth substrates include but are not limited to annealing, chemical cleaning, polishing and / or structuring of the growth surface. Additional preparation may include5 low temperature deposition of a buffer layer of semiconductor material,typically comprising a compound from the same material system as the semiconductor layers to be grown on the growth substrate. For III- nitride materials, the buffer layer may comprise low-temperature binary, ternary or quaternary III-nitrides. 0 A first layer of semiconductor material, hereafter also referred to as a semiconductor seed layer, is deposited on an upper surface of the prepared growth substrate. The semiconductor seed layer preferably comprises a binary semiconductor material, as the control of lateral5 to vertical growth is achievable through suitable variation of growthparameters, in particular growth temperature and pressure. In some aspects, the semiconductor seed layer and the subsequent laterally grown layers may comprise a ternary semiconductor material. Where ternary semiconductor materials are used, the control of lateral to0 vertical growth requires additional adjustment of process parametersbased on material composition, increasing the complexity of the process, in particular where the composition of the ternary semiconductor material is not uniform within the epitaxially grown layers. 5 A patterned dielectric mask layer is arranged on a surface of the semiconductor seed layer facing away from the growth substrate. The dielectric mask is selected to prevent nucleation and direct growth of semiconductor material on its surface, restricting epitaxial growth to0 openings in the mask. The dielectric mask layer may comprise anysuitably selective material, with dielectric materials comprising silicon oxide (SiO2), silicon nitrides (SiNX) commonly employed for ELO processes involving GaN. Suitable processes for the deposition of the dielectric mask layer include but are not limited to plasma-enhanced5 chemical vapour deposition (PECVD), metal organic chemical vapourdeposition (MOCVD) or RF sputtering.2023PF01432 - 7 -The dielectric mask layer is designed to comprise substantially rectangular elements arranged in a matrix comprising lateral rows and columns, rather than the conventionally employed stripes / gratings or point openings in the dielectric mask. In a process using conventional5 ELO, the substantially rectangular elements are incorporated into themask design in the form of rectangular openings in the mask layer. The length of the openings is restricted to a range between 1 µm and 200 µm, in particular between 5 µm and 150 µm, and in particular between 5 µm and 100 µm. Restriction of the opening length to micrometre0 dimensions serves to limit bowing of the wafer during growth and aftercooling down, and additionally prevents formation and propagation of cracks. The openings are designed with a width between 0.1 µm and 20 µm, in particular between 0.1 µm and 10µm, with the width of the opening corresponding directly to the extent of the regions of the epitaxial5 structure exhibiting an elevated density of crystal defects.The orientation of the dielectric mask openings determines the growth rate of the facets comprising the epitaxial layer. In particular, for wurtzite III-nitrides, it is particularly advantageous to align the0 openings along <1100> crystal directions of the semiconductor seedlayer. This allows achievement of cross sections with top facets aligned on the {0001} crystal plane, and sidewall topology dependent on growth conditions, in particular, growth pressure and temperature.5 Epitaxial growth of the semiconductor layers is achieved using suitableprocesses characterized by selective epitaxy and growth anisotropy. In particular, MOVPE and HVPE processes allow suppression of growth on the dielectric mask through suitable choice of growth parameters, temperature, pressure, and mole fraction of the active elements.0 Achievement of different growth rates on different crystallographicplanes as a result of growth anisotropy allows control of the topography of lateral overgrowth. Sublimation growth may also be used to implement the ELO process.5 Considering a single rectangular stripe with a length L and a width W,wherein the length is oriented along the <1100> crystal direction, initial growth occurs within the opening in the dielectric mask until2023PF01432 - 8 -the top surface of the dielectric mask layer is reached, forming a first region of semiconductor material. The density of crystal defects within this first region of semiconductor material, hereafter referred to as a first density of crystal defects, corresponds to the underlying5 semiconductor seed layer underneath the dielectric mask, as the openingprovides uninterrupted vertical growth planes. Existing crystal defects therefore propagate through the openings in the dielectric mask layer into the first region of the epitaxial layer, extending to the surface of the deposited semiconductor material in the region vertically above0 the openings in the dielectric mask.Subsequent deposition of semiconductor results in vertical growth extending the region above the mask opening upwards, extending the first region of the epitaxial layer, and additional lateral growth,5 expanding the epitaxial layer laterally over the masked area, andforming a second region of semiconductor material. This second region of semiconductor material is characterized by a second density of crystal defects that is lower than the first density of crystal defects. The reduction in threading dislocation density between the first region0 and the second region is of an order of magnitude in the range between102and 105cm-2and arises from the interruption of propagation planes of crystal defects from the semiconductor seed layer by the dielectric mask layer.5 In some aspects of the proposed principle involving pendeo-epitaxy,the dielectric mask design is modified such that instead of rectangular openings, a pattern of rectangular islands of dielectric mask material are formed on the surface of the semiconductor seed layer. A subsequent etching process results in elevated seed areas / walls with a0 substantially rectangular lateral cross-section, each column capped bya layer of dielectric mask material. These elevated columns form a first region of the semiconductor layer and are characterized by a first density of crystal defects.5 Due to the selectivity of the dielectric mask material, nucleation anddirect growth on the surface of the mask is prevented, with the overgrown layer either simply resting on the dielectric mask layer,2023PF01432 - 9 -or, in some cases, suspended above the dielectric mask layer. The ratio of lateral to vertical growth may be controlled by adjusting the growth temperature, the composition of the carrier gas, or by introduction of p-dopant material, in particular Mg in the form of (MeCp)2Mg.5 As more material is deposited and the epitaxial layer expandslaterally, the interaction between fast and slow growth facets associated with different crystal planes leads to vanishing of the {112 0} a-plane and the {1010} m-plane, resulting in a diamond-shaped structure with inclined sidewalls along the {1011} plane and internal0 angles of 60° and 120°. At termination of the lateral expansion of thegrowth facets, the width of the laterally grown structure is approximately 0.58X the length of the mask opening. Subsequent deposition of additional semiconductor material results in5 lateral growth from the sidewalls of the elevated columns, with thelateral growth surrounding and laterally enclosing the seed column / wall. The laterally grown semiconductor material forms a second region of the semiconductor layer characterized by a second density of crystal defects. The second density of crystal defects is lower than0 the first density of crystal defects by several orders of magnitude inthe range between 102and 105cm-2. The reduction in the density of crystal defects in the second region results from the orientation of the second region laterally displaced from the dislocation lines propagating within the first region of the semiconductor layer. 5 In some aspects, the epitaxial growth process is allowed to continue until a combination of vertical growth and inward-facing lateral growth results in a complete enclosure of the dielectric mask layer. The encapsulation of the dielectric mask layer may be accompanied by0 formation of a void between an upper surface of the dielectric maskand the epitaxially grown layer. The semiconductor material above the dielectric layer additionally forms an extension of the second region of semiconductor material. In these aspects, a third region of semiconductor material corresponding to the planes of coalescence of5 the laterally grown epitaxial layer develops above the structureddielectric mask layer. This third region of semiconductor material is characterized by a third density of crystal defects of a magnitude2023PF01432 - 10 -greater than the second density of crystal defects. The greater density of crystal defects arises due to the incoherent coalescence boundary acting as a nucleation source for a variety of defects such as dislocations and stacking faults.5 In alternative aspects, the dielectric mask layer capping the etchedsemiconductor seed layer areas is suppressed or removed, whereby an encapsulation of the dielectric mask layer is achieved without formation of a void within the epitaxial layers. In these aspects, the coalescence boundary comprises a third region of semiconductor material0 characterized by the aforementioned third density of crystal defects.In some aspects, an individual diamond-shaped island of semiconductor material serves as a base layer for processing of an individual chip. A substantially rectangular first region of the semiconductor layer5 runs along a central axis of the semiconductor material. The firstregion may be used for positioning of electrically conductive contacts. As the epitaxial layer sidewalls are formed by the laterally overgrown semiconductor layers, aligned with specific crystal planes depending on growth conditions, in particular, oriented along the {1011} crystal0 plane, additional mesa structuring processes are not essential.Sidewall defects associated with etching processes employed in conventional mesa structuring may thereby be avoided. In some aspects, each individual diamond-shaped island formed from a5 rectangular-shaped element may be used as to process two chips. Thisis accomplished by splitting the diamond either longitudinally or transversally with respect to the orientation of the substantially rectangular-shaped first region.0 In aspects involving a longitudinal split, the width of etching is setto remove first regions of the epitaxial layers partially or completely. In these aspects, the resultant removal of low-quality semiconductor material characterized by high defect densities allows processing of optoelectronic devices on epitaxial layers that are5 substantially defect-free. Additionally, where a void is formed underthe laterally grown layer, removal of the first region, by which the second region of the semiconductor layer is attached to the growth2023PF01432 - 11 -substrate underneath, achieves separation of the chip from the substrate. A longitudinal split of the overgrown diamond-shaped semiconductor islands however results in low aspect ratio (lower than 0.3) and sharp corners. Additionally, the etched sidewall corresponding5 to the axis of separation is characterized by a large surface area,thereby increasing surface defects on the device sidewalls occasioned by the etching process. Aspects of the proposed invention involving separation of the diamond-0 shaped epitaxial layers along a transverse axis with respect to theorientation of the substantially rectangular-shaped first region result in chips substantially in the shape of equilateral triangles, thereby exhibiting an aspect ratio of 1. The first region runs substantially along a central axis of the triangular surface, bisecting one sidewall5 of the chip. As a result, these aspects are characterized by one chipsidewall partially comprising a first region, and two adjacent sidewalls that are substantially entirely formed from the second region of semiconductor material. As the first region of the epitaxial layer remains intact in these aspects, a separate chip separation process is0 required. The first region on the resultant chip may be used forpositioning electrical contacts. Some aspects of the proposed invention relate to the arrangement of a plurality of first regions through patterning of the dielectric mask5 layer. The patterning of the dielectric mask involves formation ofsubstantially rectangular islands of mask material for pendeo-epitaxy, and substantially rectangular openings within the dielectric mask layer for conventional ELO and other similar approaches. The invention is nonetheless not restricted to the dielectric mask patterns and0 resultant patterns of first regions of semiconductor material disclosedhereafter in exemplary aspects. In some aspects, the dielectric mask layer is structured to form a plurality of substantially rectangular first regions arranged in two5 dimensional matrices comprising rows and columns. The rows and columnsof substantially rectangular first regions are arranged such that a geometric centroid of each of the substantially rectangular first2023PF01432 - 12 -regions is laterally displaced from geometric centroids of each of at least two adjacent substantially rectangular first region by translations along at least two axes. In some aspects, this results in multiple rows and columns of first regions characterized by a parallel5 orientation of their respective lengths, with translations of alternatecolumns resulting in a triangular lattice. The separation distance between adjacent columns, or the pitch, is set to approximately 1.3X the length of the first regions to avoid coalescence of adjacent islands of lateral overgrowth. 0 In alternative aspects, the dielectric mask layer is patterned to form a plurality of substantially rectangular first regions oriented with the lengths of the first regions laterally inclined towards adjacent first regions, wherein an angle substantially equal to 60° or 120° is5 formed between adjacent first regions. The overall lattice of firstregions comprises patterns of substantially equilateral triangles, with each first region laterally enclosed within a diamond-shaped second region of semiconductor material. The lateral separation between the ends of adjacent first regions may be selected to ensure that lateral0 expansion of the second region occurs without coalescence of adjacentsecond regions. An inherent advantage of aspects comprising a pattern of first regions arranged in a triangular lattice as disclosed is the formation of a highly symmetrical pattern, which is associated with a symmetric distribution of stress and bow within the entire wafer.5 Further aspects of the proposed invention are related to the processing of µLEDs on the diamond-shaped islands of semiconductor material by deposition of a semiconductor stack comprising an active layer arranged between doped semiconductor layers. A first doped semiconductor layer0 is deposited on an upper surface of the first and second regions facingaway from the growth substrate. An active layer is subsequently deposited on an upper surface of the first doped semiconductor layer facing away from the growth substrate. A second doped semiconductor layer is thereafter deposited on an upper surface of the active region5 facing away from the growth substrate.2023PF01432 - 13 -The above mentioned first and second doped semiconductor layers may comprise one or more sublayers. The sublayers may comprise different material composition based on the selected system, different doping concentration, doping gradients and may even be undoped in some5 instances. The sublayers provide a dedicated functionality such ascurrent spreading, current injection, to mention a few. The active layer may comprise a multi quantum well structure including a plurality of barrier and quantum well layers. The active layer may be undoped but can also comprise a small doping concentration in some aspects. In0 some further aspects, the active layer may comprise at least twocladding layers, which are undoped. The cladding layers reduce or prevent a diffusion of dopants into the active layer, thus reducing aging effects.5 In some aspects wherein each diamond-shaped island of semiconductormaterial is used to process a single optoelectronic device, the deposition of the semiconductor stack may be limited to a substantially hexagonal region, particularly located concentric to the diamond-shaped island. In certain aspects, sidewalls of the semiconductor stack are0 aligned to m-facets of the diamond-shaped island, such that thesidewalls of the underlying diamond-shaped islands and the sidewalls of the semiconductor stack are substantially coplanar. In other aspects, sidewalls of the semiconductor stack are aligned to a-facets of the diamond-shaped island of semiconductor material, such that the5 sidewalls of the semiconductor stack and the sidewalls of the diamond-shaped ELO layer are laterally displaced from each other. In the aspects described above, both wherein the semiconductor sidewalls are aligned to m-facets, and wherein the semiconductor sidewalls are aligned to a- facets of the diamond-shaped island, upper surfaces of the diamond-0 shaped island extending laterally from the first doped semiconductorlayer may be used for providing electrical contact to the first doped semiconductor layer. Growth of semiconductor layers by ELO processes is characterized by5 fast-growing and slow-growing facets aligned to specific crystal planesof the semiconductor material. Hereafter a growth process wherein the direction of growth is predominantly outwards from the dielectric mask2023PF01432 - 14 -windows, or, in the case of pendeo-epitaxy, from the structured seed columns, is referred to as convex growth. The resultant ELO layer is characterized by islands of second regions of semiconductor material laterally surrounding substantially rectangular first regions.5 Conversely, a growth process wherein the patterning of the dielectricmask is such that lateral growth occurs predominantly inwards, with islands of epitaxially grown layers surrounded by boundaries comprising first regions is hereafter referred to as concave growth.0 A convex epitaxial growth process is characterized by a growth of fast-growing facets to extinction, resulting in sharp corners. Slow-growing facets are left behind to form the sidewalls of the resultant epitaxial structure. In a concave epitaxial growth process, however, inward growth results in expansion of fast-growing facets, thereby resulting5 in an epitaxial structure comprising fast-growing facets laterallyadjacent to slow-growing facets, thereby increasing lateral growth rate and the area of the second regions with low dislocation density, which would otherwise form if the fast-growing facets grew to extinction.0 The proposed invention achieves the prevention of growth to extinctionand the accompanying vanishing of fast-growing facets of ELO epitaxial structures through modifications in the design of the dielectric mask layer, with exemplary aspects related thereto discussed hereunder. While the description addresses conventional ELO, and therefore refers5 to openings in the dielectric mask layer, the proposed aspects may beimplemented in pendeo-epitaxy through suitable design of dielectric mask elements arranged on the surface of the semiconductor seed layer prior to etching to form semiconductor seed columns.0 In some exemplary aspects, the substantially rectangular dielectricmask openings are arranged to form patterns comprising a primary rectangular stripe connected at each end to at least two support wings, each support wing forming an angle between 40° and 80°, in particular between 50° and 70°, and in particular between 55° and 65° with the5 primary stripe. In alternative aspects, the support wings form an anglebetween 100° and 140°, in particular between 110° and 130°, and in particular between 115° and 125° with the primary stripe. The2023PF01432 - 15 -dimensions of the primary stripe correspond to the previously specified dimensions of substantially rectangular mask openings, with the length of the openings within a range between 1 µm and 200 µm, in particular between 5 µm and 150 µm, and in particular between 5 µm and 100 µm.5 The width of the primary openings is between 0.1 µm and 20 µm, inparticular between 0.5 µm and 10µm. The support wings comprise a width substantially identical to the width of the primary openings. The length of the support wings can be smaller than the length of the primary openings in some instances, but also approximately equal or0 even longer. In certain aspects of the proposed invention, thedielectric mask layer comprises arrays of such patterns of primary stripes and associated support wings arranged in a regular periodic lattice. The positioning of individual elements each comprising a primary stripe and associated support wings with respect to each other5 is designed in some aspects to ensure that adjacent areas of lateralinward growth do not coalesce with each other. In alternative aspects, the lattice is designed to allow coalescence of adjacent areas of lateral inward growth, wherein the coalescence boundaries form third regions of semiconductor material characterized by a third density of0 crystal defects, wherein the third density of crystal defects isgreater than the second density of crystal defects. Additional aspects of the proposed invention achieve concave lateral growth through patterning of the dielectric mask such that a plurality5 of substantially rectangular mask openings are connected to formlattices of substantially equilateral polygons bounded by substantially rectangular mask openings, in particular substantially equilateral triangles, rhombuses and / or hexagons. Parallelograms with 120° / 60° and elongated hexagons are also possible. The direction of lateral growth0 of the epitaxial layer is inwards from boundaries formed by theplurality of mask openings. In some aspects the ELO layer is grown laterally until growth facets originating from the openings in the dielectric mask layer coalesce to form continuous polygonal areas of semiconductor material. The epitaxial layer comprises regions of high5 threading dislocation density in regions vertically above the openingsin the dielectric mask, and additionally in central regions substantially corresponding to the geometric centroids of the2023PF01432 - 16 -respective polygonal shapes, forming a defective core. The defective cores are formed as a result of coalescence of inward-growing facets. The resultant epitaxial structures are therefore characterized by lattices comprising polygons of ELO layers bounded by regions of high5 threading dislocation density, corresponding to the mask openings, andadditionally comprising defective cores located substantially at the geometric centroids of the respective ELO polygons. In some aspects wherein the substantially equilateral polygons comprise0 triangles, at least one face of each triangle is aligned along adirection parallel to the <1100> crystal direction of the semiconductor lattice. Certain aspects of the proposed invention relate to dielectric mask5 patterning wherein the substantially rectangular openings in thedielectric mask layer are arranged to form combinations of different polygons, in particular, combinations of equilateral hexagons and equilateral rhombuses, wherein the geometric centroids of the equilateral hexagons are laterally equidistant to adjacent equilateral0 hexagons in at least two mutually perpendicular lateral axes. An arrayof equilateral rhombuses is arranged between adjacent columns of equilateral hexagons, forming a quadratic raster array of semiconductor islands. In some aspects integrating such a quadratic raster array, the hexagonal islands of ELO material are used for processing of µLEDs,5 whereas the rhombus-shaped islands form nonfunctional areas. Thequadratic raster array forms a template suitable for processing of µLED assemblies comprising identical device pitch along both lateral axes. Aspects of the proposed invention comprising a defective core formed0 due to coalescence of laterally grown facets may be further processedby removal or passivation of the material comprising the defective core. The region corresponding to the defective core may also be used for formation of electrically conductive contacts on the second doped layer of the semiconductor stack formed thereupon. Removal of defective5 regions may be achieved by dry and / or wet etching processes, whereinthe selection of suitable etchants depends on the semiconductor material.2023PF01432 - 17 -The growth substrate and the ELO semiconductor layer form a growth template on which semiconductor stacks comprising an active layer arranged between doped semiconductor layers may be deposited to form optoelectronic devices. A first doped semiconductor layer is deposited5 on an upper surface of the first and second regions facing away fromthe growth substrate. An active layer is subsequently deposited on an upper surface of the first doped semiconductor layer facing away from the growth substrate. A second doped semiconductor layer is thereafter deposited on an upper surface of the active region facing away from0 the growth substrate. The doped semiconductor layers may each compriseone or more sublayers. The sublayers may comprise different material composition based on the selected system, different doping concentration, doping gradients and may even be undoped in some instances. The sublayers provide a dedicated functionality such as5 current spreading, current injection, to mention a few. The activelayer may comprise a multi quantum well structure including a plurality of barrier and quantum well layers. The active layer may be undoped but can also comprise a small doping concentration in some aspects. In some further aspects, the active layer may comprise at least two0 cladding layers, which are undoped. The cladding layers reduce orprevent a diffusion of dopants into the active layer, thus reducing aging effects. The epitaxially grown structure comprising the ELO semiconductor layers5 and the semiconductor stack deposited thereupon is, in a subsequentstep, separated from the growth substrate. Separation from the growth substrate may be accomplished by wet and / or dry etching processes employing suitably selected etchants. In aspects employing conventional ELO, the dielectric mask layer and the semiconductor seed layer are0 additionally removed to separate the semiconductor stack from thegrowth template. In some aspects, the dielectric mask layer may be partially or completely removed, usually through a wet etching process. Suitable etchants may comprise, for example, hydrofluoric acid for silicon oxide-based dielectric mask layers, or hot phosphoric acid for5 silicon nitride-based dielectric mask layers.2023PF01432 - 18 -The proposed invention additionally concerns an optoelectronic device, in particular, a µLED chip. The proposed optoelectronic device comprises a semiconductor stack comprising an active layer arranged between doped semiconductor layers. The semiconductor stack comprises5 a first region of epitaxially grown semiconductor material laterallysurrounded by a second region of epitaxially grown semiconductor material. The first region is characterized by a first density of crystal defects, and the second region is characterized by a second density of crystal defects, wherein the first density of crystal0 defects is greater than the second density of crystal defects. Thedifference in the threading dislocation density arises from the use of an ELO process in the deposition of a growth template on which the semiconductor stack is epitaxially grown, after which the semiconductor stack is separated from the growth template. Propagation of crystal5 defects through the growth template is restricted by deposition of apatterned dielectric mask layer, resulting in the aforementioned distinct regions characterized by different threading dislocation densities.0 In some aspects, the optoelectronic device comprises first regions ofsemiconductor material that exhibit a substantially rectangular cross- section. A corresponding second region of semiconductor material is bounded by at least three sidewalls, forming a polygon, in particular, an equilateral polygon. The first region is oriented along a central5 longitudinal axis of the substantially equilateral polygon, such thatan angle between the first region and the sidewalls of the polygon form an angle between 10° and 80°, in particular between 25° and 65°, in particular about 30° or about 60° with an optional tolerance in the range of 2° or less. The substantially rectangular first region0 comprises a length between 0.5 µm and 100 µm, and a width between 0.1µm and 10 µm, and forms at least part of at least one sidewall of the optoelectronic device, wherein the first region is positioned substantially at a lateral midpoint of at least one sidewall of the optoelectronic device. 5 In some aspects the at least one sidewall comprising a first region positioned substantially at a lateral midpoint thereof is oriented2023PF01432 - 19 -along the <1100> crystal direction of the semiconductor stack material. A top surface of the first region may also be oriented substantially parallel to the {1010} crystal plane, i.e. the m-plane. Certain aspects of optoelectronic devices according to the proposed principle comprise5 at least two sidewalls inclined substantially parallel to a {1011}crystal facet of the semiconductor stack material, in particular where the at least two sidewalls are laterally displaced from the first region of semiconductor material.0 The optoelectronic device proposed by the inventors comprises, in someaspects, a semiconductor stack comprising an active layer arranged between two doped semiconductor layers, wherein the semiconductor stack comprises a first region and a second region characterized respectively by a first and a second density of crystal defects. The first density5 of crystal defects is greater than the second density of crystaldefects, in particular, by an order of magnitude between 102and 104cm-2. The first region is laterally surrounded by and enclosed within the second region, and the second region is laterally bounded by at least three sidewalls, such that the sidewalls are laterally displaced0 from the first region, and in particular wherein the sidewalls aresubstantially equidistant from the enclosed first region. The at least three sidewalls bounding the second region of semiconductor material form in particular equilateral polygons, and particularly equilateral triangles and / or equilateral hexagons, and / or rhombuses comprising5 internal acute angles substantially equal to 60°. In some aspects, thesidewalls bounding the second region comprise surface defects associated with etching processes. At least one sidewall may be oriented along a direction substantially parallel to the <1100> crystal direction of the semiconductor stack material. 0 Further aspects of the proposed invention relate to a display device comprising the optoelectronic devices described herein. The display device comprises a carrier substrate on which a plurality of optoelectronic devices is arranged, in particular, in a regular grid-5 like arrangement. The pitch, i.e. the distance between the geometriccentroids of adjacent optoelectronic devices along at least two lateral axes, in particular, wherein the at least two lateral axes are mutually2023PF01432 - 20 -perpendicular, is equal in some aspects. The plurality of optoelectronic devices comprises semiconductor material comprising a first and a second region, respectively characterized by a first and second density of crystal defects, wherein the first density of crystal5 defects is larger than the second density of crystal defects. Each ofthe plurality of optoelectronic devices is laterally separated from adjacent optoelectronic devices. In some aspects, the sidewalls of the optoelectronic devices are laterally surrounded and enclosed by passivated semiconductor material having a density of crystal defects0 equal to or greater than the first density of crystal defects exhibitedwithin the first region of the optoelectronic devices. In alternative aspects, each of the plurality of optoelectronic devices is bounded by sidewalls comprising etching-induced defects, with said sidewalls optionally surrounded and enclosed by dielectric material. In some5 aspects the display device comprises a plurality of nonfunctionalregions comprising semiconductor material dispersed within the grid of optoelectronic devices, in particular in a grid-like arrangement comprising rows and columns.0 SHORT DESCRIPTION OF THE DRAWINGSFurther aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which 5 Figure 1 shows an optoelectronic device during an intermediate processing step according to the proposed principle. Figure 2 illustrates a top view of an optoelectronic device in0 accordance with some aspects of the proposed principle.Figures 3A and 3B show some dielectric mask designs relating to some aspects of the proposed method.5 Figures 4A an 4B illustrate exemplary top view of grown templates forprocessing of optoelectronic devices in accordance with some aspects of the proposed principle.2023PF01432 - 21 -Figures 5A and 5B illustrate further steps in processing of optoelectronic devices according to the proposed method. Figures 6A and 6B illustrate typical facet developments during5 epitaxial growth in accordance with some aspects of the proposedprinciple. Figures 7A to 8C and 10 show further aspects related to dielectric mask design in accordance with the proposed principle. 0 Figures 9A to 9D and 11A to 11B illustrate some steps in the processing of an optoelectronic device according to some aspects of the proposed principle.5 DETAILED DESCRIPTIONThe following embodiments and examples disclose various aspects and their combinations according to the proposed principle. The embodiments and examples are not always to scale. Likewise, different elements can be displayed enlarged or reduced in size to emphasize individual0 aspects. It goes without saying that the individual aspects of theembodiments and examples shown in the figures can be combined with each other without further ado, without this contradicting the principle according to the invention. Some aspects show a regular structure or form. It should be noted that in practice slight differences and5 deviations from the ideal form may occur without, however,contradicting the inventive idea. In addition, the individual figures and aspects are not necessarily shown in the correct size, nor do the proportions between individual0 elements have to be essentially correct. Some aspects are highlightedby showing them enlarged. However, terms such as "above", “over”, "below", "under" "larger", "smaller" and the like are correctly represented with regard to the elements in the figures. So it is possible to deduce such relations between the elements based on the5 figures.2023PF01432 - 22 -Figure 1 illustrates the structure of an optoelectronic device 1 comprising multiple µLED devices 150 according to the proposed principle, said optoelectronic device being at an intermediate processing stage, prior to separation from a growth template 110. The5 growth template comprises a growth substrate 100, a semiconductor seedlayer 120, and a patterned dielectric mask layer 130, said dielectric mask layer comprising a plurality of openings 131. The growth template further comprises a layer of semiconductor material deposited through an epitaxial lateral overgrowth process, wherein semiconductor material0 from the semiconductor seed layer 120 is grown vertically through theopenings 131 in the dielectric mask layer 130, and thereafter laterally deposited outwards from the openings in the dielectric mask, with lateral growth occurring in the direction A. The deposited epitaxial layer is characterized by a first region 144 and a second region 145,5 wherein the first region is characterized by a first density of crystaldefects substantially equal to the density of crystal defects in the semiconductor seed layer 120. The second region 145 is characterized by a second density of crystal defects, wherein the second density of crystal defects is smaller than the first density of crystal defects0 by a factor between 102 and 104 cm-2.The optoelectronic device structure further comprises a semiconductor stack 140 epitaxially grown on the growth template. The semiconductor stack comprises an active layer 142 arranged between a first doped5 layer 141 and a second doped layer 143. The first region ofsemiconductor material comprising a first, higher density of crystal defects propagating from the semiconductor seed layer extends into the semiconductor stack, resulting in an optoelectronic device comprising a distinct, discrete, defective region laterally surrounded by high0 quality semiconductor material forming the second region of theepitaxial structure. In Figure 2 a lateral cross section through an aspect 2 of the proposed optoelectronic device is illustrated. A first region 201 characterized5 by a first, higher density of crystal defects is observable within thestructure, surrounded by a second region 202 of epitaxially deposited semiconductor material characterized by a second, lower density of2023PF01432 - 23 -crystal defects. The first region 201 corresponds to the location of openings within the dielectric mask in the growth template, with crystal defects propagating from the underlying semiconductor seed layer to the surface of the optoelectronic device. The first region5 201 is laterally oriented along a direction u, corresponding to the <1100> crystal direction. Direction v represents the laterally perpendicular <1120> crystal direction. The first region corresponds to a dielectric mask opening comprising a length LObetween 5 µm and 100 µm and a width WObetween 0.1 µm and 10 µm. Lateral growth of0 semiconductor material through the substantially rectangular maskopening anisotropically, with fast-growing facets growing to extinction, leaving behind sidewalls 203 comprising slow-growing facets. A diamond-shaped island of semiconductor material comprising interior angles ^^ ≈ 60° and ^^ ≈ 120°, and bounded by substantially5 equilateral inclined sidewalls 203 oriented along {1011} crystal planesresults, while growth facets corresponding to the a-plane 204 and the vertical m-plane 205 vanish during the epitaxial lateral overgrowth process. The width of the resultant surface is directly proportional to the length of the dielectric mask opening and the corresponding0 first region 201, with the final chip width WC equal to about 0.58times the length LOof the first region. Aspects of the proposed principle relating to the design of dielectric mask patterns, in particular with respect to the positioning and5 orientation of multiple dielectric mask openings, are illustrated inFigures 3A and 3B, with the resultant growth templates comprising ELO- deposited semiconductor material shown in Figures 4A and 4B. In Figure 3A, a plurality of openings 301 in a dielectric mask layer 302 are oriented along substantially parallel lateral axes, with alternate0 columns of mask openings laterally translated by a displacement Ty,such that centroids 303 of adjacent dielectric mask openings are displaced from each other along at least two lateral axes, represented by the displacements Txand Ty. An alternative dielectric mask patterning according to some aspects of the proposed invention is shown5 in Figure 3B, where individual openings 301 in the dielectric mask 302are laterally inclined with respect to adjacent mask openings, forming alattice of unconnected substantially equilateral triangles (^^ ≈ 60°).2023PF01432 - 24 -Following epitaxial lateral overgrowth of semiconductor material through the openings in the dielectric mask 302, an epitaxial layer comprising a plurality of islands, each comprising a first region 201 characterized by high threading dislocation density and a second region5 202 characterized by lower threading dislocation density is formed.The second regions extend laterally above the surface of the dielectric mask 302 and are bounded by inclined sidewalls 203. Subsequent steps in the processing of an optoelectronic device0 according to the proposed principle involve the epitaxial growth of asemiconductor stack on the prepared growth template. Figures 5A and 5B illustrate exemplary aspects of µLEDs processed on the diamond-shaped epitaxial layers prepared in accordance with the proposed invention. In Figure 5A, the hexagonal semiconductor stack 410 is epitaxially5 grown with four of its sidewalls 430 aligned to the m-planes of thesemiconductor islands on the growth template. Residual surfaces of the growth template 420 are used for electrically contacting a doped semiconductor layer of the optoelectronic device. Each semiconductor device comprises two sidewalls bisected by a first region of0 semiconductor material characterized by higher defect density incomparison with surrounding regions of the optoelectronic device. Alternatively, as illustrated in Figure 5B, the sidewalls 430 of the semiconductor stack 410 are aligned to a-planes of the ELO-deposited layer of the growth template. The growth template sidewalls 203 and5 the semiconductor stack sidewalls 430 are laterally displaced from eachother. The first region 201 characterized by a high defect density laterally bisects the semiconductor stack, aligned between opposite vertices of the hexagonal surface. Residual regions 420 of semiconductor material on the growth template may be used for0 electrically contacting a doped semiconductor layer.The extinction of fast-growing facets during ELO deposition is illustrated in Figure 6A, in particular with respect to outward growth, herein also referred to as convex growth. Epitaxial growth advances5 anisotropically along fast-growing facets 500 and adjacent slow-growingfacets 510. The higher rate of growth of the fast-growing facets results in facets with decreasing lateral dimensions 501, while the slow-2023PF01432 - 25 -growing facets evolve into facets with increasing dimensions 511. The fast-growing facets eventually vanish, resulting in a convergence of slow-growing facets, which then form the sidewalls of the epitaxial structure, typically comprising acute angles between adjacent5 sidewalls. Figure 6B illustrates concave growth, wherein the facets ofthe epitaxial structure are grown inwards from openings in the dielectric mask. As the fast-growing facets 500 extend inwards, a lateral increase in dimensions occur, resulting in a larger facet 502. Conversely, the slow-growing facets 510 decrease in size, resulting in0 smaller facets 512. The resultant epitaxial structure thereby comprisesa greater number of surviving facets comprising obtuse angles between adjacent sidewalls, thereby avoiding sharp corners in the resultant epitaxial structure.5 Figures 7A and 7B show aspects of dielectric mask patterning involvingmodification of the substantially rectangular openings in the dielectric mask layer. Each primary opening 601 is connected to two support wings 603 at each end, with the connected openings forming an angle ^1substantially equal to 60° or an angle ^2substantially equal0 to 120°. The support wings form a concave growth front 604, with adisappearance of fast-growing facets emerging parallel to the primary openings 601 mitigated by merging with fast-growing facets emerging from the support wings. A large, substantially defect-free second region 602 is formed, which may be used for further processing of5 optoelectronic devices, in particular, deposition of a semiconductorstack. In some aspects, a plurality of dielectric mask openings 701 are connected to form, in particular, equilateral polygons. Figure 8A0 illustrates an aspect according to the proposed principle, whereinthree dielectric mask openings are arranged to form a substantially equilateral triangle 5. Lateral growth of the epitaxial layer originating from the openings in the dielectric mask occurs inwards, as indicated by the dashed arrows originating from the dielectric mask5 openings. Adjacent epitaxial growth fronts merge along planes ofcoalescence 703. A region characterized by a high density of crystal defects is formed at the coalescence boundary of all three growth2023PF01432 - 26 -fronts, resulting in a defective region 702 situated centrally within the region bounded by the dielectric mask openings, said defective region surrounded by higher quality, substantially defect-free semiconductor material in region 704.5 The dielectric mask layer may be patterned based on regular repetitionsof similar equilateral polygons, in particular comprising equilateral triangles 5, as shown in Figure 8B, or equilateral hexagons 6, as shown in Figure 8C. The deposited material comprises regions of substantially defect-free material surrounded by boundaries characterized by high0 threading dislocation density, and additionally comprises a centrallylocated region of high threading dislocation density resulting from the coalescence of epitaxial growth fronts 604 expanding inwards. Further aspects relate to a method for processing an optoelectronic5 device. Figure 9A illustrates an exemplary aspect 7 according to theproposed principle. The optoelectronic device comprises a first region 702 of high threading dislocation density laterally enclosed within a second region 704 of lower threading dislocation density. The second region is bounded by regions 701 of high threading dislocation density0 corresponding to openings in the dielectric mask layer through which asemiconductor seed layer is grown vertically and laterally. The proposed method involves providing a growth template comprising an upper surface of ELO-deposited semiconductor material, on which a5 semiconductor stack is grown. Figure 9B shows a growth substrate 100,on which a semiconductor seed layer 120 is deposited. A patterned dielectric mask layer 130 is deposited on an upper surface of the semiconductor seed layer facing away from the growth substrate. Vertical growth through openings in the dielectric mask layer is0 accompanied by lateral growth above the dielectric mask, resulting insubstantially mask-free regions of semiconductor material. A first doped semiconductor layer 141 is deposited on the upper surface of the growth template facing away from the growth substrate 100. An active layer 142 comprising a multi quantum well structure characterized by5 alternating quantum well and quantum barrier layers is deposited onthe upper surface of the first doped semiconductor layer. A second doped semiconductor layer 143 is deposited on the upper surface of the2023PF01432 - 27 -active layer. Propagation of crystal defects originating from the ELO- deposited growth template results in a semiconductor stack comprising a region of high threading dislocation density laterally located substantially at the geometric centroid of the semiconductor stack.5 The defective central region 702 is surrounded by a substantiallydefect-free region comprising high quality epitaxial layers, which is in turn laterally surrounded by regions 701 of high threading dislocation density, corresponding to the openings in the dielectric layer 130. 0 In a subsequent step illustrated in Figure 9C, the regions 701 forming the boundaries surrounding the individual semiconductor stacks are removed through a process involving wet and / or dry etching. The depth of the etch is such that the doped semiconductor layers 141 and 143,5 the active layer 142, the dielectric mask layer 130, and thesemiconductor seed layer 120 are removed from the first regions 701. Optionally, the growth substrate may be partially etched. The central defective region 702 is then optionally inactivated. In some aspects, not illustrated, the central defective region is removed. 0 A subsequent processing step illustrated in Figure 9D involves removal of the growth template 715, separating the optoelectronic device from the growth substrate, the semiconductor seed layer and the dielectric mask layer. Electrical contact to the doped semiconductor layers of5 the optoelectronic device is provided through electrically conductivecontacts 713 and 714 arranged on the surfaces of the device. The passivated defective region or hole may be used for this purpose, with the contacts arranged substantially concentrically with the defective region 702 and extending laterally to make contact with the doped0 semiconductor layers in regions of low threading defect density.Further aspects of the proposed principle, as illustrated in Figure 10, relate to an arrangement 8 of a µ-LED array on a semiconductor wafercomprising a plurality of optoelectronic devices 803, wherein each of the plurality of optoelectronic devices is processed on a pre-formed5 semiconductor island 800 on a growth template. In the illustratedaspect, the display device further comprises non-functional areas 801 arranged adjacent to the plurality of optoelectronic devices, resulting2023PF01432 - 28 -in a quadratic raster 804 wherein the lateral pitch along the x and y axes is equal. The semiconductor islands 800 and the non-functional areas 801 are optionally bounded by first regions 802 of semiconductor material characterized by a higher density of crystal defects in5 comparison with surrounding semiconductor material. In some aspectsnot illustrated herein, the first regions are removed by dry / wet etching, and the resultant gaps between adjacent semiconductor stacks are either left empty, or are filled with a dielectric material. The plurality of optoelectronic devices may then be transferred to a0 carrier substrate 805.In some aspects according to the proposed method, particularly wherein the dielectric mask patterning involves substantially rectangular openings growing laterally outwards, lateral growth is allowed to5 proceed to coalescence, as illustrated in Figure 11A, wherein thedirection of lateral growth from adjacent openings in the dielectric layer is shown by dashed arrows. The coalescence boundary 901 is typically characterized by notch-like structures 903 on the surface of the epitaxial layer. The epitaxial layer is characterized by high0 defect density along the coalescence boundary 901, which is surroundedby regions 902 of substantially defect-free semiconductor layers on which a semiconductor stack may be deposited. The first doped layer of the semiconductor stack is in some aspects formed by an ELO-deposited doped epitaxial layer 902. An active layer and a second doped layer5 143 are deposited on an upper surface of the first doped layer. Furtherprocessing of the optoelectronic device, as illustrated in Figure 11B, involves etching a trench 905 around the coalescence boundary, wherein the trench includes the coalescence boundary and parts of the surrounding semiconductor material of lower defect density. A trench0 diameter of at least 3 µm is typically sufficient to ensure removal ofthe coalescence boundary. The sidewalls 904 of the trench comprise etching-induced defects.2023PF01432 - 29 -LIST OF REFERENCES 1, 2 optoelectronic device3, 4 patterned dielectric mask100 growth substrate5 110, 715 growth template120 semiconductor seed layer130, 302 dielectric mask layer131,301,601 opening in dielectric mask140, 410 semiconductor stack0 141 first doped semiconductor layer142 active layer143 second doped semiconductor layer144, 201 first region of semiconductor material145, 202,602 second region of semiconductor material5 150 µLED203, 430, 904 sidewalls204 a-plane205 m-plane303 geometric centroids of dielectric mask openings0 500, 501, 502 fast-growing facet510, 511, 512 slow-growing facet603 support wings604 epitaxial growth front701 region5 702 defective region703 merging plane of growth fronts704 region711,905 etched trench712 passivated defective region0 713, 714 electrical contacts800, 801 semiconductor island802 optoelectronic device boundary803 optoelectronic device804 raster grid5 805 display carrier substrate901 coalescence boundary903 notch

Claims

2023PF01432 - 30 -CLAIMS 1. Optoelectronic device comprising:a semiconductor stack (140) comprising:5 a first doped semiconductor layer (141);an active region (142) arranged on an upper surface of the first doped semiconductor layer; a second doped semiconductor layer (143) arranged on a surface of the active region facing away from the first doped semiconductor0 layer;wherein the semiconductor stack comprises a first region (144) having a first density of crystal defects and a second region (145) having a second density of crystal lattice defects, and wherein the first density of crystal defects is greater than the5 second density of crystal defects, andwherein the first region is characterized by a substantially rectangular shape, and wherein the second region is bounded by at least three sidewalls, and0 wherein an angle between the first region and one of at leasttwo sidewalls of the at least three sidewalls of the second region is between 10° and 80°, in particular between 25° and 65°.

2. Device according to claim 1, wherein at least two adjacent sidewalls5 of the second region form an angle substantially equal to either60° or 120° with respect to each other.

3. Device according to claim 1, wherein the first region comprises alength between 1 µm and 100 µm, and a width between 0.1 µm and 100 µm.

4. Device according to any of the preceding claims, wherein the lengthof the first region is laterally oriented along the <1100> crystal direction of the semiconductor stack material. 5 5. Device according to any of the preceding claims, wherein a topsurface of the first region facing away from the growth substrate2023PF01432 - 31 -is substantially parallel to the <1010> crystal plane, i.e. the m- plane of the semiconductor stack material.

6. Device according to any of the preceding claims, wherein at least5 two sidewalls of the second region are inclined or substantiallyparallel to the (1011) crystal facet of the semiconductor stack material.

7. Optoelectronic device comprising:0 A semiconductor stack comprising:a first doped semiconductor layer; an active region arranged on an upper surface of the first doped semiconductor layer; a second doped semiconductor layer arranged on a surface of the5 active region facing away from the first doped semiconductor layer;wherein the semiconductor stack comprises a first region having a first density of crystal defects and a second region having a second density of crystal defects , and wherein the first density of crystal defects is greater than the0 second density of crystal defects , andwherein the first region is laterally surrounded by and enclosed within the second region, and wherein the second region is laterally bounded by at least three sidewalls. 5 8. Device according to claim 7, wherein the sidewalls bounding thesecond region comprise etching-induced defects.

9. Device according to any of claims 7 and 8, wherein at least one of0 the sidewalls bounding the second region is oriented along adirection substantially parallel to the <1100> crystal direction of the semiconductor stack material. 10.Device according to any of the preceding claims, wherein the5 sidewalls of the second region are laterally displaced from thefirst region.2023PF01432 - 32 -11.Device according to any of the preceding claims, further comprising at least one electrically conductive contact arranged on a surface of at least one of the doped semiconductor layers facing away from the active region. 5 12.Device according to claim 11, wherein the at least one electrically conductive contact extends laterally to cover at least portions of the first region and the second region of the semiconductor stack.0 13.Device according to any of the above claims wherein at least one ofthe at least three sidewalls bounding the second region partially extends laterally through the first region. 14.Device according to any of the above claims wherein the sidewalls5 bounding the second region are laterally substantially equidistantfrom the first region. 15.Device according to any of the preceding claims wherein the density of crystal defects in the first region is greater than the density0 of crystal defects in the second region by an order of magnitudebetween 102and 105< / sup>. 16.Light emitter array device comprising a plurality of optoelectronic devices according to any of the preceding claims. 5 17.Device according to claim 16 wherein the lateral displacement between the geometric centres of adjacent optoelectronic devices along two mutually perpendicular axes is substantially equal.0 18.Device according to any of claims 16 and 17 wherein each of theplurality of optoelectronic devices is separated from adjacent optoelectronic devices by passivated semiconductor material having a density of crystal defects equal to or greater than the first density of crystal defects. 5 19.Device according to any of claims 16 and 17 wherein each of the plurality of optoelectronic devices is bounded by sidewalls comprising etching-induced defects.2023PF01432 - 33 -20.Method of processing an optoelectronic device comprising the steps: Providing a growth template, wherein the growth template comprises: a growth substrate;5 a plurality of laterally separated first regions of semiconductormaterial having a first density of crystal defects and a plurality of second regions of semiconductor having a second density of crystal defects, and wherein each of the plurality of first regions of semiconductor0 material is at least laterally surrounded by at least one of theplurality of second regions of semiconductor material, and wherein the first density of crystal defects is greater than the second density of crystal defects; Depositing a semiconductor stack on an upper surface of the growth5 template.21.Method according to claim 20 wherein the step of depositing a semiconductor stack comprises the steps: Depositing a first doped semiconductor layer on an upper surface0 of the growth template farthest away from the growth substrate;Depositing an active layer on a surface of the first doped semiconductor layer facing away from the growth substrate; Depositing a second doped semiconductor layer on a surface of the active layer facing away from the growth substrate. 5 22.Method according to claim 20, wherein the step of providing a growth template comprises the steps: Providing a growth substrate; Depositing a first semiconductor layer on an upper surface of the0 growth substrate;Arranging a structured dielectric mask layer on a surface of the first semiconductor layer facing away from the growth substrate, wherein the structured dielectric mask layer comprises a plurality of substantially rectangular openings, and5 wherein a pattern formed by the plurality of openings comprisespluralities of openings along at least two lateral axes, and wherein the geometric centroid of each of the plurality of openings is laterally translated along two mutually perpendicular axes with2023PF01432 - 34 -respect to the geometric centroids of at least two of the plurality of openings positioned laterally adjacent to it; Growing a second semiconductor layer on exposed surfaces of the first semiconductor layer facing away from the growth substrate5 forming a plurality of first regions positioned vertically abovethe opening in the dielectric mask layer, and a plurality of second regions laterally adjacent to the plurality of first regions, wherein a lower surface of the plurality of second regions closest to the growth substrate faces an upper surface of the dielectric0 mask layer facing away from the growth substrate, andwherein the plurality of first regions is characterized by a first density of crystal defects defects, and wherein the plurality of second regions is characterized by a second density of crystal defects. 5 23.Method according to claim 22 wherein the first and second semiconductor layers comprise substantially the same material. 24.Method according to claim 20, wherein the step of providing a growth0 template comprises the steps:Providing a growth substrate; Depositing a first semiconductor layer on an upper surface of the growth substrate; Arranging a patterned dielectric mask layer on an upper surface of5 the growth substrate, wherein the patterned dielectric mask layercomprises a plurality of substantially rectangular regions of dielectric material covering substantially rectangular portions of the first semiconductor layer, and wherein a pattern formed by the plurality of substantially0 rectangular regions of dielectric material comprises pluralities ofrectangular regions along at least two lateral axes, and wherein the geometric centroid of each of the plurality of rectangular regions is laterally translated along two mutually perpendicular axes with respect to the geometric centroids of each5 of the plurality of rectangular regions positioned laterallyadjacent to it;2023PF01432 - 35 -Etching through the first semiconductor layer and at least partially through the growth substrate to form a plurality of substantially rectangular protrusions laterally bounded by substantially vertical sidewalls, wherein the plurality of5 protrusions forms a plurality of first regions of the firstsemiconductor layer, and wherein the plurality of first regions is characterized by a first density of crystal defects; Further growing the first semiconductor layer from the sidewalls0 of the plurality of protrusions to laterally extend the firstsemiconductor layer, forming a plurality of second regions of the first semiconductor layer surrounding the plurality of first regions at least laterally, wherein the plurality of second regions is characterized by a second density of crystal defects. 5 25.Method according to claim 24 further comprising a step of removing the dielectric mask layer, wherein the removal of the dielectric mask layer is performed either: prior to the step of further growing the first semiconductor0 layer from the sidewalls of the plurality of protrusions, orafter the step of further growing the first semiconductor layer from the sidewalls of the plurality of protrusions. 26.Method according to any of the preceding claims wherein at least5 some of the plurality of first regions are characterized by a lengthbetween 1 µm and 200 µm, and in particular between 1 µm and 100 µm and a width between 0.1 µm and 20 µm, and in particular between 0.1 µm and 10 µm.0 27.Method according to any of the preceding claims wherein at leastsome of the plurality of first regions are aligned along a direction corresponding to the <1100> crystal direction of the semiconductor material.5 28.Method according to any of the preceding claims wherein a lateralseparation distance between adjacent first regions along a direction perpendicular to the length of the adjacent first regions is about 1.3 times the length of the first regions.2023PF01432 - 36 -29.Method according to any of the preceding claims wherein the plurality of first regions forms a lattice of polygons comprising interior angles substantially equal to either 60° or 120°.5 30.Method according to any of the preceding claims wherein each of theplurality of second regions is laterally isolated from adjacent second regions. 31.Method according to any of the preceding claims wherein each of the0 plurality of second regions is laterally in contact with at leastone adjacent second region, and wherein a plurality of boundary regions is formed along planes of contact between adjacent second regions, and wherein the plurality of boundary regions is characterised by a5 density of crystal defects greater than the second density ofcrystal defects. 32.Method according to any of the preceding claims further comprising the steps:0 Etching through the first region of the semiconductor stack;Removing the growth substrate and, optionally, at least portions of the dielectric mask layer, and, optionally, at least portions of the first semiconductor layer; Depositing at least one electrically conductive contact on at5 least one surface of at least one doped semiconductor layer facingaway from the active layer. 33.Method according to any of the preceding claims further comprising the steps:0 Etching or cutting through the semiconductor stack along aplurality of parallel planes perpendicular to the direction of orientation of the lengths of the first regions, wherein each parallel plane comprises both first regions and second regions of the semiconductor layers;5 Removing the growth substrate and, optionally, at least portionsof the dielectric mask layer and, optionally, at least portions of the first semiconductor layer;2023PF01432 - 37 -Depositing at least one electrically conductive contact on at least one surface of at least one doped semiconductor layer facing away from the active layer.5 34.Method according to any of the preceding claims 30 and 31, furthercomprising structuring of the semiconductor mesa sidewalls. 35.Method according to any of the preceding claims 30 to 32 wherein the at least one electrically conductive contact is deposited to0 laterally cover at least portions of upper surfaces of the firstregion and the second region of the semiconductor stack facing away from the active layer. 36.Method according to any of the preceding claims wherein the density5 of crystal defects in the first region is greater than the densityof crystal defects in the second region by an order of magnitude between 102and 105< / sup>. 0

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