ESD protection device and microprocessor chip

Abstract

The present application provides an ESD protection device and a microprocessor chip. The ESD protection device comprises: an A-conductivity type substrate; a B-conductivity type deep well region; an A-conductivity type well region, a first B-conductivity type doped region, a second B-conductivity type doped region, and a third A-conductivity type doped region being arranged in the A-conductivity type well region; and a B-conductivity type well region, a first A-conductivity type doped region, a second A-conductivity type doped region, and a third B-conductivity type doped region being arranged in the B-conductivity type well region, wherein the first B-conductivity type doped region, the first A-conductivity type doped region, the second A-conductivity type doped region, and the second B-conductivity type doped region extend in a second direction, respectively; and the third A-conductivity type doped region and / or the third B-conductivity type doped region extend in a first direction. In embodiments of the present application, a simple and compact layout design mode is used to realize bidirectional ESD protection between two ports, and the present application is applicable to the whole chip.

Description

ESD protection device and micro processing chip

[0001] The present application claims priority to the Chinese patent application No. 202410544398.9, filed on April 30, 2024, and entitled "ESD protection device and micro processing chip", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of electronic technology, in particular to an ESD protection device and a micro processing chip. BACKGROUND

[0003] Electro Static Discharge (ESD) phenomenon refers to the phenomenon of charge transfer when objects with different potentials are close to or in contact with each other. Due to the extremely short discharge time, a large current is generated during the discharge process. For integrated circuits, modern chips are more susceptible to damage caused by ESD. This large current can damage or even burn internal devices, leading to chip failure. ESD phenomenon may occur at various stages of chip production, transportation and use, so ESD protection measures are indispensable for the reliability of the chip.

[0004] Direct Connected Silicon Controlled Rectifier (DCSCR) is a kind of SCR device triggered by diode string, which has many advantages such as small resistance and high robustness. At the same time, DCSCR can also adjust the trigger voltage by device stacking to meet the needs of different design windows, and is widely used in ESD protection under advanced process.

[0005] However, the DCSCR device in the prior art at least has the following problems when used for ESD protection: 1. The layout is not compact enough, resulting in a large layout area; 2. It can only be used for static protection in one direction (from anode to cathode) between two ports, and is not suitable for full chip.

[0006] It should be noted that the information disclosed in the background section of the present application is only intended to deepen the understanding of the general background of the present application, and should not be regarded as acknowledging or implying in any form that the information constitutes prior art known to those skilled in the art. SUMMARY

[0007] The present application provides an ESD protection device and a micro processing chip to solve the problems of the prior art that the ESD protection device layout is not compact enough, resulting in a large layout area, and can only be used for static protection in one direction between two ports, which is not suitable for full chip.

[0008] In a first aspect, the embodiments of the present application provide an ESD protection device, comprising:

[0009] An A-conductivity type substrate;

[0010] A B-conductivity type deep well region, which is arranged in the A-conductivity type substrate;

[0011] An A-conductivity type well region, which is arranged in the B-conductivity type deep well region, and the A-conductivity type well region is provided with a first B-conductivity type doped region, a second B-conductivity type doped region and a third A-conductivity type doped region;

[0012] A B-conductivity type well region, which is arranged in the B-conductivity type deep well region, and the B-conductivity type well region is provided with a first A-conductivity type doped region, a second A-conductivity type doped region and a third B-conductivity type doped region;

[0013] The first B-conductivity type doped region, the first A-conductivity type doped region, the second A-conductivity type doped region and the second B-conductivity type doped region are arranged along a first direction in sequence, and respectively extend along a second direction, and the first direction and the second direction are perpendicular;

[0014] The third A-conductivity type doped region and / or the third B-conductivity type doped region extend along the first direction, and the third A-conductivity type doped region and the third B-conductivity type doped region are connected by a metal wire.

[0015] In a possible implementation, the third A-conductivity type doped region and / or the third B-conductivity type doped region extend along the first direction, and specifically includes:

[0016] The third A-conductivity type doped region extends along the first direction, and the third A-conductivity type doped region is arranged at a first end of the first B-conductivity type doped region, the first A-conductivity type doped region, the second A-conductivity type doped region and the second B-conductivity type doped region;

[0017] The third B-conductivity type doped region extends along the first direction, and the third B-conductivity type doped region is arranged at a second end of the first B-conductivity type doped region, the first A-conductivity type doped region, the second A-conductivity type doped region and the second B-conductivity type doped region.

[0018] In a possible implementation, the third A-conductivity type doped region further includes:

[0019] The first branch region extends along the second direction and is arranged on a side of the first B-type doped region away from the first A-type doped region.

[0020] The second branch region extends along the second direction and is arranged on a side of the second B-type doped region away from the second A-type doped region.

[0021] In a possible implementation, the third B-type doped region further includes:

[0022] The third branch region extends along the second direction and is arranged between the first A-type doped region and the second A-type doped region.

[0023] In a possible implementation, the third A-type doped region and / or the third B-type doped region extends along the first direction, specifically including:

[0024] The third A-type doped region extends along the second direction, and the third B-type doped region extends along the first direction.

[0025] In a possible implementation, the third A-type doped region includes:

[0026] The first A-type doped sub-region is arranged on a side of the first B-type doped region away from the first A-type doped region.

[0027] The second A-type doped sub-region is arranged on a side of the second B-type doped region away from the second A-type doped region.

[0028] In a possible implementation, the third B-type doped region includes:

[0029] The first B-type doped sub-region is arranged at a first end of the first B-type doped region, the first A-type doped region, the second A-type doped region, and the second B-type doped region.

[0030] The second B-type doped sub-region is arranged at a second end of the first B-type doped region, the first A-type doped region, the second A-type doped region, and the second B-type doped region.

[0031] In a possible implementation, the third B-type doped region further includes:

[0032] a third B-conductivity-type doped sub-region, which is connected between the first B-conductivity-type doped sub-region and the second B-conductivity-type doped sub-region, extends along the second direction, and is arranged between the first A-conductivity-type doped region and the second A-conductivity-type doped region.

[0033] In a possible implementation, the third A-conductivity-type doped region and / or the third B-conductivity-type doped region extends along the first direction, and specifically includes:

[0034] The third A-conductivity-type doped region extends along the first direction, and the third B-conductivity-type doped region extends along the second direction.

[0035] In a possible implementation, the A-conductivity-type is P-type, and the B-conductivity-type is N-type.

[0036] Alternatively, the A-conductivity-type is N-type, and the B-conductivity-type is P-type.

[0037] In a second aspect, an embodiment of the present application provides a micro-processing chip, including the ESD protection device of any one of the first aspect.

[0038] In the embodiment of the present application, a simple and compact layout mode is adopted to achieve bidirectional ESD protection between two ports, and is applicable to a full chip. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0040] FIG. 1 is a cross-sectional view of a DCSCR device provided by the related art;

[0041] FIG. 2 is a layout of a DCSCR device provided by the related art;

[0042] FIG. 3 is a cross-sectional view of an ESD protection device provided by an embodiment of the present application;

[0043] FIG. 4 is a layout of an ESD protection device provided by an embodiment of the present application;

[0044] FIG. 5 is a layout of another ESD protection device provided by an embodiment of the present application;

[0045] FIG. 6 is a layout of another ESD protection device provided by an embodiment of the present application;

[0046] Fig. 7 is a layout of another ESD protection device provided by embodiments of the present application;

[0047] Fig. 8A is a structural schematic diagram of an ESD protection circuit provided by embodiments of the present application;

[0048] Fig. 8B is a structural schematic diagram of another ESD protection circuit provided by embodiments of the present application;

[0049] Fig. 8C is a structural schematic diagram of another ESD protection circuit provided by embodiments of the present application;

[0050] Fig. 9 is a structural schematic diagram of an ESD circuit device provided by embodiments of the present application;

[0051] Fig. 10 is a structural schematic diagram of a micro-processing chip provided by embodiments of the present application;

[0052] Fig. 11 is a structural schematic diagram of another micro-processing chip provided by embodiments of the present application. DETAILED DESCRIPTION

[0053] In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the drawings.

[0054] It should be clear that the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0055] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0056] It should be understood that the term "and / or" used herein is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0057] In order to facilitate understanding, the acronyms involved in the present application are described first as follows.

[0058] ESD: Electro Static Discharge, electrostatic discharge;

[0059] DCSCR: Direct Connected Silicon Controlled Rectifier, diode direct connection trigger thyristor

[0060] N-type: doping donor impurities in a semiconductor to obtain an N-type semiconductor, in which the number of electrons is greater than the number of holes;

[0061] P-type: doping acceptor impurities in a semiconductor to obtain a P-type semiconductor, in which the number of holes is greater than the number of electrons;

[0062] A conduction type: N-type or P-type, and different from the B conduction type;

[0063] B conduction type: N-type or P-type, and different from the A conduction type;

[0064] Psub: P-type substrate;

[0065] NWell / NW: N-type well region, which can also be referred to as "N well" for short;

[0066] PWell / PW: P-type well region, which can also be referred to as "P well" for short;

[0067] DNWell / DNW: N-type deep well region, which can also be referred to as "deep N well" for short;

[0068] N+ / NPLUS: N-type doped region;

[0069] P+ / PPLUS: P-type doped region.

[0070] ESD phenomenon refers to the charge transfer phenomenon that occurs when objects with different potentials are close to or in contact with each other. Due to the extremely short discharge time, a large current is generated during the discharge process. For integrated circuits, modern chips are more susceptible to damage caused by ESD. This large current can damage or even burn internal devices, leading to chip failure. Electrostatic discharge phenomena can occur at various stages of chip production, transportation, and use. Therefore, ESD protection measures are indispensable for the reliability of chips.

[0071] DCSCR is a kind of SCR device triggered by diode string, which has many advantages such as small resistance, high robustness, etc. At the same time, DCSCR can also adjust the trigger voltage by device stacking to meet the needs of different design windows, and is widely used in ESD protection under advanced process. DCSCR device is equivalent to two series diodes, which can be used in ESD protection network instead of diodes. The trigger voltage of DCSCR is only about 1.4V, which is the lowest opening voltage that SCR type device can achieve on silicon process, and is very suitable for the most advanced low voltage ESD window (such as 0.8V circuit under 14nm FinFET process); for the relatively high working voltage in traditional planar CMOS process, DCSCR can be used in a flexible way to meet the needs of the stacked structure, and can also replace the diode device of I / O port in the full chip ESD protection architecture based on power rail, to achieve better parasitic capacitance characteristics; on the other hand, in DCSCR, the two transistors of the SCR structure are both on the auxiliary trigger path, so their charging time (i.e. Tcharge) is very fast, which makes DCSCR have the advantage of fast conduction speed.

[0072] Referring to FIG. 1, a cross-sectional view of a DCSCR device provided by the related art is shown; referring to FIG. 2, a layout of the DCSCR device provided by the related art is shown. For ease of illustration, a first direction X and a second direction Y perpendicular to each other are defined on the layout, wherein the first direction X and the second direction Y are perpendicular to each other.

[0073] As shown in FIG. 1 and in combination with FIG. 2, the DCSCR device includes a P-type substrate Psub, an N-type deep well region DNW is provided on the P-type substrate Psub, an N-type well region NWell (may also be referred to as “N well” in other parts of this document) and a P-type well region PWell (may also be referred to as “P well” in other parts of this document) are provided in the N-type deep well region DNW. Among them, an N-type doped region 111 and a P-type doped region 121 are provided in the N-type well region NWell, and an N-type doped region 112 and a P-type doped region 122 are provided in the P-type well region PWell. Among them, the N-type doped region 111, the P-type doped region 121, the N-type doped region 112 and the P-type doped region 122 are arranged along the first direction X in turn, and respectively extend along the second direction Y. In addition, the N-type doped region 111 in the N-type well region NWell and the P-type doped region 122 in the P-type well region PWell are connected by metal. The P-type doped region 121 is used to connect the anode, and the N-type doped region 112 is used to connect the cathode.

[0074] Based on the structure of the DCSCR device, a diode D11 is formed between the N-type doped region 111 and the P-type doped region 121, and a diode D12 is formed between the N-type doped region 112 and the P-type doped region 122. When the voltage between the anode and the cathode meets a preset condition, current can be discharged from the anode to the cathode along the current discharge path, thereby achieving ESD protection.

[0075] However, the DCSCR device has at least the following problems: 1. The layout is not compact enough, resulting in a large layout area; 2. It can only be used for static protection in one direction between two ports (current discharge can only be performed from the anode to the cathode, and cannot be performed from the cathode to the anode), and is not suitable for full-chip applications.

[0076] Based on the above problems, an ESD protection device is provided in the embodiments of the present application, which adopts a simple and compact layout arrangement and achieves bidirectional ESD protection between two ports, and is suitable for full-chip applications. Details will be described below in conjunction with specific implementation manners.

[0077] Referring to FIG. 3, it is a cross-sectional view of an ESD protection device provided in the embodiments of the present application; and referring to FIG. 4, it is a layout of an ESD protection device provided in the embodiments of the present application. For ease of description, a first direction X and a second direction Y perpendicular to each other are defined on the layout, wherein the first direction X and the second direction Y are perpendicular to each other.

[0078] As shown in FIG. 3 and in conjunction with FIG. 4, the ESD protection device includes a P-type substrate Psub, an N-type deep well region DNW is provided on the P-type substrate Psub, and a P-type well region PWell and an N-type well region NWell are provided in the N-type deep well region DNW. A first N-type doped region 211, a second N-type doped region 212 and a third P-type doped region 223 are provided in the P-type well region NWell; and a first P-type doped region 221, a second P-type doped region 222 and a third N-type doped region 213 are provided in the N-type well region NWell. The first N-type doped region 211, the first P-type doped region 221, the second P-type doped region 222 and the second N-type doped region 212 are arranged in sequence along the first direction and extend along the second direction respectively. The third P-type doped region 223 and the third N-type doped region 213 extend along the first direction respectively and are located at two ends of the "first N-type doped region 211, first P-type doped region 221, second P-type doped region 222 and second N-type doped region 212". Specifically, the third P-type doped region 223 is located at a first end (lower end in the orientation shown in FIG. 4) of the "first N-type doped region 211, first P-type doped region 221, second P-type doped region 222 and second N-type doped region 212"; and the third N-type doped region 213 is located at a second end (upper end in the orientation shown in FIG. 4) of the "first N-type doped region 211, first P-type doped region 221, second P-type doped region 222 and second N-type doped region 212".

[0079] In addition, the third P-type doped region 223 and the third N-type doped region 213 are connected by a metal. The first N-type doped region 211 and the second P-type doped region 222 are used to connect the IO port, the first P-type doped region 221 is used to connect the second level port VSS, and the second N-type doped region 212 is used to connect the first level port VDD.

[0080] Based on the above structure of the ESD device, a first diode D21 and a second diode D22 are formed between the first N-type doped region 211 and the first P-type doped region 221, i.e., a current discharge path between the first N-type doped region 211 and the first P-type doped region 221. A third diode D23 and a fourth diode D24 are formed between the second P-type doped region 222 and the second N-type doped region 212, i.e., a current discharge path between the second P-type doped region 222 and the second N-type doped region 212. When there is no ESD event on the IO port, the voltage of the IO port is usually less than the voltage of the first level port VDD and greater than the voltage of the second level port VSS. In this state, the first diode D21, the second diode D22, the third diode D23, and the fourth diode D24 are all in a reverse blocking state, so that the ESD protection device does not generate a leakage current, thereby not interfering with the normal working circuit. When there is a positive ESD event (possibly due to static charge accumulation caused by external contact or coupling) on the IO port, the voltage of the IO port is usually greater than the voltage of the first level port VDD and the second level port VSS. In this state, the first diode D21 and the second diode D22 are reversely broken down, while the third diode D23 and the fourth diode D24 are in a forward bias state, so that the current caused by the positive ESD event can be discharged to the first level port VDD and / or the second level port VSS through the current discharge path shown in FIG. 3. When there is a negative ESD event on the IO port, the voltage of the IO port is usually less than the voltage of the first level port VDD and the second level port VSS. In this state, the first diode D21 and the second diode D22 are in a forward bias state, while the third diode D23 and the fourth diode D24 are reversely broken down, so that the current caused by the negative ESD event can be discharged to the first level port VDD and / or the second level port VSS through the current discharge path shown in FIG. 3. Based on the same principle, when there is an ESD event on the first level VSS port or the second level VDD port, the current can also be discharged to the IO port through the current discharge path shown in FIG. 3. That is, the ESD protection device provided in the embodiments of the present application can realize bidirectional ESD protection between two ports.

[0081] Please continue to refer to FIG. 4, since, in the present application, in addition to the first N-type doped region 211, the first P-type doped region 221, the second P-type doped region 222 and the second N-type doped region 212 extending along the second direction, there are also the third P-type doped region 223 and the third N-type doped region 213 extending along the first direction, so that the overall layout of the ESD protection device is more compact, and thus the area of the layout can be reduced.

[0082] Referring to FIG. 5, the layout of another ESD protection device provided by an embodiment of the present application is shown. The embodiment of the present application is different from the embodiment shown in FIG. 4 in that the third P-type doped region 223 further includes a first branch region 2231 and a second branch region 2232. The first branch region 2231 extends along the second direction and is arranged on the side of the first N-type doped region 211 away from the first P-type doped region 221, i.e., the first branch region 2231 is arranged on the left side of the first N-type doped region 211. The second branch region 2232 extends along the second direction and is arranged on the side of the second N-type doped region 212 away from the second P-type doped region 222, i.e., the second branch region 2232 is arranged on the right side of the second N-type doped region 212. The third N-type doped region 213 further includes a third branch region 2131, which extends along the second direction and is arranged between the first P-type doped region 221 and the second P-type doped region 222.

[0083] It can be understood that, when the third P-type doped region 223 further includes the first branch region 2231 and the second branch region 2232, the free ends (upper ends in the orientation shown in FIG. 5) of the first branch region 2231 and the second branch region 2232 are closer to the third N-type doped region 213, so that the side of the third N-type doped region 213 close to the first branch region 2231 can be connected to the free end of the first branch region 2231 by metal, and the side of the third N-type doped region 213 close to the second branch region 2232 can be connected to the free end of the second branch region 2232 by metal, so as to realize the connection between the third N-type doped region 213 and the third P-type doped region 223. It should be noted that the layout shown in FIG. 5 is only an exemplary illustration provided by an embodiment of the present application. One skilled in the art can also arrange only one branch region or two branch regions among the first branch region 2231, the second branch region 2232 and the third branch region 2131 according to actual needs, and the present application does not specifically limit this.

[0084] In the embodiments of the present application, the layout of the ESD protection device is more compact, there are more contact points between elements, the connection is more compact, and at the same time, the triggering capability of the diode is stronger, and the reverse breakdown voltage bearing capacity is enhanced.

[0085] It can be understood that in the implementation shown in FIG. 4 and FIG. 5, the third N-type doped region 213 and the third P-type doped region 223 both extend along the first direction. In a possible implementation, one of the third N-type doped region 213 and the third P-type doped region 223 can be arranged to extend along the first direction, and the other can be arranged to extend along the second direction. For example, the third N-type doped region 213 extends along the first direction, and the third P-type doped region 223 extends along the second direction; or, the third P-type doped region 223 extends along the first direction, and the third N-type doped region 213 extends along the second direction. Details are described below in combination with specific embodiments.

[0086] Referring to FIG. 6, a layout of another ESD protection device provided by an embodiment of the present application is shown. The embodiment of the present application is different from the embodiment shown in FIG. 4 in that the third P-type doped region 223 includes a first P-type sub-doped region 2233 and a second P-type sub-doped region 2234, and the first P-type sub-doped region 2233 and the second P-type sub-doped region 2234 extend along the second direction respectively. The first P-type sub-doped region 2233 is arranged on the side of the first N-type doped region 211 away from the first P-type doped region 221, i.e., the first P-type sub-doped region 2233 is arranged on the left side of the first N-type doped region 211. The second P-type sub-doped region 2234 is arranged on the side of the second N-type doped region 212 away from the second P-type doped region 222, i.e., the second P-type sub-doped region 2234 is arranged on the right side of the second N-type doped region 212.

[0087] The third N-type doped region 213 includes a first N-type sub-doped region 2132 and a second N-type sub-doped region 2133, and the first N-type sub-doped region 2132 and the second N-type sub-doped region 2133 extend along the first direction respectively and are located at two ends of the "first N-type doped region 211, first P-type doped region 221, second P-type doped region 222 and second N-type doped region 212". Specifically, the first N-type sub-doped region 2132 is located at the first end (lower end in the orientation shown in FIG. 6) of the "first N-type doped region 211, first P-type doped region 221, second P-type doped region 222 and second N-type doped region 212"; and the second N-type sub-doped region 2133 is located at the second end (upper end in the orientation shown in FIG. 6) of the "first N-type doped region 211, first P-type doped region 221, second P-type doped region 222 and second N-type doped region 212".

[0088] Furthermore, the two ends of the first N-type doped sub-region 2132 are respectively connected to the first ends (lower ends in the orientation shown in FIG6) of the first P-type doped sub-region 2233 and the second P-type doped sub-region 2234 through metal connections; the two ends of the second N-type doped sub-region 2133 are respectively connected to the second ends (upper ends in the orientation shown in FIG6) of the first P-type doped sub-region 2233 and the second P-type doped sub-region 2234 through metal connections, thereby realizing the electrical connection between the third N-type doped region 213 and the third P-type doped region 223.

[0089] It should be noted that in some possible implementations, the first P-type doped sub-region 2233 and the second P-type doped sub-region 2234 can be configured to extend along a first direction, and the first N-type doped sub-region 2132 and the second N-type doped sub-region 2133 can be configured to extend along a second direction. This application embodiment does not limit this.

[0090] In the embodiments of this application, the layout of the ESD protection device can achieve simultaneous discharge triggered from both the top and bottom, and can respond quickly when subjected to an ESD event, thereby improving the discharge efficiency.

[0091] Referring to Figure 7, which shows a layout of another ESD protection device provided in an embodiment of this application. The difference between this embodiment and the embodiment shown in Figure 6 is that the ESD protection device further includes a third N-type doped sub-region 2134. The third N-type doped sub-region 2134 is connected between the first N-type doped sub-region 2132 and the second N-type doped sub-region 2133, extends along a second direction, and is disposed between the first P-type doped region 221 and the second P-type doped region 222. It can be understood that after the third N-type doped sub-region 2134 is provided, the shape of the third N-type doped region 213, composed of the first N-type doped sub-region 2132, the second N-type doped region 2133, and the third N-type doped region 2134, is "I"-shaped.

[0092] It should be noted that, compared with the layout design scheme in Figure 4, the layout design schemes in Figures 5-7 can enable the diodes in the ESD protection device to have a lower trigger voltage and a faster response speed, thereby improving the ESD protection performance of the ESD protection device.

[0093] In addition, the P-type and the N-type in each part of the ESD protection device in the above embodiments can be interchanged. In general, the ESD protection device comprises: an A-conductivity-type substrate; a B-conductivity-type deep well region, which is arranged in the A-conductivity-type substrate; an A-conductivity-type well region, which is arranged in the B-conductivity-type deep well region, and the A-conductivity-type well region is provided with a first B-conductivity-type doped region, a second B-conductivity-type doped region and a third A-conductivity-type doped region; a B-conductivity-type well region, which is arranged in the B-conductivity-type deep well region, and the B-conductivity-type well region is provided with a first A-conductivity-type doped region, a second A-conductivity-type doped region and a third B-conductivity-type doped region; the first B-conductivity-type doped region, the first A-conductivity-type doped region, the second A-conductivity-type doped region and the second B-conductivity-type doped region are arranged in a first direction in sequence and extend in a second direction respectively, and the first direction and the second direction are perpendicular; the third A-conductivity-type doped region and / or the third B-conductivity-type doped region extend in the first direction, and the third A-conductivity-type doped region and the third B-conductivity-type doped region are connected by a metal wire.

[0094] In the above embodiments, the A-conductivity-type is P-type and the B-conductivity-type is N-type. In a specific implementation, the A-conductivity-type can be N-type and the B-conductivity-type can be P-type, and the specific content can be referred to the description of the above embodiments, which will not be described herein for the sake of brevity.

[0095] Corresponding to the above embodiments, the embodiments of the present application further provide an ESD circuit for full-chip protection.

[0096] Referring to FIG. 8A, a structural diagram of an ESD circuit for full-chip protection is provided in an embodiment of the present application. As shown in FIG. 8A, the ESD circuit includes an ESD protection device and an RC detection module. The ESD protection device includes a first DCSCR device and a second DCSCR device. A first end of the first DCSCR device is configured to be connected to a first voltage level port VDD, and a second end of the first DCSCR device is configured to be connected to an IO port. The first DCSCR device is configured to discharge current of the first voltage level port VDD to the IO port when an ESD event occurs at the first voltage level port VDD, or discharge current of the IO port to the first voltage level port VDD when an ESD event occurs at the IO port. That is, the first DCSCR device can realize bidirectional ESD protection between the first voltage level port VDD and the IO port, thereby protecting internal circuits. A first end of the second DCSCR device is configured to be connected to a second voltage level port VSS, and a second end of the second DCSCR device is configured to be connected to the IO port. The second DCSCR device is configured to discharge current of the second voltage level port VSS to the IO port when an ESD event occurs at the second voltage level port VSS, or discharge current of the IO port to the second voltage level port VSS when an ESD event occurs at the IO port. That is, the second DCSCR device can realize bidirectional ESD protection between the second voltage level port VSS and the IO port, thereby protecting internal circuits.

[0097] The RC detection module includes a first transistor Mesd and a control circuit. A drain of the first transistor Mesd is configured to be connected to the first voltage level port VDD, and a source of the first transistor Mesd is configured to be connected to the second voltage level port VSS. A first end of the control circuit is configured to be connected to the first voltage level port VDD, a second end of the control circuit is configured to be connected to the second voltage level port VSS, and a third end of the control circuit is electrically connected to a gate of the first transistor Mesd. The control circuit is configured to:

[0098] When an ESD event occurs at the first voltage level port VDD or the second voltage level port VSS, the control circuit controls the first transistor Mesd to be turned on; and when no ESD event occurs at the first voltage level port VDD and the second voltage level port VSS, the control circuit controls the first transistor Mesd to be turned off. In a specific implementation, the first transistor Mesd is a PMOS transistor or an NMOS transistor. It can be understood that when an ESD event occurs, the first transistor Mesd is turned on, thereby discharging current of the first voltage level port VDD to the second voltage level port VSS or discharging current of the second voltage level port VSS to the first voltage level port VDD, realizing bidirectional ESD protection between the first voltage level port VDD and the second voltage level port VSS, and protecting internal circuits. In addition, when no ESD event occurs, the first transistor Mesd is turned off, and the RC detection module does not generate a leakage current, thereby not interfering with the normal operation of internal circuits.

[0099] In summary, in the embodiments of the present application, when an ESD event occurs, the current between different ports can be discharged by the ESD protection device and the RC detection module at the same time, the current discharge speed is improved, and the protection effect on the internal circuit is improved. It should be pointed out that in some possible implementation manners, the ESD circuit can only include an ESD protection device, and does not include an RC detection module, and the embodiments of the present application do not make specific limitations thereto.

[0100] Please continue to refer to FIG. 8A. In a possible implementation manner, the control circuit includes an RC circuit, a second transistor Mp and a third transistor Mn. The RC circuit includes a first resistor R1 and a first capacitor C1 connected in series with each other. A first end of the RC circuit is used to connect the first voltage level port VDD, and a second end of the RC circuit is used to connect the second voltage level port VSS. Specifically, a first end of the first resistor R1 is used to connect the first voltage level port VDD, a second end of the first resistor R1 is electrically connected with a first end of the first capacitor C1, and a second end of the first capacitor C1 is used to connect the second voltage level port VSS. A gate of the second transistor Mp is electrically connected with a node between the first resistor R1 and the first capacitor C1, a source of the second transistor Mp is used to connect the first voltage level port VDD, and a drain of the second transistor Mp is electrically connected with a gate of the first transistor Mesd. A gate of the third transistor Mn is electrically connected with the node between the first resistor R1 and the first capacitor C1, a source of the third transistor Mn is used to connect the second voltage level port VSS, and a drain of the third transistor Mn is electrically connected with the gate of the first transistor Mesd. In a specific implementation, the second transistor Mp is a PMOS transistor, and the third transistor Mn is an NMOS transistor.

[0101] In the embodiment of the present application, when there is no ESD event, the first capacitor C1 is equivalent to an open circuit, the gates of the second transistor Mp and the third transistor Mn receive a high level through the first resistor R1, so that the second transistor Mp is turned off and the third transistor Mn is turned on. Further, since the second transistor Mp is turned off and the third transistor Mn is turned on, the first transistor Mesd receives a low level and is turned off. It can be understood that when the first transistor Mesd is turned off, the RC detection module does not generate a leakage current, thereby not interfering with the normal working circuit. When an ESD event occurs at the first voltage level port VDD or the second voltage level port VSS, the RC circuit composed of the first resistor R1 and the first capacitor C1 is equivalent to receiving an alternating current with a very high frequency, the first capacitor C1 is regarded as a pass, and the gates of the second transistor Mp and the third transistor Mn receive a low level, so that the second transistor Mp is turned on and the third transistor Mn is turned off. Further, since the second transistor Mp is turned on and the third transistor Mn is turned off, the first transistor Mesd receives a high level and is turned on. It can be understood that when the first transistor Mesd is turned on, the current of the first voltage level port VDD can be discharged to the second voltage level port VSS through the RC detection module, or the current of the second voltage level port VSS can be discharged to the first voltage level port VDD through the RC detection module, thereby achieving ESD protection.

[0102] Please continue to refer to FIG. 8A, in a possible implementation manner, the first DCSCR device includes a fourth transistor M4, a fifth transistor M5, a third resistor R3 (P-well resistance RPW) and a fourth resistor R4 (N-well resistance RNW). Wherein, the source of the fourth transistor M4 is used for connecting the first voltage level port VDD; the drain of the fifth transistor M5 is electrically connected with the gate of the fourth transistor M4, the gate of the fifth transistor M5 is electrically connected with the drain of the fourth transistor M4, and the source of the fifth transistor M5 is used for connecting the IO port; the first end of the third resistor R3 is connected with a node between the gate of the fourth transistor M4 and the drain of the fifth transistor M5; the first end of the fourth resistor R4 is electrically connected with the second end of the third resistor R3, and the second end of the fourth resistor R4 is connected with a node between the drain of the fourth transistor M4 and the gate of the fifth transistor M5. In a specific implementation, the fourth transistor M4 is an NMOS tube, and the fifth transistor M5 is a PMOS tube.

[0103] In a possible implementation, the second DCSCR device includes a sixth transistor M6, a seventh transistor M7, a fifth resistor R5 (P-well resistor RPW) and a sixth resistor R6 (N-well resistor RNW). The source of the sixth transistor M6 is configured to be connected to the IO port; the drain of the seventh transistor M7 is electrically connected to the gate of the sixth transistor M6, the gate of the seventh transistor M7 is electrically connected to the drain of the sixth transistor M6, and the source of the seventh transistor M7 is configured to be connected to the second voltage level port VSS; the first end of the fifth resistor R5 is connected to a node between the gate of the sixth transistor M6 and the drain of the seventh transistor M7; the first end of the sixth resistor R6 is electrically connected to the second end of the fifth resistor R5, and the second end of the sixth resistor R6 is connected to a node between the drain of the sixth transistor M6 and the gate of the seventh transistor M7. In a specific implementation, the sixth transistor M6 is an NMOS transistor, and the seventh transistor M7 is a PMOS transistor.

[0104] It should be noted that FIG. 8A is only an exemplary description of the ESD circuit in the embodiments of the present application, and those skilled in the art can add devices or adjust the connection relationship of each device on the basis of FIG. 8A to achieve the same or similar functions according to actual needs, which should all fall within the protection scope of the present application.

[0105] For example, the connection order of the first resistor R1 and the first capacitor C1 can be adjusted, that is, the first end of the first capacitor C1 is configured to be connected to the first voltage level port VDD, the second end of the first capacitor C1 is electrically connected to the first end of the first resistor R1, and the second end of the first resistor R1 is configured to be connected to the second voltage level port VSS, as shown in FIG. 8B.

[0106] For example, a resistor in series with the first transistor Mesd is added. Specifically, the second resistor R2 is connected in series between the second voltage level port VSS and the source of the first transistor Mesd, as shown in FIG. 8C. Of course, the second resistor R2 can also be connected in series between the first voltage level port VDD and the drain of the first transistor Mesd, which is not limited in the embodiments of the present application.

[0107] It should be noted that the layout design of the ESD protection device in the ESD circuit can refer to the description above, and for the sake of brevity, it will not be described again in the ESD circuit part.

[0108] Corresponding to the above embodiments, the embodiments of the present application also provide an ESD circuit device for full-chip protection.

[0109] Referring to FIG. 9, a structural schematic diagram of an ESD circuit device for full-chip protection provided by an embodiment of the present application is shown. As shown in FIG. 9, the ESD circuit device includes an ESD circuit, which is the ESD circuit described in the above embodiments. The specific content of the ESD circuit can be referred to the description in the above embodiments, and will not be repeated here for the sake of brevity.

[0110] Corresponding to the above embodiments, the present application further provides a micro processing chip.

[0111] Referring to FIG. 10, a structural schematic diagram of a micro processing chip provided by an embodiment of the present application is shown. As shown in FIG. 10, the micro processing chip includes an ESD protection device, which is the ESD protection device described in the above embodiments. The ESD protection device can realize full-chip ESD protection for the micro processing chip.

[0112] It should be noted that the micro processing chip can be an MCU, a DSP, an MPU, a micro CPU, or other micro central control chips or system-on-chip that can process digital signals, analog signals, or perform signal control functions, instruction processing and operation functions.

[0113] The specific content of the ESD protection device can be referred to the description in the above embodiments, and will not be repeated here for the sake of brevity.

[0114] Corresponding to the above embodiments, the present application further provides another micro processing chip.

[0115] Referring to FIG. 11, a structural schematic diagram of another micro processing chip provided by an embodiment of the present application is shown. As shown in FIG. 11, the micro processing chip includes an ESD circuit, which is the ESD circuit described in the above embodiments. The ESD circuit can realize full-chip ESD protection for the micro processing chip.

[0116] It should be noted that the micro processing chip can be an MCU, a DSP, an MPU, a micro CPU, or other micro central control chips or system-on-chip that can process digital signals, analog signals, or perform signal control functions, instruction processing and operation functions.

[0117] The specific content of the ESD circuit can be referred to the description in the above embodiments, and will not be repeated here for the sake of brevity.

[0118] In the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the cases of A alone, A and B together, and B alone. Wherein A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects. "At least one of the following" and the like means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b and c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

[0119] Those skilled in the art can appreciate that the units and algorithm steps described in the embodiments disclosed herein can be realized by electronic hardware, computer software and combination of electronic hardware and computer software. Whether the functions are realized in hardware or software mode depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0120] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0121] In several embodiments provided by the present application, any function realized in the form of a software function unit and sold or used as an independent product can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the parts that make contributions to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0122] The above is merely specific implementation of the present application, and any skilled person in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. The protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An ESD protection device, characterized by, Comprising: An A-conductivity type substrate; A B-conductivity type deep well region, which is arranged in the A-conductivity type substrate; An A-conductivity type well region, which is arranged in the B-conductivity type deep well region, and which is provided with a first B-conductivity type doped region, a second B-conductivity type doped region and a third A-conductivity type doped region; A B-conductivity type well region, which is arranged in the B-conductivity type deep well region, and which is provided with a first A-conductivity type doped region, a second A-conductivity type doped region and a third B-conductivity type doped region; The first B-conductivity type doped region, the first A-conductivity type doped region, the second A-conductivity type doped region and the second B-conductivity type doped region are arranged in a first direction in turn, and respectively extend in a second direction, the first direction and the second direction are perpendicular; The third A-conductivity type doped region and / or the third B-conductivity type doped region extend in the first direction, and the third A-conductivity type doped region and the third B-conductivity type doped region are connected by a metal wire.

2. The ESD protection device of claim 1, wherein, The third A-conductivity type doped region and / or the third B-conductivity type doped region extend in the first direction, specifically comprising: The third A-conductivity type doped region extends in the first direction, and the third A-conductivity type doped region is arranged at a first end of the first B-conductivity type doped region, the first A-conductivity type doped region, the second A-conductivity type doped region and the second B-conductivity type doped region; The third B-conductivity type doped region extends in the first direction, and the third B-conductivity type doped region is arranged at a second end of the first B-conductivity type doped region, the first A-conductivity type doped region, the second A-conductivity type doped region and the second B-conductivity type doped region.

3. The ESD protection device of claim 2, wherein, The third A-conductivity type doped region further comprises: A first branch region, which extends in the second direction, and is arranged at a side of the first B-conductivity type doped region away from the first A-conductivity type doped region; A second branch region, which extends in the second direction, and is arranged at a side of the second B-conductivity type doped region away from the second A-conductivity type doped region.

4. The ESD protection device of claim 2, wherein, The third B-conductivity type doped region further comprises: A third branch region, which extends in the second direction, and is arranged between the first A-conductivity type doped region and the second A-conductivity type doped region.

5. The ESD protection device of claim 1, wherein, The third A-conductivity type doped region and / or the third B-conductivity type doped region extend in the first direction, specifically comprising: The third A-conductivity type doped region extends in the second direction, and the third B-conductivity type doped region extends in the first direction.

6. The ESD protection device of claim 5, wherein, The third A-conductivity type doped region comprises: A first A-conductivity type sub-doped region, which is arranged at a side of the first B-conductivity type doped region away from the first A-conductivity type doped region; A second A-conductivity type doped sub-region, disposed on a side of the second B-conductivity type doped region away from the second A-conductivity type doped region.

7. The ESD protection device of claim 5, wherein, The third B-conductivity type doped region comprises: A first B-conductivity type doped sub-region, disposed on a first end of the first B-conductivity type doped region, the first A-conductivity type doped region, the second A-conductivity type doped region and the second B-conductivity type doped region. A second B-conductivity type doped sub-region, disposed on a second end of the first B-conductivity type doped region, the first A-conductivity type doped region, the second A-conductivity type doped region and the second B-conductivity type doped region.

8. The ESD protection device of claim 7, wherein, The third B-conductivity type doped region further comprises: A third B-conductivity type doped sub-region, connected between the first B-conductivity type doped sub-region and the second B-conductivity type doped sub-region, extending along the second direction, and disposed between the first A-conductivity type doped region and the second A-conductivity type doped region.

9. The ESD protection device of claim 1, wherein, The third A-conductivity type doped region and / or the third B-conductivity type doped region extends along the first direction, in particular comprising: The third A-conductivity type doped region extends along the first direction, and the third B-conductivity type doped region extends along the second direction.

10. The ESD protection device according to any one of claims 1-9, wherein: The A-conductivity type is P-type, and the B-conductivity type is N-type; or The A-conductivity type is N-type, and the B-conductivity type is P-type. An ESD protection device according to any one of claims 1-10.

11. A microprocessing chip, characterized by ​

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