Method for transmitting signal between drive chip and flash memory, and drive chip

Abstract

The present disclosure provides a method for transmitting a signal between a drive chip and a flash memory, and a drive chip. By means of an IOBUF, an APR directly transmits to a flash memory a control signal for reading / writing the flash memory. Upon receiving a read / write request, the flash memory feeds back the read / write request to the IOBUF. A feedback signal is registered for one clock cycle by means of a register inside the IOBUF to obtain a delayed signal, thereby reducing timing urgency of directly providing the feedback signal from the flash memory to the inside of the APR. The delayed signal is transmitted to an asynchronous FIFO memory of the APR for clock domain crossing processing to obtain an internal signal required by the APR. Clock domain crossing transmission of the signal output by the register of the IOBUF is performed by means of the asynchronous FIFO memory, avoiding a timing impact caused by an interactive routing delay between an APR circuit and an IOBUF circuit.

Description

A signal transmission method between a driver chip and a flash memory, and the driver chip.

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410577814.5, filed on May 10, 2024, entitled “A Signal Transmission Method and Driver Chip for a Driver Chip and Flash Memory”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of communication technology, and more specifically, to a signal transmission method for a driver chip and a flash memory, as well as the driver chip itself. Background Technology

[0004] Flash memory, also known as electrostatic discharge (ESD) memory, is a form of electrically erasable programmable read-only memory. It can be erased and rewritten multiple times during operation. EEPROM and high-speed RAM are currently the two most commonly used and fastest-growing storage technologies. Flash memory is used in computer BIOS, memory cards in digital cameras, and other applications. The main characteristic of flash memory is its ability to retain stored information for an extended period without power loss. Essentially, flash memory belongs to the EEPROM type. It possesses the characteristics of ROM, along with high access speeds, ease of erasure and rewriting, and low power consumption. Currently, its integration density has reached 4MB, and its price has also decreased. Due to the unique advantages of flash memory, such as the use of flashROM BIOS on some newer motherboards, BIOS upgrades are very convenient. Flash memory can also be used as a solid-state, high-capacity storage device.

[0005] The IBUF is primarily used as a tri-state port, connecting the internal tri-state signals of the driver chip with external bidirectional signals, all sharing the same pad. When the driver chip needs to output a signal, it outputs the signal from the pad through the IBUF driver circuit, at which point the IBUF circuit is turned off. When the driver chip needs to receive a signal, it receives the signal transmitted from the pad to the IC through the IBUF circuit, at which point the OBUF circuit is turned off. However, in this transmission method, the routing delays on the IBUF and FPC board can cause signal setup and hold time violations during timing verification after placement and routing.

[0006] Summary of the Invention

[0007] The purpose of this disclosure is to provide a signal transmission method and a driver chip for a driver chip and a flash memory, so as to solve the problem in the prior art that the signal establishment and hold time violations occur in the timing verification stage after placement and routing due to the routing delay of the traces on the IOBUF and FPC board.

[0008] This disclosure provides a signal transmission method between a driver chip and a flash memory, wherein the driver chip includes an APR module and an IOUBF module;

[0009] The method is applied to driver chips and includes:

[0010] The APR module is used to send the control signals for reading and writing the flash memory to the IOBUF module;

[0011] The IOUBUF module is used to send control signals to the flash memory;

[0012] The IOBUF module is used to receive feedback signals from the flash memory, and the IOBUF module's registers are used to store the feedback signals for one clock cycle to obtain a delayed signal, which is then sent to the APR module.

[0013] The delayed signal is received using the asynchronous FIFO memory of the APR module, and cross-clock domain processing is performed to obtain the internal signal of APR.

[0014] In the above technical solution, the APR module sends the control signals for reading and writing the flash memory directly to the flash memory through the IOBUF module. Upon receiving the read / write request, the flash memory feeds back to the IOBUF module. The IOBUF module's internal registers store the feedback signal for one clock cycle to obtain a delayed signal, thus reducing the timing urgency of directly sending the flash memory's feedback signal to the APR module. Then, the delayed signal is sent to the APR module's asynchronous FIFO memory for cross-clock domain processing to obtain the internal signals required by the APR module. This embodiment uses the asynchronous FIFO memory to transmit the signals output from the IOBUF module's registers across clock domains, avoiding the timing impact caused by the routing delays between the APR and IOBUF module circuits. This ensures that the routing delays on the IOBUF and FPC board do not affect the timing verification after placement and routing, and ensures that signal setup and hold times do not violate regulations.

[0015] In some alternative implementations, the control signals include: SCK clock signal, CSB control signal, SDO control signal, SDI control signal, WP control signal, and Hold control signal.

[0016] SCK stands for Serial Clock, used to synchronize the transmission of serial data. In SPI (Serial Peripheral Interface) or other serial communication protocols, the SCK signal switches at a certain frequency to indicate when data bits are sent or received. Typically, when the SCK signal is high, the data bits remain stable; when the SCK signal changes from high to low (or from low to high, depending on the specific communication protocol), the data bits change or are read.

[0017] CSB typically stands for chip select or chip enable. In some flash memory or other memory devices, multiple devices may be connected to the same serial bus. Chip select signals are used to distinguish and select which device should respond to a specific command or data. When the CSB signal is pulled low (or, depending on the specific design, pulled high), the corresponding flash memory chip is selected or enabled, thus enabling it to respond to subsequent read, write, or other operations.

[0018] SDO (Serial Data Output): In Flash or other digital devices, SDO typically stands for Serial Data Output. In serial communication, data is transmitted bit by bit, rather than multiple bits being transmitted in parallel at once. The SDO pin is used to serially output data from the device.

[0019] SDI (Serial Data Input): Corresponding to SDO, SDI stands for Serial Data Input. In Flash or other digital devices, the SDI pin is used to receive serial input data.

[0020] WP (Write Protect): WP typically stands for write protection. In Flash memory or other storage devices, the WP pin or signal is used to prevent data from being written to or erased. When WP is active (usually low), the device will not allow write or erase operations to protect the stored data from accidental modification.

[0021] HOLD: HOLD is typically used to pause or lock device operation. In Flash or other digital devices, the HOLD pin or signal can be used to pause device operation for specific operations or tests. When HOLD is active, the device will cease its normal operation until HOLD is released.

[0022] In some alternative implementations, it also includes:

[0023] The IOBUF module is used to send the sck clock signal to the APR module;

[0024] The asynchronous FIFO memory of the APR module is used to receive the sck clock signal, and the clk clock signal and sck clock signal of the APR module are set to asynchronous clocks with the same frequency.

[0025] In the above technical solution, the clk clock signal and sck clock signal of the APR module are set to asynchronous clocks of the same frequency, and the signal output from the register of the IOBUF module is transmitted across clock domains through the asynchronous FIFO memory. This avoids the timing impact caused by the circuit interaction delay between the APR module and the IOBUF module, ensures that the routing delay on the IOBUF and FPC boards has no impact on the timing verification after placement and routing, and ensures that there will be no violations in the signal setup and hold times.

[0026] In some optional implementations, while setting the clk clock signal and sck clock signal of the APR module to asynchronous clocks at the same frequency, the following is also included:

[0027] In the IOBUF module, the sck clock signal is sent to the ck terminal of the register.

[0028] In some alternative implementations, the feedback signals include: SDO feedback signal, SDI feedback signal, WP feedback signal, and Hold feedback signal.

[0029] In some alternative implementations, it also includes:

[0030] Using the IOBUF module, the CSB control signal is sent to the register of the IOBUF module, the CSB control signal is stored for one clock cycle to obtain the CSB delay signal, and the CSB delay signal is sent to the APR module.

[0031] This disclosure provides a driver chip, including an APR module and an IOUBUF module;

[0032] The APR module is used to send control signals for reading and writing flash memory to the IOBUF module;

[0033] The IOBUF module is used to send control signals to the flash memory; receive feedback signals from the flash memory, and use the registers of the IOBUF module to register the feedback signals for one clock cycle to obtain a delayed signal, and send the delayed signal to the APR module;

[0034] The APR module is also used to receive delayed signals using the asynchronous FIFO memory of the APR module and perform cross-clock domain processing to obtain the internal signals of the APR.

[0035] In the above technical solution, the driver chip includes an APR module and an IOBUF module. The APR module sends the control signals for reading and writing the flash memory directly to the flash memory through the IOBUF module. After receiving the read / write request, the flash memory feeds back to the IOBUF module. The IOBUF module registers the feedback signal for one clock cycle to obtain a delayed signal, thereby reducing the timing urgency of directly sending the flash memory feedback signal to the APR module. Then, the delayed signal is sent to the asynchronous FIFO memory of the APR module for cross-clock domain processing to obtain the internal signals required by the APR module. This embodiment uses the asynchronous FIFO memory to transmit the signal output from the register of the IOBUF module across clock domains, avoiding the timing impact caused by the interaction trace delay between the APR module and the IOBUF module circuits. This ensures that the trace delay on the IOBUF and FPC board has no impact on the timing verification after placement and routing, and ensures that the signal setup and hold times will not violate the rules.

[0036] In some alternative implementations, the control signals include: SCK clock signal, CSB control signal, SDO control signal, SDI control signal, WP control signal, and Hold control signal.

[0037] In some optional implementations, the IOBUF module is also used to: send the sck clock signal to the APR module;

[0038] The APR module is also used to: receive the sck clock signal using the asynchronous FIFO memory of the APR module, and set the clk clock signal and sck clock signal of the APR module to be asynchronous clocks of the same frequency.

[0039] In some optional implementations, while setting the clk clock signal and sck clock signal of the APR module to asynchronous clocks at the same frequency, the following is also included:

[0040] The IOBUF module is also used to send the sck clock signal to the ck terminal of the register while the clk clock signal and the sck clock signal are set to asynchronous clocks of the same frequency.

[0041] In some alternative implementations, the feedback signals include: SDO feedback signal, SDI feedback signal, WP feedback signal, and Hold feedback signal.

[0042] In some optional implementations, the IOBUF module is also used to: send the CSB control signal to the register of the IOBUF module, register the CSB control signal for one clock cycle to obtain the CSB delay signal, and send the CSB delay signal to the APR module. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments of this disclosure will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this disclosure and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 is a flowchart of a signal transmission method between a driver chip and a flash memory provided in an embodiment of this disclosure;

[0045] Figure 2 is a schematic diagram of the signal transmission process between the driver chip and the flash memory provided in an embodiment of this disclosure;

[0046] Figure 3 is a functional block diagram of a driver chip provided in an embodiment of this disclosure. Detailed Implementation

[0047] The technical solutions of the embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0048] Please refer to Figure 1, which is a flowchart of a signal transmission method between a driver chip and a flash memory provided in an embodiment of this disclosure. The driver chip includes an APR module and an IOBUF module.

[0049] This method is applied to driver chips and specifically includes:

[0050] Step 100: Using the APR module, send the control signals for reading and writing the flash memory to the IOBUF module;

[0051] Step 200: Use the IOBUF module to send control signals to the flash memory;

[0052] Step 300: Using the IOBUF module, receive the feedback signal from the flash memory, and use the register of the IOBUF module to register the feedback signal for one clock cycle to obtain the delayed signal, and send the delayed signal to the APR module.

[0053] Step 400: Receive the delayed signal using the asynchronous FIFO memory of the APR module and perform cross-clock domain processing to obtain the internal signal of APR.

[0054] APR stands for Automatic Placement and Route, and it has become a crucial part of chip back-end design. With the advanced development of Electronic Design Automation (EDA) tools, manually placing cells and drawing connections has become impractical, making automated chip design essential. The APR process mainly includes four steps: Floorplan, Placement, Clock Tree Synthesis (CTS), and Route. In short, APR is an indispensable part of chip back-end design, utilizing automated tools to complete the entire process from placement planning to routing, ensuring the design meets functional safety and performance requirements. Specifically, "auto placement" in APR refers to automatic placement, which automatically places the various functional modules in the chip in appropriate locations to meet the design's performance, power consumption, and area requirements. "Route" refers to automatic routing, which automatically connects the functional modules after their locations are determined, completing the overall chip design.

[0055] In this embodiment, the APR module sends the control signals for reading and writing the flash memory directly to the flash memory via the IOBUF module. Upon receiving the read / write request, the flash memory feeds back to the IOBUF module. The IOBUF module's internal registers store the feedback signal for one clock cycle to obtain a delayed signal, thus reducing the timing urgency of directly sending the flash memory's feedback signal to the APR module. Then, the delayed signal is sent to the APR module's asynchronous FIFO memory for cross-clock domain processing to obtain the internal signals required by the APR module. This embodiment uses the asynchronous FIFO memory to transmit the signals output from the IOBUF module's registers across clock domains, avoiding the timing impact caused by the routing delays between the APR and IOBUF module circuits. This ensures that the routing delays on the IOBUF and FPC board do not affect timing verification after placement and routing, and ensures that signal setup and hold times do not violate regulations.

[0056] Specifically, please refer to Figure 2, which is a schematic diagram of the signal transmission process between the driver chip and the flash memory provided in the embodiments of this disclosure.

[0057] Flash memory includes SCK, CSB, SDO, SDI, WP, and HOT interfaces.

[0058] SCK stands for Serial Clock, used to synchronize the transmission of serial data. In SPI (Serial Peripheral Interface) or other serial communication protocols, the SCK signal switches at a certain frequency to indicate when data bits are sent or received. Typically, when the SCK signal is high, the data bits remain stable; when the SCK signal changes from high to low (or from low to high, depending on the specific communication protocol), the data bits change or are read.

[0059] CSB typically stands for chip select or chip enable. In some flash memory or other memory devices, multiple devices may be connected to the same serial bus. Chip select signals are used to distinguish and select which device should respond to a specific command or data. When the CSB signal is pulled low (or, depending on the specific design, pulled high), the corresponding flash memory chip is selected or enabled, thus enabling it to respond to subsequent read, write, or other operations.

[0060] SDO (Serial Data Output): In Flash or other digital devices, SDO typically stands for Serial Data Output. In serial communication, data is transmitted bit by bit, rather than multiple bits being transmitted in parallel at once. The SDO pin is used to serially output data from the device.

[0061] SDI (Serial Data Input): Corresponding to SDO, SDI stands for Serial Data Input. In Flash or other digital devices, the SDI pin is used to receive serial input data.

[0062] WP (Write Protect): WP typically stands for write protection. In Flash memory or other storage devices, the WP pin or signal is used to prevent data from being written to or erased. When WP is active (usually low), the device will not allow write or erase operations to protect the stored data from accidental modification.

[0063] HOLD: HOLD is typically used to pause or lock device operation. In Flash or other digital devices, the HOLD pin or signal can be used to pause device operation for specific operations or tests. When HOLD is active, the device will cease its normal operation until HOLD is released.

[0064] The control signals used for reading and writing flash memory in the APR module include: sck clock signal sck_flash_out, csb control signal csb_flash_out, sdo control signal sdo_flash_out, sdi control signal sdi_flash_out, wp control signal wp_flash_out, and hold control signal hold_flash_out.

[0065] The signal transmission process also includes: using the IOBUF module to send the sck clock signal sck_flash_out to the APR module; using the asynchronous FIFO memory of the APR module to receive the sck clock signal sck_flash_out, and setting the clk clock signal and sck clock signal sck_flash_out of the APR module to asynchronous clocks of the same frequency.

[0066] In this embodiment, the clk clock signal and sck clock signal sck_flash_out of the APR module are set to asynchronous clocks of the same frequency, and the signal output from the register of the IOBUF module is transmitted across clock domains through an asynchronous FIFO memory. This avoids the timing impact caused by the circuit routing delay between the APR module and the IOBUF module, ensures that the routing delay on the IOBUF and FPC boards has no impact on the timing verification after placement and routing, and ensures that there will be no violations in the signal setup and hold times.

[0067] Furthermore, while setting the clk clock signal and sck clock signal sck_flash_out of the APR module to asynchronous clocks at the same frequency, the IOBUF module also includes sending the sck clock signal sck_flash_out to the ck terminals of the first register csb reg, the second register sdo reg, the third register sdi reg, the fourth register wp reg, and the fifth register hold reg.

[0068] The feedback signals of flash memory include: SDO feedback signal, SDI feedback signal, WP feedback signal, and Hold feedback signal.

[0069] The SDO feedback signal is input to the D terminal of the second register SDO reg, and the Q terminal of the second register SDO reg outputs the SDO delay signal sdo_flash_in. The SDO delay signal sdo_flash_in passes through the asynchronous FIFO memory to obtain the internal signal sdo_apr required by the APR module.

[0070] The SDI feedback signal is input to the D terminal of the third register SDI reg, and the Q terminal of the third register SDI reg outputs the SDI delay signal SDI_flash_in. The SDI delay signal SDI_flash_in passes through the asynchronous FIFO memory to obtain the internal signal SDI_apr required by the APR module.

[0071] The WP feedback signal is input to the D terminal of the fourth register WP reg, and the Q terminal of the fourth register WP reg outputs the WP delay signal wp_flash_in. The WP delay signal wp_flash_in passes through the asynchronous FIFO memory to obtain the internal signal wp_apr required by the APR module.

[0072] The hold feedback signal is input to the D terminal of the fifth register hold reg, and the Q terminal of the fifth register hold reg outputs the hold delay signal hold_flash_in. The hold delay signal hold_flash_in is passed through the asynchronous FIFO memory to obtain the internal signal hold_apr required by the APR module.

[0073] The signal transmission process also includes: using the IOBUF module, sending the csb control signal csb_flash_out to the D terminal of the first register csb reg of the IOBUF module; registering the csb control signal csb_flash_out for one clock cycle through the first register csb reg; outputting the csb delay signal csb_flash_in from the Q terminal of the first register csb reg; sending the csb delay signal csb_flash_in to the APR module; and obtaining the internal signal csb_apr required by the APR module through the asynchronous FIFO memory.

[0074] Please refer to Figure 3, which is a functional block diagram of a driver chip provided in an embodiment of this disclosure. The driver chip includes an APR module and an IOUBF module.

[0075] The APR module sends control signals for reading and writing the flash memory to the IOBUF module. The IOBUF module sends control signals to the flash memory; receives feedback signals from the flash memory and uses the IOBUF module's registers to store the feedback signals for one clock cycle to obtain a delayed signal, which is then sent to the APR module. The APR module also uses its asynchronous FIFO memory to receive the delayed signal and performs cross-clock domain processing to obtain the internal APR signal.

[0076] In this embodiment, the driver chip includes an APR module and an IOBUF module. The APR module sends the control signals for reading and writing the flash memory directly to the flash memory through the IOBUF module. After receiving the read / write request, the flash memory feeds back to the IOBUF module. The IOBUF module registers the feedback signal for one clock cycle to obtain a delayed signal, thereby reducing the timing urgency of directly sending the flash memory feedback signal to the APR module. Then, the delayed signal is sent to the asynchronous FIFO memory of the APR module for cross-clock domain processing to obtain the internal signals required by the APR module. This embodiment uses the asynchronous FIFO memory to transmit the signal output from the register of the IOBUF module across clock domains, avoiding the timing impact caused by the circuit routing delay between the APR module and the IOBUF module. This ensures that the routing delay on the IOBUF and FPC board has no impact on the timing verification after placement and routing, and ensures that the signal setup and hold times will not violate the rules.

[0077] In some alternative implementations, the control signals include: SCK clock signal, CSB control signal, SDO control signal, SDI control signal, WP control signal, and Hold control signal.

[0078] In some optional implementations, the IOBUF module is also used to: send the sck clock signal to the APR module;

[0079] The APR module is also used to: receive the sck clock signal using the asynchronous FIFO memory of the APR module, and set the clk clock signal and sck clock signal of the APR module to be asynchronous clocks of the same frequency.

[0080] In some optional implementations, while setting the clk clock signal and sck clock signal of the APR module to asynchronous clocks at the same frequency, the following is also included:

[0081] The IOBUF module is also used to send the sck clock signal to the ck terminal of the register while the clk clock signal and the sck clock signal are set to asynchronous clocks of the same frequency.

[0082] In some alternative implementations, the feedback signals include: SDO feedback signal, SDI feedback signal, WP feedback signal, and Hold feedback signal.

[0083] In some optional implementations, the IOBUF module is also used to: send the CSB control signal to the register of the IOBUF module, register the CSB control signal for one clock cycle to obtain the CSB delay signal, and send the CSB delay signal to the APR module.

[0084] In the embodiments provided in this disclosure, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0085] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0086] Furthermore, the functional modules in the various embodiments of this disclosure can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0087] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0088] The above description is merely an embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure. Industrial applicability

[0089] This disclosure provides a signal transmission method and driver chip for a driver chip and a flash memory. The APR module sends the control signals for reading and writing the flash memory directly to the flash memory via the IOBUF module. Upon receiving the read / write request, the flash memory feeds back to the IOBUF module. The chip's register stores the flash memory feedback signal for one clock cycle to obtain a delayed signal, reducing the timing urgency of directly providing the flash memory feedback signal to the APR module. Then, the delayed signal is sent to the asynchronous FIFO memory of the APR module for cross-clock domain processing to obtain the internal signals required by the APR module. This avoids timing effects caused by the interaction and routing delays between the APR module and the IOBUF module, ensuring that the routing delays on the IOBUF and FPC board do not affect timing verification after placement and routing, and ensuring that signal setup and hold times do not violate regulations.

Claims

1. A signal transmission method between a driver chip and a flash memory, characterized in that, The driver chip includes an APR module and an IOUBF module; The method is applied to the driver chip, and the method includes: The APR module is used to send control signals for reading and writing the flash memory to the IOBUF module; The control signal is sent to the flash memory using the IOBUF module. Using the IOBUF module, the feedback signal from the flash memory is received, and the feedback signal is stored in the register of the IOBUF module for one clock cycle to obtain a delayed signal, which is then sent to the APR module. The delayed signal is received using the asynchronous FIFO memory of the APR module, and cross-clock domain processing is performed to obtain the internal APR signal.

2. The signal transmission method as described in claim 1, characterized in that, The control signals include: SCK clock signal, CSB control signal, SDO control signal, SDI control signal, WP control signal, and Hold control signal.

3. The signal transmission method as described in claim 2, characterized in that, Also includes: The IOBUF module is used to send the sck clock signal to the APR module; The asynchronous FIFO memory of the APR module is used to receive the sck clock signal, and the clk clock signal of the APR module and the sck clock signal are set to asynchronous clocks with the same frequency.

4. The signal transmission method as described in claim 3, characterized in that, The method of setting the clk clock signal and the sck clock signal of the APR module to asynchronous clocks of the same frequency also includes: In the IOBUF module, the sck clock signal is sent to the ck terminal of the register.

5. The signal transmission method as described in claim 4, characterized in that, The feedback signals include: sdo feedback signal, sdi feedback signal, wp feedback signal and hold feedback signal; The method further includes: Using the IOBUF module, the csb control signal is sent to the register of the IOBUF module, the csb control signal is stored for one clock cycle to obtain the csb delay signal, and the csb delay signal is sent to the APR module.

6. A driver chip, characterized in that, Includes the APR module and the IOUBUF module; The APR module is used to send control signals for reading and writing the flash memory to the IOBUF module; The IOUF module is used to send the control signal to the flash memory; receive the feedback signal from the flash memory, and use the register of the IOUF module to register the feedback signal for one clock cycle to obtain a delayed signal, and send the delayed signal to the APR module. The APR module is also used to receive the delayed signal using the asynchronous FIFO memory of the APR module and perform cross-clock domain processing to obtain the internal APR signal.

7. The driver chip as described in claim 6, characterized in that, The control signals include: SCK clock signal, CSB control signal, SDO control signal, SDI control signal, WP control signal, and Hold control signal.

8. The driver chip as described in claim 7, characterized in that, The IOBUF module is also used to: send the sck clock signal to the APR module; The APR module is also used to: receive the sck clock signal using the asynchronous FIFO memory of the APR module, and set the clk clock signal and the sck clock signal of the APR module to be asynchronous clocks of the same frequency.

9. The driver chip as described in claim 8, characterized in that, The method of setting the clk clock signal and the sck clock signal of the APR module to asynchronous clocks of the same frequency also includes: The IOUBF module is also used to: send the sck clock signal to the ck terminal of the register while the clk clock signal and the sck clock signal are set to asynchronous clocks of the same frequency.

10. The driver chip as described in claim 9, characterized in that, The feedback signals include: sdo feedback signal, sdi feedback signal, wp feedback signal, and hold feedback signal; The IOBUF module is further configured to: send the csb control signal to the register of the IOBUF module, register the csb control signal for one clock cycle to obtain the csb delay signal, and send the csb delay signal to the APR module.

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