DCDC converter using dual-mode adaptive off-time timer

Abstract

The present invention provides a DCDC converter using a dual-mode adaptive off-time timer, comprising: a PWM comparator, an on-time timer, a current detection module, an off-time timer logic control circuit, a drive control circuit, a dual-mode adaptive off-time timer, an inductor LOUT, an NMOS transistor MH, an NMOS transistor ML, a resistor RFB2, a resistor RFB1, and a capacitor COUT. The present invention is implemented by means of the PWM comparator, the on-time timer, the current detection module, the off-time timer logic control circuit, the drive control circuit, and the dual-mode adaptive off-time timer. The off-time of the internal dual-mode adaptive off-time timer has the function of adaptively adjusting an input signal and an output feedback signal, and a minimum off-time timer and an overcurrent off-time timer are simultaneously implemented by using one off-time timer.

Description

DCDC converter applying dual-mode adaptive shutdown timer TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and particularly relates to a DCDC converter applying a dual-mode adaptive shutdown timer. BACKGROUND

[0002] Shutdown timers are usually used in the control circuit of DCDC converters, which can limit the minimum shutdown time to control the maximum duty cycle, and provide the minimum shutdown time by using the minimum shutdown timer to ensure sufficient charging time of the drive bootstrap capacitor in a single period and sufficient gate drive capability of the power tube. In addition, the shutdown timer can also be used for current limiting shutdown, and when the current exceeds the threshold, the current detection module sends a signal to shut down the high-side power tube, and the shutdown time is controlled by the shutdown timer. The common shutdown timer has two problems. On the one hand, the timing time is a fixed value and cannot be adaptively adjusted, which limits the maximum duty cycle and the maximum limit of the output voltage, and cannot meet the design requirements. On the other hand, the minimum shutdown timer and the overcurrent shutdown timer usually exist independently in the control circuit of the DCDC converter, which wastes the chip area and power consumption.

[0003] SUMMARY

[0004] In order to solve the problems in the background art, the present application proposes a DCDC converter applying a dual-mode adaptive shutdown timer, which has the function of adaptively adjusting the input signal and the output feedback signal, and simultaneously realizes the minimum shutdown timer and the overcurrent shutdown timer by using one shutdown timer.

[0005] In order to achieve the above technical purposes, the present application provides the following technical scheme:

[0006] A DCDC converter applying a dual-mode adaptive shutdown timer, comprising: a PWM comparator, a conduction time timer, a current detection module, a shutdown timer logic control circuit, a drive control circuit, and a dual-mode adaptive shutdown timer. OUT NMOS tube M H NMOS tube M L resistor R FB2 resistor R FB1 and capacitor C OUT The drain of the NMOS tube M H is connected to the VIN end; the source of the NMOS tube M H , the drain of the NMOS tube M L and one end of the inductor L OUT are connected; and the other end of the inductor L OUTone end of the resistor R FB2 and one end of the capacitor C OUT ; a source of the NMOS transistor M L , one end of the resistor R FB1 and the other end of the capacitor C OUT are grounded; the other end of the resistor R FB2 and the other end of the resistor R FB1 are connected as a V FB signal terminal; the PWM comparator outputs an on-period trigger signal FB_COMP according to a reference signal Vref and the V FB signal; the on-time timer outputs an off-period trigger signal OFF according to the on-period trigger signal FB_COMP; the current detection module is used for detecting a drain current of the NMOS transistor M H and outputs an off signal CURRENT_DET according to the drain current of the NMOS transistor M H ; the off timer logic control circuit outputs a gate drive control signal MOSFET_SET, a function selection signal SN1, a control signal SN2 and an off timing trigger signal ENN according to the on-period trigger signal FB_COMP, the off-period trigger signal OFF, the off signal CURRENT_DET and an off timer output signal OFF_MIN; the dual-mode adaptive off timer outputs the off timer output signal OFF_MIN according to the function selection signal SN1, the control signal SN2, an output feedback signal V FB , an input signal VIN and the off timing trigger signal ENN; the output end of the drive control circuit is connected to a gate of the NMOS transistor M H and a gate of the NMOS transistor M L , and is used for driving the NMOS transistor M H and the NMOS transistor M L to be on and off according to the gate drive control signal MOSFET_SET.

[0007] Preferably, the off timer logic control circuit comprises an AND gate, an OR gate OR1, an OR gate OR2, RS flip-flops RS1 to RS3 and an inverter INV1; one input end of the AND gate is connected to the on-period trigger signal FB_COMP; the output end of the AND gate and the reset end R of the flip-flop RS1 are connected; the complement output end of the flip-flop RS1 outputs the gate drive signal MOSFET_SET; one input end of the OR gate OR1 is connected to the off-period trigger signal OFF; the output end of the OR gate OR1, the set end S of the flip-flop RS1 and the set end S of the flip-flop RS2 are connected; the complement output end the other input terminal of the AND gate AND1 is connected with the other input terminal of the OR gate OR2; the output terminal of the OR gate OR2 is connected with the input terminal of the inverter INV1; the output terminal of the inverter INV1 outputs a control signal SN2; the complement output terminal of the flip-flop RS3 is connected with the other input terminal of the OR gate OR1 the other input terminal of the OR gate OR2; the output terminal of the OR gate OR2 is connected with the input terminal of the inverter INV1; the output terminal of the inverter INV1 outputs a control signal SN2; the complement output terminal of the flip-flop RS3 is connected with the other input terminal of the OR gate OR1 outputs a function selection signal SN1; the complement output terminal of the flip-flop RS2 is connected with the other input terminal of the OR gate OR1 outputs an off timing trigger signal ENN.

[0008] Preferably, the dual-mode adaptive off timer comprises: a current source I0, PMOS tubes MP2-MP14, NMOS tubes MN3-MN6, a PNP tube Q1, an NPN tube Q2, resistors R2-R5, a two-way selector MUX1, a two-way selector MUX2, an OR gate OR3, and an inverter INV2.

[0009] The positive terminal of the current source I0, the collector of Q1, one end of the resistor R2, the drain of MP8, the drain of MP10, the source of MN3, one end of the capacitor C0, the source of MN4, the source of MN5, one end of the resistor R3, and the source of MN6 are connected with ground; the negative terminal of the current source I0, the drain of MP2, the gate of MP2, the gate of MP3, the gate of MP4, the gate of MP9, the gate of MP11 and the gate of MP14 are connected; the source of MP2, the source of MP3, the source of MP4, the source of MP5, the source of MP6, the source of MP7, the source of MP9, the source of MP11 and the source of MP14 are connected; the drain of MP3, the drain of MP6, the base of Q2 and the emitter of Q1 are connected; the base of Q1 is connected with V FBMP5, the drain of MP5, the gate of MP5, the gate of MP6, the gate of MP7, and the collector of Q2 are connected; the emitter of Q2 and the other end of resistor R2 are connected; the drain of MP9, the 1-channel input of MUX1, and the source of MP10 are connected; the gate of MP10 is connected to control signal SN2; the gate of MP8, the control end of MUX1, and the control end of MUX2 are connected to function selection signal SN1; the drain of MP11, the source of MP12, and the source of MP13 are connected; the gate of MP12, the output of MUX1, the drain of MN3, and the other end of capacitor C0 are connected; the gate of MN3 is connected to off timing trigger signal ENN; the drain of MP12, the drain of MN4, the gate of MN4, and the gate of MN5 are connected; the drain of MN5, the drain of MP13, and the gate of MN6 are connected; the gate of MP13 and the output of MUX2 are connected; one end of resistor R5 is connected to power supply VIN; the other end of resistor R5, the 0-channel input of MUX2, and one end of resistor R4 are connected; the other end of resistor R4, the other end of resistor R3, and the 1-channel input of MUX2 are connected; the drain of MN6, the drain of MP14, and one input of OR gate OR3 are connected; the other input of OR gate OR3 is connected to off timing trigger signal ENN; the output of OR gate OR3 and the input of inverter INV2 are connected; the output of inverter INV2 outputs off timing signal OFF_MIN.

[0010] Preferably, the dual-mode adaptive off timing includes: a minimum off timing mode and an over-current off timing mode; when VFB is less than Vref, the PWM comparator triggers the DCDC converter to enter the on period, and the on period trigger signal FB_COMP changes from low to high; after the on period Ton, the DCDC converter ends the on period, the off period trigger signal OFF changes from low to high, FB_COMP changes from high to low, through OR gate OR1 and flip-flop RS2, the off timing trigger signal ENN changes from high to low, SN1 is low, through OR gate OR2 and inverter INV1, the control signal SN2 changes from low to high, the dual-mode adaptive off timing enters the minimum off timing mode, and the dual-mode adaptive off timing starts timing; after the minimum off time T1, the dual-mode adaptive off timing output signal OFF_MIN changes from low to high, through RS flip-flop RS2, ENN changes from low to high, SN2 changes from high to low, the timing ends, through AND gate and RS flip-flop RS1, the gate drive control signal MOSFET_SET changes from low to high; the NMOS tube MP H turns on, the NMOS tube MP LTurn off, realize the minimum turn-off time control of DCDC converter;

[0011] When NMOS transistor M H When the current of drain exceeds the threshold current, the current detection module output turn-off signal CURRENT_DET changes from low level to high level, through OR gate OR1 and RS flip-flop RS2, ENN changes from high level to low level, the dual-mode adaptive turn-off timer starts timing, SN1 changes from low level to high level, SN2 remains low level, the dual-mode adaptive turn-off timer enters the over-current turn-off timing mode, through OR gate OR1 and RS flip-flop RS1, gate drive control signal MOSFET_SET changes from high level to low level, NMOS transistor M H Turn off, NMOS transistor M L Turn on, inductance current drops, after the over-current turn-off time T2, the timing ends, the dual-mode adaptive turn-off timer output signal OFF_MIN changes from low level to high level, through RS flip-flop RS2, ENN changes from low level to high level, through AND gate and RS flip-flop RS2, gate drive control signal MOSFET_SET changes from low level to high level, NMOS transistor M H Turn on, NMOS transistor M L Turn off, realize the over-current turn-off timing control of DCDC converter.

[0012] Preferably, the minimum turn-off time T1 of the dual-mode adaptive turn-off timer is adaptive to input signal VIN, when the function selection signal SN1 is low level, the dual-mode adaptive turn-off timer is in the minimum turn-off timing mode, MUX1 and MUX2 open 0 channel; Turn-off timing trigger signal ENN changes from high level to low level, NMOS transistor MN3 turns off, SN1 is low level, PMOS transistor MP8 turns on, control signal SN2 is high level, PMOS transistor MP10 turns off, the drain current I3 of MP9 is obtained by the current mirror composed of current source I0, MP2 and MP9, current I3 flows into capacitor C0, the charging capacitor C0 starts to charge, the voltage V p The relationship with the minimum turn-off time T1 is:

[0013] When the voltage V p After reaching the 0 channel input end reference voltage VREF0 of MUX2, the charging ends, the reference voltage VREF0 is represented as:

[0014] The minimum turn-off time T1 is represented as:

[0015] Preferably, the over-current off-time T2 of the dual-mode adaptive off timer is adaptive to the input signal VIN and the output feedback signal VFB FB When the function selection signal SN1 is high, the dual-mode adaptive off timer is in the over-current off timing mode, MUX1 and MUX2 are open 1 channel, MP8 is off; ENN changes from high to low, MN3 is off, SN1 is high, PMOS MP8 is off, the control signal SN2 is low, PMOS MP10 is on, the current I1 and I2 flow into the charging capacitor C0, and the charging capacitor C0 starts to charge; the drain current I1 of MP4 is obtained by the current mirror composed of MP2 and MP4; the drain current I2 of MP7 is obtained by the current mirror composed of MP5 and MP7 with a ratio of 1:K1; by adjusting the size of MP3 and MP6, the emitter junction voltage V BE1 of Q1 is ensured to be equal to the emitter junction voltage V BE2 of Q2; and the drain current I4 of MP5 is represented as:

[0016] The current I1 and the current I2 flow into the capacitor C0, and the charging capacitor C0 starts to charge; and the voltage V p of the charging capacitor C0 is related to the over-current off-time T2 as:

[0017] When the voltage V p of the charging capacitor C0 reaches the reference voltage VREF1 of the 1 channel input end of MUX2, the charging is ended, and the size of the reference voltage VREF1 can be represented as:

[0018] The over-current off-time T2 is represented as:

[0019] The present application has at least the following beneficial effects

[0020] (1) The off timer logic control circuit and the dual-mode adaptive off timer of the present application can realize automatic switching of the minimum off timer and the over-current off timer dual-mode functions.

[0021] (2) The dual-mode adaptive off timer of the present application can adapt to the input signal VIN and the output feedback signal VFB, and realize adaptive adjustment of the off time.

[0022] (3) The present application inherits the minimum off timer and the over-current off timer into a dual-mode adaptive off timer, which overcomes the problem that the minimum off timer and the over-current off timer usually exist independently in the control circuit of the DCDC converter in the prior art, and avoids the waste of chip area and power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0023] Fig. 1 is a schematic diagram of a conventional off timer generation circuit;

[0024] Fig. 2 is a schematic diagram of a DCDC converter circuit using a dual-mode adaptive off timer according to the present application;

[0025] Fig. 3 is a schematic diagram of a logic control circuit for the off timer according to the present application;

[0026] Fig. 4 is a schematic diagram of a dual-mode adaptive off timer according to the present application;

[0027] Fig. 5 is a timing diagram of the logic control circuit for the dual-mode adaptive off timer according to the present application. DETAILED DESCRIPTION

[0028] The present application is described herein with reference to particular embodiments for a particular application. Those skilled in the art will understand that the application is not limited to those embodiments but is applicable to other embodiments and applications as appreciated by those skilled in the art on the basis of the teachings hereof. The description herein of specific embodiments, sets out the best modes contemplated by the inventors of carrying out their application, and of bringing it to a practical realization. Embodiments will be readily apparent to those of ordinary skill in the art from this description and from the claims that follow. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The description is presented in the order of appearance and for ease of explanation.

[0029] The drawings are only intended for illustrative purposes, and the representation is only a schematic diagram, not a physical diagram, and should not be understood as a limitation of the present application. In order to better illustrate the embodiments of the present application, some components in the drawings are omitted, enlarged or reduced, and do not represent the actual size of the product. It is understandable to those skilled in the art that some well-known structures and their descriptions in the drawings can be omitted.

[0030] The same or similar reference numerals in the drawings of the embodiments of the present application correspond to the same or similar components; in the description of the present application, it should be understood that the orientation or position relationship indicated by the terms "upper", "lower", "left", "right", "front", "back" and the like is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore the terms describing the position relationship in the drawings are only for illustrative purposes, and should not be understood as a limitation of the present application. For those skilled in the art, the specific meanings of the above terms can be understood according to the specific circumstances.

[0031] Please refer to Fig. 1, which is a conventional off timer generating circuit, operational amplifier A0, NMOS transistor MN0, voltage dividing resistor R0 and resistor R1 generate current source I10 through a negative feedback loop, and the current mirror structure composed of PMOS transistors MP0 and MP1 with a ratio of 1:K, the size of I10 is related to reference voltage Vref and resistor R1, that is, the size of I10 can be expressed as:

[0032] The size of I11 is related to I10 and their ratio, I 11 The size of I11 can be expressed as:

[0033] NMOS transistors MN1 and MN2 are used as switches and are controlled by a control circuit, when MN1 is on and MN2 is off, current I11 starts to charge capacitor C; when capacitor C is charged to Vref, MN1 is off and MN2 is on, the charging of capacitor C by current I1 is ended, and capacitor C is discharged through MN2, preparing for the next charging. The relationship between the capacitor voltage Vc and the off time is:

[0034] Therefore, the off time is: off R1C

[0035] It can be seen that the off time of the conventional off timer is a fixed value R1C, which cannot meet the characteristics of adaptive adjustment of the off time, and once R1C is determined, the off time cannot be changed.

[0036] In order to overcome the shortcomings of the conventional off timer that the off time is fixed and cannot be adaptively adjusted, and the minimum off timer and the over-current off timer are independently designed, wasting chip area and power consumption, the application provides a DCDC converter using a dual-mode adaptive off timer, as shown in Fig. 2, which comprises a PWM comparator, a on-time timer, a current detection module, an off timer logic control circuit, a drive control circuit, a dual-mode adaptive off timer, an inductor L OUT , an NMOS transistor M H , an NMOS transistor M L , a resistor R FB2 , a resistor R FB1 and a capacitor C OUT ; the drain of the NMOS transistor M H is connected to the VIN terminal; the source of the NMOS transistor M H , the drain of the NMOS transistor M L and one end of the inductor L OUT are connected; the other end of the inductor L OUT , one end of the resistor R FB2 and the capacitor C OUTone end of the NMOS transistor M L source, resistor R FB1 one end of the capacitor C OUT the other end of the resistor R FB2 the other end of the resistor R FB1 connected to the other end of the capacitor C FB signal terminal; the PWM comparator outputs the on-period trigger signal FB_COMP according to the reference signal Vref and the V FB signal; the on-time timer outputs the off-period trigger signal OFF according to the on-period trigger signal FB_COMP; the current detection module detects the drain current of the NMOS transistor M H and outputs the off signal CURRENT_DET according to the drain current of the NMOS transistor M H ; the off timer logic control circuit outputs the gate drive control signal MOSFET_SET, the function selection signal SN1, the control signal SN2 and the off timing trigger signal ENN according to the on-period trigger signal FB_COMP, the off-period trigger signal OFF, the off signal CURRENT_DET and the off timer output signal OFF_MIN; the dual-mode adaptive off timer outputs the off timer output signal OFF_MIN according to the function selection signal SN1, the control signal SN2, the output feedback signal V FB , the input signal VIN and the off timing trigger signal ENN; the output end of the drive control circuit is connected to the gate of the NMOS transistor M H and the gate of the NMOS transistor M L , for driving the NMOS transistor M H and the NMOS transistor M L to turn on and off according to the gate drive control signal MOSFET_SET.

[0037] In this embodiment, the PWM comparator is used to generate the on-period trigger signal FB_COMP according to Vref and V FB signal, Vref as the positive input end signal of the PWM comparator and V FB signal as the negative input end signal of the PWM comparator, the PWM comparator determines whether the output on-period trigger signal FB_COMP is high or low by comparing Vref and V FB , when the output feedback signal VFB is greater than the reference voltage Vref, the on-period trigger signal FB_COMP output by the PWM comparator changes from high to low; when the output feedback signal VFB is less than the reference voltage Vref, the on-period trigger signal FB_COMP output by the PWM comparator changes from low to high, triggering the on-period of the DCDC converter;

[0038] When FB_COMP changes from low level to high level, the turn-on time timer outputs an off period trigger signal OFF, which is a pulse signal, i.e. the off period trigger signal OFF changes from low level to high level and then to low level in a unit time; at this time, after the off period trigger signal OFF rising edge is received by the off time timer logic control circuit, the double-mode adaptive off timing timer works in the minimum off timing mode to charge the capacitor COUT to realize the minimum off time control of the DCDC converter; in the embodiment, the current monitoring module is used to monitor the current flowing into the NMOS tube M H The current monitoring module is commonly used in the current monitoring module, the Hall effect sensor, the resistor type current sensor, etc.

[0039] The turn-on time timer is used to generate the OFF pulse signal; the turn-on time timer is a commonly used turn-on time timer for DCDC circuit, which belongs to the commonly used devices in the field of DCDC circuit, and thus the specific structure thereof is not described; when VFB is less than Vref, the PWM comparator triggers the DCDC converter to enter the turn-on period, the turn-on period trigger signal FB_COMP changes from low level to high level, the current inside the turn-on time timer starts to charge the capacitor, after the turn-on period Ton, the DCDC converter ends the turn-on period, the turn-on time timer sends the off period trigger signal OFF changing from low level to high level, and FB_COMP changes from high level to low level.

[0040] In the embodiment, the essence of the drive control circuit is to perform power amplification on the gate drive control signal MOSFET_SET to drive the turn-on and turn-off of the NMOS tube MH and the NMOS tube ML; the existing drive circuit includes the MOSFET drive, the triode drive circuit, the push-pull drive circuit, etc., which belong to the commonly used devices in the field of DCDC circuit, and thus the specific structure thereof is not described.

[0041] Preferably, the off timing timer logic control circuit includes an AND gate, an OR gate OR1, an OR gate OR2, RS flip-flops RS1 to RS3, and an inverter INV1; the output end of the PWM comparator is connected with one input end of the AND gate; the output end of the AND gate is connected with the reset end of the flip-flop RS1; the complement output end of the flip-flop RS1 is connected with one input end of the OR gate OR1; the output end of the OR gate OR1 is connected with one input end of the OR gate OR2; the output end of the OR gate OR2 is connected with the reset end of the flip-flop RS2; the output end of the flip-flop RS2 is connected with the reset end of the flip-flop RS3; the output end of the flip-flop RS3 is connected with the input end of the inverter INV1; and the output end of the inverter INV1 is the output end of the gate drive signal MOSFET_SET. The gate drive signal MOSFET_SET is outputted to adjust the gate voltage of the power tube to control the turn-off of the power tube;

[0042] An output terminal of the on-time timer is connected with one input terminal of an OR gate OR1; an output terminal of the OR gate OR1, a set terminal of a flip-flop RS1 and a set terminal of a flip-flop RS2 are connected; a complement output terminal of the flip-flop RS2, another input terminal of an AND gate and one input terminal of an OR gate OR2 are connected; an output terminal of the current detection module, another input terminal of the OR gate OR1 and a reset terminal of a flip-flop RS3 are connected; an output terminal of the adaptive off-time timer, a reset terminal of the flip-flop RS2 and a set terminal of the flip-flop RS3 are connected; a complement output terminal of the flip-flop RS3 and another input terminal of the OR gate OR2 are connected; an output terminal of the OR gate OR2 is connected with an input terminal of an inverter INV1; an output terminal of the inverter INV1 outputs a control signal SN2; a complement output terminal of the flip-flop RS3 outputs a function selection signal SN1; a complement output terminal of the flip-flop RS2 outputs an off timing trigger signal ENN; wherein the adaptive off-time timer outputs an off timing signal OFF_MIN according to the function selection signal SN1, the off timing trigger signal ENN and the control signal SN2.

[0043] Preferably, the dual-mode adaptive off-time timer comprises: a current source I0, PMOS tubes MP2-MP14, NMOS tubes MN3-MN6, a PNP tube Q1, an NPN tube Q2, resistors R2-R5, a two-way selector MUX1, a two-way selector MUX2, an OR gate OR3 and an inverter INV2.

[0044] The positive terminal of the current source I0, the collector of Q1, one terminal of the resistor R2, the drain of MP8, the drain of MP10, the source of MN3, one terminal of the capacitor C0, the source of MN4, the source of MN5, one terminal of the resistor R3, and the source of MN6 are grounded; the negative terminal of the current source I0, the drain of MP2, the gate of MP2, the gate of MP3, the gate of MP4, the gate of MP9, the gate of MP11 and the gate of MP14 are connected; the source of MP2, the source of MP3, the source of MP4, the source of MP5, the source of MP6, the source of MP7, the source of MP9, the source of MP11 and the source of MP14 are connected; the drain of MP3, the drain of MP6, the base of Q2 and the emitter of Q1 are connected; the base of Q1 outputs the feedback signal VFB; the drain of MP4, the drain of MP7, one input terminal of MUX1 and the source of MP8 are connected; the drain of MP5, the gate of MP5, the gate of MP6, the gate of MP7 and the collector of Q2 are connected; the emitter of Q2 and the other terminal of the resistor R2 are connected; the drain of MP9, the other input terminal of MUX1 and the source of MP10 are connected; the gate of MP10 receives the control signal SN2; the gate of MP8, the control terminal of MUX1 and the control terminal of MUX2 receive the function selection signal SN1; the drain of MP11, the source of MP12 and the source of MP13 are connected; the gate of MP12, the output terminal of MUX1, the drain of MN3 and the other terminal of the capacitor C0 are connected; the gate of MN3 receives the off timing trigger signal ENN; the drain of MP12, the drain of MN4, the gate of MN4 and the gate of MN5 are connected; the drain of MN5, the drain of MP13 and the gate of MN6 are connected; the gate of MP13 and the output terminal of MUX2 are connected; one terminal of the resistor R5 receives the power supply VIN; the other terminal of the resistor R5, one input terminal of MUX2 and one terminal of the resistor R4 are connected; the other terminal of the resistor R4, the other terminal of the resistor R3 and the other input terminal of MUX2 are connected; the drain of MN6, the drain of MP14 and one input terminal of OR3 are connected; the other input terminal of OR3 receives the off timing trigger signal ENN; the output terminal of OR3 and the input terminal of INV2 are connected; the output terminal of INV2 outputs the off timing signal OFF_MIN.

[0045] Referring to FIG. 3, preferably, the off timer logic control circuit comprises an AND gate, OR1, OR2, RS flip-flops RS1-RS3, and an inverter INV1; one input terminal of the AND gate receives the on period trigger signal FB_COMP; the output terminal of the AND gate and the reset terminal R of the flip-flop RS1 are connected; the complement output terminal of the flip-flop RS1 and the reset terminal R of the flip-flop RS2 are connected; the output terminal of the flip-flop RS2 and the reset terminal R of the flip-flop RS3 are connected; the output terminal of the flip-flop RS3 and the input terminal of the inverter INV1 are connected; the output terminal of the inverter INV1 outputs the off timing signal OFF_MIN. The output gate drive signal MOSFET_SET; one input terminal of the OR gate OR1 is connected with the off period trigger signal OFF; the output terminal of the OR gate OR1, the set terminal S of the flip-flop RS1 and the set terminal S of the flip-flop RS2 are connected; the complement output terminal of the flip-flop RS2 is connected with the output terminal of the OR gate OR1 The other input terminal of the AND gate and one input terminal of the OR gate OR2 are connected; the other input terminal of the OR gate OR1 and the reset terminal R of the flip-flop RS3 are connected with the off signal CURRENT_DET; the reset terminal R of the flip-flop RS2 and the set terminal S of the flip-flop RS3 are connected with the off timer output signal OFF_MIN; the complement output terminal of the flip-flop RS3 is connected with the output terminal of the OR gate OR2 The other input terminal of the AND gate and one input terminal of the OR gate OR2 are connected; the other input terminal of the OR gate OR1 and the reset terminal R of the flip-flop RS3 are connected with the off signal CURRENT_DET; the reset terminal R of the flip-flop RS2 and the set terminal S of the flip-flop RS3 are connected with the off timer output signal OFF_MIN; the complement output terminal of the flip-flop RS3 is connected with the output terminal of the OR gate OR2 The output function selection signal SN1; the complement output terminal of the flip-flop RS2 The off timer trigger signal ENN is outputted.

[0046] Please refer to Fig. 4, the dual-mode adaptive off timer comprises: a current source I0, PMOS tubes MP2-14, NMOS tubes MN3-MN6, PNP tube Q1, NPN tube Q2, resistors R2-R5, dual-path selector MUX1, dual-path selector MUX2, OR gate OR3 and inverter INV2;

[0047] The positive terminal of the current source I0, the collector of Q1, one terminal of the resistor R2, the drain of MP8, the drain of MP10, the source of MN3, one terminal of the capacitor C0, the source of MN4, the source of MN5, one terminal of the resistor R3 and the source of MN6 are grounded; the negative terminal of the current source I0, the drain of MP2, the gate of MP2, the gate of MP3, the gate of MP4, the gate of MP9, the gate of MP11 and the gate of MP14 are connected; the source of MP2, the source of MP3, the source of MP4, the source of MP5, the source of MP6, the source of MP7, the source of MP9, the source of MP11 and the source of MP14 are connected; the drain of MP3, the drain of MP6, the base of Q2 and the emitter of Q1 are connected; the base of Q1 is connected with V FB; the drain of MP4, the drain of MP7, the 0 channel input of MUX1 and the source of MP8 are connected; the drain of MP5, the gate of MP5, the gate of MP6, the gate of MP7 and the collector of Q2 are connected; the emitter of Q2 and the other end of resistor R2 are connected; the drain of MP9, the 1 channel input of MUX1 and the source of MP10 are connected; the gate of MP10 is connected to control signal SN2; the gate of MP8, the control end of MUX1 and the control end of MUX2 are connected to function selection signal SN1; the drain of MP11, the source of MP12 and the source of MP13 are connected; the gate of MP12, the output of MUX1, the drain of MN3 and the other end of capacitor CO are connected; the gate of MN3 is connected to off timing trigger signal ENN; the drain of MP12, the drain of MN4, the gate of MN4 and the gate of MN5 are connected; the drain of MN5, the drain of MP13 and the gate of MN6 are connected; the gate of MP13 and the output of MUX2 are connected; one end of resistor R5 is connected to power supply VIN; the other end of resistor R5, the 0 channel input of MUX2 and one end of resistor R4 are connected; the other end of resistor R4, the other end of resistor R3 and the 1 channel input of MUX2 are connected; the drain of MN6, the drain of MP14 and one input of OR gate OR3 are connected; the other input of OR gate OR3 is connected to off timing trigger signal ENN; the output of OR gate OR3 and the input of inverter INV2 are connected; the output of inverter INV2 outputs off minimum signal OFF_MIN.

[0048] Please refer to figure 5, the dual-mode adaptive off timer includes: minimum off timing mode and over-current off timing mode; wherein, when PWM comparator starts the on period, when VFB is less than Vref, PWM comparator triggers DCDC converter to enter the on period, on period trigger signal FB_COMP changes from low level to high level; after the on period Ton, DCDC converter ends the on period, off period trigger signal OFF changes from low level to high level, FB_COMP changes from high level to low level, through OR gate OR1 and flip-flop RS2, off timing trigger signal ENN changes from high level to low level, SN1 is low level, through OR gate OR2 and inverter INV1, control signal SN2 changes from low level to high level, the dual-mode adaptive off timer enters the minimum off timing mode, the dual-mode adaptive off timer starts timing, after the minimum off time T1, the dual-mode adaptive off timer output signal OFF_MIN changes from low level to high level, through RS flip-flop RS2, ENN changes from low level to high level, SN2 changes from high level to low level, ends timing, through AND gate and RS flip-flop RS1, gate drive control signal MOSFET_SET changes from low level to high level; NMOS tube M H turns on, NMOS tube ML turn-off, the minimum turn-off time control of the DCDC converter is realized;

[0049] When NMOS transistor M H When the current of the drain exceeds the threshold current, the turn-off signal CURRENT_DET output by the current detection module changes from low level to high level, ENN changes from high level to low level through OR gate OR1 and RS flip-flop RS2, the dual-mode adaptive turn-off timer starts timing, SN1 changes from low level to high level, SN2 remains low level, the dual-mode adaptive turn-off timer enters the over-current turn-off timing mode, the gate drive control signal MOSFET_SET changes from high level to low level through OR gate OR1 and RS flip-flop RS1, NMOS transistor M H turn-off, NMOS transistor M L turn-on, the inductor current decreases, after the over-current turn-off time T2, the timing ends, the OFF_MIN signal output by the dual-mode adaptive turn-off timer changes from low level to high level, ENN changes from low level to high level through RS flip-flop RS2, the gate drive control signal MOSFET_SET changes from low level to high level through AND gate and RS flip-flop RS2, NMOS transistor M H turn-on, NMOS transistor M L turn-off, the over-current turn-off timing control of the DCDC converter is realized.

[0050] Preferably, the minimum turn-off time T1 of the dual-mode adaptive turn-off timer is adaptive to the input signal VIN, when the function selection signal SN1 is low level, the dual-mode adaptive turn-off timer is in the minimum turn-off timing mode, MUX1 and MUX2 open the 0 channel; the turn-off timing trigger signal ENN changes from high level to low level, NMOS transistor MN3 turns off, SN1 is low level, PMOS transistor MP8 turns on, the control signal SN2 is high level, PMOS transistor MP10 turns off, the drain current I3 of MP9 is obtained by the current mirror composed of current source I0, MP2 and MP9, the current I3 flows into the capacitor C0, the charging capacitor C0 starts to charge, the voltage V p The relationship with the minimum turn-off time T1 is:

[0051] When the voltage V p After reaching the 0 channel input end reference voltage VREF0 of MUX2, the charging ends, the reference voltage VREF0 is represented as:

[0052] The minimum turn-off time T1 is represented as:

[0053] It can be found that the minimum off time T1 is adaptive to VIN. Taking a constant on time buck DCDC as an example, the output VOUT is required to be the same, when the input voltage VIN is a small power supply, the duty cycle D is required to be large, and the minimum off time T1 is required to be small. For a power supply with a high input voltage VIN, the leakage of the bootstrap capacitor of the drive circuit is more serious, and the minimum off time T1 needs to be longer to charge the bootstrap capacitor of the drive circuit, so as to ensure that the gate has sufficient driving capability. Compared with the traditional off time timer, the off timer of the application is more suitable for power converters with wide input range.

[0054] Preferably, the overcurrent off time T2 of the dual-mode adaptive off timer is adaptive to the input signal VIN and the output feedback signal V FB When the function selection signal SN1 is high, the dual-mode adaptive off timer is in the overcurrent off timing mode, MUX1 and MUX2 open the 1 channel, MP8 is off; ENN changes from high to low, MN3 is off, SN1 is high, PMOS MP8 is off, control signal SN2 is low, PMOS MP10 is on, currents I1 and I2 flow into the charging capacitor C0, and the charging capacitor C0 starts to charge; the drain current I1 of MP4 is obtained by the current mirror composed of MP2 and MP4 from the current source I0; the drain current I2 of MP7 is obtained by the current mirror composed of MP5 and MP7 with a ratio of 1:K1; by adjusting the size of MP3 and MP6, the emitter junction voltage V BE1 of Q1 is equal to the emitter junction voltage V BE2 of Q2, and the drain current I4 of MP5 is represented as:

[0055] The currents I1 and I2 flow into the capacitor C0, and the charging capacitor C0 starts to charge, and the voltage V p of the charging capacitor C0 is related to the overcurrent off time T2 as:

[0056] When the voltage V p of the charging capacitor C0 reaches the reference voltage VREF1 of the 1 channel input end of MUX2, the charging is ended, and the size of the reference voltage VREF1 can be represented as:

[0057] The overcurrent off time T2 is represented as:

[0058] It can be found from the off-time T2 formula that the off-time T2 is adaptive to VFB and VIN. In the output short circuit or start-up stage, the current limit off-time timer can ensure a longer off-time, increase the inductor current drop amplitude, and reduce the surge voltage caused by overcharging of the output capacitor by the inductor current. At the same time, for a high input power supply voltage VIN of a high-power power converter, increasing the inductor current drop amplitude is beneficial to reducing the thermal stress of the inductor. In the overcurrent condition in the normal working state, the current limit off-time timer only needs to provide a shorter off-time, a smaller inductor current drop amplitude, and a shorter chip overload recovery time. The above is only a preferred embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0059] Finally, it should be pointed out that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit the present application. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced equivalently without departing from the purpose and scope of the present application, and they should be included in the scope of the claims of the present application.

Claims

1. A DC-DC converter employing a dual-mode adaptive shutdown timer, characterized in that, include: PWM comparator, on-time timer, current detection module, shutdown timer logic control circuit, drive control circuit, dual-mode adaptive shutdown timer, inductor L OUT NMOS transistor M H NMOS transistor M L Resistance R FB2 Resistance R FB1 and capacitor C OUT ; The NMOS transistor M H The drain is connected to the VIN terminal; The NMOS transistor M H The source of the NMOS transistor M L Drain and inductance L OUT One end is connected; The inductor L OUT The other end, resistor R FB2 one end and capacitor C OUT One end is connected; The NMOS transistor M L The source and resistor R FB1 one end and capacitor C OUT The other end is grounded; The resistor R FB2 The other end and resistor R FB1 The other end is connected as V FB signal end; The PWM comparator is based on the reference signal Vref and V... FB The signal output conduction cycle triggers the signal FB_COMP; The on-time timer outputs the off-time trigger signal OFF based on the on-cycle trigger signal FB_COMP. The current detection module is used to detect the NMOS transistor M. H The drain current, and according to the NMOS transistor M H The drain current outputs the shutdown signal CURRENT_DET; The shutdown timer logic control circuit outputs the gate drive control signal MOSFET_SET, function selection signal SN1, control signal SN2, and shutdown timing trigger signal ENN based on the on-cycle trigger signal FB_COMP, the shutdown cycle trigger signal OFF, the shutdown signal CURRENT_DET, and the shutdown timer output signal OFF_MIN. The dual-mode adaptive shutdown timer is based on the function selection signal SN1, control signal SN2, and output feedback signal V. FB The input signal VIN and the shutdown timer trigger signal ENN output the shutdown timer output signal OFF_MIN; The output terminal of the drive control circuit is connected to the NMOS transistor M. H The gate and NMOS transistor M L The gate is used to drive the NMOS transistor M according to the gate drive control signal MOSFET_SET. H and NMOS transistor M L The conduction and shutdown.

2. A DC-DC converter using a dual-mode adaptive shutdown timer according to claim 1, characterized in that, The shutdown timer logic control circuit includes: AND gate, OR gate OR1, OR gate OR2, RS flip-flops RS1~RS3, and inverter INV1; One input of the AND gate is connected to the on-cycle trigger signal FB_COMP; The output of the AND gate is connected to the reset terminal R of the flip-flop RS1; the supplementary output terminal of the flip-flop RS1 Output gate drive signal MOSFET_SET; One input of the OR gate OR1 is connected to the off-cycle trigger signal OFF; the output of the OR gate OR1, the setting terminal S of the flip-flop RS1, and the setting terminal S of the flip-flop RS2 are connected. The supplementary output terminal of the trigger RS2 Connect the other input of the AND gate and the one input of the OR gate; The other input of the OR gate OR1 and the reset terminal R of the flip-flop RS3 are connected to the turn-off signal CURRENT_DET; The reset terminal R of the trigger RS2 and the setting terminal S of the trigger RS3 are connected to the turn-off timer output signal OFF_MIN; The supplementary output terminal of the trigger RS3 Connect the OR gate OR2 to the other input; The output of the OR gate OR2 is connected to the input of the inverter INV1; The inverter INV1 outputs a control signal SN2. The supplementary output terminal of the trigger RS3 Output function selection signal SN1; The supplementary output terminal of the trigger RS2 Output the shutdown timing trigger signal ENN.

3. A DC-DC converter using a dual-mode adaptive shutdown timer according to claim 1, characterized in that, The dual-mode adaptive shutdown timer includes: current source I0, PMOS transistors MP2 to MP14, NMOS transistors MN3 to MN6, PNP transistor Q1, NPN transistor Q2, resistors R2 to R5, dual-channel selector MUX1, dual-channel selector MUX2, OR gate OR3, and inverter INV2. The positive terminal of current source I0, the collector of Q1, one end of resistor R2, the drain of MP8, the drain of MP10, the source of MN3, one end of capacitor C0, the source of MN4, the source of MN5, and the resistor R3. One end and the source of MN6 are grounded; the negative terminal of current source I0, the drain of MP2, the gate of MP2, the gate of MP3, the gate of MP4, the gate of MP9, the gate of MP11, and the gate of MP14 are connected; the sources of MP2, MP3, MP4, MP5, MP6, MP7, MP9, MP11, and MP14 are connected; the drains of MP3 and MP6, the base of Q2, and the emitter of Q1 are connected; the base of Q1 is connected to V. FB The drain of MP4, the drain of MP7, the 0th channel input of MUX1, and the source of MP8 are connected; the drain of MP5, the gate of MP5, the gate of MP6, the gate of MP7, and the collector of Q2 are connected; the emitter of Q2 is connected to the other end of resistor R2; the drain of MP9, the 1st channel input of MUX1, and the source of MP10 are connected; the gate of MP10 is connected to control signal SN2; the gate of MP8, the control terminal of MUX1, and the control terminal of MUX2 are connected to function selection signal SN1; the drain of MP11, the source of MP12, and the source of MP13 are connected; the gate of MP12, the output terminal of MUX1, the drain of MN3, and the other end of capacitor C0 are connected; the gate of MN3 is connected to the turn-off timing trigger signal ENN; MP The drain of MN12, the drain of MN4, the gate of MN4, and the gate of MN5 are connected; the drain of MN5, the drain of MP13, and the gate of MN6 are connected; the gate of MP13 is connected to the output of MUX2; one end of resistor R5 is connected to the power supply VIN; the other end of resistor R5, the 0th channel input of MUX2, and one end of resistor R4 are connected; the other end of resistor R4, the other end of resistor R3, and the 1st channel input of MUX2 are connected; the drain of MN6, the drain of MP14, and one input of OR gate OR3 are connected; the other input of OR gate OR3 is connected to the shutdown timing trigger signal ENN; the output of OR gate OR3 is connected to the input of inverter INV2; the output of inverter INV2 outputs the shutdown timing signal OFF_MIN.

4. A DC-DC converter using a dual-mode adaptive shutdown timer according to claim 1, characterized in that, The dual-mode adaptive shutdown timer includes a minimum shutdown timing mode and an overcurrent shutdown timing mode. When VFB is less than Vref, the PWM comparator triggers the DC-DC converter to enter the conduction cycle, and the conduction cycle trigger signal FB_COMP changes from low to high. After the conduction cycle Ton, the DC-DC converter ends its conduction cycle, and the conduction timer sends a shutdown cycle trigger signal OFF, which changes from low to high. FB_COMP changes from high to low, and through OR gate OR1 and flip-flop RS2, the shutdown timing trigger signal ENN changes from high to low, and SN1 becomes low. After passing through OR gate OR2 and inverter INV1, the control signal SN2 changes from low to high, and the dual-mode adaptive shutdown timer enters the minimum shutdown timing mode. The dual-mode adaptive shutdown timer starts counting. After the minimum shutdown time T1, the dual-mode adaptive shutdown timer output signal OFF_MIN changes from low to high. After passing through RS flip-flop RS2, ENN changes from low to high, and SN2 changes from high to low, ending the timing. After passing through AND gate AND and RS flip-flop RS1, the gate drive control signal MOSFET_SET changes from low to high; NMOS transistor M... H Turn on, NMOS transistor M L Turn off to achieve minimum turn-off time control of the DC-DC converter; When NMOS transistor M H When the drain current exceeds the threshold current, the current detection module outputs a shutdown signal CURRENT_DET that changes from low to high. After passing through OR1 and RS flip-flop RS2, ENN changes from high to low, and the dual-mode adaptive shutdown timer starts counting. SN1 changes from low to high, while SN2 remains low, and the dual-mode adaptive shutdown timer enters overcurrent shutdown timing mode. After passing through OR1 and RS flip-flop RS1, the gate drive control signal MOSFET_SET changes from high to low, and the NMOS transistor M... H Turn off, NMOS transistor M L When the circuit is turned on, the inductor current decreases. After the overcurrent turn-off time T2, the dual-mode adaptive turn-off timer output signal OFF_MIN changes from low to high. Passing through RS flip-flop RS2, ENN changes from low to high, ending the timer. Passing through AND gate and RS flip-flop RS2, the gate drive control signal MOSFET_SET changes from low to high, and the NMOS transistor M... H Turn on, NMOS transistor M L The overcurrent shutdown timing control of the DC-DC converter is implemented.

5. A DC-DC converter using a dual-mode adaptive shutdown timer according to claim 4, characterized in that, The minimum shutdown time T1 of the dual-mode adaptive shutdown timer is adapted to the input signal VIN. When the function selection signal SN1 is low, the dual-mode adaptive shutdown timer is in the minimum shutdown timing mode, and MUX1 and MUX2 open channel 0. When the shutdown timing trigger signal ENN changes from high to low, NMOS transistor MN3 is turned off, SN1 is low, PMOS transistor MP8 is turned on, control signal SN2 is high, PMOS transistor MP10 is turned off, and the drain current I3 of MP9 is obtained from the current source I0 through the current mirror composed of MP2 and MP9. Current I3 flows into capacitor C0, and charging capacitor C0 begins to charge. The voltage V of charging capacitor C0... p The relationship with the minimum turn-off time T1 is as follows: When the voltage V of the charging capacitor C0 p Charging ends after the reference voltage VREF0 at channel 0 input of MUX2 is reached. The reference voltage VREF0 is expressed as: but: Where T1 represents the minimum shutdown time.

6. A DC-DC converter using a dual-mode adaptive shutdown timer according to claim 4, characterized in that, The dual-mode adaptive shutdown timer adapts its overcurrent shutdown time T2 to the input signal VIN and the output feedback signal V. FB When the function selection signal SN1 is high, the dual-mode adaptive shutdown timer is in overcurrent shutdown timing mode, MUX1 and MUX2 turn on channel 1, and MP8 is turned off; ENN changes from high to low, MN3 is turned off, SN1 is high, PMOS transistor MP8 is turned off, control signal SN2 is low, PMOS transistor MP10 is turned on, and currents I1 and I2 flow into charging capacitor C0, and charging capacitor C0 begins to charge; the drain current I1 of MP4 is obtained from the current source I0 through the current mirror composed of MP2 and MP4; the drain current I2 of MP7 is obtained from the current mirror composed of MP5 and MP7 with a ratio of 1:K1; by adjusting the dimensions of MP3 and MP6, the emitter junction voltage V of Q1 is ensured. BE1 Equal to the emitter-junction voltage V of Q2 BE2 Then the drain current I4 of MP5 is expressed as: Currents I1 and I2 flow into capacitor C0, and capacitor C0 begins to charge. The voltage V of capacitor C0... p The relationship with the overcurrent turn-off time T2 is as follows: When the voltage V of the charging capacitor C0 p Charging ends after the reference voltage VREF1 at channel 1 of MUX2 is reached. The magnitude of the reference voltage VREF1 can be expressed as: but: Where T2 represents the overcurrent turn-off time.

Images