Display device, display module including the display device, and electronic device including the display device or the display module

Abstract

The present invention relates to a display device, a display module including the display device, and an electronic device including the display device or the display module. A display device with low power consumption and high display quality is provided. The display device includes a first electrode and a second electrode. A pixel includes: an area in which the distance between the first electrode and the second electrode is constant, and an area in which the distance varies. This structure enables the switching operation of the liquid crystal to start in a predetermined area, thereby improving the stability of the liquid crystal operation. The pixel area is divided into two areas, wherein when switching is performed, the liquid crystal is aligned in two respective directions in the two areas, thereby improving the viewing angle characteristics. In addition, the potential applied to the third electrode suppresses the confusion of the alignment of the liquid crystal, thereby improving the display quality.

Description

Technical Field

[0001] An embodiment of the present invention relates to a display device, and more particularly, to a liquid crystal display device including a liquid crystal element.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the present invention disclosed in this specification, etc. relates to a product, a method, or a manufacturing method. In addition, the present invention relates to a process, a machine, a manufacturing, or a composition of matter thereof. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, an energy storage device, a memory device, and a driving method or a manufacturing method thereof.

[0003] In this specification, etc., a display device refers to any device having a display function. The display device may include semiconductor elements such as transistors, semiconductor circuits, computing devices, memory devices, etc. The display device also includes a driver circuit for driving a plurality of pixels, etc. The display device also includes a control circuit, a power supply circuit, a signal generating circuit, etc. provided on another substrate. Background Art

[0004] The transistors used in most flat panel displays represented by liquid crystal display devices and light-emitting display devices are made of silicon semiconductors (such as amorphous silicon, single crystal silicon and polycrystalline silicon provided on a glass substrate). Transistors made of these silicon semiconductors are also used in integrated circuits (ICs) and the like. In recent years, the technology of manufacturing transistors using metal oxides with semiconductor properties instead of silicon semiconductors has received attention. In this specification, metal oxides with semiconductor properties are referred to as oxide semiconductors. For example, a technology is disclosed in which transistors are manufactured using zinc oxide or In-Ga-Zn-based oxides as oxide semiconductors, and such transistors are used as switching elements in pixels of display devices, etc. (see patent documents 1 and 2).

[0005] [literature]

[0006] [Patent Document]

[0007] [Patent Document 1] Japanese Patent Application No. 2007-123861

[0008] [Patent Document 2] Japanese Patent Application No. 2007-096055 Summary of the invention

[0009] An object of one embodiment of the present invention is to provide a new display device with no deterioration in display quality. Another object of one embodiment of the present invention is to provide a new display device with low power consumption. Another object of one embodiment of the present invention is to provide a new display device. Note that the description of these objects does not prevent the existence of other objects. In one embodiment of the present invention, it is not necessary to achieve all objects. Other objects will be clear and can be derived from the description, drawings, claims, etc. of this specification.

[0010] One embodiment of the present invention is a display device including a pixel. The pixel includes a first electrode, a second electrode, a liquid crystal and a substrate. The first electrode and the second electrode are located on the substrate. An electric field parallel to the substrate is generated by the potential provided to the first electrode and the second electrode. The liquid crystal is driven by the electric field generated between the first electrode and the second electrode. The pixel includes a region where the distance between the first electrode and the second electrode is constant and a region where the distance between the first electrode and the second electrode varies.

[0011] Another embodiment of the present invention is a display device including a pixel. The pixel includes: first to third electrodes, liquid crystal, a first substrate and a second substrate. The first electrode and the second electrode are on the first substrate. The third electrode is on the side of the second substrate facing the first substrate. An electric field parallel to the first substrate is generated by the potential applied to the first electrode and the second electrode. A potential is applied to the third electrode. The liquid crystal is driven by the electric field generated between the first to third electrodes. The pixel includes a region where the distance between the first electrode and the second electrode is constant and a region where the distance between the first electrode and the second electrode varies.

[0012] Another embodiment of the present invention is a display device including a pixel. The pixel includes: a first electrode, a second electrode, a liquid crystal, a substrate, and a switching element. The first electrode and the second electrode are located on the substrate. An electric field parallel to the substrate is generated by the potential provided to the first electrode and the second electrode. The liquid crystal is driven by the electric field generated between the first electrode and the second electrode. The pixel includes a region where the distance between the first electrode and the second electrode is constant and a region where the distance between the first electrode and the second electrode varies.

[0013] Another embodiment of the present invention is a display device including a pixel. The pixel includes: first to third electrodes, liquid crystal, a first substrate and a second substrate, and a switching element. The first electrode and the second electrode are located on the first substrate. The third electrode is on the side of the second substrate facing the first substrate. An electric field parallel to the first substrate is generated by the potential applied to the first electrode and the second electrode. A potential is applied to the third electrode. The liquid crystal is driven by the electric field generated between the first to third electrodes. The pixel includes a region where the distance between the first electrode and the second electrode is constant and a region where the distance between the first electrode and the second electrode varies.

[0014] Another embodiment of the present invention is a display device, wherein the switching element is located on a first substrate.

[0015] Another embodiment of the present invention is a display device, wherein the switching element is a field effect transistor.

[0016] Another embodiment of the present invention is a display device, wherein the switching element includes an oxide semiconductor.

[0017] Another embodiment of the present invention is an electronic device including the display device and at least one of a switch, a speaker, and a housing.

[0018] According to one embodiment of the present invention, a new display device with no deterioration in display quality can be provided. According to another embodiment of the present invention, a new display device with low power consumption can be provided. According to another embodiment of the present invention, a new display device can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a top view illustrating one embodiment of a pixel of a display device;

[0020] Figure 2 is a cross-sectional view showing an embodiment of a display device;

[0021] Figure 3A and 3B 1. A top view and a circuit diagram showing an embodiment of a display device, respectively;

[0022] Figures 4A-4C One embodiment of the optical characteristics of the liquid crystal element and the operation of the liquid crystal molecules is exemplarily shown.

[0023] Figure 5A and 5B One embodiment of the operation of liquid crystal molecules is exemplarily shown.

[0024] Figure 6 is a block diagram showing the configuration of a liquid crystal display device having a display function;

[0025] Fig. 7A and Figure 7B shows the configuration of a display portion of a liquid crystal display device having a display function;

[0026] Figure 8 shows the configuration of a display portion of a liquid crystal display device having a display function;

[0027] Fig. 9 is a circuit diagram showing a liquid crystal display device having a display function;

[0028] Figure 10A-1 , 10A-2 , 10B-1, 10B-2 and Fig. 10C The source line inversion driving and dot inversion driving of a liquid crystal display device having a display function are shown;

[0029] Fig.11 is a timing diagram showing source line inversion driving and dot inversion driving of a liquid crystal display device having a display function;

[0030] Fig. 12A shows the configuration of the display device, and Fig. 12B schematically shows image data generated by the display device;

[0031] Fig.13A and Fig. 13B are a top view and a cross-sectional view respectively showing one embodiment of a semiconductor device;

[0032] Fig.14A and Fig. 14B are a top view and a cross-sectional view respectively showing one embodiment of a semiconductor device;

[0033] Fig.15A and Fig. 15B Each of them is a cross-sectional view showing one embodiment of a semiconductor device;

[0034] Figures 16A-16D is a cross-sectional view showing one embodiment of a method for manufacturing a semiconductor device;

[0035] Figures 17A-17C is a cross-sectional view showing one embodiment of a method for manufacturing a semiconductor device;

[0036] Figures 18A-18C is a cross-sectional view showing one embodiment of a method for manufacturing a semiconductor device;

[0037] Fig.19A and 19B is a cross-sectional view showing one embodiment of a method for manufacturing a semiconductor device;

[0038] Fig. 20A and 20B are a top view and a cross-sectional view respectively showing one embodiment of a semiconductor device;

[0039] Figures 21A-21D is a cross-sectional view showing one embodiment of a method for manufacturing a semiconductor device;

[0040] Figures 22A-22C is a cross-sectional view showing one embodiment of a method for manufacturing a semiconductor device;

[0041] Fig.23A and 23B are a top view and a cross-sectional view respectively showing one embodiment of a semiconductor device;

[0042] Figures 24A-24D is a cross-sectional view showing one embodiment of a method for manufacturing a semiconductor device;

[0043] Figures 25A-25C is a cross-sectional view showing one embodiment of a method for manufacturing a semiconductor device;

[0044] Figures 26A-26C is a Cs-corrected high-resolution TEM image of a cross section of CAAC-OS; and Fig.26D is a schematic cross-sectional view of a CAAC-OS;

[0045] Figures 27A-27D This is a Cs-corrected high-resolution TEM image of one surface of CAAC-OS;

[0046] Figures 28A-28C shows structural analysis of CAAC-OS and single crystal oxide semiconductors using XRD;

[0047] Fig.29A and 29B shows the electron diffraction pattern of CAAC-OS;

[0048] Fig.30 shows the changes in the crystal portion of In-Ga-Zn caused by electron irradiation;

[0049] Fig.31 A method for depositing CAAC-OS is shown;

[0050] Figures 32A-32C InMZnO4 crystal is shown;

[0051] Figures 33A-33F A method for depositing CAAC-OS is shown;

[0052] Figures 34A-34Care a top view and a cross-sectional view showing an example of a transistor;

[0053] Figures 35A-35D is a cross-sectional view showing an example of a transistor;

[0054] Fig.36A and 36B The band structure is shown;

[0055] Fig.37A and 37B are a top view and a cross-sectional view showing an example of a transistor;

[0056] Fig.38 is a top view showing an embodiment of a display device;

[0057] Fig.39 is a cross-sectional view showing an embodiment of a display device;

[0058] Fig.40 is a cross-sectional view showing an embodiment of a display device;

[0059] Fig.41 is a cross-sectional view showing an embodiment of a display device;

[0060] Fig.42 is a top view showing one embodiment of a pixel of a display device;

[0061] Fig.43 is a cross-sectional view showing an embodiment of a display device;

[0062] Fig.44A and Fig.44B are respectively a top view and a cross-sectional view showing an embodiment of a display device;

[0063] Fig.45A and Fig.45B shows a display on a display device;

[0064] Fig.46A and Fig.46B shows a display on a display device;

[0065] Figures 47A-47E is an example showing a method of displaying an image on a display device;

[0066] Figures 48A-48E is an example showing a method of displaying an image on a display device;

[0067] Fig.49 A display module is shown;

[0068] Figures 50A-50G An electronic device is shown;

[0069] Figures 51A-51D The calculation results of Example 1 are shown;

[0070] Fig.52A and 52B The calculation results of Example 1 are shown;

[0071] Figures 53A-53D The calculation results of Example 2 are shown;

[0072] Fig.54A shows the temporal variation of the gray level of the display device of Example 3; and Fig.54B showing an image displayed thereon;

[0073] Fig.55 The temporal variation of the gray level of the display device of Example 3 is shown;

[0074] Fig.56A is a schematic cross-sectional view of a pixel portion; and Fig.56B The deviation of the gray level in Example 3 is shown as a function of the gray level of the display device. DETAILED DESCRIPTION

[0075] Embodiments of the present invention are described in detail below with reference to the accompanying drawings. Note that the embodiments of the present invention are not limited to the following description, and it is easy for those skilled in the art to understand that various changes and modifications can be made without departing from the concept and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the following embodiments. In addition, in the following embodiments, in different drawings, the same parts with similar functions are represented by the same reference numerals or the same hatching patterns. The description thereof will not be repeated.

[0076] In each of the drawings described in this specification, the size, film thickness or region of each element may be exaggerated for clarity. Therefore, the embodiments of the present invention are not limited to this ratio.

[0077] In this specification, etc., ordinal numbers such as "first", "second", and "third" are used to avoid confusing components. And these terms do not limit these elements in a numerical sense. Therefore, for example, the term "first" can be replaced by the term "second" or "third" when appropriate.

[0078] In this specification, etc., the terms "film" and "layer" may be interchanged. For example, in some cases, the term "conductive film" may be used instead of the term "conductive layer", and the term "insulating layer" may be used instead of the term "insulating film".

[0079] In this specification and the like, for example, if a "semiconductor" has a sufficiently low conductivity, the semiconductor may have the characteristics of an "insulator". In addition, in some cases, "semiconductor" and "insulator" may not be strictly distinguished from each other because the boundary between them is not clear. Thus, in this specification and the like, in some cases, a "semiconductor" may also be referred to as an "insulator". Similarly, in this specification and the like, in some cases, an "insulator" may also be referred to as a "semiconductor".

[0080] In this specification and the like, for example, if a "semiconductor" has a sufficiently high conductivity, the semiconductor may have the characteristics of a "conductor". Moreover, in some cases, "semiconductor" and "conductor" may not be strictly distinguished from each other because the boundary between them is not clear. Therefore, in this specification and the like, in some cases, a "semiconductor" may also be referred to as a "conductor". Similarly, in this specification and the like, in some cases, a "conductor" may also be referred to as a "semiconductor".

[0081] Note that, for example, when using transistors of opposite polarity, or when changing the direction of current in circuit operation, the functions of the "source" and "drain" of a transistor may sometimes be interchangeable. Therefore, in this specification, the terms "source" and "drain" may be used to refer to the drain and source, respectively.

[0082] In this specification, etc., patterning is considered to be performed by a photolithography process. Note that patterning is not limited to the photolithography process, and a process other than the photolithography process may be used.

[0083] Furthermore, after the etching process, the mask formed in the photolithography process is removed.

[0084] In this specification, etc., a silicon oxynitride film refers to a film in which the proportion of oxygen is greater than the proportion of nitrogen. The silicon oxynitride film preferably contains oxygen, nitrogen, silicon, and hydrogen in the ranges of 55 atomic % to 65 atomic %, 1 atomic % to 20 atomic %, 25 atomic % to 35 atomic %, and 0.1 atomic % to 10 atomic %. In addition, a silicon nitride oxide film refers to a film in which the proportion of nitrogen is greater than the proportion of oxygen. The silicon nitride oxide film preferably contains nitrogen, oxygen, silicon, and hydrogen in the ranges of 55 atomic % to 65 atomic %, 1 atomic % to 20 atomic %, 25 atomic % to 35 atomic %, and 0.1 atomic % to 10 atomic %.

[0085] (Example 1)

[0086] In this embodiment, refer to Figure 1 , Figure 2 , Figure 3A and 3B , Figures 4A-4C as well as Figure 5A and 5BA display device 80 according to an embodiment of the present invention will be described.

[0087] Figure 3A The display device 80 shown in FIG. 8 includes: a pixel portion 71; a scan line drive circuit 74; a signal line drive circuit 76; m scan lines 77, which are arranged in parallel or substantially parallel to each other, and whose potentials are controlled by the scan line drive circuit 74; and n signal lines 79, which are arranged in parallel or substantially parallel to each other, and whose potentials are controlled by the signal line drive circuit 76. The pixel portion 71 includes a plurality of pixels 70 arranged in a matrix. In addition, common lines 75 are arranged in parallel or substantially parallel to each other along the scan lines 77. In some cases, the scan line drive circuit 74 and the signal line drive circuit 76 are collectively referred to as a drive circuit portion.

[0088] In the pixel portion 71, each scan line 77 is electrically connected to n pixels 70 in a corresponding row among the pixels 70 arranged in m rows and n columns. Each signal line 79 is electrically connected to m pixels 70 in a corresponding column among the pixels 70 arranged in m rows and n columns. Note that m and n are each an integer of 1 or greater. The common line 75 is electrically connected to n pixels 70 in a corresponding row among the pixels 70 arranged in m rows and n columns.

[0089] Figure 3B Shows the available Figure 3A An example of a circuit structure of a pixel 70 of a display device 80 is shown.

[0090] Figure 3B The pixel 70 includes: a liquid crystal element 51 , a transistor 52 and a capacitor 55 .

[0091] One of the pair of electrodes of the liquid crystal element 51 is electrically connected to the signal line 79 through the transistor 52. The potential of the one of the pair of electrodes of the liquid crystal element 51 is appropriately set according to the specification of the pixel 70. The other of the pair of electrodes of the liquid crystal element 51 is connected to the common line 75 and a common potential is applied. The alignment state of the liquid crystal included in the liquid crystal element 51 is controlled by the data provided by the transistor 52.

[0092] The liquid crystal element 51 controls the transmission and non-transmission of light by the light modulation action of the liquid crystal. Note that the light modulation action of the liquid crystal is controlled by the electric field (including the horizontal electric field, the vertical electric field and the inclined electric field) applied to the liquid crystal. As the liquid crystal used for the liquid crystal element 51, thermotropic liquid crystal, low molecular liquid crystal, high molecular liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. Depending on the situation, these liquid crystal materials present a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc.

[0093] In the case of using a horizontal electric field mode, a liquid crystal in a blue phase that does not require an alignment film can be used. The blue phase is one of the liquid crystal phases, which occurs just before the cholesteric phase becomes an isotropic phase when the temperature of the cholesteric liquid crystal increases. Because the blue phase only appears within a narrow temperature range, a liquid crystal component in which a chiral material is mixed with several weight percentages or more is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composite including a liquid crystal in a blue phase and a chiral material has a short response time and optical isotropy. In addition, a liquid crystal composite including a liquid crystal in a blue phase and a chiral material does not require an alignment treatment and has a small viewing angle dependence. There is no need to provide an alignment film, and thus, no friction process is required; accordingly, electrostatic discharge damage caused by the friction process can be avoided, and defects and damage to the liquid crystal display device in the manufacturing process can be reduced.

[0094] Note that a liquid crystal material having positive or negative dielectric anisotropy may be used for the liquid crystal layer. In some cases, the use of a material having negative dielectric anisotropy may suppress the influence of a flexoelectric effect due to polarization of liquid crystal molecules included in the liquid crystal material of the liquid crystal layer. The liquid crystal material may be appropriately selected according to the operation mode of the liquid crystal.

[0095] The display device 80 including the liquid crystal element 51 can be driven in the following modes: twisted nematic (TN) mode, in-plane switching (IPS) mode, fringe field switching (FFS) mode, axisymmetric alignment microcell (ASM) mode, optically compensated birefringence (OCB) mode, ferroelectric liquid crystal (FLC) mode, or antiferroelectric liquid crystal (AFLC) mode, etc.

[0096] The display device 80 may be a normally black liquid crystal display device, such as a vertical alignment (VA) mode transmissive liquid crystal display device. As the vertical alignment mode, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, or an advanced super-visual (ASV) mode may be used.

[0097] In this embodiment, the horizontal electric field mode represented by the FFS mode is mainly described.

[0098] exist Figure 3B In the pixel 70, one of the source electrode and the drain electrode of the transistor 52 is electrically connected to the signal line 79, and the other is electrically connected to one of a pair of electrodes of the liquid crystal element 51. The gate of the transistor 52 is electrically connected to the scanning line 77. The transistor 52 has a function of controlling the transmission and reception of data signals between the signal line 79 and the capacitor 55 and between the signal line 79 and the liquid crystal element 51.

[0099] exist Figure 3BIn the pixel 70, one of the pair of electrodes of the capacitor 55 is connected to the other of the source electrode and the drain electrode of the transistor 52. The other of the pair of electrodes of the capacitor 55 is electrically connected to the common line 75. The potential of the common line 75 is appropriately set according to the specification of the pixel 70. The capacitor 55 serves as a storage capacitor for storing written data. In the display device 80 driven in the FFS mode, one of the pair of electrodes of the capacitor 55 corresponds to part or all of the one of the pair of electrodes of the liquid crystal element 51, and the other of the pair of electrodes of the capacitor 55 corresponds to part or all of the other of the pair of electrodes of the liquid crystal element 51.

[0100] Next, a specific structure of a pixel included in the display device 80 will be described. Figure 1 A top view of a plurality of pixels 70 a and 70 b included in a display device 80 driven in the FFS mode is shown.

[0101] Figure 2 Shown along Figure 1 The cross-sectional view is obtained along the dot-dash line Q1-R1 and the dot-dash line S1-T1. Figure 2 The transistor 52 in FIG. 1 is a channel-etched transistor. The transistor 52 along the channel length direction is shown in the cross-sectional view taken along the dashed line Q1 - R1 , and the transistor 52 along the channel width direction is shown in the cross-sectional view taken along the dashed line S1 - T1 .

[0102] exist Figure 1 In the figure, the conductive film 13 extends substantially perpendicularly to the signal line 79 (conductive film 21a) (in the horizontal direction in the figure). The conductive film 21a extends substantially perpendicularly to the scanning line 77 (conductive film 13) (in the vertical direction in the figure).

[0103] The conductive film 13 is electrically connected to the scanning line driving circuit 74, and the conductive film 21a is electrically connected to the signal line driving circuit 76 ( Figure 3A ).

[0104] The transistor 52 is arranged near the intersection of the conductive film 13 and the conductive film 21a. The transistor 52 includes: the conductive film 13 as a gate electrode, the oxide semiconductor film 19a formed on the insulating films 15 and 17 in which a channel region is formed, and the conductive film 21ah and the conductive film 21b as a source electrode and a drain electrode. The conductive film 13 also serves as a scan line, and the region where the conductive film 13 overlaps with the oxide semiconductor film 19a serves as the gate electrode of the transistor 52. The conductive film 21a also serves as a signal line, and the region where the conductive film 21a overlaps with the oxide semiconductor film 19a serves as the source electrode or the drain electrode of the transistor 52. Figure 1In the top view in FIG. 1 , the end of the conductive film 13 is located on the outer side of the end of the oxide semiconductor film 19a. Thus, the scanning line acts as a light blocking film to block light from a light source such as a backlight. For this reason, the oxide semiconductor film 19a included in the transistor is not irradiated with light, so that changes in the electrical characteristics of the transistor can be suppressed (see FIG. 1 ). Figure 1 and Figure 2 ).

[0105] The conductive film 21b is electrically connected to the oxide semiconductor film 19b as a pixel electrode. The common electrode 29 is provided on the oxide semiconductor film 19b with the insulating film 27 therebetween (see FIG. 21b). Figure 2 ).

[0106] The common electrode 29 includes a region extending in a direction crossing the signal line. The region is connected to a region extending parallel or substantially parallel to the signal line. Therefore, in a plurality of pixels included in the display device 80, the strip-shaped region of the common electrode 29 has the same potential.

[0107] The capacitor 55 is formed in a region where the oxide semiconductor film 19b and the common electrode 29 overlap each other. The oxide semiconductor film 19b and the common electrode 29 can transmit light. That is, the capacitor 55 can transmit light.

[0108] In the case where the capacitor 55 is light-transmitting, a large capacitor 55 (large area) can be formed in the pixel 70. In this way, a display device with large capacitance and high aperture ratio (generally 50% or higher, preferably 60% or higher) can be obtained. For example, in a high-resolution display device (such as a high-resolution liquid crystal display device), the pixel area is small, and accordingly, the area of ​​the capacitor is also small. Therefore, in a high-resolution display device, the amount of charge accumulated in the capacitor is small. However, when the light-transmitting capacitor 55 of the present embodiment is provided in each pixel, sufficient capacitance can be obtained in the pixel, and the aperture ratio can be increased. Typically, the capacitor 55 can be advantageously used in a high-resolution display device with a pixel density of 200 pixels per inch (ppi) or higher, 300ppi or higher, or 500ppi or higher.

[0109] In a liquid crystal display device, an increase in the capacitance of the capacitor can increase the time period during which the alignment of the liquid crystal molecules in the liquid crystal element can remain constant when an electric field is applied. When a still image is displayed, this time period can be made longer; therefore, the number of times the image data is rewritten can be reduced, which reduces power consumption. In addition, even in the case of a high-resolution display device, the structure of this embodiment can increase the aperture ratio, which makes it possible to effectively use the light from the light source (e.g., backlight), thereby reducing the power consumption of the display device.

[0110] Figure 2The transistor 52 in has a single gate structure and includes a conductive film 13 provided on a substrate 11 and serving as a gate. The transistor 52 also includes: an insulating film 15 formed on the substrate 11 and the conductive film 13 serving as a gate; an insulating film 17 formed on the insulating film 15; an oxide semiconductor film 19a overlapping the conductive film 13 serving as a gate, with the insulating film 15 and the insulating film 17 located therebetween; and conductive films 21a and 21b contacting the oxide semiconductor film 19a and serving as a source electrode and a drain electrode. The insulating film 23 is formed on the insulating film 17, the oxide semiconductor film 19a, and the conductive films 21a and 21b serving as a source electrode and a drain electrode. The insulating film 25 is formed on the insulating film 23. The oxide semiconductor film 19b is formed on the insulating film 25. The oxide semiconductor film 19b is electrically connected to one of the conductive films 21a and 21b serving as a source electrode and a drain electrode (here, the conductive film 21b) through openings provided in the insulating film 23 and the insulating film 25. The insulating film 27 is formed over the insulating film 25 and the oxide semiconductor film 19 b . The common electrode 29 is formed over the insulating film 27 .

[0111] A film formed simultaneously with the oxide semiconductor film 19 b may be provided over the insulating film 25 so as to overlap with the oxide semiconductor film 19 a , in which case the transistor 52 has a dual-gate structure in which the oxide semiconductor film 19 b functions as a second gate.

[0112] The region where the oxide semiconductor film 19b, the insulating film 27, and the common electrode 29 overlap each other functions as a capacitor 55. The capacitor 55 can prevent a potential from being lowered during a period in which a pixel is not selected, thereby improving display quality.

[0113] exist Figure 1 , each of the pixels 70a and 70b includes a region 522a and a region 522b. When viewed from above, the oxide semiconductor film 19b and the common electrode 29 in the region 522a and the oxide semiconductor film 19b and the common electrode 29 in the region 522b are line-symmetrical with respect to the portion of the common electrode 29 extending parallel to the conductive film 13.

[0114] A common electrode is preferably provided at the boundary between the two regions 522a, 522b for the following reasons: In this structure, when the liquid crystal is driven by applying an electric field in the two regions, the liquid crystal is aligned symmetrically with respect to the common electrode line at the boundary between the two regions 522a, 522b as an axis.

[0115] like Figure 1As in the pixel 70b in FIG. 1 , the oxide semiconductor film 19b as the pixel electrode in the region 522a has: a region 524a in which a plurality of patterns having a plurality of slits (comb-like) are arranged in parallel to the common electrode 29; and regions 524b, 524c in which the patterns are not parallel to the common electrode 29. In other words, the pixel has: a region 524a in which the common electrode 29 and the oxide semiconductor film 19b as the pixel electrode are arranged in parallel to each other, a region 524b in which the oxide semiconductor film 19b is bent toward the common electrode 29, and a region 524c in which the common electrode 29 is bent toward the oxide semiconductor film 19b.

[0116] The oxide semiconductor film 19b as the pixel electrode in the region 52 has: a region 526a in which a plurality of patterns having a plurality of slits (comb-shaped) are arranged in parallel to the common electrode 29; and regions 526b, 526c in which the patterns are not parallel to the common electrode 29. In other words, the pixel has: a region 526a in which the common electrode 29 and the oxide semiconductor film 19b as the pixel electrode are arranged in parallel to each other, a region 526b in which the common electrode 29 is bent toward the oxide semiconductor film 19b, and a region 526c in which the oxide semiconductor film 19b is bent toward the common electrode 29.

[0117] In regions 524a and 526a (which are the central portions of regions 52a and 52b), the slits of the pixel electrode and the slits of the common electrode are arranged at regular intervals. In regions 524b, 524c, 526b, and 526c arranged near the peripheries of regions 522a and 522b, the slits of the pixel electrode and the slits of the common electrode are not arranged at regular intervals, but the intervals gradually decrease toward the peripheries of regions 52a and 52b.

[0118] Refer to the following Figures 4A-4C The role of such an electrode pattern in the pixel portion is described.

[0119] The liquid crystal material has fluidity. When a voltage is applied between the pixel electrode and the common electrode, the liquid crystal molecules 800 included in the liquid crystal material interact with the electric field generated between the pixel electrode and the common electrode to move, so that the alignment is changed from the initial state.

[0120] Figures 4A to 4C The response of a liquid crystal material to an electric field is schematically shown. Figures 4A to 4C In the example of FIG. 8 , the alignment of the liquid crystal molecules 800 is changed by an electric field generated between electrodes 802 and 804 on a substrate 806. The liquid crystal material is positioned between the substrate 806 and the substrate 807 and includes the liquid crystal molecules 800. Figure 4A , the horizontal axis represents the voltage between electrodes 802 and 804, and the vertical axis represents the transmittance. Figure 4BThe schematic diagram shows that the strength of the electric field between electrodes 802 and 804 on substrate 806 is low, for example, less than or equal to Figure 4A The orientation of the liquid crystal molecules 800 at Vmin in the state. The orientation changes with the increase of the electric field strength; the stronger the electric field, the Figure 4B The larger the rotation angle of the state ( Figure 4C ).

[0121] The liquid crystal molecules have a rod shape. The liquid crystal molecules may have positive or negative dielectric constant anisotropy. The response of the liquid crystal molecules 800 to incident polarized light changes according to the relationship between the vibration plane of the polarized light and the direction in which the liquid crystal molecules are aligned. In other words, the liquid crystal molecules 800 have refractive index anisotropy. The refractive index anisotropy of the liquid crystal may lead to viewing angle dependence.

[0122] At the same time, the liquid crystal element can be divided into a plurality of regions with different alignment directions. Therefore, when the liquid crystal element is divided into a plurality of regions in respective alignment states, the refractive index anisotropy in one region can be offset by the refractive index anisotropy in another region. This method can be used to reduce the viewing angle dependence. Specifically, the refractive index anisotropy is balanced between one region and another region, thereby reducing the viewing angle dependence.

[0123] When the electrode pattern is bent at the pixel centerline, molecular switching is performed in two different directions. Figure 5A and 5B Schematically shows a top view of a substrate on which pixel electrodes and common electrodes and liquid crystal molecules 800 are arranged. Figure 5A and 5B In the example, the liquid crystal molecules 800 above the dot-dashed line AB and the liquid crystal molecules 800 below the dot-dashed line AB are aligned in two directions, respectively. Figure 5A 8 shows an initial state, in which no electric field is applied between the pixel electrode 808 and the common electrode 810, and Figure 5B shows the state of applying electric field. Figure 5B As shown, the tilt angle of the liquid crystal molecules 800 above the dot-dash line AB is different from the tilt angle of the liquid crystal molecules 800 below the dot-dash line AB.

[0124] In this structure, the refractive index anisotropy can be balanced as follows: before the electric field is applied, the liquid crystal molecules are aligned in Figure 5A in one direction as shown; when an electric field is applied, Figure 5B As shown, the alignment is different for two regions horizontally divided by the dot-dash line AB. Figure 1 An example in which this method is applied to a pixel portion of a display device 80 is shown.

[0125] Generally, liquid crystal molecules in a liquid crystal cell are aligned so that their long axes face substantially the same direction; however, alignment disorder (alignment defect) may occur in one portion. The light transmission properties of a portion with alignment disorder differ from those of a well-aligned portion.

[0126] In addition, although as described above, the rotation angle relative to the initial alignment state increases with the increase in the intensity of the electric field, the rotation angle saturates at a certain angle. As long as the electric field intensity is within the range where the rotation angle is not saturated, the rotation angle changes between regions with different electric field intensity on the same plane. The liquid crystal in the region with higher electric field intensity moves first. The electric field intensity is obtained by dividing the potential difference by the distance between the electrodes. Therefore, in the case of providing a constant potential to each of the pixel electrode and the common electrode, the electric field intensity is more likely to change in the region where the distance between the pixel electrode and the common electrode is smaller. A sudden change in the electric field intensity is likely to cause a significant alignment disorder of the liquid crystal; on the contrary, a slow change in the electric field intensity rarely causes alignment disorder.

[0127] In the structure of this embodiment in which the distance between the pixel electrode and the common electrode is gradually reduced, a region where the direction of the lines of electric force generated between the pixel electrode and the common electrode suddenly changes can be eliminated, whereby alignment defects can be reduced.

[0128] exist Figure 1 In the top view of FIG. 2 , the common electrode 29 is provided adjacent to the conductive film 21a. In this structure, the common electrode 29 blocks the electric field generated from the conductive film 21a to the oxide semiconductor film 19b; therefore, alignment defects can be reduced, and thus display quality can be improved.

[0129] When a light-blocking conductive material is used for the portion of the common electrode 29 that is disposed between the two regions 522a and 522b and extends parallel to the conductive film 13, the common electrode 29 can mask the alignment defect of the liquid crystal that occurs at the boundary between the two regions 522a and 522b, thereby preventing the user of the display device from perceiving the alignment defect. Therefore, the display quality can be improved.

[0130] In addition, although most of the conductive film 21a has a linear pattern, the pattern width is small in the regions 528a and 528b. This structure makes it possible to reduce the parasitic capacitance between the conductive film 21a and the common electrode 29, thereby suppressing an increase in power consumption.

[0131] Therefore, by Figure 1 By arranging the conductive film 21a, the oxide semiconductor film 19b, and the common electrode 29 as in FIG. 1 , the viewing angle characteristics can be improved, the liquid crystal molecules can be driven more stably, and the power consumption can be reduced.

[0132] Note that this embodiment can be combined with any other embodiments in this specification as appropriate.

[0133] (Example 2)

[0134] In this embodiment, reference will be made to Figure 6 and Fig. 7A and 7B An example of a liquid crystal display device including a display portion including the pixels described in Embodiment 1 is described.

[0135] Figure 6 : is a block diagram showing the configuration of a liquid crystal display device having a display function according to one embodiment of the present invention.

[0136] Fig. 7A and 7B 1 and 2 are a top view and a circuit diagram, respectively, showing the configuration of a display portion of a liquid crystal display device having a display function according to an embodiment of the present invention.

[0137] <1. Configuration of Liquid Crystal Display Device>

[0138] In this embodiment, reference will be made to Figure 6 A liquid crystal display device 600 having a display function is described. The liquid crystal display device 600 includes: an operation device 620, a control part 610, a display part 630 and an input unit 500.

[0139] The display portion 630 includes a pixel portion 631. The pixel portion 631 includes a plurality of pixels 631p, and each pixel 631p includes a pixel circuit 634.

[0140] Next, the relationship between these components will be summarized. First, the arithmetic device 620 outputs a primary control signal 625_C and a primary image signal 625_V to the control portion 610 .

[0141] The input unit 500 is provided to output a control signal to the operation device 620 , whereby a signal based on information provided to the input unit by a user may be output from the operation device 620 to the control portion 610 .

[0142] The control section 610 controls a signal line driver circuit (hereinafter referred to as an S driver circuit 633 ) and a scan line driver circuit (hereinafter referred to as a G driver circuit 632 ).

[0143] The G driver circuit 632 outputs a G signal 632_G. By controlling the G signal 632_G, the frequency of selecting a pixel circuit among the plurality of pixel circuits 634 provided in the pixel portion 631 can be changed.

[0144] In a display device having the configuration of this embodiment, operation can be switched between the following modes: an operation mode for displaying smooth moving images and an operation mode for displaying images at a lower frame rate, thereby reducing power consumption and achieving an eye-friendly display with less flicker.

[0145] For example, the following modes may be adopted: a first mode in which a G signal for selecting a pixel is output at a frequency of 60 Hz or higher, and a second mode in which a G signal is output at a frequency of 1 Hz or lower (preferably, 0.2 Hz or lower).

[0146] As a result, the liquid crystal display device 600 can have a display function that generates less eye fatigue of the user.

[0147] The elements of a liquid crystal display device having a display function according to one embodiment of the present invention will be described below.

[0148] <2. Computing Device>

[0149] The computing device 620 generates a primary image signal 625_V and a primary control signal 625_C.

[0150] The primary control signal 625_C generated by the computing device 620 includes a mode switching signal.

[0151] For example, the operation device 620 may output a primary control signal 625_C including a mode switching signal according to the image switching signal 500_C output from the input unit 500 .

[0152] <3. Control section>

[0153] The control part 610 outputs a secondary image signal 615_V generated from the primary image signal 625_V. Figure 6 The primary image signal 625_V is output to the S driver circuit 633, but one embodiment of the present invention is not limited to this configuration, and the primary image signal 625_V may be directly output to the display portion 630.

[0154] The control part 610 has a function of generating a secondary control signal 615_C (such as a start pulse signal SP, a latch signal LP, and a pulse width control signal PWC) using a primary control signal 625_C (including a synchronization signal such as a vertical synchronization signal or a horizontal synchronization signal), and providing the secondary control signal to the display part 630. The secondary control signal 615_C also includes a clock signal CK and the like.

[0155] The control section 610 may be provided with an inversion control circuit so as to have a function of inverting the polarity of the secondary image signal 615_V at a timing notified by the inversion control circuit. Specifically, the polarity of the secondary image signal 615_V may be inverted in the control section 610, or may be inverted in the display section 630 according to an instruction from the control section 610.

[0156] The inversion control circuit has a function of determining the timing of inverting the polarity of the secondary image signal 615_V using the synchronization signal. For example, the inversion control circuit includes a counter and a signal generating circuit.

[0157] The counter has a function of counting the number of frame periods by using the pulses of the horizontal synchronization signal.

[0158] The signal generating circuit has a function of notifying control section 610 of a timing of inverting the polarity of secondary image signal 615_V, thereby inverting the polarity of secondary image signal 615_V every a plurality of consecutive frame periods by using information on the number of frame periods obtained by the counter.

[0159] <4. Display section>

[0160] The display portion 630 includes: a pixel portion 631 including a display element 635 in each pixel; and a driver circuit such as an S driver circuit 633 and a G driver circuit 632. The pixel portion 631 includes a plurality of pixels 631p, each of which is provided with a display element 635 (see Figure 6 ).

[0161] The secondary image signal 615_V input from the control section 610 to the display section 630 is supplied to the S driver circuit 633. In addition, a power supply potential is supplied to the S driver circuit 633 and the G driver circuit 632, and the secondary control signal 615_C is supplied to the G driver circuit 632.

[0162] The S driver circuit 633 holds the input first drive signal (also referred to as an S signal) 633_S and outputs it to the pixel portion 631. The display element 635 included in the pixel circuit 634 of the pixel portion 631 displays an image according to the S signal 633_S.

[0163] The G driver circuit 632 outputs a second drive signal (G signal) 632_G for selecting the pixel circuit 634 to the pixel portion 631 .

[0164] Note that the secondary control signal 615_C includes: an S driver circuit clock signal CK and an S driver circuit start pulse signal SP for controlling the operation of the S driver circuit 633, a latch signal LP, a G driver circuit clock signal CKG and a driver circuit start pulse SP for controlling the operation of the G driver circuit 632, a pulse width control signal PWC, and the like.

[0165] Fig. 7A One configuration example of the display portion 630 is shown.

[0166] exist Fig. 7A In the display portion 630, a plurality of pixels 631p, a plurality of scanning lines G for selecting the pixels 631p row by row, and a plurality of signal lines S for providing an S signal 633_S generated from a secondary image signal 615_V to the selected pixels 631p are provided in the pixel portion 631.

[0167] The input of the G signal 632_G to the scan line G is controlled by the G driving circuit 632. The input of the S signal 633_S to the signal line S is controlled by the S driving circuit 633. Each of the plurality of pixels 631p is connected to at least one scan line G and at least one signal line S.

[0168] Note that the type and number of wires provided in the pixel portion 631 can be determined according to the configuration, number, and arrangement of the pixels 631p. Fig. 7A In the pixel portion 631 of FIG. 6A , pixels 631 p are arranged in a matrix of x columns and y rows, and signal lines S1 to Sx and scan lines G1 to Gy are arranged in the pixel portion 631 .

[0169] <4-1. Pixels>

[0170] Each pixel 631p includes a pixel circuit 634 including a display element 635.

[0171] <4-2. Pixel Circuit>

[0172] As an example of this embodiment, Figure 7B A configuration of a pixel circuit 634 is shown in which a liquid crystal element 635LC is used as a display element 635.

[0173] The pixel circuit 634 includes a transistor 634t for controlling supply of an S signal 633_S to the liquid crystal element 635LC. An example of a connection relationship between the transistor 634t and the display element 635 will be described.

[0174] The gate of the transistor 634t is connected to one of the scanning lines G1 to Gy. One of the source electrode and the drain electrode of the transistor 634t is connected to one of the signal lines S1 to Sx. The other of the source electrode and the drain electrode of the transistor 634t is connected to the first electrode of the liquid crystal element 635LC.

[0175] As necessary, the pixel 631p may include, in addition to the capacitor 634c for maintaining a voltage between the first electrode and the second electrode of the liquid crystal element 635LC, another circuit element such as a transistor, a diode, a resistor, a capacitor, or an inductor.

[0176] exist Figure 7B In the pixel 631p of FIG. 6A , a transistor 634t is used as a switching element to control the input of the S signal 633_S to the pixel 631p. Alternatively, a plurality of transistors as a switching element can be used for the pixel 631p. A plurality of transistors as a switching element can be connected to each other in parallel, in series, or in a combination of parallel and series.

[0177] Note that the capacitance in the pixel circuit 634 can be appropriately adjusted. For example, in the case where the S signal 633_S is maintained for a relatively long period of time (specifically, 1 / 60 seconds or longer) in the second mode, a capacitor 634c is provided. The capacitance of the pixel circuit 634 can be adjusted using components other than the capacitor 634c. For example, the first electrode and the second electrode of the liquid crystal element 635LC can overlap each other so as to essentially form a capacitor.

[0178] It is also possible to use an oxide semiconductor as a first electrode or a second electrode of a capacitor. For a method of using an oxide semiconductor as an electrode of a capacitor, refer to another embodiment.

[0179] The configuration of the pixel circuit 634 can be selected according to the type of the display element 635 or the driving method.

[0180] <4-2a. Display element>

[0181] The liquid crystal element 635LC includes a first electrode, a second electrode, and a liquid crystal layer containing a liquid crystal material, to which a voltage between the first electrode and the second electrode is applied. In the liquid crystal element 635LC, the alignment of the liquid crystal molecules changes according to the voltage applied between the first electrode and the second electrode, thereby changing the transmittance. Therefore, the transmittance of the display element 635 is controlled by the potential of the S signal 633_S, thereby expressing a gradual change.

[0182] <4-2b. Transistor>

[0183] The transistor 634t controls whether or not the potential of the signal line S is supplied to the first electrode of the display element 635. A predetermined reference potential Vcom is supplied to the second electrode of the display element 635.

[0184] Note that a transistor including an oxide semiconductor can be suitably used as a transistor in a liquid crystal display device of one embodiment of the present invention. For details of the transistor including an oxide semiconductor, refer to Embodiments 7 to 9 or Embodiment 11.

[0185] <5. Light supply section>

[0186] In the case of using a liquid crystal element as the display element 635, a light supplying part 650 is provided to the display part 630. A plurality of light sources are provided in the light supplying part 650. The control part 610 controls the operation of the light sources included in the light supplying part 650.

[0187] In the reflective liquid crystal display device, it is not necessary to set the light supply part 650, because, for example, sunlight can be used as a light source outdoors, and internal lighting can be used as a light source in a room. However, considering the use at night or in a dark environment without a light source or only with a light source with low brightness, the light supply part 650 can be set to supply light to the pixel part 631 including the liquid crystal element; therefore, the displayed image can be seen even in a dark environment.

[0188] The light source of the light supplying part 650 may be a cold cathode fluorescent lamp, a light emitting diode (LED), an OLED element that generates fluorescence (electroluminescence) when an electric field is applied thereto, etc. The light from the light source of the light supplying part 650 may be colored by any of the following systems: a three-color system using red light, green light, and blue light, a quantum dot system or a color conversion system that converts part of the blue light into red light or green light, a color filter system that converts part of the white light into red light, green light, and blue light through a color filter, etc.

[0189] <6. Input unit>

[0190] As the input unit 500, a touch panel, a touch pad, a finger joystick, a trackball, a data glove, an imaging device, etc. can be used. In the computing device 620, the electric signal output from the input unit 500 can be associated with the coordinates of the display part. Therefore, the user can input an instruction for processing information to be displayed on the display part.

[0191] Examples of information input by the user with input unit 500 include: drag instructions for changing the display position of an image on the display portion, swipe instructions for switching a displayed image so as to display a next image, scroll instructions for continuously switching a series of images, selection instructions for a specific image, pinch instructions for changing the size of a displayed image, and input instructions for handwritten characters.

[0192] Multiple display modes, for example, two modes (a first mode and a second mode) are switched in the following manner: when the image switching signal 500_C is input from the input unit 500 through the control part 610 to the G driving circuit 632 operating in the second mode, the G driving circuit 632 switches from the second mode to the first mode, outputs the G signal at least once, and then switches to the second mode.

[0193] <7. Operation examples>

[0194] For example, when the input unit 500 senses a page turning operation, the input unit 500 outputs an image switching signal 500_C to the computing device 620 .

[0195] The operation device 620 generates a primary image signal 625_V including a page turning operation signal, and outputs the primary image signal 625_V and a primary control signal 625_C including an image switching signal 500_C.

[0196] The control portion 610 outputs a secondary control signal 615_C to the G driving circuit 632 , and outputs a secondary image signal 615_V including a page turning operation signal to the S driving circuit 633 .

[0197] The G driving circuit 632 has: a first mode, in which the G signal 632_G is output to the pixel at a frequency of 30 or more times per second (preferably, 60 or more times and less than 960 times per second); and a second mode, in which the G signal 632G is output at a frequency of once or more per day and less than 0.1 times per second (preferably, once or more per hour and less than once per second).

[0198] Note that the G driving circuit 632 is switched between the first mode and the second mode according to the input mode switching signal.

[0199] The G driving circuit 632 is switched from the second mode to the first mode, and outputs a G signal 632_G through a signal rewriting operation at a rate at which a viewer cannot perceive an image change.

[0200] At the same time, the S driving circuit 633 outputs an S signal 633_S generated from the secondary image signal 615_V including the page turning operation signal to the pixel circuit 634 .

[0201] In this manner, the secondary image signal 615_V including the page turning operation signal is supplied to the pixel 631p. Therefore, many frame images including the page turning operation can be displayed in a short time, so that a smooth page turning operation can be displayed.

[0202] The computing device 620 can be configured to determine whether the primary image signal 625_V output from the computing device 620 to the display portion 630 is a motion image signal or a static image signal, and output a switching signal for selecting a first mode when the primary image signal 625_V is a motion image signal, and output a switching signal for selecting a second mode when the primary image signal 625_V is a static image signal.

[0203] Whether the primary image signal 625_V is a moving image signal or a static image signal may be determined based on a difference between a frame signal in the primary image signal 625_V and a previous or next frame signal. When the difference is greater than a predetermined value, the primary image signal 625_V may be determined to be a moving image signal, and when the difference is less than or equal to the predetermined value, it may be determined to be a static image signal.

[0204] Furthermore, the following configuration may be adopted: when switching from the second mode to the first mode, the G driving circuit 632 outputs the G signal 632_G a predetermined number of times (at least once), and then switches to the second mode.

[0205] The configuration described in Example 3 can reduce eye fatigue during use.

[0206] In this embodiment, an embodiment of the present invention is described. Other embodiments of the present invention will be described in other embodiments. Note that an embodiment of the present invention is not limited to this. That is, because various embodiments of the present invention are disclosed in this embodiment and in other embodiments, an embodiment of the present invention is not limited to a specific embodiment. Although an example in which a channel formation region, a source region, a drain region, etc. of a transistor include an oxide semiconductor is described as an embodiment of the present invention, the embodiment of the present invention is not limited to this. Depending on the circumstances or conditions, various transistors of an embodiment of the present invention or a channel formation region, a source region, a drain region, etc. of a transistor may include various semiconductors. Depending on the circumstances or conditions, various transistors of an embodiment of the present invention or a channel formation region, a source region, a drain region, etc. of a transistor may include, for example, at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and an organic semiconductor. Alternatively, for example, depending on the circumstances or conditions, various transistors of an embodiment of the present invention or a channel formation region, a source region, a drain region, etc. of a transistor do not necessarily include an oxide semiconductor.

[0207] Note that this embodiment can be combined with any other embodiments in this specification as appropriate.

[0208] (Example 3)

[0209] <Partial drive>

[0210] In this embodiment, reference will be made to Fig. 7A and 7B and Figure 8 An example of a method for driving a liquid crystal display device is described.

[0211] Fig. 7A and 7B 1 and 2 are a top view and a circuit diagram respectively, showing the configuration of a display portion of a liquid crystal display device having a display function according to an embodiment of the present invention. Figure 8 is a top view showing a modified example of the configuration of the display portion of the liquid crystal display device with a display function of one embodiment of the present invention.

[0212] <1. Method for Writing S Signal to Pixel Portion>

[0213] Use the description to Fig. 7A or Figure 8 An example of a method for writing an S signal 633_S to a pixel portion 631 in the pixel portion 631 will be described. Figure 7B A method of writing an S signal 633_S to each pixel 631p in the pixel circuit.

[0214] <Writing Signals to Pixel Part>

[0215] In the first frame period, the G signal 632_G is input to the scan line G1 so as to select the scan line G1. In each of the plurality of pixels 631p connected to the selected scan line G1, the transistor 634t is turned on.

[0216] When the transistor 634t is turned on (in one line period), the potential of the S signal 633_S generated from the secondary image signal 615_V is supplied to the signal lines S1 to Sx. By each of the transistors 634t being turned on, charges corresponding to the potential of the S signal 633_S are accumulated in the capacitor 634c, and the potential of the S signal 633_S is supplied to the first electrode of the liquid crystal element 635LC.

[0217] When the scan line G1 is selected in the first frame period, the S signal 633_S with positive polarity is continuously input to all the signal lines S1 to Sx. The S signal 633_S with positive polarity is provided to the first electrodes G1S1 to G1Sx in the pixel 631p connected to the scan line G1 and the corresponding signal lines S1 to Sx. Therefore, the transmittance of the liquid crystal element 635LC is controlled by the potential of the S signal 633_S; therefore, the gradient is expressed by the pixel.

[0218] In a similar manner, the scan lines G2 to Gy are sequentially selected, and operations similar to those performed when the scan line G1 is selected are sequentially performed on the pixels 631p connected to the scan lines G2 to Gy. Through the above operations, an image of the first frame can be displayed on the pixel portion 631.

[0219] In one embodiment of the present invention, the scan lines G1 to Gy are not necessarily selected sequentially.

[0220] Dot sequential driving may be adopted in which the S signal 633_S is sequentially input from the S driving circuit 633 to the signal lines S1 to Sx, or row sequential driving may be adopted in which the S signal 633_S is simultaneously input. Alternatively, a driving method in which the S signal 633_S is sequentially input to each of the plurality of signal lines S may be adopted.

[0221] The method for selecting the scanning lines G is not limited to progressive scanning; the scanning lines G may also be selected using interlaced scanning.

[0222] In a given frame period, the polarities of the S signal 633_S input to all signal lines may be the same, or the polarities of the S signal 633_S input to the pixel may be inverted every other signal line.

[0223] <Writing Signals to Pixel Portions Divided into Multiple Regions>

[0224] Figure 8 A modified example of the configuration of the display portion 630 is shown.

[0225] exist Figure 8 In the display portion 630, a plurality of pixels 631p, a plurality of scan lines G for selecting the pixels 631p row by row, and a plurality of signal lines S for providing S signals 633_S to the selected pixels 631p are arranged in a pixel portion 631 divided into a plurality of regions (specifically, a first region 631a, a second region 631b, and a third region 631c).

[0226] The input of the G signal 632_G to the scan line G in each region is controlled by the corresponding G driving circuit 632. The input of the S signal 633_S to the signal line S is controlled by the S driving circuit 633. Each of the plurality of pixels 631p is connected to at least one scan line G and at least one signal line S.

[0227] This configuration allows the pixel portion 631 to be divided into areas that are driven separately.

[0228] For example, it is possible to operate as follows: when information is input from the touch panel used as the input unit 500, the coordinates indicating the area where the information is to be input are obtained, the G driving circuit 632 of the area corresponding to the coordinates is driven to operate in the first mode, and the G driving circuit 632 of another area is driven to operate in the second mode. Therefore, the operation of the G driving circuit for the area to which information is not input from the touch panel (that is, the area where the rewriting of the displayed image is not necessary) can be stopped.

[0229] <2. G Driving Circuit in First Mode and Second Mode>

[0230] The S signal 633_S is input to the pixel circuit 634 to which the G signal 632_G output from the G driving circuit 632 is input. During a period in which the G signal 632_G is not input, the pixel circuit 634 holds the potential of the S signal 633_S. In other words, the pixel circuit 634 holds the state in which the potential of the S signal 633_S is written.

[0231] The pixel circuit 634 to which the display data is written maintains the display state corresponding to the S signal 633_S. Note that maintaining the display state is to maintain the number of changes in the display state within a given range. This given range is appropriately set, and is preferably set so that the user can view the displayed image as the same image.

[0232] The G driving circuit 632 has a first mode and a second mode.

[0233] <2-1. First Mode>

[0234] The G driving circuit 632 in the first mode outputs a G signal 632_G to the pixel at a frequency of 30 or more times per second (preferably, 60 or more times and less than 960 times per second).

[0235] The G driving circuit 632 in the first mode rewrites the signal at a speed at which the user cannot perceive the image change that occurs each time the signal is rewritten. As a result, a smooth moving image can be displayed.

[0236] <2-2. Second Mode>

[0237] The G driving circuit 632 in the second mode outputs a G signal 632_G to the pixel at a frequency of once or more per day and less than 0.1 times per second (preferably, once or more per hour and less than once per second).

[0238] During a period in which the G signal 632_G is not input, the pixel circuit 634 continues to hold the S signal 633_S, and maintains a display state corresponding to the potential of the S signal 633_S.

[0239] Therefore, in the second mode, an image without flickering due to rewriting in pixels can be displayed.

[0240] As a result, eye fatigue of a user of a liquid crystal display device having a display function can be reduced.

[0241] During a period in which the G driving circuit 632 does not operate, the power consumed by the G driving circuit 632 may be reduced.

[0242] Note that the pixel circuit driven by the G driving circuit 632 in the second mode is preferably configured to hold the S signal 633_S for a long time. For example, the off-state leakage current of the transistor 634t is preferably as low as possible.

[0243] An example of the structure of the transistor 634t having low off-state leakage current can be referred to another embodiment.

[0244] Note that this embodiment can be combined with any other embodiments in this specification as appropriate.

[0245] (Example 4)

[0246] <Reverse drive>

[0247] In this embodiment, reference will be made to Fig. 9 , Figure 10A-1 , 10A-2 , 10B-1, 10B-2 and 10C and Fig.11 An example of a method for driving the liquid crystal display device described in Embodiments 2 and 3 is described.

[0248] Fig. 9 1 is a circuit diagram showing a liquid crystal display device having a display function according to an embodiment of the present invention.

[0249] Figure 10A-1 , 10A-2 10B-1, 10B-2 and 10C show the source line inversion drive and dot inversion drive of a liquid crystal display device with display function according to an embodiment of the present invention. Fig.11 1 is a timing chart showing source line inversion driving and dot inversion driving of a liquid crystal display device having a display function according to an embodiment of the present invention.

[0250] <1. Overdrive>

[0251] The saturated liquid crystal response time from voltage application to transmittance change is generally about 10 milliseconds. Therefore, the slow response of liquid crystal is often perceived as blurring of moving images.

[0252] The liquid crystal display device with display function of one embodiment of the present invention can adopt overdrive, in which the voltage applied to the liquid crystal element 635LC is temporarily increased to quickly change the orientation of the liquid crystal. Overdrive can increase the response speed of the liquid crystal, prevent blurring of moving images, and improve the quality of moving images.

[0253] If the transmittance of the liquid crystal element 635LC continues to change without saturation after the transistor 634t is turned off, the relative permittivity of the liquid crystal also changes; therefore, the voltage held by the liquid crystal element 635LC is likely to change.

[0254] For example, when the capacitor 634c is not connected in parallel to the liquid crystal element 635LC, or when the capacitor 634c connected to the liquid crystal element 635LC has a small capacitance, the change in the voltage held by the liquid crystal element 635LC tends to occur significantly. However, because overdriving can shorten the response time, the change in the transmittance of the liquid crystal element 635LC after the transistor 634t is turned off can be reduced. Therefore, even if the capacitor 634c connected in parallel to the liquid crystal element 635LC has a small capacitance, the voltage held by the liquid crystal element 635LC can be prevented from changing after the transistor 634t is turned off.

[0255] <2. Source Line Inversion Drive and Dot Inversion Drive>

[0256] Connecting to Fig. 10C In the pixel 631p of the pixel circuit of the signal line Si, the pixel electrode 635_1 is positioned between the signal line Si and the signal line Si+1 adjacent to the signal line Si. It is ideal that the pixel electrode 635_1 and the signal line Si are electrically separated from each other when the transistor 634t is turned off. In addition, ideally, the pixel electrode 635_1 and the signal line Si+1 are electrically separated from each other. However, in reality, there is a parasitic capacitance 634c(i) between the pixel electrode 635_1 and the signal line Si, and there is a parasitic capacitance 634c(i+1) between the pixel electrode 635_1 and the signal line Si+1 (see Fig. 10C ).Notice, Fig. 10C The pixel electrode 635_1 is shown as the first electrode or the second electrode of the liquid crystal element 635LC, instead of Fig. 9 The liquid crystal element 635LC in.

[0257] When the first electrode and the second electrode of the liquid crystal element 635LC overlap each other and the overlap of the two electrodes is actually used as a capacitor, the capacitor 634c formed using the capacitor wiring is not necessarily connected to the liquid crystal element 635LC, or the capacitance of the capacitor 634c connected to the liquid crystal element 635LC may be small. In this case, the potential of the pixel electrode 635_1 as the first electrode or the second electrode of the liquid crystal element is easily affected by the parasitic capacitance 634c (i) and the parasitic capacitance 634c (i + 1).

[0258] Therefore, the following phenomenon easily occurs: even when the transistor 634t is turned off in a period in which the potential of the image signal is held, a change in the potential of the signal line Si or the signal line Si+1 causes fluctuation in the potential of the pixel electrode 635_1.

[0259] The above phenomenon is called crosstalk; that is, in the period in which the potential of the image signal is maintained, the change in the potential of the signal line causes the fluctuation of the potential of the pixel electrode. Crosstalk causes a reduction in display contrast. For example, in the case of using normally-white liquid crystal for the liquid crystal element 635LC, a whitish image is displayed.

[0260] In view of the above description, a liquid crystal display device with a display function of an embodiment of the present invention can adopt a driving method in which, in a given frame period, image signals with opposite polarities are input to a signal line Si and a signal line Si+1 between which a pixel electrode 635_1 is arranged.

[0261] Note that the image signals having opposite polarities mean: assuming that the potential of the common electrode of the liquid crystal element is a reference potential, an image signal having a potential higher than a reference potential and an image signal having a potential lower than the reference potential.

[0262] Two methods (source line inversion and dot inversion) can be given as examples of methods for continuously and alternately writing image signals having opposite polarities to selected pixels.

[0263] In either method, in the first frame period, an image signal having a positive (+) polarity is input to the signal line Si, and an image signal having a negative (-) polarity is input to the signal line Si+1. Next, in the second frame period, an image signal having a negative (-) polarity is input to the signal line Si, and an image signal having a positive (+) polarity is input to the signal line Si+1. Then, in the third frame period, an image signal having a positive (+) polarity is input to the signal line Si, and an image signal having a negative (-) polarity is input to the signal line Si+1 (see Fig. 10C ).

[0264] This driving method in which the potentials of a pair of signal lines fluctuate with opposite polarities can cancel out the fluctuation of the potential of the pixel electrode, thereby suppressing crosstalk.

[0265] <2-1. Source Line Inversion Drive>

[0266] In source line inversion, in a given frame period, an image signal having one polarity is input to a plurality of pixels connected to a signal line, and an image signal having an opposite polarity is input to a plurality of pixels connected to another signal line adjacent to the signal line.

[0267] Figure 10A-1 and 10A-2 Schematically shows the polarity of the image signal supplied to the pixel driven with source line inversion. Figure 10A-1 and 10A-2 In FIG. 1 , “+” indicates a pixel supplied with an image signal having a positive polarity in a given frame period, and “−” indicates a pixel supplied with an image signal having a negative polarity. Figure 10A-2 The frames in Figure 10A-1 After the frame in .

[0268] <2-2. Dot Reversal Drive>

[0269] In dot inversion, in a given frame period, an image signal having one polarity is input to a plurality of pixels connected to a signal line, and an image signal having an opposite polarity is input to a plurality of pixels connected to another signal line adjacent to the signal line, so that the image signals provided to adjacent pixels connected to the same signal line have opposite polarities.

[0270] Figure 10B-1 and 10B-2 Schematically shows the polarity of the image signal supplied to the pixel driven by dot inversion. Figure 10B-1 and 10B-2 In FIG. 1 , “+” indicates a pixel supplied with an image signal having a positive polarity in a given frame period, and “−” indicates a pixel supplied with an image signal having a negative polarity. Figure 10B-2 The frames in Figure 10B-1 After the frame in .

[0271] <23. Timing diagram>

[0272] Fig.11 yes Fig. 9 631 is driven by source line inversion. Specifically, Fig.11 Shown are temporal changes in the potential of a signal supplied to the scanning line G1 , the potential of image signals supplied to the signal lines S1 to Sx, and the potential of pixel electrodes included in pixels connected to the scanning line G1 .

[0273] First, the scan line G1 is selected by a signal input to the scan line G1. In each of the plurality of pixels 631p connected to the selected scan line G1, the transistor 634t is turned on. When the potential of the image signal is supplied to the signal lines S1 to Sx when the transistor 634t is turned on, the potential of the image signal is supplied to the pixel electrode of the liquid crystal element 635LC through the turned-on transistor 634t.

[0274] exist Fig.11 In the example shown in the timing diagram of , during the period in which the scanning line G1 is selected in the first frame period, the image signal with positive polarity is sequentially input to the odd signal lines S1, S3, ..., and the image signal with negative polarity is sequentially input to the even signal lines S2, s4, ..., and Sx. Therefore, the image signal with positive polarity is supplied to the pixel electrodes (S1), (S3), ... in the pixel 631p connected to the odd signal lines S1, S3, .... The image signal with negative polarity is supplied to the pixel electrodes (S2), (S4), ..., and (Sx) in the pixel 631p connected to the even signal lines S2, s4, ..., and Sx.

[0275] In the liquid crystal element 635LC, the alignment of the liquid crystal molecules changes according to the voltage applied between the pixel electrode and the common electrode, thereby changing the transmittance. Therefore, the transmittance of the liquid crystal element 635LC can be controlled by the potential of the image signal; therefore, gradation can be expressed.

[0276] When the input of the image signal to the signal lines S1 to Sx is completed, the selection of the scan line G1 is terminated. When the selection of the scan line is terminated, the transistor 634t in the pixel 631p connected to the scan line is turned off. Therefore, the liquid crystal element 635LC maintains the voltage applied between the pixel electrode and the common electrode, thereby maintaining the display grayscale. Then, the scan lines G2 to Gy are sequentially selected, and an operation similar to the operation during the period in which the scan line G1 is selected is performed in the pixels connected to the corresponding scan lines above.

[0277] Next, the scan line G1 is selected again in the second frame period. When the scan line G1 is selected in the second frame period, an image signal with a negative polarity is sequentially input to the odd signal lines S1, S3, ..., and an image signal with a positive polarity is sequentially input to the even signal lines S2, S4, ... and Sx, which is different from the operation performed when the scan line G1 is selected in the first frame period. Therefore, an image signal with a negative polarity is provided to the pixel electrodes (S1), (S3), ... in the pixel 631p connected to the odd signal lines S1, S3, .... An image signal with a positive polarity is provided to the pixel electrodes (S2), (S4), ... and (Sx) in the pixel 631p connected to the even signal lines S2, S4, ... and Sx.

[0278] In addition, in the second frame period, when the input of the image signal to the signal lines S1 to Sx is completed, the selection of the scan line G1 is terminated. Then, the scan lines G2 to Gy are sequentially selected, and an operation similar to that during the period in which the scan line G1 is selected is performed in the pixels connected to the corresponding scan lines above.

[0279] Operations similar to the above are repeated in the third frame period and the fourth frame period.

[0280] Although Fig.11 The timing diagram shows an example in which image signals are sequentially input to the signal lines S1 to Sx, but the embodiment of the present invention is not limited to this configuration. The image signals may be simultaneously input to the signal lines S1 to Sx, or the image signals may be sequentially input every several signal lines.

[0281] In this embodiment, the scanning lines are selected in progressive scanning; however, the scanning lines may be selected according to interlaced scanning.

[0282] Inversion driving in which the polarity of the potential of the image signal is inverted using the potential of the common electrode as a reference can prevent liquid crystal degradation known as burn-in.

[0283] However, in the inversion drive, when the polarity of the image signal changes, the change in the potential supplied to the signal line increases; therefore, the potential difference between the source electrode and the drain electrode of the transistor 634t as a switching element increases. Therefore, it is easy to cause the characteristics of the transistor 634t to deteriorate, such as a threshold voltage shift.

[0284] Furthermore, in order to maintain the voltage held by the liquid crystal element 635LC, the off-state current of the transistor 634t needs to be low even when the potential difference between the source electrode and the drain electrode is large.

[0285] Note that this embodiment can be combined with any other embodiments in this specification as appropriate.

[0286] (Example 5)

[0287] In this embodiment, reference will be made to Fig. 12A and 12B A method for generating an image that can be displayed on a liquid crystal display device of one embodiment of the present invention is described. Specifically, a method for switching images in an eye-friendly manner, a method for switching images with less user eye fatigue, and a method for switching images without causing user eye fatigue will be described.

[0288] When displayed images are rapidly switched, for example, when scenes of a moving image are frequently switched or when a still image is switched to another still image, the user may feel eyestrain.

[0289] When the displayed image is switched from one image to another, it is preferable that the images are not switched instantaneously but are switched gradually (smoothly) and naturally.

[0290] For example, when the first image is switched to a second image different from the first image, it is preferred to insert a fade-out image of the first image or a fade-in image of the second image between the first image and the second image. It is also possible to insert an image obtained by overlapping the first image and the second image so that the second image fades in when the first image fades out (this technique is also called crossfading), or insert a moving image in which the first image gradually changes into the second image (this technique is also called morphing).

[0291] Specifically, a first static image is displayed at a low refresh rate, an image for image switching is displayed at a high refresh rate, and then, a second static image is displayed at a low refresh rate.

[0292] <fade in, fade out>

[0293] An example of a method of switching the display from an image A to another image B will be described below.

[0294] Fig. 12A is a block diagram showing a configuration of a display device capable of switching images. Fig. 12A The display device includes: a computing device 671, a memory device 672, a graphic unit 673 and a display unit 674.

[0295] In the first step, the operation device 671 stores the data of the image A and the data of the image B output from the external memory device or the like in the memory device 672 .

[0296] In the second step, the operation device 671 sequentially generates new image data based on the data of image A and the data of image B according to the predetermined number by which the image data is to be divided.

[0297] In the third step, the generated image data is output to the graphic unit 673. The graphic unit 673 causes the display unit 674 to display the input image data.

[0298] Fig. 12B Image data generated for a gradual image change from image A to image B is schematically shown.

[0299] Fig. 12B An example is shown in which N image data (N is a natural number) are generated between image A and image B, and each is displayed for f frame periods (f is a natural number). Therefore, switching display from image A to image B takes f×N frames.

[0300] Preferably, the user can freely set parameters such as N and f. The operation device 671 acquires these parameters in advance and generates image data based on these parameters.

[0301] As an example, the i-th generated image data (i is an integer greater than or equal to 1 and less than or equal to N) can be generated by weighting the data of image A and the data of image B and adding the weighted data. For example, when the brightness (grayscale) of a pixel displaying image A is represented by a, and the brightness (grayscale) of a pixel displaying image B is represented by b, the brightness (grayscale) c of a pixel displaying the i-th generated image data is represented by formula (1).

[0302] [Formula 1]

[0303]

[0304] Display switching from image A to image B is performed using image data generated in this way, so that discontinuous images can be changed gradually (smoothly) and naturally.

[0305] Note that the case where all pixels satisfy a=0 in formula (1) corresponds to a fade-in where a black image gradually changes to image B. The case where all pixels satisfy b=0 corresponds to a fade-out where image A gradually changes to a black image.

[0306] In the above method, the display is switched from one image to another so that the two images temporarily overlap each other; however, a method without overlapping operation may also be employed.

[0307] In the case where the two images do not overlap each other, a black image may be inserted between image A and image B. In this case, when the display is switched from image A to a black image and / or from a black image to image B, the above image switching method may be used. The image inserted between image A and image B is not limited to a black image, and may be a monochrome image, such as a white image, or a multi-color image when different from image A and image B. Inserting another image, particularly a monochrome image (such as a black image), between image A and image B enables the user to perceive the image switching more naturally without feeling stress.

[0308] Note that this embodiment can be combined with any other embodiments in this specification as appropriate.

[0309] (Example 6)

[0310] In this embodiment, reference will be made to Fig.13A and 13B , Fig.14A and 14B , Fig.15Aand 15B , Figures 16A to 16D , Figures 17A to 17C and Figures 18A to 18C A semiconductor device according to an embodiment of the present invention is described.

[0311] <Structural Example of Semiconductor Device>

[0312] Fig.13A A top view of a semiconductor device that can be used in a display device according to an embodiment of the present invention is shown, and Fig. 13B Shown along Fig.13A The cross-sectional view is taken along the dot-dash line AB, the dot-dash line CD and the dot-dash line EF. Note that Fig.13A Some components of the semiconductor device (eg, a gate insulating film) are not shown to avoid complexity. Fig.13A As shown, in some cases certain components are not shown in the top view of the transistor described below.

[0313] Fig.13A The direction of the dot-dash line AB in corresponds to the channel length direction of the transistor 150. The direction of the dot-dash line EF corresponds to the channel width direction of the transistor 150. In this specification, the channel length direction of the transistor means: the direction in which carriers move between the source (source region or source electrode) and the drain (drain region or drain electrode). The channel width direction means a direction perpendicular to the channel length direction in a plane parallel to the substrate.

[0314] Fig.13A and 13B The semiconductor device in the embodiment includes a transistor 150 including a first oxide semiconductor film 110 and a capacitor 160 including an insulating film between a pair of electrodes. In the capacitor 160, one of the pair of electrodes is the second oxide semiconductor film 111 and the other of the pair of electrodes is the conductive film 120.

[0315] The transistor 150 includes: a gate electrode 104 on a substrate 102, an insulating film 108 as a gate insulating film on the gate electrode 104, a first oxide semiconductor film 110 on the insulating film 108 and overlapping with the gate electrode 104, and a source electrode 112a and a drain electrode 112b on the first oxide semiconductor film 110. In other words, the transistor 150 includes: a first oxide semiconductor film 110, an insulating film 108 provided in contact with the first oxide semiconductor film 110 and as a gate insulating film, a gate electrode 104 provided in contact with the insulating film 108 and overlapping with the first oxide semiconductor film 110, and a source electrode 112a and a drain electrode 112b electrically connected to the first oxide semiconductor film 110. Note that Fig.13A and 13B The transistor 150 in FIG. 1 has a bottom gate structure.

[0316] In addition, insulating films 114, 116, and 118 are formed over the transistor 150, specifically, over the first oxide semiconductor film 110, the source electrode 112a, and the drain electrode 112b. The insulating films 114, 116, and 118 serve as protective insulating films for the transistor 150. An opening 142 that reaches the drain electrode 112b is formed in the insulating films 114, 116, and 118. A conductive film 120 is formed over the insulating film 118 to cover the opening 142. The conductive film 120 serves as a pixel electrode, for example.

[0317] The capacitor 160 includes the second oxide semiconductor film 111 which is over the insulating film 116 and serves as one electrode of a pair of electrodes, the insulating film 118 which is over the second oxide semiconductor film 111 and serves as a dielectric film, and the conductive film 120 which overlaps the second oxide semiconductor film 111 with the insulating film 118 therebetween and serves as the other electrode of the pair of electrodes. In other words, the conductive film 120 serves as a pixel electrode and an electrode of the capacitor.

[0318] Note that the first oxide semiconductor film 110 serves as a channel region of the transistor 150. The second oxide semiconductor film 111 serves as one electrode of the pair of electrodes of the capacitor 160. Therefore, the second oxide semiconductor film 111 has a lower resistivity than the first oxide semiconductor film 110. In addition, the first oxide semiconductor film 110 and the second oxide semiconductor film 111 preferably contain the same metal element. When the first oxide semiconductor film 110 and the second oxide semiconductor film 111 contain the same metal element, a common manufacturing device (e.g., a deposition device or a processing device) can be used, and thus the manufacturing cost can be suppressed.

[0319] In addition, the second oxide semiconductor film 111 can be connected to a wiring or the like formed separately using a metal film or the like. For example, in Figure 1 When the structure is applied to a transistor and a capacitor in a pixel portion of a display device, lead wiring, gate wiring, and the like can be formed using a metal film and connected to the second oxide semiconductor film 111. Since the lead wiring, gate wiring, and the like are formed using a metal film, wiring resistance can be reduced, and thus signal delay can be suppressed.

[0320] In addition, the second oxide semiconductor film 111 may be connected to a pattern of a terminal separately formed using a metal film or the like. Figure 1 In the case where the structure is applied to a transistor and a capacitor in a pixel portion of a display device, the second oxide semiconductor film 111 can be connected to a metal film of a terminal or the like. As an example, Fig.14A and 14BA structure in which the second oxide semiconductor film 111 is connected to the drain electrode 112 b of the transistor 150 is shown.

[0321] In addition, the capacitor 160 can transmit light. In this case, each of the second oxide semiconductor film 111, the conductive film 120, and the insulating film 118 included in the capacitor 160 is formed of a light-transmitting material. Because the capacitor 160 transmits light, a large capacitor 160 (large area) can be formed in the pixel except for the region where the transistor is formed; therefore, the display device can have a large capacitance and a high aperture ratio. Therefore, the display device can have excellent display quality.

[0322] As the insulating film 118 provided over the transistor 150 and for the capacitor 160, an insulating film containing at least hydrogen is used. As the insulating film 107 for the transistor 150 and the insulating films 114 and 116 provided over the transistor 150, an insulating film containing at least oxygen is used. Such an insulating film is used as an insulating film for the transistor 150 and the capacitor 160, and as an insulating film over the transistor 150 and the capacitor 160, so that the resistivity of the first oxide semiconductor film 110 included in the transistor 150 and the resistivity of the second oxide semiconductor film 111 included in the capacitor 160 can be controlled.

[0323] When the insulating film for the capacitor 160 and the insulating film over the transistor 150 and the capacitor 160 are set as follows, the flatness of the conductive film 120 can be increased. Specifically, the insulating films 114 and 116 are set over the first oxide semiconductor film 110, and the insulating film 118 is set over the second oxide semiconductor film 111, so that the second oxide semiconductor film 111 is positioned between the insulating film 116 and the insulating film 118; therefore, the resistivity of the second oxide semiconductor film 111 can be controlled without setting openings in the insulating films 114 and 116 overlapping the second oxide semiconductor film 111. Fig.13A and 13B When such a structure of the semiconductor device in is applied to a transistor and a capacitor in a pixel portion of a liquid crystal display device, the alignment of liquid crystal over the conductive film 120 can be improved.

[0324] Note that the conductive film 120a, which is deposited, etched, and completed simultaneously with the conductive film 120, can be provided to overlap with the channel region of the transistor. Fig.15AAn example of this situation is shown. For example, because the conductive film 120a is deposited, etched and completed simultaneously with the conductive film 120, the conductive film 120a contains the same material as the conductive film 120. Therefore, the number of process steps will not be increased. Note that one embodiment of the present invention is not limited to this. The conductive film 120 and the conductive film 120a can be formed in different steps. The conductive film 120a includes a region overlapping with the channel region of the transistor. Therefore, the conductive film 120a serves as the second gate electrode of the transistor. Therefore, the conductive film 120a can be connected to the gate electrode 104. Instead of being connected to the gate electrode 104, the conductive film 120a can be supplied with a signal or potential different from the signal or potential supplied to the gate electrode 104. This structure can further improve the current driving capability of the transistor 150. In this case, the insulating films 114, 116 and 118 serve as gate insulating films for the second gate electrode.

[0325] Note that the second oxide semiconductor film 111 a which is deposited, etched, and completed simultaneously with the second oxide semiconductor film 111 can be provided so as to overlap with the channel region of the transistor. Fig. 15B An example of such a case is shown. For example, since the second oxide semiconductor film 111a is deposited, etched, and completed simultaneously with the second oxide semiconductor film 111, the second oxide semiconductor film 111a contains the same material as the second oxide semiconductor film 111. Therefore, the number of process steps is not increased. Note that one embodiment of the present invention is not limited to this. The second oxide semiconductor film 111 and the second oxide semiconductor film 111a may be formed in different steps. The second oxide semiconductor film 111a includes a region overlapping with the first oxide semiconductor film 110 serving as a channel region of the transistor 150. Therefore, the second oxide semiconductor film 111a serves as a second gate electrode of the transistor 150. Therefore, the second oxide semiconductor film 111a may be connected to the gate electrode 104. Instead of being connected to the gate electrode 104, the second oxide semiconductor film 111a may be supplied with a signal or potential different from a signal or potential supplied to the gate electrode 104. Fig.15A Compared with the structure of the transistor 150, this structure in which the insulating films 114 and 116 serve as the gate insulating film of the second gate electrode can further improve the current driving capability of the transistor 150.

[0326] Note that the first oxide semiconductor film 110 used as a channel region of the transistor 150 has a higher resistivity than the second oxide semiconductor film 111. In contrast, the second oxide semiconductor film 111 used as an electrode has a lower resistivity than the first oxide semiconductor film 110.

[0327] A method for controlling the resistivity of the first oxide semiconductor film 110 and the resistivity of the second oxide semiconductor film 111 will be described below.

[0328] <Method for controlling resistivity of oxide semiconductor>

[0329] The oxide semiconductor film that can be used as the first oxide semiconductor film 110 and the second oxide semiconductor film 111 includes a semiconductor material whose resistivity can be controlled by the number of oxygen vacancies in the film and / or the concentration of impurities such as hydrogen or moisture in the film. Therefore, in order to control the resistivity of the first oxide semiconductor film 110 and the resistivity of the second oxide semiconductor film 111, the process performed on each oxide semiconductor film is selected from the processes for increasing the oxygen vacancies and / or the impurity concentration.

[0330] Specifically, plasma treatment is performed on the oxide semiconductor film of the second oxide semiconductor film 111 serving as an electrode of the capacitor 160 to increase oxygen vacancies and / or impurities such as hydrogen or moisture in the oxide semiconductor film; therefore, the oxide semiconductor film can have a high carrier density and a low resistance. Alternatively, an insulating film containing hydrogen is formed, for example, as an insulating film 118 in contact with the oxide semiconductor film, so that hydrogen can diffuse from the insulating film containing hydrogen into the oxide semiconductor film, and therefore, the oxide semiconductor film can have a high carrier density and a low resistance. As described above, before the step of increasing oxygen vacancies or diffusing hydrogen into the film, the second oxide semiconductor film 111 acts as a semiconductor, and after the step it acts as a conductor.

[0331] On the contrary, since the insulating films 107, 114, and 116 are provided, the first oxide semiconductor film 110 as the channel region of the transistor 150 is not in contact with the insulating films 106 and 118 containing hydrogen. By using an insulating film containing oxygen (i.e., an insulating film capable of releasing oxygen) as at least one of the insulating films 107, 114, and 116, oxygen can be supplied to the first oxide semiconductor film 110. Since oxygen vacancies in the film or at the contact surface are filled, the first oxide semiconductor film 110 to which oxygen is supplied has a high resistivity. As the insulating film capable of releasing oxygen, for example, a silicon oxide film or a silicon oxynitride film can be used.

[0332] In order to obtain an oxide semiconductor film having low resistivity, hydrogen, boron, phosphorus, or nitrogen can be introduced into the oxide semiconductor film by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like.

[0333] In order to reduce the resistivity of the oxide semiconductor film, the oxide semiconductor film may be subjected to plasma treatment. A typical example of plasma treatment is plasma treatment using a gas containing at least one of a rare gas (He, Ne, Ar, Kr or Xe), hydrogen and nitrogen. Specifically, plasma treatment in an argon atmosphere, plasma treatment in a mixed gas atmosphere of argon and hydrogen, plasma treatment in an ammonia atmosphere, plasma treatment in a mixed gas atmosphere of argon and ammonia, or plasma treatment in a nitrogen atmosphere, etc. may be used.

[0334] In the oxide semiconductor film subjected to plasma treatment, oxygen vacancies are formed in the lattice from which oxygen is released (or in the portion from which oxygen is released). Such oxygen vacancies may cause carrier generation. In addition, hydrogen supplied from an insulating film near the oxide semiconductor film (specifically, an insulating film in contact with the bottom surface or top surface of the oxide semiconductor film) may be bonded to the oxygen vacancies, thereby possibly generating electrons as carriers.

[0335] An oxide semiconductor film in which oxygen vacancies are filled and hydrogen concentration is reduced can be referred to as a high-purity intrinsic or high-purity substantially intrinsic oxide semiconductor film. The term “substantially intrinsic” means that the oxide semiconductor film has a concentration of less than 8×10 11 / cm 3 (Preferably less than 1×10 11 / cm 3 , more preferably less than 1×10 10 / cm 3 ) of the carrier density. The high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has few carrier generation sources and thus can have a low carrier density. The high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low defect state density and thus can have a low trap state density.

[0336] In addition, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has an extremely low off-state current; even when the element has a 1×10 6 When the channel width is 10 μm and the channel length L is 10 μm, the off-state current can also be lower than or equal to the measurement limit of the semiconductor parameter analyzer, that is, when the voltage between the source electrode and the drain electrode (drain voltage) is 1 V to 10 V, it is lower than or equal to 1×10 -13 A. Therefore, the transistor 150 in which the channel region is formed in the first oxide semiconductor film 110 which is a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has only a small change in electrical characteristics and is very reliable.

[0337] For example, an insulating film containing hydrogen (that is, an insulating film capable of releasing hydrogen, typically a silicon nitride film) is used as the insulating film 118, whereby hydrogen can be supplied to the second oxide semiconductor film 111. The insulating film capable of releasing hydrogen preferably has a thickness of 1×10 22 Atom / cm 3 Or a higher hydrogen concentration. Such an insulating film is formed to be in contact with the second oxide semiconductor film 111, whereby hydrogen can be effectively contained in the second oxide semiconductor film 111. Therefore, the resistivity of the first oxide semiconductor film 110 and the resistivity of the second oxide semiconductor film 111 can be controlled by using different materials for the insulating film in contact with the oxide semiconductor film. Note that the material of the insulating film 106 can be similar to that of the insulating film 118. Silicon nitride used for the insulating film 106 can prevent the gate electrode 104 from being supplied with oxygen released from the insulating film 107 and being oxidized by it.

[0338] The hydrogen contained in the oxide semiconductor film reacts with the oxygen bound to the metal atom to form water, and also causes oxygen vacancies in the lattice from which oxygen is released (or the portion from which oxygen is released). Hydrogen entering the oxygen vacancies can generate electrons as carriers. In some cases, the combination of part of the hydrogen with the oxygen bound to the metal element generates electrons as carriers. Therefore, the second oxide semiconductor film 111, which is arranged to be in contact with the insulating film containing hydrogen, is an oxide semiconductor film having a higher carrier density than the first oxide semiconductor film 110.

[0339] It is preferable to reduce hydrogen in the first oxide semiconductor film 110 in which the channel region of the transistor 150 is formed as much as possible. Specifically, the hydrogen concentration in the first oxide semiconductor film 110 measured by secondary ion mass spectrometry (SIMS) is lower than or equal to 2×10 20 Atom / cm 3 , preferably less than or equal to 5×10 19 Atom / cm 3 , more preferably less than or equal to 1×10 19 Atom / cm 3 , less than 5×10 18 Atom / cm 3 , preferably less than or equal to 1×10 18 Atom / cm 3 , more preferably less than or equal to 5×10 17 Atom cm 3 , more preferably less than or equal to 1×10 16 Atom / cm 3 .

[0340] The second oxide semiconductor film 111 as an electrode of the capacitor 160 is an oxide semiconductor film having a higher hydrogen concentration and / or a larger number of oxygen vacancies (i.e., a lower resistivity) than the first oxide semiconductor film 110. The concentration of hydrogen contained in the second oxide semiconductor film 111 is higher than or equal to 8×10 19 Atom / cm 3 , preferably greater than or equal to 1×10 20 Atom / cm 3 , more preferably greater than or equal to 5×10 20 Atom / cm 3 The concentration of hydrogen contained in the second oxide semiconductor film 111 is twice or more, preferably 10 times or more, the concentration of hydrogen contained in the first oxide semiconductor film 110. The resistivity of the second oxide semiconductor film 110 is preferably greater than or equal to 1×10 of the resistivity of the first oxide semiconductor film 110. -8 times and less than 1×10 of the resistivity of the first oxide semiconductor film 110 -1 The resistivity of the second oxide semiconductor film 111 is generally greater than or equal to 1×10 -3 Ωcm and less than 1×10 4 Ωcm, preferably greater than or equal to 1×10 -3 Ωcm and less than 1×10 -1 Ωcm.

[0341] The following will describe Fig.13A and 13B as well as Fig.14A and 14B Details of other components of the semiconductor device.

[0342] <Substrate>

[0343] There is no particular restriction on the material of the substrate 102, etc., as long as the material has at least sufficiently high heat resistance so as to be able to withstand the heat treatment performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, or a sapphire substrate can be used as the substrate 102. Alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate formed of silicon or silicon carbide, a composite semiconductor substrate formed of silicon germanium, etc., an SOI substrate, etc. can be used. Alternatively, any of these substrates provided with a semiconductor element can be used as the substrate 102. In the case of using a glass substrate as the substrate 102, a large substrate having any of the following sizes can be used: the 6th generation (1500mm×1850mm), the 7th generation (1870mm×2200mm), the 8th generation (2200mm×2400mm), the 9th generation (2400mm×2800mm) and the 10th generation (2950mm×3400mm). Therefore, a large display device can be manufactured. Alternatively, a flexible substrate may be used as the substrate 102 , and the transistor 150 , the capacitor 160 , and the like may be directly formed on the flexible substrate.

[0344] In addition to the above, a variety of substrates can be used as substrate 102 to form transistors. The type of substrate is not limited to a specific type. As a substrate, for example, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate including a stainless steel foil, a tungsten substrate, a substrate including a tungsten foil, a flexible substrate, an attachment film, paper containing a fiber material, or a base film can be used. As examples of glass substrates, barium borosilicate glass substrates, aluminum borosilicate glass substrates, and soda-lime glass substrates can be given. For flexible substrates, flexible synthetic resins can be used, such as plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyether sulfone (PES) or acrylic resins. Examples of attachment films are films formed using polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, and the like. Examples of base films include: films formed using polyester, polyamide, or polyimide, inorganic vapor deposition films, and paper. In particular, transistors formed using semiconductor substrates, single crystal substrates, SOI substrates, and the like can have very small changes in characteristics, size, shape, and the like, large current capabilities, and small sizes. This transistor can achieve lower power consumption or higher circuit integration.

[0345] A transistor can be formed using one substrate, and then the transistor can be transferred to another substrate. Examples of substrates to which transistors are transferred include, in addition to the above-mentioned substrates on which transistors can be formed, paper substrates, cellophane substrates, stone substrates, wooden substrates, cloth substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane or polyester), regenerated fibers (acetate, cupra, rayon or regenerated polyester), etc.), leather substrates, and rubber substrates. When such a substrate is used, a transistor with excellent characteristics or a transistor with low power consumption can be formed, a device with high durability can be manufactured, high heat resistance can be provided, or reduced weight or thickness can be achieved.

[0346] <First Oxide Semiconductor Film and Second Oxide Semiconductor Film>

[0347] Each of the first oxide semiconductor film 110 and the second oxide semiconductor film 111 preferably includes an In-M-Zn oxide film containing at least indium (In), zinc (Zn), and M (metal such as Al, Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). In order to reduce changes in electrical characteristics of a transistor including an oxide semiconductor, the oxide semiconductor preferably further includes a stabilizer in addition to In, Zn, and M.

[0348] Examples of stabilizers, including metals that can be used as M, are gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al) and zirconium (Zr). As another stabilizer, a lanthanide element such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) or lutetium (Lu) can be given.

[0349] As the oxide semiconductor included in the first oxide semiconductor film 110 and the second oxide semiconductor film 111, for example, the following oxides can be used: In-Ga-Zn-based oxide, In-Al-Zn-based oxide, In-Sn-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide material, an oxide based on In-Tb-Zn, an oxide based on In-Dy-Zn, an oxide based on In-Ho-Zn, an oxide based on In-Er-Zn, an oxide based on In-Tm-Zn, an oxide based on In-Yb-Zn, an oxide based on In-Lu-Zn, an oxide based on In-Sn-Ga-Zn, an oxide based on In-Hf-Ga-Zn, an oxide based on In-Al-Ga-Zn, an oxide based on In-Sn-Al-Zn, an oxide based on In-Sn-Hf-Zn, or an oxide based on In-Hf-Al-Zn.

[0350] Here, "In-Ga-Zn-based oxide" means an oxide containing In, Ga and Zn as its main components, and there is no limitation on the ratio of In to Ga and Zn. "In-Ga-Zn-based oxide" may contain another metal element in addition to In, Ga and Zn.

[0351] The first oxide semiconductor film 110 and the second oxide semiconductor film 111 may contain the same metal element selected from the metal elements contained in the above oxide. Using the same metal element for the first oxide semiconductor film 110 and the second oxide semiconductor film 111 can reduce manufacturing costs. For example, when a metal oxide target having the same metal component is used, manufacturing costs can be reduced, and the same etching gas or the same etchant can be used when processing the oxide semiconductor film. Even when the first oxide semiconductor film 110 and the second oxide semiconductor film 111 contain the same metal element, they have different components in some cases. For example, in the manufacturing process of transistors and capacitors, the metal element can be released from the film, which results in different metal components.

[0352] In the case where the first oxide semiconductor film 110 includes In-M-Zn oxide, assuming that the sum of In and M is 100 atomic %, the ratio of In and M is preferably as follows: the ratio of In is higher than 25 atomic % and the ratio of M is lower than 75 atomic %, more preferably, the ratio of In is higher than 34 atomic % and the ratio of M is lower than 66 atomic %.

[0353] The energy gap of the first oxide semiconductor film 110 is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. By using an oxide semiconductor having such a wide energy gap, the off-state current of the transistor 150 can be reduced.

[0354] The thickness of the first oxide semiconductor film 110 is greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, and more preferably greater than or equal to 3 nm and less than or equal to 50 nm.

[0355] In the case where the first oxide semiconductor film 110 includes In-M-Zn oxide (M represents Al, Ga, Y, Zr, La, Ce or Nd), the atomic ratio of the metal element in the sputtering target for depositing the In-M-Zn oxide preferably satisfies In≥M and Zn≥M. As an example of the atomic ratio of the metal element in such a sputtering target, In:M:Zn=1:1:1, 1:1:1.2, 3:1:2, 1:3:4 and 1:3:6 can be given. Note that the atomic ratio of the metal element in the deposited first oxide semiconductor film 110 can be changed within an error range of ±40% of the above atomic ratio of the metal element in the sputtering target.

[0356] An oxide semiconductor film having a low carrier density is used as the first oxide semiconductor film 110. For example, the carrier density is 1×10 17 cm 3 or lower (preferably 1×10 15 / cm 3 or lower, more preferably 1×10 13 / cm 3 or lower, more preferably 1×10 11 cm 3 An oxide semiconductor film (of a thickness of 0.5 Å or lower) is used as the first oxide semiconductor film 110 .

[0357] Without being limited to the above examples, materials with appropriate compositions may be used according to the semiconductor characteristics and electrical characteristics (e.g., field effect mobility and threshold voltage) of the required transistor. In order to obtain the required semiconductor characteristics of the transistor, preferably, the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. of the first oxide semiconductor film 110 are appropriately set.

[0358] If silicon or carbon (which is an element belonging to Group 14) is contained in the first oxide semiconductor film 110, the number of oxygen vacancies in the first oxide semiconductor film 110 increases, and the first oxide semiconductor film 110 becomes an n-type film. In order to prevent this, the concentration of silicon or carbon in the first oxide semiconductor film 110 (the concentration measured by SIMS) is set to 2×10 18 Atom / cm 3 or lower, preferably 2×10 17 Atom / cm 3 Or lower.

[0359] The concentration of the alkali metal or alkaline earth metal in the first oxide semiconductor film 110 measured by SIMS is set to 1×10 18 Atom / cm 3 or lower, preferably 2×10 16 Atom / cm 3 When bonded to an oxide semiconductor, the alkali metal and the alkaline earth metal may generate carriers, in which case the off-state current of the transistor may be increased. Therefore, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the first oxide semiconductor film 110.

[0360] If nitrogen is contained in the first oxide semiconductor film 110, electrons as carriers are generated and the carrier density increases, so that the first oxide semiconductor film 110 easily becomes an n-type film. Therefore, a transistor formed using an oxide semiconductor containing nitrogen is likely to be normally on. Therefore, it is preferable to reduce nitrogen in the oxide semiconductor film as much as possible; the nitrogen concentration measured by SIMS is preferably, for example, 5×10 18 Atom / cm 3 Or lower.

[0361] The first oxide semiconductor film 110 may have, for example, a non-single-crystal structure. The non-single-crystal structure includes, for example, a c-axis oriented crystalline oxide semiconductor (CAAC-OS) described later, a polycrystalline structure, a microcrystalline structure described later, or an amorphous structure. Among the non-single-crystal structures, the amorphous structure has the highest defect state density, while the CAAC-OS has the lowest defect state density.

[0362] For example, the first oxide semiconductor film 110 may have an amorphous structure. For example, an oxide semiconductor film having an amorphous structure has a disordered atomic alignment and has no crystalline component. Alternatively, an amorphous oxide film has, for example, a completely amorphous structure and has no crystalline portion.

[0363] Note that the first oxide semiconductor film 110 may be a mixed film including two or more of the following regions: a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a CAAC-OS region, and a region having a single crystal structure. The mixed film may include, for example, two or more of the following regions in some cases: a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a CAAC-OS region, and a region having a single crystal structure. In addition, for example, in some cases the mixed film has a stacked structure of two or more of the following regions: a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a CAAC-OS region, and a region having a single crystal structure.

[0364] <Insulating film>

[0365] Each of the insulating films 106 and 107 as the gate insulating film of the transistor 150 can use an insulating film including at least one of the following films formed by a plasma enhanced chemical vapor deposition (PECVD) method or a sputtering method, etc.: a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. Instead of stacking the insulating films 106 and 107, a single-layer insulating film selected from the above films can be used.

[0366] The insulating film 106 functions as a barrier film for preventing penetration of oxygen. For example, when excessive oxygen is supplied to the insulating film 107, the insulating film 114, the insulating film 116, and / or the first oxide semiconductor film 110, the insulating film 106 can suppress the penetration of oxygen.

[0367] Note that the insulating film 107 in contact with the first oxide semiconductor film 110 as the channel region of the transistor 150 is preferably an oxide insulating film, and more preferably includes a region containing oxygen exceeding the stoichiometric ratio (oxygen excess region). In other words, the insulating film 107 is an insulating film capable of releasing oxygen. In order to provide an oxygen excess region in the insulating film 107, for example, the insulating film 107 can be formed in an oxygen atmosphere. Alternatively, the oxygen excess region can be formed by introducing oxygen into the deposited insulating film 107. As a method for introducing oxygen, ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, or the like can be used.

[0368] In the case of using hafnium oxide for the insulating films 106 and 107, the following effect is obtained. Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, the thickness of the insulating films 106 and 107 can be made larger than that of silicon oxide; as a result, the leakage current generated by the tunneling current can be reduced. That is, a transistor with a low off-state current can be provided. In addition, hafnium oxide having a crystal structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, it is preferable to use hafnium oxide having a crystal structure to provide a transistor with a low off-state current. Examples of crystal structures include monoclinic structures and cubic crystal structures. Note that one embodiment of the present invention is not limited to these examples.

[0369] In this embodiment, a silicon nitride film is formed as the insulating film 106, and a silicon oxide film is formed as the insulating film 107. The silicon nitride film has a higher dielectric constant than the silicon oxide film, and a larger thickness is required for a capacitance equivalent to that of the silicon oxide film. Therefore, when the insulating film 108 as the gate insulating film of the transistor 150 includes a silicon nitride film, the physical thickness of the insulating film can be increased. This makes it possible to suppress the reduction in the withstand voltage of the transistor 150, and to increase the withstand voltage, thereby suppressing electrostatic discharge damage to the transistor 150.

[0370] <Gate Electrode, Source Electrode, and Drain Electrode>

[0371] Each of the gate electrode 104, the source electrode 112a, and the drain electrode 112b may have a single-layer structure or a stacked-layer structure formed using a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the metal as its main component. For example, a double-layer structure in which a titanium film is stacked on an aluminum film; a double-layer structure in which a titanium film is stacked on a tungsten film; a double-layer structure in which a copper film is stacked on a molybdenum film; a double-layer structure in which a copper film is stacked on an alloy film containing molybdenum and tungsten; a double-layer structure in which a copper film is stacked on an alloy film containing copper, magnesium, and aluminum; a three-layer structure in which a titanium film or a titanium nitride film, an aluminum film or a copper film, and a titanium film or a titanium nitride film are stacked in this order; or a three-layer structure in which a molybdenum film or a molybdenum nitride film, an aluminum film or a copper film, and a molybdenum film or a molybdenum nitride film are stacked in this order. In the case where the source electrode 112a and the drain electrode 112b have a three-layer structure, it is preferable to form a film of titanium, titanium nitride, molybdenum, tungsten, an alloy containing molybdenum and tungsten, an alloy containing molybdenum and zirconium, or molybdenum nitride as each of the first layer and the third layer, and to form a film of a low-resistance material such as copper, aluminum, gold, silver, or an alloy containing copper and manganese as the second layer. Note that a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used. The materials that can be used as the gate electrode 104, the source electrode 112a, and the drain electrode 112b can be formed by, for example, a sputtering method.

[0372] <Conductive Film>

[0373] The conductive film 120 serves as a pixel electrode. For example, a material that transmits visible light can be used for the conductive film 120. Specifically, it is preferable to use a material containing one of indium (In), zinc (Zn) and tin (Sn). For the conductive film 120, for example, a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used. For example, the conductive film 120 can be formed by a sputtering method.

[0374] <Protective insulating film>

[0375] For each of the insulating films 114, 116 and 118 serving as a protective insulating film for the transistor 150, an insulating film including at least one of the following films formed by a PECVD method, a sputtering method, or the like can be used: a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film.

[0376] The insulating film 114 in contact with the first oxide semiconductor film 110 serving as the channel region of the transistor 150 is preferably an oxide insulating film capable of releasing oxygen. In other words, the insulating film capable of releasing oxygen is an insulating film including a region containing oxygen exceeding the stoichiometric ratio (oxygen excess region). In order to provide an oxygen excess region in the insulating film 114, for example, the insulating film 114 can be formed in an oxygen atmosphere. Alternatively, an oxygen excess region can be formed by introducing oxygen into the deposited insulating film 114. As a method for introducing oxygen, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment, etc. can be used.

[0377] Using an insulating film capable of releasing oxygen as the insulating film 114 enables oxygen to move to the first oxide semiconductor film 110 as the channel region of the transistor 150, thereby reducing the number of oxygen vacancies in the first oxide semiconductor film 110. For example, the number of oxygen vacancies in the first oxide semiconductor film 110 can be reduced by using an insulating film having the following characteristics: when measured by thermal desorption spectroscopy (hereinafter referred to as TDS), the number of oxygen molecules released from the insulating film is greater than or equal to 1.0×10 18 Molecules / cm 3 .

[0378] In addition, the number of defects in the insulating film 114 is preferably small; generally, in ESR measurement, the spin density of the signal appearing at g=2.001 due to the dangling bonds of silicon is preferably lower than or equal to 3×10 17 Spin / cm 3 (spins / cm 3 ). This is because the high defect density in the insulating film 114 causes oxygen to combine with the defects and reduces the amount of oxygen that penetrates the insulating film 114. In addition, the number of defects at the interface between the insulating film 114 and the first oxide semiconductor film 110 is preferably small; generally, in ESR measurement, the spin density of the signal appearing at g = 1.89 or more and 1.96 or less due to defects in the first oxide semiconductor film 110 is preferably lower than or equal to 1×10 17 Spin / cm 3 , more preferably, lower than or equal to the lower limit of detection.

[0379] Note that in some cases, all of the oxygen that enters the insulating film 114 from the outside moves to the outside of the insulating film 114. Alternatively, part of the oxygen that enters the insulating film 114 from the outside remains in the insulating film 114 in some cases. In some cases, movement of oxygen occurs in the insulating film 114 in such a manner that oxygen enters the insulating film 114 from the outside and oxygen contained in the insulating film 114 moves to the outside of the insulating film 114. When an oxygen-permeable oxide insulating film is formed as the insulating film 114, oxygen released from the insulating film 116 provided over the insulating film 114 can move to the first oxide semiconductor film 110 through the insulating film 114.

[0380] The insulating film 114 can be formed using an oxide insulating film having a low state density due to nitrogen oxide. Note that the state density due to nitrogen oxide can be formed between the energy of the valence band maximum value (Ev_os) and the energy of the conduction band minimum value (Ec_os) of the oxide semiconductor film. A silicon oxynitride film that releases only a small amount of nitrogen oxide, an aluminum oxynitride film that releases only a small amount of nitrogen oxide, or the like can be used as the above-mentioned oxide insulating film.

[0381] Note that a silicon oxynitride film that releases only a small amount of nitrogen oxide is a film that releases more ammonia than nitrogen oxide in TDS; the number of ammonia molecules released from the silicon oxynitride film is generally greater than or equal to 1×10 18 Molecules / cm 3 , and less than or equal to 5×10 19 Molecules / cm 3 Note that the amount of released ammonia is the amount of ammonia released by heat treatment at a film surface temperature higher than or equal to 50° C. and lower than or equal to 650° C. (preferably higher than or equal to 50° C. and lower than or equal to 550° C.).

[0382] For example, nitrogen oxide (NOx; x is greater than 0 and less than or equal to 2, preferably, greater than or equal to 1 and less than or equal to 2) (typically NO2 or NO) forms a state in the insulating film 114. The state is located in the energy gap of the first oxide semiconductor film 110. Therefore, when nitrogen oxide diffuses into the interface between the insulating film 114 and the first oxide semiconductor film 110, electrons are captured by the state on the insulating film 114 side in some cases. As a result, the captured electrons are held near the interface between the insulating film 114 and the first oxide semiconductor film 110; therefore, the threshold voltage of the transistor moves in the positive direction.

[0383] Nitrogen oxide reacts with ammonia and oxygen during heat treatment. Since nitrogen oxide contained in the insulating film 114 reacts with ammonia contained in the insulating film 116 during heat treatment, the amount of nitrogen oxide contained in the insulating film 114 is reduced. Therefore, electrons are rarely trapped at the interface between the insulating film 114 and the first oxide semiconductor film 110.

[0384] By using the above oxide insulating film as the insulating film 114, shift in the threshold voltage of the transistor can be reduced, which leads to reduced variation in electrical characteristics of the transistor.

[0385] In the ESR spectrum at 100K or lower of the insulating film 114 subjected to heat treatment in the transistor manufacturing process (generally, heat treatment at a temperature lower than 400°C or lower than 375°C (preferably higher than or equal to 340°C and lower than or equal to 360°C)), a first signal appearing at a g factor greater than or equal to 2.037 and less than or equal to 2.039, a second signal appearing at a g factor greater than or equal to 2.001 and less than or equal to 2.003, and a third signal appearing at a g factor greater than or equal to 1.964 and less than or equal to 1.966 were observed. Each of the split widths of the first and second signals and the split widths of the second and third signals obtained by ESR measurement using the X-band is approximately 5 mT. The sum of the spin densities of the first signal appearing at a g-factor of 2.037 or more and 2.039 or less, the second signal appearing at a g-factor of 2.001 or more and 2.003 or less, and the third signal appearing at a g-factor of 1.964 or more and 1.966 or less is less than 1×10 18 Spin / cm 3 , typically greater than or equal to 1×10 17 Spin / cm 3 And less than 1×10 18 Spin / cm 3 .

[0386] In the ESR spectrum at 100K or lower, the first signal appearing at a g factor greater than or equal to 2.037 and less than or equal to 2.039, the second signal appearing at a g factor greater than or equal to 2.001 and less than or equal to 2.003, and the third signal appearing at a g factor greater than or equal to 1.964 and less than or equal to 1.966 correspond to signals attributed to nitrogen oxides (NOx: x greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2). Typical examples of nitrogen oxides include nitrogen monoxide and nitrogen dioxide. Therefore, the smaller the sum of the spin densities of the first signal appearing at a g factor greater than or equal to 2.037 and less than or equal to 2.039, the second signal appearing at a g factor greater than or equal to 2.001 and less than or equal to 2.003, and the third signal appearing at a g factor greater than or equal to 1.964 and less than or equal to 1.966, the lower the content of nitrogen oxides in the oxide insulating film.

[0387] The nitrogen concentration in the upper oxide insulating film measured by SIMS is less than or equal to 6×10 20 Atom / cm 3 .

[0388] The above oxide insulating film is formed by a PECVD method using silane and nitrous oxide at a substrate temperature higher than or equal to 220° C. and lower than or equal to 350° C., whereby a dense and hard film can be formed.

[0389] The insulating film 116 in contact with the insulating film 114 is formed using an oxide insulating film having an oxygen content higher than the stoichiometric ratio. By heating, part of oxygen is released from the oxide insulating film having an oxygen content higher than the stoichiometric ratio. The oxide insulating film having an oxygen content higher than the stoichiometric ratio has the following characteristics: in TDS, the amount of oxygen released from the oxide insulating film that is converted into oxygen atoms is greater than or equal to 1.0×10 19 Atom / cm 3 , preferably greater than or equal to 3.0×10 20 Atom / cm 3 Note that the film surface temperature in TDS is preferably higher than or equal to 100°C and lower than or equal to 700°C, or higher than or equal to 100°C and lower than or equal to 500°C.

[0390] In addition, the number of defects in the insulating film 116 is preferably small; generally, in ESR measurement, the spin density of the signal appearing at g=2.001 due to dangling bonds of silicon is preferably lower than 1.5×10 18 Spin / cm 3 , more preferably less than or equal to 1×10 18 Spin / cm 3 Note that the insulating film 116 is located farther from the first oxide semiconductor film 110 than the insulating film 114 is; therefore, the insulating film 116 can have a higher defect density than the insulating film 114.

[0391] The thickness of the insulating film 114 may be greater than or equal to 5 nm and less than or equal to 150 nm, preferably greater than or equal to 5 nm and less than or equal to 50 nm, more preferably greater than or equal to 10 nm and less than or equal to 30 nm. The thickness of the insulating film 116 may be greater than or equal to 30 nm and less than or equal to 500 nm, preferably greater than or equal to 150 nm and less than or equal to 400 nm.

[0392] In addition, the insulating film 114 and the insulating film 116 may be formed using the same type of material; therefore, the interface between the insulating film 114 and the insulating film 116 cannot be clearly observed in some cases. Therefore, in this embodiment, the interface between the insulating film 114 and the insulating film 116 is shown with a dotted line. Although a double-layer structure including the insulating film 114 and the insulating film 116 is described in this embodiment, one embodiment of the present invention is not limited thereto. For example, a single-layer structure of the insulating film 114, a single-layer structure of the insulating film 116, or a stacked layer structure including three or more layers may be used.

[0393] The insulating film 118 as the dielectric film of the capacitor 160 is preferably a nitride insulating film. In particular, a silicon nitride film has a higher dielectric constant than a silicon oxide film, and a larger thickness is required for a capacitance equivalent to that of a silicon oxide film. Therefore, when the insulating film 118 as the dielectric film of the capacitor 160 includes a silicon nitride film, the physical thickness of the insulating film can be increased. This makes it possible to suppress the reduction in the withstand voltage of the capacitor 160, and more precisely, to increase the withstand voltage, thereby preventing electrostatic discharge damage to the capacitor 160. Note that the insulating film 118 also has a function of reducing the resistivity of the second oxide semiconductor film 111 as an electrode of the capacitor 160.

[0394] The insulating film 118 also has a function of blocking oxygen, hydrogen, moisture, alkali metals, alkaline earth metals, and the like. The insulating film 118 can prevent oxygen from diffusing outward from the first oxide semiconductor film 110, oxygen contained in the insulating films 114 and 116 from diffusing outward, and hydrogen, moisture, and the like from entering the first oxide semiconductor film 110 from the outside. Instead of the nitride insulating film having the function of blocking oxygen, hydrogen, moisture, alkali metals, alkaline earth metals, and the like, an oxide insulating film having the function of blocking oxygen, hydrogen, moisture, and the like can be provided. As examples of the oxide insulating film having the function of blocking oxygen, hydrogen, moisture, and the like, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, a yttrium oxide film, an yttrium oxynitride film, a hafnium oxide film, and a hafnium oxynitride film can be given.

[0395] <Method for Manufacturing Semiconductor Device>

[0396] Next, refer to Figures 16A to 16D , Figures 17A to 17C , Figures 18A to 18C and Fig.19A and 19B Description for manufacturing Fig.13A and 13B An example of a method for a semiconductor device in the present invention.

[0397] First, a gate electrode 104 is formed on a substrate 102. Then, an insulating film 108 including insulating films 106 and 107 is formed on the substrate 102 and the gate electrode 104 (see FIG. Fig.16A ).

[0398] Note that each of the substrate 102, the gate electrode 104, and the insulating films 106 and 107 can be formed using a material selected from the materials listed above. In this embodiment, a glass substrate is used as the substrate 102; a tungsten film is used as the conductive film of the gate electrode 104; a silicon nitride film capable of releasing hydrogen is used as the insulating film 106; and a silicon oxynitride film capable of releasing oxygen is used as the insulating film 107.

[0399] The gate electrode 104 can be formed in the following manner: a conductive film is deposited on the substrate 102, and patterned so that a desired region is left, and then unnecessary regions of the conductive film are etched away.

[0400] Next, a first oxide semiconductor film 110 is formed over the insulating film 108 so as to overlap with the gate electrode 104 (see FIG. Fig. 16B ).

[0401] The first oxide semiconductor film 110 can be formed using a material selected from the materials listed above. In this embodiment, as the first oxide semiconductor film 110, an In-Ga-Zn oxide film formed using a metal oxide target of In:Ga:Zn=1:1:1.2 is used.

[0402] The first oxide semiconductor film 110 can be formed by depositing an oxide semiconductor film over the insulating film 108 , patterning the oxide semiconductor film so that a desired region remains, and then etching away unnecessary regions of the oxide semiconductor film.

[0403] After forming the first oxide semiconductor film 110, heat treatment is preferably performed. The heat treatment may be performed in an inert gas atmosphere, an atmosphere containing 10 ppm or more of oxygen, or a reduced pressure atmosphere at a temperature higher than or equal to 250°C and lower than or equal to 650°C, preferably higher than or equal to 300°C and lower than or equal to 500°C, and more preferably higher than or equal to 350°C and lower than or equal to 450°C. Alternatively, heat treatment may be performed first in an inert gas atmosphere, and then another heat treatment may be performed in an atmosphere containing 10 ppm or more of oxygen to compensate for oxygen released from the first oxide semiconductor film 110. By this heat treatment, impurities (such as hydrogen or moisture) may be removed from at least one of the following films: the insulating films 106 and 107 and the first oxide semiconductor film 110. Note that the above heat treatment may be performed before the first oxide semiconductor film 110 is processed into an island shape.

[0404] Note that by reducing impurities in the first oxide semiconductor film 110 so that the first oxide semiconductor film 110 is intrinsic or substantially intrinsic, stable electric characteristics can be effectively imparted to the transistor 150 in which the first oxide semiconductor film 110 serves as a channel region.

[0405] Next, a conductive film is deposited over the insulating film 108 and the first oxide semiconductor film 110 and patterned so that a desired region is left, and then unnecessary regions of the conductive film are etched away, thereby forming a source electrode 112 a and a drain electrode 112 b over the insulating film 108 and the first oxide semiconductor film 110 (see FIG. 1 ). Fig. 16C ).

[0406] The source electrode 112a and the drain electrode 112b may be formed using a material selected from the materials listed above. In this embodiment, the source electrode 112a and the drain electrode 112b have a three-layer structure including a tungsten film, an aluminum film, and a titanium film.

[0407] After forming the source electrode 112a and the drain electrode 112b, the surface of the first oxide semiconductor film 110 may be cleaned. For example, cleaning may be performed using a chemical solution such as phosphoric acid. Cleaning using a chemical solution such as phosphoric acid may remove impurities (e.g., elements included in the source electrode 112a and the drain electrode 112b) attached to the surface of the first oxide semiconductor film 110. Note that cleaning does not necessarily need to be performed, and cleaning may be omitted depending on circumstances.

[0408] In the step of forming the source electrode 112 a and the drain electrode 112 b and / or the cleaning step, the thickness of a region of the first oxide semiconductor film 110 not covered with the source electrode 112 a or the drain electrode 112 b may be reduced.

[0409] Next, insulating films 114 and 116 are formed over the insulating film 108, the first oxide semiconductor film 110, the source electrode 112a, and the drain electrode 112b. Then, the insulating films 114 and 116 are patterned so that desired regions are left, and then unnecessary regions are etched away, thereby forming an opening 141 (see FIG. 1 ). Fig.16D ).

[0410] After forming the insulating film 114, it is preferred that the insulating film 116 is continuously formed without being exposed to air. After forming the insulating film 114, the insulating film 116 is continuously formed while adjusting at least one of the flow rate, pressure, high-frequency power, and substrate temperature of the source gas without being exposed to air, whereby the concentration of impurities due to the atmospheric components at the interface between the insulating films 114 and 116 can be reduced, and oxygen contained in the insulating films 114 and 116 can be moved toward the first oxide semiconductor film 110; therefore, the number of oxygen vacancies in the first oxide semiconductor film 110 can be reduced.

[0411] The insulating film 114 serves as a protective film for the first oxide semiconductor film 110 in the step of forming the insulating film 116. Therefore, the insulating film 116 can be formed using high-intensity high-frequency power while reducing damage to the first oxide semiconductor film 110.

[0412] Each of the insulating films 114 and 116 can be formed using a material selected from the materials listed above. In this embodiment, as each of the insulating films 114 and 116, a silicon oxynitride film capable of releasing oxygen is used.

[0413] Preferably, heat treatment (hereinafter referred to as first heat treatment) is performed after the insulating films 114 and 116 are deposited. The first heat treatment can reduce nitrogen oxides included in the insulating films 114 and 116. Through the first heat treatment, part of the oxygen included in the insulating films 114 and 116 can be moved toward the first oxide semiconductor film 110, so that the number of oxygen vacancies included in the first oxide semiconductor film 110 can be reduced.

[0414] The temperature of the first heat treatment is generally lower than 400°C, preferably lower than 375°C, more preferably higher than or equal to 150°C and lower than or equal to 350°C. The first heat treatment can be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a moisture content of 20ppm or less (preferably 1ppm or less, more preferably 10ppb or less)) or a rare gas (e.g., argon or helium). The atmosphere of nitrogen, oxygen, ultra-dry air or a rare gas preferably does not contain hydrogen and moisture, etc. For the heat treatment, an electric furnace or a rapid thermal annealing (RTA) device, etc. can be used.

[0415] The opening 141 is formed to expose a portion of the drain electrode 112 b. An example of a method for forming the opening 141 is (but not limited to) a dry etching method. Alternatively, a wet etching method or a combination of dry etching and wet etching may be used as a method for forming the opening 141. Note that the etching step for forming the opening 141 reduces the thickness of the drain electrode 112 b in some cases.

[0416] Next, an oxide semiconductor film to be the second oxide semiconductor film 111 is formed over the insulating film 116 so as to cover the opening 141 (see FIG. 14A ). Fig.17A and 17B ).

[0417] Notice, Fig.17A 116 is a schematic cross-sectional view of the interior of a deposition apparatus used when an oxide semiconductor film is formed over the insulating film 116. Fig.17A , a sputtering device is used as a deposition device, and a target 193 placed in the sputtering device and a plasma 194 generated under the target 193 are schematically shown.

[0418] When an oxide semiconductor film is formed, first, plasma discharge is performed in an atmosphere containing oxygen. At this time, oxygen is added to the insulating film 116 on which the oxide semiconductor film is to be formed. When the oxide semiconductor film is formed, an inert gas (e.g., helium, argon, or xenon) and a third oxygen gas may be mixed. For example, argon gas and a third oxygen gas having a flow rate higher than that of argon gas are preferably used. When the flow rate of the third oxygen gas is high, oxygen may be advantageously added to the insulating film 116. As an example of the formation conditions of an oxide semiconductor film, the proportion of the third oxygen gas in the entire deposition gas may be higher than or equal to 50% and lower than or equal to 100%, preferably higher than or equal to 80% and lower than or equal to 100%.

[0419] exist Fig.17A , oxygen or excess oxygen added to the insulating film 116 is schematically shown by a dotted arrow.

[0420] The oxide semiconductor film is deposited at a substrate temperature higher than or equal to room temperature and lower than 340°C (preferably higher than or equal to room temperature and lower than or equal to 300°C, more preferably higher than or equal to 100°C and lower than or equal to 250°C, more preferably higher than or equal to 100°C and lower than or equal to 200°C). The oxide semiconductor film is deposited while being heated, so that the crystallinity of the oxide semiconductor film can be increased. On the other hand, in the case of using a large glass substrate (for example, 6th to 10th generation) as the substrate 102 and depositing the oxide semiconductor film at a substrate temperature higher than or equal to 150°C and lower than 340°C, the substrate 102 may be deformed (twisted or warped). Even in the case of using a large glass substrate, the change in the shape of the glass substrate can be suppressed by depositing the oxide semiconductor film at a substrate temperature higher than or equal to 100°C and lower than 150°C.

[0421] The oxide semiconductor film can be formed using a material selected from the materials listed above. In this embodiment, an oxide semiconductor film is formed by a sputtering method using an In-Ga-Zn metal oxide target having an atomic ratio of In:Ga:Zn=1:3:6.

[0422] Next, the oxide semiconductor film is processed into a desired shape to form an island-shaped second oxide semiconductor film 111 (see Fig. 17C ).

[0423] The second oxide semiconductor film 111 can be formed in the following manner: an oxide semiconductor film is deposited over the insulating film 116 and patterned so that a desired region is left, and then unnecessary regions of the oxide semiconductor film are etched away.

[0424] Next, an insulating film 118 is formed over the insulating film 116 and the second oxide semiconductor film 111 (see Fig.18A ).

[0425] The insulating film 118 contains hydrogen and / or nitrogen. As the insulating film 118, for example, a silicon nitride film is preferably used. For example, the insulating film 118 can be formed by a sputtering method or a PECVD method. In the case of depositing the insulating film 118 by the PECVD method, for example, the substrate temperature is lower than 400°C, preferably lower than 375°C, more preferably higher than or equal to 180°C and lower than or equal to 350°C. The substrate temperature when depositing the insulating film 118 is preferably within the above range because a dense film can be formed. In addition, when the substrate temperature for depositing the insulating film 118 is within the above range, oxygen or excess oxygen in the insulating films 114 and 116 can be moved toward the first oxide semiconductor film 110.

[0426] After forming the insulating film 118, heat treatment similar to the first heat treatment described above (hereinafter referred to as second heat treatment) may be performed. After oxygen is added to the insulating film 116 while depositing the oxide semiconductor film to be the second oxide semiconductor film 111, heat treatment is performed at a temperature lower than 400° C. (preferably lower than 375° C., more preferably higher than or equal to 180° C. and lower than or equal to 350° C.), whereby oxygen or excess oxygen in the insulating film 116 can move toward the first oxide semiconductor film 110 and compensate for oxygen vacancies in the first oxide semiconductor film 110.

[0427] Reference Fig.19A and 19B The migration of oxygen to the first oxide semiconductor film 110 is described. Fig.19A and 19B: is a model diagram showing oxygen moving to the first oxide semiconductor film 110 due to the substrate temperature (typically, lower than 375° C.) when the insulating film 118 is deposited or the second heat treatment (typically, lower than 375° C.) after the insulating film 118 is formed. Fig.19A and 19B In FIG. 1 , oxygen (oxygen radicals, oxygen atoms, or oxygen molecules) in the first oxide semiconductor film 110 is shown by a dotted arrow. Note that Fig.19A and 19B Along the Fig.13A It is a cross-sectional view taken along the dashed line AB and the dashed line EF in FIG. 1 , and shows a state in which the insulating film 118 has been deposited.

[0428] exist Fig.19A and 19B In the first oxide semiconductor film 110, oxygen vacancies are compensated by oxygen moved from the film in contact with the first oxide semiconductor film 110 (here, the insulating film 107 and the insulating film 114). Specifically, in a semiconductor device of one embodiment of the present invention, since oxygen is added to the insulating film 107 when the oxide semiconductor film to be the first oxide semiconductor film 110 is deposited by sputtering using oxygen, the insulating film 107 includes an oxygen excess region. Since oxygen is added to the insulating film 116 when the oxide semiconductor film to be the second oxide semiconductor film 111 is deposited by sputtering using oxygen, the insulating film 116 also includes an oxygen excess region. Therefore, oxygen vacancies in the first oxide semiconductor film 110 between the insulating films including the oxygen excess region can be advantageously compensated.

[0429] In addition, the insulating film 106 is provided under the insulating film 107, and the insulating film 118 is provided over the insulating films 114 and 116. When each of the insulating films 106 and 118 is formed using a material having low oxygen permeability such as silicon nitride, oxygen contained in the insulating films 107, 114, and 116 can be confined on the first oxide semiconductor film 110 side; therefore, oxygen can be favorably moved toward the first oxide semiconductor film 110. Note that the insulating film 118 also has an effect of preventing impurities such as moisture, alkali metal, or alkaline earth metal from diffusing into the first oxide semiconductor film 110 included in the transistor 150.

[0430] The insulating film 118 contains hydrogen and / or nitrogen. Therefore, hydrogen and / or nitrogen are added to the second oxide semiconductor film 111 in contact with the formed insulating film 118, so that the second oxide semiconductor film 111 has a high carrier density and can function as an oxide conductive film.

[0431] Since the resistivity of the second oxide semiconductor film is reduced, Fig.18A The shadow pattern of the second oxide semiconductor film 111 in Fig. 17C The difference in.

[0432] The resistivity of the second oxide semiconductor film 111 is at least lower than that of the first oxide semiconductor film 110, and is preferably higher than or equal to 1×10 -3 Ωcm and less than 1×10 4 Ωcm, more preferably greater than or equal to 1×10 -3 Ωcm and less than 1×10 -1 Ωcm.

[0433] Then, the opening 142 is formed in the following manner: the insulating film 118 is patterned so as to leave a desired area, and then the unnecessary area is etched away (see FIG. Fig.18B ).

[0434] The opening 142 is formed to expose a portion of the drain electrode 112 b. An example of a method for forming the opening 142 is (but not limited to) a dry etching method. Alternatively, a wet etching method or a combination of dry etching and wet etching may be used as a method for forming the opening 142. Note that the etching step for forming the opening 142 reduces the thickness of the drain electrode 112 b in some cases.

[0435] Note that the openings may be formed in the insulating films 114, 116, and 118 simultaneously in the step of forming the opening 142 without performing the step of forming the opening 141. In this case, the number of manufacturing steps of the semiconductor device of one embodiment of the present invention can be reduced, resulting in reduced manufacturing cost.

[0436] Then, a conductive film is deposited over the insulating film 118 so as to cover the opening 142, and is patterned and etched into a desired shape; thus, a conductive film 120 (see FIG. 1 ) is formed. Fig.18C ).

[0437] The conductive film 120 can be formed using a material selected from the materials listed above. In this embodiment, an indium tin oxide film is used as the conductive film 120.

[0438] When the conductive film 120 is formed, the capacitor 160 is completed. The capacitor 160 includes a dielectric layer between a pair of electrodes. One of the pair of electrodes corresponds to the second oxide semiconductor film 111, and the other of the pair of electrodes corresponds to the conductive film 120. In addition, the insulating film 118 serves as a dielectric layer of the capacitor 160.

[0439] Through the above steps, the transistor 150 and the capacitor 160 may be formed over the substrate.

[0440] The structure, method, and the like described in this embodiment can be appropriately combined with the structure, method, and the like described in any other embodiment.

[0441] (Example 7)

[0442] In this embodiment, reference will be made to Fig. 20A and 20B , Figures 21A to 21D and Figures 22A to 22C A modified example of the semiconductor device of one embodiment of the present invention is described. Note that the same reference numerals are used to denote the same Fig.13A and 13B , Fig.14A and 14B , Fig.15A and 15B , Figures 16A to 16D , Figures 17A to 17C , Figures 18A to 18C as well as Fig.19A and 19B The parts that are similar to the parts in the specification or have similar functions are described herein and their description will not be repeated.

[0443] <Structural Example of Semiconductor Device (Modification 1)>

[0444] Fig. 20A A top view of a semiconductor device according to an embodiment of the present invention is shown. Fig. 20B Shown along Fig. 20A The cross-sectional view obtained by the dashed line GH, dashed line IJ and dashed line KL in FIG. Note that Fig. 20A Some components of the semiconductor device (eg, a gate insulating film) are not shown to avoid complexity.

[0445] Fig. 20A and 20B The semiconductor device in the embodiment includes a transistor 151 including a first oxide semiconductor film 110 and a second oxide semiconductor film 111a, and a gate wiring contact portion 170 including a second oxide semiconductor film 111b. Note that the gate wiring contact portion 170 refers to a region where the gate wiring 105 is electrically connected to the wiring 112.

[0446] Notice, Fig. 20A The direction of the dot-dash line GH corresponds to the channel length direction of the transistor 151. The direction of the dot-dash line KL corresponds to the channel width direction of the transistor 151.

[0447] The transistor 151 includes: a gate electrode 104 on the substrate 102, an insulating film 108 on the gate electrode 104 and serving as a first gate insulating film, a first oxide semiconductor film 110 on the insulating film 108 and overlapping with the gate electrode 104, a source electrode 112a and a drain electrode 112b on the first oxide semiconductor film 110, insulating films 114 and 116 on the first oxide semiconductor film 110, the source electrode 112a, and the drain electrode 112b and serving as a second gate insulating film, and a second oxide semiconductor film 111a on the insulating film 116 and overlapping with the first oxide semiconductor film 110. The second oxide semiconductor film 111a serves as a second gate electrode of the transistor 151. In other words, Fig. 20A and 20B The transistor 151 in FIG. 1 has a dual-gate structure.

[0448] In addition, over the transistor 151, specifically, over the insulating film 116 and the second oxide semiconductor film 111a, an insulating film 118 is formed. The insulating films 114 and 116 function not only as a second gate insulating film of the transistor 151 but also as a protective insulating film of the transistor 151. The insulating film 118 functions as a protective insulating film of the transistor 151.

[0449] In the gate wiring contact portion 170 , the second oxide semiconductor film 111 b is formed over the gate wiring 105 and the wiring 112 to cover the opening 144 provided in the insulating film 108 and the opening 146 provided in the insulating films 114 and 116 .

[0450] In the gate wiring contact portion 170 of the semiconductor device described in this embodiment, the gate wiring 105 is electrically connected to the wiring 112 through the second oxide semiconductor film 111b. In this structure, the opening 144 and the opening 146 can be continuously formed, and therefore, the manufacturing process of the semiconductor device can be shortened.

[0451] If a protective film that blocks oxygen ingress is not provided over the second oxide semiconductor film 111b, the second oxide semiconductor film 111b may deteriorate to have a higher resistivity in a high temperature and high humidity environment. In the semiconductor device described in this embodiment, the second oxide semiconductor film 111b is covered with the insulating film 118; therefore, the high temperature and high humidity resistance of the semiconductor device can be improved without forming another protective film.

[0452] Note that an insulating film containing at least hydrogen is used as the insulating film 118. In addition, an insulating film containing at least oxygen is used as each of the insulating films 107, 114, and 116. As described above, when the insulating film used for the transistor 151 and the gate wiring contact portion 170 or the insulating film in contact with the transistor 151 and the gate wiring contact portion 170 has the above-described structure, the resistivity of the first oxide semiconductor film 110 and the resistivity of the second oxide semiconductor films 111a and 111b can be controlled.

[0453] Note that for a method for controlling the resistivity of the first oxide semiconductor film 110 and the resistivity of the second oxide semiconductor films 111 a and 111 b , the description of Embodiment 6 can be referred to.

[0454] Described in Example 6 Fig.13A and 13B semiconductor devices and Fig. 20A and 20B The main differences between the semiconductor devices are that the gate wiring contact portion 170 is provided instead of the capacitor 160, the transistor 151 includes the second oxide semiconductor film 111a as the second gate electrode, and the conductive film 120 is not provided.

[0455] <Method for Manufacturing Display Device (Modification 1)>

[0456] Next, refer to Figures 21A to 21D and Figures 22A to 22C Description for manufacturing Fig. 20A and 20B An example of a method for a semiconductor device in the present invention.

[0457] First, the gate electrode 104 and the gate wiring 105 are formed on the substrate 102. Then, the insulating film 108 including the insulating films 106 and 107 is formed over the gate electrode 104 and the gate wiring 105 (see Fig.21A ). The gate wiring 105 can be formed simultaneously with the gate electrode 104 using a material similar to that of the gate electrode 104 .

[0458] Next, a first oxide semiconductor film 110 is formed over the insulating film 108 so as to overlap with the gate electrode 104 (see FIG. Fig.21B ).

[0459] The first oxide semiconductor film 110 can be formed by depositing an oxide semiconductor film over the insulating film 108 and patterning it so that a desired region is left, and then etching away unnecessary regions of the oxide semiconductor film.

[0460] When the first oxide semiconductor film 110 is processed by etching, part of the insulating film 107 (region not covered with the first oxide semiconductor film 110) may be over-etched and reduced in thickness.

[0461] Heat treatment is preferably performed after forming the first oxide semiconductor film 110. For the heat treatment here, the description of the heat treatment after forming the first oxide semiconductor film 110 of Embodiment 6 can be referred to.

[0462] Next, a conductive film is deposited over the insulating film 108 and the first oxide semiconductor film 110 and patterned so that a desired region is left, and then unnecessary regions of the conductive film are etched away, thereby forming a source electrode 112a, a drain electrode 112b, and a wiring 112 (see FIG. 1 ). Fig. 21C ). The wiring 112 may be formed simultaneously with the source electrode 112a and the drain electrode 112b using a material similar to that of the source electrode 112a and the drain electrode 112b.

[0463] Next, insulating films 114 and 116 are formed over the insulating film 108, the first oxide semiconductor film 110, the source electrode 112a, the drain electrode 112b, and the wiring 112 (see FIG. 114 ). Fig.21D ). After the insulating films 114 and 116 are formed, the first heat treatment described in Embodiment 6 is preferably performed.

[0464] Then, the openings 144 and 146 are formed in the following manner: the insulating films 106, 107, 114, and 116 are patterned so as to leave desired regions, and then unnecessary regions are etched away (see FIG. Fig.22A ).

[0465] The openings 144 and 146 are formed to expose a portion of the wiring 112 and a portion of the gate wiring 105. An example of a method for forming the openings 144 and 146 is (but not limited to) a dry etching method. Alternatively, a wet etching method or a combination of dry etching and wet etching may be used as a method for forming the openings 144 and 146.

[0466] By one patterning step followed by etching, opening 144 and opening 146 may be formed simultaneously, which results in a shorter manufacturing process.

[0467] Next, a second oxide semiconductor film 111a is formed over the insulating film 116 so as to overlap with the first oxide semiconductor film 110, and at the same time, a second oxide semiconductor film 111b is formed over the insulating film 116 so as to cover the openings 144 and 146 (see FIG. 14). Fig. 22B ). For a method for forming the second oxide semiconductor film 111 a and the second oxide semiconductor film 111 b , the method for forming the second oxide semiconductor film 111 of Embodiment 6 can be referred to.

[0468] The second oxide semiconductor films 111 a and 111 b can be formed in the following manner: an oxide semiconductor film is deposited on the insulating film 116 and patterned so that a desired region is left, and then unnecessary regions of the oxide semiconductor film are etched away.

[0469] When the second oxide semiconductor films 111 a and 111 b are processed by etching, part of the insulating film 116 (regions not covered by the second oxide semiconductor films 111 a and 111 b ) may be over-etched and reduced in thickness.

[0470] Next, an insulating film 118 is formed over the insulating film 116 and the second oxide semiconductor films 111a and 111b (see Fig. 22C ). Hydrogen contained in the insulating film 118 diffuses into the second oxide semiconductor films 111a and 111b, thereby reducing the resistivity of the second oxide semiconductor films 111a and 111b. Since the resistivity of the second oxide semiconductor films 111a and 111b is reduced, Fig. 22B The hatching pattern of the second oxide semiconductor films 111a and 111b in FIG. Fig. 22C In addition, the second heat treatment described in Embodiment 6 may be performed after the insulating film 118 is formed.

[0471] Through the above steps, the transistor 151 and the gate wiring contact portion 170 can be formed over one substrate.

[0472] The structure, method, and the like described in this embodiment can be appropriately combined with the structure, method, and the like described in other embodiments.

[0473] (Example 8)

[0474] In this embodiment, reference will be made to Fig.23A and 23B , Figures 24A to 24D and Figures 25A to 25C A modified example of the semiconductor device of one embodiment of the present invention described in Embodiment 6 is described. Note that the same reference numerals as those used in Embodiment 6 are used to denote the semiconductor device of Embodiment 6. Fig.13A and 13B , Fig.14A and 14B , Fig.15A and 15B , Figures 16A to 16D , Figures 17A to 17C , Figures 18A to 18C as well as Fig.19A and 19B The parts that are similar to the parts in the specification or have similar functions are described herein and their description will not be repeated.

[0475] <Structural Example of Semiconductor Device (Modification 2)>

[0476] Fig.23A A top view of a semiconductor device according to an embodiment of the present invention is shown. Fig. 23B Shown along Fig.23A The cross-sectional part obtained by the dot-dash line MN, dot-dash line OP and dot-dash line QR in FIG. Note that Fig.23A Some components of the semiconductor device (eg, a gate insulating film) are not shown to avoid complexity.

[0477] Fig.23A and 23B The semiconductor device in includes a transistor 151 including a first oxide semiconductor film 110 and a second oxide semiconductor film 111a, and a gate wiring contact portion 171. Note that the gate wiring contact portion 171 refers to a region in which the gate wiring 105 is electrically connected to the wiring 112.

[0478] Notice, Fig.23A The direction of the midpoint chain line MN corresponds to the channel length direction of the transistor 151. The direction of the dot chain line QR corresponds to the channel width direction of the transistor 151.

[0479] The transistor 151 includes: a gate electrode 104 on the substrate 102, an insulating film 108 on the gate electrode 104 and serving as a first gate insulating film, a first oxide semiconductor film 110 on the insulating film 108 and overlapping with the gate electrode 104, a source electrode 112a and a drain electrode 112b on the first oxide semiconductor film 110, insulating films 114 and 116 on the first oxide semiconductor film 110, the source electrode 112a, and the drain electrode 112b and serving as a second gate insulating film, and a second oxide semiconductor film 111a on the insulating film 116 and overlapping with the first oxide semiconductor film 110. The second oxide semiconductor film 111a serves as a second gate electrode of the transistor 151. In other words, Fig.23A and 23B The transistor 151 in FIG. 1 has a dual-gate structure.

[0480] In addition, over the transistor 151, specifically, over the insulating film 116 and the second oxide semiconductor film 111a, an insulating film 118 and an insulating film 119 are formed. The insulating films 114 and 116 serve not only as a second gate insulating film of the transistor 151, but also as a protective insulating film of the transistor 151. The insulating film 118 serves as a protective insulating film of the transistor 151. The insulating film 119 serves as a planarizing film. In addition, an opening reaching the drain electrode 112b is formed in the insulating films 114, 116, 118, and 119. A conductive film 120 is formed over the insulating film 119 to cover these openings. The openings provided in the insulating films 114 and 116 are referred to as openings 146, and the openings provided in the insulating films 118 and 119 are referred to as openings 148. The conductive film 120 serves as, for example, a pixel electrode.

[0481] In the gate wiring contact portion 171 , the wiring 112 is formed over the gate wiring 105 so as to cover the opening 144 provided in the insulating film 108 .

[0482] In the semiconductor device described in this embodiment, the end of the insulating film 118 and the end of the insulating film 119 are substantially aligned with each other in the opening 148. Since the semiconductor device has such a structure, the number of patterning masks can be reduced, and thus the manufacturing cost can be reduced.

[0483] Note that an insulating film containing at least hydrogen is used as the insulating film 118. In addition, an insulating film containing at least oxygen is used as each of the insulating films 107, 114, and 116. As described above, when the insulating film used for the transistor 151 or the insulating film in contact with the transistor 151 has the above-described structure, the resistivity of the first oxide semiconductor film 110 and the resistivity of the second oxide semiconductor film 111a included in the transistor 151 can be controlled.

[0484] Note that for a method for controlling the resistivity of the first oxide semiconductor film 110 and the resistivity of the second oxide semiconductor film 111 a , the description of Embodiment 6 can be referred to.

[0485] Described in Example 6 Fig.13A and 13B semiconductor devices and Fig.23A and 23B The main differences between the semiconductor devices are that the gate wiring contact portion 171 is provided instead of the capacitor 160, the transistor 151 includes the second oxide semiconductor film 111a as the second gate electrode, and the insulating film 119 is provided.

[0486] <Method for Manufacturing Display Device (Modification 2)>

[0487] Next, refer to Figures 24A to 24D and Figures 25A to 25CDescription for manufacturing Fig.23A and 23B An example of a method for a semiconductor device.

[0488] First, the gate electrode 104 and the gate wiring 105 are formed over the substrate 102. Then, the insulating film 108 including the insulating films 106 and 107 is formed over the gate electrode 104 and the gate wiring 105. The gate wiring 105 can be formed simultaneously with the gate electrode 104 using a material similar to that of the gate electrode 104.

[0489] Next, a first oxide semiconductor film 110 is formed over the insulating film 108 so as to overlap with the gate electrode 104 (see FIG. Fig.24A ).

[0490] The first oxide semiconductor film 110 can be formed by depositing an oxide semiconductor film over the insulating film 108 , patterning the oxide semiconductor film so that a desired region remains, and then etching away unnecessary regions of the oxide semiconductor film.

[0491] When the first oxide semiconductor film 110 is processed by etching, part of the insulating film 108 (region not covered with the first oxide semiconductor film 110 ) may be over-etched and reduced in thickness.

[0492] Heat treatment is preferably performed after forming the first oxide semiconductor film 110. For the heat treatment here, the description of the heat treatment after forming the first oxide semiconductor film 110 in Embodiment 6 can be referred to.

[0493] The opening 144 is formed in the following manner: the insulating films 106 and 107 are patterned so as to leave a desired area, and then, unnecessary areas are etched away (see FIG. Fig. 24B ).

[0494] The opening 144 is formed to expose part of the gate wiring 105. An example of a method for forming the opening 144 is, but not limited to, dry etching. Alternatively, a wet etching method or a combination of dry etching and wet etching may be employed as a method for forming the opening 144.

[0495] Next, a conductive film is deposited over the insulating film 108, the gate wiring 105, and the first oxide semiconductor film 110, and is patterned so that a desired region is left, and then unnecessary regions of the conductive film are etched away, thereby forming a source electrode 112a, a drain electrode 112b, and a wiring 112 (see FIG. 1 ). Fig.24C ). The wiring 112 may be formed simultaneously with the source electrode 112a and the drain electrode 112b using a material similar to that of the source electrode 112a and the drain electrode 112b.

[0496] Next, insulating films 114 and 116 are formed over the insulating film 108, the first oxide semiconductor film 110, the source electrode 112a, the drain electrode 112b, and the wiring 112. After the insulating films 114 and 116 are formed, the first heat treatment described in Embodiment 6 is preferably performed.

[0497] Then, the opening 146 is formed in the following manner: the insulating films 114 and 116 are patterned so as to leave a desired area, and then the unnecessary area is etched away (see FIG. Fig.24D ).

[0498] The opening 146 is formed to expose a portion of the drain electrode 112 b. An example of a method for forming the opening 146 is, but not limited to, a dry etching method. Alternatively, a wet etching method or a combination of dry etching and wet etching may be used as a method for forming the opening 146 .

[0499] Next, the second oxide semiconductor film 111a is formed over the insulating film 116 so as to overlap with the first oxide semiconductor film 110. The method for forming the second oxide semiconductor film 111 in Embodiment 6 can be referred to for a method of forming the second oxide semiconductor film 111a.

[0500] The second oxide semiconductor film 111 a can be formed in the following manner: an oxide semiconductor film is deposited over the insulating film 116 , patterned so that a desired region is left, and then unnecessary regions of the oxide semiconductor film are etched away.

[0501] When the second oxide semiconductor film 111 a is processed by etching, part of the insulating film 116 (region not covered by the second oxide semiconductor film 111 a ) may be over-etched and reduced in thickness.

[0502] Next, the insulating film 118 is formed over the insulating film 116, the second oxide semiconductor film 111a, and the drain electrode 112b. Hydrogen contained in the insulating film 118 diffuses into the second oxide semiconductor film 111a, thereby reducing the resistivity of the second oxide semiconductor film 111a.

[0503] Next, an insulating film 119 is formed on the insulating film 118 (see Fig.25A ). The insulating film 119 can be formed using a heat-resistant organic material such as a polyimide resin, an acrylic resin, a polyimide amide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin. An organic resin film is formed over the insulating film and patterned so that a desired region is left, and then an unnecessary region is etched away, thereby forming an opening overlapping with the opening 146.

[0504] Then, the insulating film 118 is etched using the insulating film 119 having the opening as a mask, thereby forming the opening 148 (see FIG. Fig.25B ). Since the insulating film 119 can be used as a mask, the opening 148 can be formed without additional masking and patterning. Therefore, the manufacturing cost of the semiconductor device can be reduced.

[0505] Then, a conductive film is deposited over the insulating film 119 so as to cover the opening 148, and is patterned and etched into a desired shape; thus, a conductive film 120 (see FIG. 1 ) is formed. Fig.25C ).

[0506] Through the above steps, the transistor 151 and the gate wiring contact portion 171 can be formed over one substrate.

[0507] The structure, method, and the like described in this embodiment can be appropriately combined with the structure, method, and the like described in any other embodiment.

[0508] (Example 9)

[0509] In this embodiment, examples of oxide semiconductors which can be used for transistors, capacitors, and gate wiring contact portions of a semiconductor device of one embodiment of the present invention will be described.

[0510] The structure of the oxide semiconductor will be described below.

[0511] In this specification, the term "parallel" means that the angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and therefore also includes the case where the angle is greater than or equal to -5° and less than or equal to 5°. The term "substantially parallel" means that the angle formed between two straight lines is greater than or equal to -30° and less than or equal to 30°. The term "perpendicular" means that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and therefore also includes the case where the angle is greater than or equal to 85° and less than or equal to 95°. The term "substantially perpendicular" means that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°.

[0512] In this specification, the hexagonal crystal system includes the trigonal crystal system and the rhombohedral crystal system.

[0513] Oxide semiconductors are classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include c-axis aligned crystalline oxide semiconductors (CAAC-OS), polycrystalline oxide semiconductors, nanocrystalline semiconductor oxides (nc-OS), amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0514] From another perspective, oxide semiconductors are classified into amorphous oxide semiconductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS.

[0515] It is known that amorphous structures are typically defined as being metastable and not fixed, and being isotropic, and having no inconsistency. In other words, amorphous structures have flexible bond angles and short-range order, but no long-range order.

[0516] This means that an intrinsically stable oxide semiconductor cannot be considered a completely amorphous oxide semiconductor. In addition, a non-isotropic oxide semiconductor (e.g., an oxide semiconductor having a periodic structure in a microscopic range) cannot be considered a completely amorphous oxide semiconductor. Although it has a periodic structure in a microscopic range, an a-like OS has an unstable structure including voids. Therefore, an a-like OS has physical properties similar to those of an amorphous oxide semiconductor.

[0517] <caac-os>

[0518] First, CAAC-OS will be described.

[0519] CAAC-OS is a type of oxide semiconductor, and has a plurality of c-axis aligned crystal portions (also referred to as pellets).

[0520] In a combined analysis image of a bright field image and a diffraction pattern of CAAC-OS obtained using a TEM (transmission electron microscope), also referred to as a high-resolution transmission electron microscope (TEM) image, a plurality of small particles can be observed. However, in a high-resolution TEM image, the boundaries between the small particles, i.e., the grain boundaries, cannot be clearly observed. Therefore, in CAAC-OS, a reduction in electron mobility due to grain boundaries rarely occurs.

[0521] The CAAC-OS observed by TEM will be described below. Fig.26A A high-resolution TEM image of a cross section of the CAAC-OS observed in a direction substantially parallel to the sample surface is shown. The high-resolution TEM image is obtained using a spherical aberration corrector function. The high-resolution TEM image obtained using the spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be obtained using, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

[0522] Fig.26B Shows Fig.26A Enlarged Cs-corrected high-resolution TEM image of area (1). Fig.26B It is shown that metal atoms are arranged in a layered manner in a small particle. Each metal atomic layer has a configuration that reflects the unevenness of the surface on which the CAAC-OS is formed (the surface is also referred to as the formation surface) or the top surface of the CAAC-OS, and is arranged parallel to the top surface of the CAAC-OS or the formation surface.

[0523] like Fig.26B As shown, CAAC-OS has a characteristic atomic arrangement. Fig.26C Indicated by auxiliary lines. Fig.26B and 26C It is proved that the size of the small particle is 1nm or more, or 3nm or more, and the space caused by the inclination of the small particle is approximately 0.8nm. Therefore, the small particle can also be called a nanocrystal (nc). In addition, CAAC-OS can also be called an oxide semiconductor including c-axis aligned nanocrystals (CANC).

[0524] Here, according to the Cs-corrected high-resolution TEM image, a schematic arrangement of the small particles 5100 of CAAC-OS on the substrate 5120 is shown as a structure in which bricks or blocks are stacked together (see FIG. Fig.26D ).exist Fig.26C The part where the small particles are tilted corresponds to Fig.26D Area 5161 in.

[0525] Fig.27A A Cs-corrected high-resolution TEM image of a plane of CAAC-OS observed in a direction substantially perpendicular to the sample surface is shown. Fig.27B , 27C and 27D respectively show Fig.27A Enlarged Cs-corrected high-resolution TEM images of regions (1), (2), and (3) in FIG. Fig.27B , 27C 27D and 27D indicate that the metal atoms are arranged in a triangular, quadrilateral or hexagonal configuration in the pellet. However, there is no regularity in the arrangement of metal atoms between different pellets.

[0526] Next, the CAAC-OS analyzed by X-ray diffraction (XRD) will be described. For example, when the structure of the CAAC-OS including InGaZnO4 crystals is analyzed by an out-of-plane method, as shown in FIG. Fig.28A As shown, a peak appears at a diffraction angle (2θ) of about 31°. This peak originates from the (009) plane of the InGaZnO4 crystal, indicating that the crystal in the CAAC-OS has a c-axis orientation, and the c-axis is aligned in a direction substantially perpendicular to the top surface or the formation surface of the CAAC-OS.

[0527] In the structural analysis of CAAC-OS performed by the out-of-plane method, in addition to the peak at 2θ of about 31°, another peak may appear when 2θ is about 36°. The peak at 2θ of about 36° indicates that part of the CAAC-OS includes crystals that do not have c-axis alignment. In the structural analysis of the preferred CAAC-OS performed by the out-of-plane method, a peak appears when 2θ is about 31°, and no peak appears when 2θ is about 36°.

[0528] On the other hand, in the structural analysis of CAAC-OS by the in-plane method in which X-rays are incident on the sample in a direction substantially perpendicular to the c-axis, a peak appears when 2θ is approximately 56°. This peak originates from the (110) plane of the InGaZnO4 crystal. Fig.28B As shown in Figure 2, when 2θ is fixed at about 56° and the sample is rotated using the normal vector of the sample surface as the axis (Φ axis), the CAAC-OS is analyzed (Φ scan), and the peak cannot be clearly observed. Fig.28C As shown, when a single crystal oxide semiconductor of InGaZnO4 is Φ scanned with 2θ fixed at about 56°, 6 peaks originating from a crystal plane equivalent to the (110) plane are observed. Therefore, structural analysis using XRD shows that the directions of the a-axis and the b-axis are irregularly oriented in CAAC-OS.

[0529] Next, CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam having a detection diameter of 300 nm is incident on a CAAC-OS including InGaZnO4 crystal in a direction parallel to the sample surface, it is possible to obtain Fig.29A The diffraction pattern shown in FIG. 1 (also referred to as a selected area transmission electron diffraction pattern). This diffraction pattern includes spots originating from the (009) plane of the InGaZnO4 crystal. Therefore, the electron diffraction result also indicates that the small particles included in the CAAC-OS have a c-axis alignment, and the c-axis is aligned in a direction substantially perpendicular to the top surface or the formation surface of the CAAC-OS. At the same time, Fig.29B The diffraction pattern obtained in a manner where an electron beam having a detection diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface is shown. Fig.29B Therefore, the electron diffraction results also indicate that the a-axis and the b-axis of the small particles included in the CAAC-OS do not have a regular alignment. Fig.29B The first ring in is believed to originate from the (010) plane, (100) plane, and so on of the InGaZnO4 crystal. Fig.29B The second ring in is thought to originate from the (110) plane, and so on.

[0530] As described above, CAAC-OS is an oxide semiconductor with high crystallinity. The ingress of impurities, the formation of defects, etc. may reduce the crystallinity of the oxide semiconductor. This means that CAAC-OS has a negligible amount of impurities and defects (eg, oxygen vacancies).

[0531] Note that impurities mean elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or transition metal elements. For example, an element (e.g., silicon) having a stronger bonding force to oxygen than the metal element contained in the oxide semiconductor extracts oxygen from the oxide semiconductor, which causes disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. Heavy metals such as iron or nickel, argon, carbon dioxide, etc. have a large atomic radius (or molecular radius), and thus interfere with the atomic arrangement of the oxide semiconductor and reduce the crystallinity.

[0532] The properties of an oxide semiconductor having impurities or defects may be changed by light, heat, etc. Impurities contained in an oxide semiconductor may, for example, serve as a carrier trap or a carrier generation source. In addition, oxygen vacancies in an oxide semiconductor may serve as a carrier trap or a carrier generation source when hydrogen is trapped therein.

[0533] CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with a low carrier density (specifically, less than 8×10 11 / cm 3 , preferably less than 1×10 11 / cm 3 , more preferably less than 8×10 10 / cm 3 , and greater than or equal to 1×10 -9 / cm 3 ). This oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and a low defect state density. Therefore, CAAC-OS can be called an oxide semiconductor with stable characteristics.

[0534] <nc-os>

[0535] Next, nc-OS will be described.

[0536] The high-resolution TEM image of nc-OS has an area in which a crystalline portion is observed, and an area in which the crystalline portion cannot be clearly observed. In most cases, the size of the crystalline portion included in the nc-OS is greater than or equal to 1nm and less than or equal to 10nm, or greater than or equal to 1nm and less than or equal to 3nm. An oxide semiconductor including a crystalline portion having a size greater than 10nm and less than or equal to 100nm can be referred to as a microcrystalline oxide semiconductor. In the high-resolution TEM image of nc-OS, for example, the grain boundaries cannot be clearly observed in some cases. Note that there is a possibility that the source of the nanocrystals is the same as the source of the small particles in the CAAC-OS. Therefore, the crystalline portion of the nc-OS may also be referred to as a small particle in the following description.

[0537] In nc-OS, a microscopic region (for example, a region having a size greater than or equal to 1 nm and less than or equal to 10 nm, and in particular, a region having a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement.

[0538] There is no regular crystal orientation between different particles in nc-OS. Therefore, the orientation of the entire film is not observed. Therefore, according to this analysis method, nc-OS cannot be distinguished from a-like OS or amorphous oxide semiconductors. For example, when an X-ray beam having a diameter greater than the size of the particles is used to analyze nc-OS by an out-of-plane method, no peak indicating a crystal plane appears. In addition, when an electron beam having a detection diameter greater than the size of the particles (e.g., 50nm or greater) is used to electron diffract nc-OS, a diffraction pattern similar to a halo pattern is observed. At the same time, when an electron beam having a detection diameter close to or less than the size of the particles is used, spots are observed in the nanobeam electron diffraction pattern of nc-OS. In addition, in the nanobeam electron diffraction pattern of nc-OS, a circular (annular) pattern with a high brightness area is observed in some cases. In some cases, multiple spots are also observed in the annular region.

[0539] Since there is no regular crystal orientation between small particles (nanocrystals) as described above, the nc-OS may also be referred to as an oxide semiconductor including randomly aligned nanocrystals (RANCs) or an oxide semiconductor including non-aligned nanocrystals (NANCs).

[0540] nc-OS is an oxide semiconductor with higher regularity than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect state density than a-like OS and amorphous oxide semiconductors. Note that there is no regular crystal orientation between different particles in nc-OS. Therefore, nc-OS has a higher defect state density than CAAC-OS.

[0541] <a-like OS>

[0542] The a-like OS has a structure between that of the nc-OS and that of the amorphous oxide semiconductor.

[0543] In the high-resolution TEM image of a-like OS, voids can be observed. In addition, the high-resolution TEM image has a region where a crystal portion is clearly observed, and a region where a crystal portion is not observed.

[0544] a-like OS has an unstable structure including voids. In order to verify that a-like OS has an unstable structure compared with CAAC-OS and nc-OS, the structural changes caused by electron irradiation will be described below.

[0545] As samples subjected to electron irradiation, a-like OS (sample A), nc-OS (sample B), and CAAC-OS (sample C) were prepared. Each sample was an In-Ga-Zn oxide.

[0546] First, a high-resolution cross-sectional TEM image of each sample was obtained. The high-resolution cross-sectional TEM image showed that all samples had a crystalline portion.

[0547] Note that which part is considered to be the crystal part can be determined as follows. The unit cell of the known InGaZnO4 crystal has a structure in which 9 layers consisting of 3 In-O layers and 6 Ga-Zn-O layers are stacked in the c-axis direction. The distance between adjacent layers is equivalent to the lattice spacing (also known as the d value) of the (009) plane. According to the crystal structure analysis, this value is calculated to be 0.29nm. Therefore, the part where the interval between the lattice fringes is greater than or equal to 0.28nm and less than or equal to 0.30nm can be considered to be the crystal part of InGaZnO4. Each lattice fringe corresponds to the ab plane of the InGaZnO4 crystal.

[0548] Fig.30 The change in the average size of the crystal part (22 points to 45 points) in each sample is shown. Note that the crystal part size corresponds to the length of the lattice fringes. Fig.30 It is shown that the size of the crystal part in a-like OS increases with the increase of the accumulated electron dose. Fig.30 As shown in (1) in the figure, at the beginning of TEM observation, the crystal part of approximately 1.2 nm (also called the initial nucleus) is 4.2×10 8 e - / nm 2 The size of the crystalline part in nc-OS and CAAC-OS increases from the initial size of electron irradiation to 4.2×10 8 e - / nm 2 The cumulative electron dose of shows little change. Specifically, Fig.30 As shown in (2) and (3) in FIG, regardless of the accumulated electron dose, the average crystal sizes in nc-OS and CAAC-OS are approximately 1.4 nm and approximately 2.1 nm, respectively.

[0549] In this way, the growth of the crystal part in a-like OS can be induced by electron irradiation. In contrast, in nc-OS and CAAC-OS, it is difficult to induce the growth of the crystal part by electron irradiation. That is, a-like OS has an unstable structure compared with nc-OS and CAAC-OS.

[0550] Since a-like OS includes voids, a-like OS has a lower density than nc-OS and CAAC-OS. Specifically, the density of a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of a single crystal oxide semiconductor having the same composition. The density of nc-OS and the density of CAAC-OS are each higher than or equal to 92.3% and lower than 100% of the density of a single crystal oxide semiconductor having the same composition. It is difficult to deposit an oxide semiconductor having a density lower than 78% of the density of a single crystal oxide semiconductor.

[0551] For example, in the case of an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO4 having a rhombohedral crystal structure is 6.357 g / cm 3 Therefore, in the case of an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of the a-like OS is higher than or equal to 5.0 g / cm 3 And less than 5.9g / cm 3 For example, in the case of an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, each of the density of nc-OS and the density of CAAC-OS is higher than or equal to 5.9 g / cm 3 And less than 6.3g / cm 3 .

[0552] Note that there is a possibility that an oxide semiconductor having a certain composition cannot exist in a single crystal state. In this case, single crystal oxide semiconductors having different compositions are combined in appropriate ratios, which makes it possible to calculate a density equivalent to the density of a single crystal oxide semiconductor having a desired composition. The density of a single crystal oxide semiconductor having a desired composition can be calculated using a weighted average of the combination ratios of single crystal oxide semiconductors having different compositions. Note that it is preferred to calculate the density using as few types of single crystal oxide semiconductors as possible.

[0553] As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be, for example, a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, a nc-OS, and a CAAC-OS.

[0554] <Method of Depositing CAAC-OS>

[0555] An example of a method of depositing the CAAC-OS will be described below. Fig.31 The interior of a deposition chamber is schematically shown. CAAC-OS may be deposited by a sputtering method.

[0556] like Fig.31 As shown, a substrate 5220 and a target 5230 are arranged facing each other. Plasma 5240 is generated between the substrate 5220 and the target 5230. A heating mechanism 5260 is located under the substrate 5220. The target 5230 is attached to a backing plate (not shown). A plurality of magnets are arranged to face the target 5230, and the backing plate is positioned between the magnets and the target 5230. A sputtering method that uses the magnetic field of a magnet to increase the deposition rate is called a magnetron sputtering method.

[0557] The distance d between the substrate 5220 and the target 5230 (also referred to as the target-substrate distance (TS distance)) is greater than or equal to 0.01 m and less than or equal to 1 m, preferably greater than or equal to 0.02 m and less than or equal to 0.5 m. The deposition chamber is mainly filled with a deposition gas (for example, oxygen, argon, or a mixed gas containing 5 vol% or more of oxygen), and the pressure in the deposition chamber is controlled to be greater than or equal to 0.01 Pa and less than or equal to 100 Pa, preferably greater than or equal to 0.1 Pa and less than or equal to 10 Pa. Here, the discharge is started by applying a specific voltage or a higher voltage to the target 5230, and the plasma 5240 is observed. The magnetic field forms a high-density plasma region near the target 5230. The deposition gas is ionized in the high-density plasma region, thereby generating ions 5201. Examples of ions 5201 include oxygen cations (O + ) and argon cations (Ar + ).

[0558] The target 5230 has a polycrystalline structure including a plurality of grains, any one of which includes a cleavage plane. Figures 32A to 32C An example of a crystal structure of InMZnO4 (element M is, for example, Al, Ga, Y, or Sn) included in the target 5230 is shown. Note that Fig.32A The crystal structure of InMZnO4 observed in the direction parallel to the b-axis is shown. In InMZnO4, oxygen atoms are negatively charged, thereby generating a repulsive force between two adjacent M-Zn-O layers. Therefore, the InMZnO4 crystal has a cleavage plane between two adjacent M-Zn-O layers.

[0559] The ions 5201 generated in the high-density plasma region are accelerated by the electric field to reach the target 5230 side, and then collide with the target 5230. At this time, the small particles 5200 are separated from the cleavage surface (see Fig.31 ), the small particles 5200 are flat plate-shaped or small granular sputtered particles. The small particles 5200 correspond to Fig.32A Therefore, the cross section of the pellet 5200 is as follows: Fig.32B As shown, and its top view is as Fig.32C Note that the structure of pellet 5200 may be deformed by the collision of ion 5201.

[0560] The small particles 5200 are flat or granular sputtered particles with triangular faces (e.g., regular triangular faces). Alternatively, the small particles 5200 are flat or granular sputtered particles with hexagonal faces (e.g., regular hexagonal faces). However, the planar shape of the small particles 5200 is not limited to triangles or hexagons. For example, the face can have a shape formed by combining two or more triangles. For example, a quadrilateral (e.g., rhombus) is formed by combining two triangles (e.g., regular triangles).

[0561] The thickness of the small particle 5200 is determined according to the type of deposition gas, etc. For example, the thickness of the small particle 5200 is greater than or equal to 0.4nm and less than or equal to 1nm, preferably greater than or equal to 0.6nm and less than or equal to 0.8nm. The width of the small particle 5200 is, for example, greater than or equal to 1nm and less than or equal to 100nm, preferably greater than or equal to 2nm and less than or equal to 50nm, more preferably greater than or equal to 3nm and less than or equal to 30nm. For example, ions 5201 collide with a target 5230 including In-M-Zn oxide. As a result, the small particle 5200 including three layers (i.e., M-Zn-O layer, In-O layer, and M-Zn-O layer) is separated. As the small particle 5200 is separated, the particle 5203 is also sputtered out from the target 5230. The particle 5203 has an atom or an aggregate of several atoms. Therefore, the particle 5203 can also be referred to as an atomic particle.

[0562] When passing through plasma 5240, the surface of particle 5200 may be negatively or positively charged. 2- As a result, the oxygen atoms on the surface of the particle 5200 may be negatively charged. In addition, when passing through the plasma 5240, the particle 5200 sometimes combines with indium, element M, zinc, oxygen, etc. in the plasma 5240 to grow.

[0563] The particles 5200 and the particles 5203 that have passed through the plasma 5240 reach the surface of the substrate 5220. Note that since the mass of some of the particles 5203 is very small, they may be discharged to the outside by a vacuum pump or the like.

[0564] Next, refer to Figures 33A to 33F Describes the deposition of pellets 5200 and particles 5203 on the surface of substrate 5220.

[0565] First, the first particle 5200 is deposited on the substrate 5220. The particle 5200 having a plate shape is deposited so that its flat surface faces the surface of the substrate 5220. Here, the charge on the surface of the particle 5200 on the substrate 5220 side is lost through the substrate 5220.

[0566] Next, the second particle 5200 reaches the substrate 5220. Since the surface of the first particle 5200 and the surface of the second particle 5200 are charged, they repel each other. As a result, the second particle 5200 avoids being deposited on the first particle 5200, but is deposited at a position a small distance from the first particle 5200, with its flat surface facing the surface of the substrate 5220. This process is repeated, and millions of particles 5200 are deposited on the surface of the substrate 5220 until the thickness of a layer. Areas where no particles 5200 are deposited are formed between adjacent particles 5200 (see Fig.33A ).

[0567] Then, the particle 5203 having received energy from the plasma reaches the surface of the substrate 5220. The particle 5203 cannot be deposited on an active region such as the surface of the particle 5200. Therefore, the particle 5203 moves to a region where the particle 5200 is not deposited, and adheres to the side surface of the particle 5200. The available bonds of the particle 5203 are activated with the energy received from the plasma, so that the particle 5203 is chemically bonded to the particle 5200 to form a lateral growth portion 5202 (see FIG. 5 ). Fig.33B ).

[0568] The lateral growth portion 5202 further grows laterally, so that the particles 5200 are anchored to each other (see Fig.33C ). In this way, the lateral growth portion 5202 is formed until the area in which the small particle 5200 is not deposited is filled. This mechanism is similar to the deposition mechanism of the atomic layer deposition (ALD) method.

[0569] Even when the deposited particles 5200 are oriented in different directions, the particles 5203 cause lateral growth to fill the gaps between the particles 5200; therefore, no clear grain boundaries are formed. In addition, since the particles 5203 form a smooth connection between the particles 5200, a crystal structure different from a single crystal structure and a polycrystalline structure is formed. In other words, a deformed crystal structure including tiny crystal regions (particles 5200) is formed. The regions that fill the gaps between the crystal regions are distorted crystal regions, and therefore, it may not be appropriate to say that these regions have an amorphous structure.

[0570] Next, a new pellet 5200 is deposited with its flat surface facing the surface of the substrate 5220 (see Fig.33D ). Then, particles 5203 are deposited to fill the area where no small particles 5200 are deposited, thereby forming a lateral growth portion 5202 (see Fig.33E ). In this way, the particles 5203 are attached to the side surfaces of the small particles 5200, and the lateral growth of the lateral growth portion 5202 continues, so that the small particles 5200 in the second layer are anchored to each other (see Fig.33F ). The deposition is continued until the m-th layer (m is an integer of 2 or more) is formed; as a result, a stacked thin film structure is formed.

[0571] The deposition manner of the small particles 5200 changes according to the surface temperature of the substrate 5220, etc. For example, if the surface temperature of the substrate 5220 is high, migration of the small particles 5200 occurs above the surface of the substrate 5220. As a result, the proportion of small particles 5200 directly connected to each other without particles 5203 increases, thereby forming a CAAC-OS with a higher orientation. The surface temperature of the substrate 5220 on which the CAAC-OS is deposited is higher than or equal to room temperature and lower than or equal to 340°C, preferably higher than or equal to room temperature and lower than or equal to 300°C, more preferably higher than or equal to 100°C and lower than or equal to 250°C, more preferably higher than or equal to 100°C and lower than or equal to 200°C. Therefore, even when a large substrate of the 8th generation or larger is used as the substrate 5220, warping and the like due to the deposition of CAAC-OS hardly occur.

[0572] On the other hand, if the surface temperature of the substrate 5220 is low, the migration of the small particles 5200 on the surface of the substrate 5220 is not likely to occur. As a result, the small particles 5200 are stacked to form, for example, nc-OS with low orientation. In nc-OS, when the small particles 5200 are negatively charged, the small particles 5200 may be deposited with some gaps. Therefore, nc-OS has a low orientation, but has a certain regularity, and thus has a denser structure than an amorphous oxide semiconductor.

[0573] In CAAC-OS, small particles positioned very close to each other can form a large small particle. The large small particle has a single crystal structure inside. For example, when viewed from above, the size of the small particle may be greater than or equal to 10nm and less than or equal to 200nm, greater than or equal to 15nm and less than or equal to 100nm, or greater than or equal to 20nm and less than or equal to 50nm.

[0574] As shown in this deposition model, small particles are considered to be deposited on the surface of the substrate. CAAC-OS can be deposited even when the forming surface does not have a crystalline structure. This shows that the above-mentioned deposition model, as a growth mechanism different from epitaxial growth, has high validity. In addition, according to the above-mentioned deposition model, uniform and consistent CAAC-OS or nc-OS can be deposited even on a large glass substrate, etc. For example, CAAC-OS can be deposited even on the surface (forming surface) of a substrate having an amorphous structure (e.g., amorphous silicon oxide).

[0575] In addition, even when the surface (formation surface) of the substrate has an uneven shape, the particles are aligned along the shape.

[0576] The above deposition model suggests that CAAC-OS with high crystallinity can be deposited in the following manner: deposition is performed in a high vacuum to obtain a long mean free path, plasma energy is weakened to reduce damage around the substrate, and thermal energy is applied to the forming surface to repair damage caused by plasma during deposition.

[0577] The above deposition model is applicable not only to the case where the target has a polycrystalline structure of a composite oxide (e.g., In-M-Zn oxide) (wherein the composite oxide has multiple grains, any one of which has a cleavage plane), but also to the case where, for example, a target containing a mixture of indium oxide, an oxide of element M and zinc oxide is used.

[0578] Since there is no cleavage plane in the target of the mixture, the atomic particles are separated from the target by sputtering. During deposition, a high electric field region of plasma is formed around the target. Due to the high electric field region of plasma, the atomic particles separated from the target are combined with each other, thereby causing lateral growth. For example, lateral growth occurs first in the form of atomic particles of indium combined with each other to become nanocrystals of the In-O layer. Then, the M-Zn-O layer is complementarily bonded to the top and bottom surfaces of the nanocrystalline In-O layer. In this way, small particles can be formed even when a mixture target is used. Therefore, the above deposition model is also applicable to the case of using a target of a mixture. In the case where a high electric field region of plasma is not formed around the target, the atomic particles separated from the target are only deposited on the substrate surface. In this case, lateral growth of atomic particles may occur on the substrate surface. However, since the atomic particles are unevenly oriented, the crystal orientation in the resulting film is uneven. As a result, nc-OS or the like is obtained.

[0579] (Example 10)

[0580] In this embodiment, reference will be made to Figures 34A to 34C , Figures 35A to 35D , Fig.36A and 36B as well as Fig.37A and 37B A transistor having a structure different from that of the transistor described in Embodiment 6 is described.

[0581] <Transistor Structure Example 1>

[0582] Fig.34A A top view of transistor 270 is shown. Fig.34B Shown along Fig.34A The cross section is obtained by the dot-dash line X1-X2 in Fig.34C Shown along Fig.34A The direction of the dot-dash line X1-X2 may be referred to as a channel length direction, and the direction of the dot-dash line Y1-Y2 may be referred to as a channel width direction.

[0583] The transistor 270 includes a conductive film 204 which is over the substrate 202 and serves as a first gate electrode, an insulating film 206 which is over the substrate 202 and the conductive film 204, an insulating film 207 which is over the insulating film 206, an oxide semiconductor film 208 which is over the insulating film 207, a conductive film 212a which is electrically connected to the oxide semiconductor film 208 and serves as a source electrode, a conductive film 212b which is electrically connected to the oxide semiconductor film 208 and serves as a drain electrode, insulating films 214 and 216 which are over the oxide semiconductor film 208 and the conductive films 212a and 212b, and an oxide semiconductor film 211b which is over the insulating film 216. In addition, an insulating film 218 is provided over the oxide semiconductor film 211b.

[0584] In the transistor 270, the insulating film 214 and the insulating film 216 serve as a second gate insulating film of the transistor 270. The oxide semiconductor film 211a is connected to the conductive film 212b through the opening 252c provided in the insulating film 214 and the insulating film 216. The oxide semiconductor film 211a serves as, for example, a pixel electrode for a display device. The oxide semiconductor film 211b serves as a second gate electrode (also referred to as a back gate electrode) of the transistor 270.

[0585] like Fig.34C As shown, the oxide semiconductor film 211b is connected to the conductive film 204 as a first gate electrode through openings 252a and 252b provided in the insulating films 206, 207, 214, and 216. Therefore, the conductive film 204 and the oxide semiconductor film 211b are supplied with the same potential.

[0586] One embodiment of the present invention is not limited to the structure described in this embodiment in which the oxide semiconductor film 211b and the conductive film 204 are connected to each other through the openings 252a and 252b. For example, only one of the openings 252a and 252b may be formed to connect the oxide semiconductor film 211b and the conductive film 204 to each other, or the openings 252a and 252b for connecting the oxide semiconductor film 211b to the conductive film 204 do not need to be provided. In the case where the oxide semiconductor film 211b and the conductive film 204 are not connected to each other, different potentials may be provided to the oxide semiconductor film 211b and the conductive film 204.

[0587] like Fig.34B As shown, the oxide semiconductor film 208 is located between the conductive film 204 as the first gate electrode and the oxide semiconductor film 211b as the second gate electrode, that is, between the two conductive films as gate electrodes. The length of the oxide semiconductor film 211b as the second gate electrode in the channel length direction and the length in the channel width direction are longer than the length of the oxide semiconductor film 208 in the channel length direction and the length in the channel width direction. The entire oxide semiconductor film 208 is covered with the oxide semiconductor film 211b, and the insulating films 214 and 216 are located between them. Since the oxide semiconductor film 211b as the second gate electrode is connected to the conductive film 204 as the first gate electrode through the openings 252a and 252b provided in the insulating films 206, 207, 214 and 216, the side surface of the oxide semiconductor film 208 in the channel width direction faces the oxide semiconductor film 211b as the second gate electrode, and the insulating films 214 and 216 are located between them.

[0588] In other words, in the channel width direction of the transistor 270, the conductive film 204 serving as the first gate electrode and the oxide semiconductor film 211b serving as the second gate electrode are connected to each other through openings provided in the insulating films 206 and 207 serving as the first gate insulating film and the insulating films 214 and 216 serving as the second gate insulating film, and the conductive film 204 and the oxide semiconductor film 211b surround the oxide semiconductor film 208, with the insulating films 206 and 207 serving as the first gate insulating film and the insulating films 214 and 216 serving as the second gate insulating film located therebetween.

[0589] This structure enables the oxide semiconductor film 208 included in the transistor 270 to be electrically surrounded by the electric field of the conductive film 204 as the first gate electrode and the oxide semiconductor film 211b as the second gate electrode. A device structure of a transistor such as the transistor 270 in which the electric field of the first gate electrode and the second gate electrode electrically surrounds the oxide semiconductor film in which the channel region is formed can be referred to as a wrapped channel (S-channel) structure.

[0590] Since the transistor 270 has an S-channel structure, an electric field for inducing a channel can be effectively applied to the oxide semiconductor film 208 through the conductive film 204 as the first gate electrode; therefore, the current driving capability of the transistor 270 can be improved, and a high on-state current characteristic can be obtained. Since the on-state current can be increased, the size of the transistor 270 can be reduced. In addition, since the oxide semiconductor film 208 is surrounded by the conductive film 204 as the first gate electrode and the oxide semiconductor film 211b as the second gate electrode, the mechanical strength of the transistor 270 can be increased.

[0591] <Transistor Structure Example 2>

[0592] Next, refer to Figures 35A to 35D Description and Figures 34A to 34C The structural example of the transistor 270 in FIG. 1 is different from the structural example.

[0593] Fig.35A and 35B A cross-sectional view is shown, showing Fig.34B and 34C A modified example of the transistor 270 in FIG. Fig.35C and 35D A cross-sectional view is shown, showing Fig.34B and 34C A modified example of the transistor 270 in FIG.

[0594] In addition to the oxide semiconductor film 208 having a three-layer structure, Fig.35A and 35B The transistor 270A has Fig.34B and 34C The transistor 270A has the same structure as the transistor 270. Specifically, the oxide semiconductor film 208 of the transistor 270A includes an oxide semiconductor film 208a, an oxide semiconductor film 208b, and an oxide semiconductor film 208c.

[0595] In addition to the oxide semiconductor film 208 having a two-layer structure, Fig.35C and 35D The transistor 270B has the same Fig.34B and 34C The transistor 270B has the same structure as the transistor 270 in FIG. Specifically, the oxide semiconductor film 208 of the transistor 270B includes an oxide semiconductor film 208b and an oxide semiconductor film 208c.

[0596] For the structures of the transistors 270, 270A, and 270B described in this embodiment, the description of the structure of the semiconductor device of Embodiment 6 can be referred to. Therefore, for the material and the formation method of the substrate 202, the description of the substrate 102 can be referred to. For the material and the formation method of the conductive film 204, the description of the gate electrode 104 can be referred to. For the materials and the formation method of the insulating film 206 and the insulating film 207, the description of the insulating film 106 and the insulating film 107 can be referred to, respectively. For the material and the formation method of the oxide semiconductor film 208, the description of the first oxide semiconductor film 110 can be referred to. For the materials and the formation method of the oxide semiconductor film 211a and the oxide semiconductor film 211b, the description of the second oxide semiconductor film 111 can be referred to. For the materials and the formation method of the conductive film 212a and the conductive film 212b, the description of the source electrode 112a and the drain electrode 112b can be referred to. For the materials and formation methods of the insulating films 214 , 216 , and 218 , reference can be made to the descriptions of the insulating films 114 , 116 , and 118 , respectively.

[0597] Here, we will refer to Fig.36A and 36B An energy band structure of a region including an oxide semiconductor film and an insulating film in contact with the oxide semiconductor film is described.

[0598] Fig.36A An example of an energy band structure in the thickness direction of a stacked-layer structure including the insulating film 207 , the oxide semiconductor films 208 a , 208 b , and 208 c , and the insulating film 214 is shown. Fig.36B 2 shows an example of an energy band structure in the thickness direction of a stacked structure including an insulating film 207, oxide semiconductor films 208b and 208c, and an insulating film 214. For easy understanding, the energy band structure shows the energy levels of the conduction band minimum energy level (Ec) of the insulating film 207, the oxide semiconductor films 208a, 208b, and 208c, and the insulating film 214.

[0599] Fig.36A An energy band diagram of a structure is shown in which a silicon oxide film is used as each of the insulating films 207 and 214, an oxide semiconductor film formed using a metal oxide target having a metal element atomic ratio of In:Ga:Zn=1:1:1.2 is used as each of the oxide semiconductor films 208a and 208c, and an oxide semiconductor film formed using a metal oxide target having a metal element atomic ratio of In:Ga:Zn=4:2:4.1 is used as the oxide semiconductor film 208b.

[0600] Fig.36B An energy band diagram of a structure is shown in which a silicon oxide film is used as each of the insulating films 207 and 214, an oxide semiconductor film formed using a metal oxide target having a metal element atomic ratio of In:Ga:Zn=4:2:4.1 is used as the oxide semiconductor film 208b, and an oxide semiconductor film formed using a metal oxide target having a metal element atomic ratio of In:Ga:Zn=1:1:1.2 is used as the oxide semiconductor film 208c.

[0601] like Fig.36A and 36B As shown, the conduction band minimum energy level gradually changes between the oxide semiconductor film 208a and the oxide semiconductor film 208b, and between the oxide semiconductor film 208b and the oxide semiconductor film 208c. In other words, the energy level of the conduction band minimum energy level changes continuously, or a continuous junction is formed. This energy band structure requires that there are no impurities that form defect states (such as capture centers or recombination centers) at the interface between the oxide semiconductor film 208a and the oxide semiconductor film 208b or at the interface between the oxide semiconductor film 208b and the oxide semiconductor film 208c.

[0602] In order to form a continuous junction between the oxide semiconductor film 208a and the oxide semiconductor film 208b and between the oxide semiconductor film 208b and the oxide semiconductor film 208c, it is necessary to stack the films successively without exposure to the air by using a multi-chamber deposition apparatus (sputtering apparatus) provided with a loadlock chamber.

[0603] In having Fig.36A or Fig.36B In the above-mentioned stacked structure transistor, a channel region is formed in the oxide semiconductor film 208b serving as a well.

[0604] By providing the oxide semiconductor films 208 a and 208 c , the oxide semiconductor film 208 b can be away from a trap state.

[0605] If the trap state is farther from the vacuum energy level than the conduction band minimum energy level (Ec) of the oxide semiconductor film 208b as the channel region, the electrons are likely to be accumulated in the trap state. The electrons accumulated in the trap state become negative fixed charges, so that the threshold voltage of the transistor shifts in the positive direction. Therefore, preferably, the trap state is closer to the vacuum energy level than the conduction band minimum energy level (Ec) of the oxide semiconductor film 208b. This structure suppresses the accumulation of electrons in the trap state. As a result, the on-state current and field effect mobility of the transistor can be increased.

[0606] The conduction band minimum energy level of each of the oxide semiconductor films 208a and 208c is closer to the vacuum energy level than the conduction band minimum energy level of the oxide semiconductor film 208b. Typically, the difference between the conduction band minimum energy level of the oxide semiconductor film 208b and the conduction band minimum energy level of each of the oxide semiconductor films 208a and 208c is 0.15 eV or more or 0.5 eV or more, and 2 eV or less or 1 eV or less. That is, the difference between the electron affinity of each of the oxide semiconductor films 208a and 208c and the electron affinity of the oxide semiconductor film 208b is 0.15 eV or more or 0.5 eV or more, and 2 eV or less or 1 eV or less.

[0607] In this structure, the oxide semiconductor film 208b serves as the main current path. In other words, the oxide semiconductor film 208b serves as a channel region, and the oxide semiconductor films 208a and 208c serve as oxide insulating films. In addition, since the oxide semiconductor films 208a and 208c contain one or more metal elements contained in the oxide semiconductor film 208b in which the channel region is formed, interface scattering rarely occurs at the interface between the oxide semiconductor film 208a and the oxide semiconductor film 208b or at the interface between the oxide semiconductor film 208b and the oxide semiconductor film 208c. Therefore, since the movement of carriers is not hindered at the interface, the transistor can have a high field effect mobility.

[0608] In order to prevent the oxide semiconductor films 208a and 208c from being part of the channel region, a material having a sufficiently low conductivity is used for the oxide semiconductor films 208a and 208c. In view of their properties and / or functions, the oxide semiconductor films 208a and 208c may also be referred to as oxide insulating films. The material used for the oxide semiconductor films 208a and 208c has a lower electron affinity (the difference between the vacuum energy level and the conduction band minimum energy level) than the material of the oxide semiconductor film 208b, and is selected so that there is a difference (band offset) between the conduction band minimum energy level of each of the oxide semiconductor films 208a and 208c and the conduction band minimum energy level of the oxide semiconductor film 208b. In addition, in order to prevent the threshold voltage from changing according to the drain voltage, it is preferred to form the oxide semiconductor films 208a and 208c using a material whose conduction band minimum energy level is closer to the vacuum energy level by 0.2 eV or more, more preferably 0.5 eV or more, than the conduction band minimum energy level of the material of the oxide semiconductor film 208b.

[0609] For the following reasons, preferably, each of the oxide semiconductor films 208a and 208c does not have a spinel crystal structure. If the oxide semiconductor film 208a or 208c has a spinel crystal structure, the constituent elements of the conductive films 212a and 212b may diffuse into the oxide semiconductor film 208b through the interface between the spinel crystal structure and another region. Note that each of the oxide semiconductor films 208a and 208c is preferably a CAAC-OS film, in which case a higher barrier performance is obtained for the constituent elements (e.g., copper) of the conductive films 212a and 212b.

[0610] Each of the oxide semiconductor films 208a and 208c has a thickness that can suppress diffusion of constituent elements of the conductive films 212a and 212b into the oxide semiconductor film 208b and does not hinder supply of oxygen from the insulating film 214 to the oxide semiconductor film 208b. For example, when the thickness of each of the oxide semiconductor films 208a and 208c is greater than or equal to 10 nm, diffusion of constituent elements of the conductive films 212a and 212b into the oxide semiconductor film 208b can be suppressed. When the thickness of each of the oxide semiconductor films 208a and 208c is less than or equal to 100 nm, oxygen can be efficiently supplied from the insulating film 214 to the oxide semiconductor film 208b.

[0611] One embodiment of the present invention is not limited to the example described in this embodiment, in which an oxide semiconductor film formed using a metal oxide target having an atomic ratio of metal elements In:Ga:Zn=1:1:1.2 is used as each of the oxide semiconductor films 208a and 208c. For example, an oxide semiconductor film formed using a metal oxide target having an atomic ratio of In:Ga:Zn=1:1:1, 1:3:2, 1:3:4, or 1:3:6 may be used as each of the oxide semiconductor films 208a and 208c.

[0612] When the oxide semiconductor films 208a and 208c are formed using a metal oxide target having an atomic ratio of In:Ga:Zn=1:1:1, the oxide semiconductor films 208a and 208c have an atomic ratio of In:Ga:Zn=1:β1(0<β1≤2):β2(0<β2≤3) in some cases. When the oxide semiconductor films 208a and 208c are formed using a metal oxide target having an atomic ratio of In:Ga:Zn=1:3:4, the oxide semiconductor films 208a and 208c have an atomic ratio of In:Ga:Zn=1:β3(1≤β3≤5):β4(2≤β4≤6) in some cases. When the oxide semiconductor films 208a and 208c are formed using a metal oxide target having an atomic ratio of In:Ga:Zn=1:3:6, the oxide semiconductor films 208a and 208c have an atomic ratio of In:Ga:Zn=1:β5(1≤β5≤5):β6(4≤β6≤8) in some cases.

[0613] The drawings show an example in which the oxide semiconductor film 208 included in the transistor 270 and the oxide semiconductor film 208c included in the transistors 270A and 270B have a small thickness in a region that does not overlap with the conductive film 212a or the conductive film 212b, that is, an example in which a portion of the oxide semiconductor film has a concave portion. However, one embodiment of the present invention is not limited thereto, and the oxide semiconductor film does not necessarily have a concave portion in a region that does not overlap with the conductive film 212a or the conductive film 212b. Fig.37A and 37B An example of this situation is shown. Fig.37A and 37B 2 is a cross-sectional view showing an example of a transistor. Except that the oxide semiconductor film 208 does not have a concave portion, Fig.37A and 37B The transistor 270B in has the same structure as described above.

[0614] The structures of the transistors of this embodiment can be freely combined with each other.

[0615] The structure and method described in this embodiment may be appropriately combined with the structure and method described in any other embodiment.

[0616] (Example 11)

[0617] In this embodiment, reference will be made to Fig.38 and Fig.39 An example of a display device including the transistor described in the above embodiment is described.

[0618] <Overview>

[0619] Fig.38 is a plan view showing an example of a display device. Fig.38 The display device 700 in the embodiment includes: a pixel portion 702 arranged on a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 arranged above the first substrate 701, a sealant 712 arranged around the pixel portion 702, the source driver circuit portion 704 and the gate driver circuit portion 706, and a second substrate 705 arranged facing the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with the sealant 712. That is, the pixel portion 702, the source driver circuit portion 704 and the gate driver circuit portion 706 are enclosed with the first substrate 701, the sealant 712 and the second substrate 705. Although Fig.38 As not shown in the figure, the display element is arranged between the first substrate 701 and the second substrate 705.

[0620] In the display device 700, a flexible printed circuit (FPC) terminal portion 708 electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 is provided in a region different from the region above the first substrate 701 and surrounded by the sealant 712. In addition, the FPC 716 is connected to the FPC terminal portion 708, and various signals and the like are provided from the FPC 716 to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706. In addition, the wiring 710 is connected to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708. Through the wiring 710, various signals and the like are provided from the FPC 716 to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708.

[0621] A plurality of gate driver circuit portions 706 may be provided in the display device 700. In the display device 700 shown as an example, a source driver circuit portion 704 and a gate driver circuit portion 706 and a pixel portion 702 are formed over a first substrate 701; however, the structure is not limited thereto. For example, only the gate driver circuit portion 706 may be formed over the first substrate 701, or only the source driver circuit portion 704 may be formed over the first substrate 701. In this case, a substrate on which a source driver circuit or a gate driver circuit, etc. is formed (for example, a driver circuit board formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701. Note that there is no particular limitation on the method for connecting a separately prepared driver circuit board, and a chip on glass (COG) method or a wire bonding method, etc. may be used.

[0622] The structure of the semiconductor device described in Embodiment 6 can be applied to a plurality of transistors and capacitors included in the pixel portion 702 of the display device 700. In addition, the structure of the semiconductor device described in Embodiment 7 can be applied to a plurality of transistors and wiring contact portions included in the source driver circuit portion 704 and the gate driver circuit portion 706.

[0623] <Display Components>

[0624] The display device 700 can adopt various modes and include various display elements. Examples of display elements include: liquid crystal elements, electroluminescent (EL) elements (EL elements including organic and inorganic materials, organic EL elements, or inorganic EL elements) including LEDs (e.g., white light LEDs, red light LEDs, green light LEDs, or blue light LEDs), transistors (transistors that emit light according to current), electron emitters, electrophoretic elements, display elements using microelectromechanical systems (MEMS), such as grating light valves (GLVs), digital micromirror devices (DMDs), digital microshutters (DMS) elements, MIRASOL (registered trademark) displays, interferometric modulator displays (IMOD) elements, or piezoelectric ceramic displays, and electrowetting elements. In addition, display media that change their contrast, brightness, reflectivity, transmittance, etc. through electrical or magnetic effects may be included. Alternatively, quantum dots may be used as display elements. An example of a display device including a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, or projection liquid crystal display). An example of a display device including an EL element is an EL display. Examples of display devices including electron emitters include field emission displays (FED) and SED type flat panel displays (SED: surface-conduction electron-emitter, surface conduction electron emitter display). An example of a display device including quantum dots is a quantum dot display. An example of a display device including electronic ink or electrophoretic elements is electronic paper. In a transflective liquid crystal display or a reflective liquid crystal display, some or all of the pixel electrodes can be used as reflective electrodes. For example, some or all of the pixel electrodes can contain aluminum, silver, etc. In this case, a memory circuit such as SRAM can be set under the reflective electrode, which results in lower power consumption.

[0625] <Display System>

[0626] As the display system of the display device 700, a progressive system, an interlaced system, etc. can be adopted. In addition, the color elements controlled in the pixel during color display are not limited to three colors: R, G and B (R, G and B correspond to red, green and blue, respectively). For example, four pixels of R pixel, G pixel, B pixel and W (white) pixel can be used. Alternatively, as in the PenTile layout, a color element can be composed of two colors of R, G and B. These two colors can be different for different color elements. Alternatively, one or more colors of yellow, cyan, magenta, etc. can be added to RGB. Note that the size of the display area can be different between color element points. The embodiments of the disclosed invention are not limited to color display devices; the disclosed invention can also be applied to monochrome display devices.

[0627] <Color display method>

[0628] A full-color display device can be obtained using a color film (also referred to as a color filter), in which white light (W) is used as a backlight (e.g., an organic EL element, an inorganic EL element, an LED, or a fluorescent lamp). For example, a red (R) color film, a green (G) color film, a blue (B) color film, and a yellow (Y) color film can be appropriately combined. Using a color film, high color reproducibility can be obtained compared to the case where there is no color film. Here, by setting an area with a color film and an area without a color film, the white light in the area without the color film can be directly used for display. By partially setting an area without a color film, the reduction in brightness of a bright image caused by the color film can be suppressed, and in some cases, power consumption can be reduced by about 20% to 30%. In the case of performing a full-color display using a self-luminous element (such as an organic EL element or an inorganic EL element), the element can emit light in their corresponding R, G, B, Y, and W colors. By using a self-luminous element, power consumption can be further reduced compared to the case where a color film is used.

[0629] <Structure>

[0630] In this embodiment, reference will be made to Fig.39 A structure of a display device including a liquid crystal element as a display element is described.

[0631] Fig.39 It is along Fig.38 The cross-sectional view obtained by the dot-dash line UV. Fig.39 The display device 700 in the embodiment includes: a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. The lead wiring portion 711 includes a wiring 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit portion 704 includes a transistor 752.

[0632] For example, the transistor 150 described in Embodiment 7 can be used as the transistor 750. The transistor 151 described in Embodiment 8 can be used as the transistor 752.

[0633] The transistor used in this embodiment includes a highly purified oxide semiconductor film in which the formation of oxygen vacancies is suppressed. The transistor can have a low off-state current (off-state current). Therefore, an electrical signal such as an image signal can be maintained for a long time, and a long write interval can be set in the on state. Therefore, the frequency of the refresh operation can be reduced, and power consumption can be suppressed.

[0634] In addition, the transistor used in this embodiment can have a relatively high field effect mobility and thus can operate at high speed. For example, in a liquid crystal display device including a transistor capable of high-speed operation, a switching transistor in a pixel portion and a driving transistor in a driving circuit portion can be formed on one substrate. That is, there is no need to use an additional semiconductor device formed using a silicon wafer or the like as a driving circuit; therefore, the number of components of the semiconductor device can be reduced. In addition, a transistor capable of high-speed operation can also be used in the pixel portion, thereby providing a high-quality image.

[0635] The capacitor 160 described in Embodiment 6 can be used as the capacitor 790. Since the capacitor 790 transmits light, a large capacitor 790 (large area) can be formed in a pixel included in the pixel portion 702. Therefore, the display device can have a large capacitance and a high aperture ratio.

[0636] exist Fig.39 In the embodiment, insulating films 764, 766 and 768 are provided over the transistor 750.

[0637] The insulating films 764, 766, and 768 can be formed using materials and methods similar to those of the insulating films 114, 116, and 118 described in Embodiment 7, respectively. A planarization film can be provided over the insulating film 768. The planarization film can be formed using materials and methods similar to those of the insulating film 119 described in Embodiment 8.

[0638] The wiring 710 is formed in the same process as a conductive film as the source electrode and the drain electrode of the transistors 750 and 752. As the wiring 710, a conductive film formed in a different process from the source electrode and the drain electrode of the transistors 750 and 752, for example, a conductive film formed in the same process as a conductive film as a gate electrode can be used. In the case of forming the wiring 710 using a material containing copper, signal delay or the like due to wiring resistance is reduced, which enables display on a large screen.

[0639] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. Note that the connection electrode 760 is formed in the same process as the conductive film as the source electrode and the drain electrode of the transistors 750 and 752. The connection electrode 760 is electrically connected to a terminal included in the FPC 716 through the anisotropic conductive film 780.

[0640] For example, a glass substrate can be used as the first substrate 701 and the second substrate 705. The first substrate 701 and the second substrate 705 can be formed using a material similar to that of the substrate 102 described in Embodiment 7.

[0641] On the second substrate 705 side, a light-blocking film 738 as a black matrix, a color film 736 as a color filter, and an insulating film 734 in contact with the light-blocking film 738 and the color film 736 are provided.

[0642] A structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selective etching of an insulating film and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Alternatively, a spherical spacer may be used as the structure 778.

[0643] One embodiment of the present invention is not limited to the structure described in this embodiment in which the structure 778 is provided on the first substrate 701 side. For example, the structure 778 may be provided on the second substrate 705 side, or the structure 778 may be provided to both the first substrate 701 and the second substrate 705.

[0644] The display device 700 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the side of the second substrate 705 facing the first substrate 701, and serves as a counter electrode. The display device 700 can display an image in such a manner that light transmission or non-transmission is controlled by the alignment state in the liquid crystal layer 776 that changes according to the voltage applied between the conductive film 772 and the conductive film 774.

[0645] The conductive film 772 is connected to a conductive film that serves as a source electrode or a drain electrode of the transistor 750. The conductive film 772 is formed over the insulating film 768 and serves as a pixel electrode, that is, one electrode of the display element. The display device 700 is a transmissive color liquid crystal display device in which a backlight or a sidelight is provided on the first substrate 701 side to perform display through the liquid crystal element 775 and the color film 736.

[0646] The oxide semiconductor film 782 is provided under the conductive film 772 with the insulating film 768 therebetween, and the oxide semiconductor film 782 serves as the other electrode of the capacitor 790 .

[0647] A conductive film that transmits visible light or a conductive film that reflects visible light can be used as each of the conductive films 772 and 774. For example, for the conductive film that transmits visible light, a material containing an element selected from indium (In), zinc (Zn), and tin (Sn) can be used. The conductive film 772 and the conductive film 774 can be formed using a material similar to that of the conductive film 120 described in Embodiment 6. The oxide semiconductor film 782 can be formed using a material similar to that of the second oxide semiconductor film 111 described in Embodiment 6.

[0648] For example, Fig.38 and Fig.39 The display device 700 may be (but not limited to): a transmissive color liquid crystal display device, in which a conductive film that transmits visible light is used as the conductive film 772; a reflective color liquid crystal display device, in which a conductive film that reflects visible light is used as the conductive film 772; or a transflective color liquid crystal display device, in which a reflective film and a transmissive film are used in combination.

[0649] Although Fig.39 Although not shown in the figure, an optical component (optical substrate) or the like, such as a polarizing component, a delay component, or an anti-reflection component, may be appropriately provided. For example, circular polarization may be obtained by using a polarizing substrate and a delay substrate.

[0650] exist Fig.39 In the method adopted in the embodiment, an image is displayed in such a manner that the alignment state of the liquid crystal layer 776 is changed by a voltage applied between the conductive film 772 and the conductive film 774 to control light transmission or opacity; however, the following method can also be adopted: an image is displayed in such a manner that the alignment state in the liquid crystal layer 776 is changed by a horizontal electric field (substantially parallel to the electric field of the first substrate 701) generated between the conductive film 772 and the oxide semiconductor film 782 to control light transmission or opacity (see Fig.41 In the latter method, although the alignment state in the liquid crystal layer can be simply changed by the conductive film 772 and the oxide semiconductor film 782, alignment disorder in the liquid crystal layer 776 can be suppressed by providing a potential to the conductive film 774 provided on the second substrate 705 side.

[0651] Here, we will refer to Figure 1 , Fig.41 and Fig.42 The above-mentioned horizontal electric field and the alignment disorder in the liquid crystal layer are described.

[0652] For example, in Example 1 Figure 1 In the electrode layout in, the electric field from the conductive film 21a to the oxide semiconductor film 19b may cause the alignment disorder in the liquid crystal layer 776, and Fig.42 In the electrode layout of the second substrate 705, the electric field from the conductive film 21c to the oxide semiconductor film 19c may cause alignment disorder. However, by providing a potential to the conductive film 774 provided on the second substrate 705 side, the extension of the electric field from the conductive film 21a or the conductive film 21c can be suppressed; therefore, the light leakage caused by the alignment disorder in the liquid crystal layer 776 is reduced, which leads to an improvement in the display quality of the display device. Note that Fig.42 The oxide semiconductor film 19c and the conductive film 29b in the transistor are used as a pixel electrode and a common electrode, respectively. In addition, the conductive film 13b is used as a scanning line, and a channel region is formed in the oxide semiconductor film 19d.

[0653] exist Fig.41 In the embodiment, the conductive film 772 is formed over the oxide semiconductor film 782, and the insulating film 768 is located therebetween. Fig.41 The conductive film 772 and the oxide semiconductor film 782 are respectively used as an example of a common electrode and a pixel electrode, but the oxide semiconductor film 782 and the conductive film 772 may be respectively used as a common electrode and a pixel electrode (see Fig.40 ).

[0654] <Outer protective film>

[0655] like Fig.43 As shown, a protection film 717 may be formed on the outer surface of the display device 700. For example, preferably, the protection film 717 is deposited by an atomic layer deposition method (hereinafter referred to as an ALD method).

[0656] The ALD method enables extremely uniform deposition of films on the deposition surface. By the ALD method, for example, the following can be deposited as protective films: aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, zinc oxide, indium oxide, tin oxide, indium tin oxide (ITO), tantalum oxide, silicon oxide, manganese oxide, nickel oxide, erbium oxide, cobalt oxide, tellurium oxide, barium titanate, titanium nitride, tantalum nitride, aluminum nitride, tungsten nitride, cobalt nitride, manganese nitride, or hafnium nitride. In addition, the protective film is not limited to an insulating film, and a conductive film can also be deposited. For example, ruthenium, platinum, nickel, cobalt, manganese, or copper can be deposited.

[0657] In addition, preferably, a portion for electrical connection, such as the FPC terminal portion 708, is masked so that the protective film 717 is not deposited on the portion. For masking, an organic film, an inorganic film, a metal, or the like can be used. For example, an oxide insulating film containing silicon oxide, silicon oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like, a nitride insulating film containing silicon nitride, aluminum nitride, or the like, or an organic material such as a photoresist, a polyimide resin, an acrylic resin, a polyimide amide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin can be used. A mask formed using a film containing any of these materials can be removed after the protective film is deposited.

[0658] Alternatively, a metal mask may be used to mask the area on which the protective film is deposited by the ALD method. The metal mask may be formed using a metal element selected from iron, chromium, nickel, cobalt, tungsten, molybdenum, aluminum, copper, tantalum, and titanium, an alloy containing the aforementioned metal element as a component thereof, an alloy containing a combination of the aforementioned metal elements, and the like. The metal mask may be positioned close to or in contact with the display panel.

[0659] The film formed by the ALD method can be extremely uniform and dense. When the protective film 717 is formed on the side surface portion of the display panel by the ALD method, the entry of external components such as moisture can be suppressed. As a result, the change of transistor characteristics can be suppressed, and the peripheral circuit can be stably operated. In addition, the frame size can be reduced, the pixel area can be expanded, and the resolution of the display device can be increased.

[0660] For the liquid crystal used for the liquid crystal layer 776, the description of the liquid crystal used for the liquid crystal element 51 in Embodiment 1 can be referred to.

[0661] In addition, any of the driving methods described in Embodiments 6 to 13 can be used as a driving method of a display device including a liquid crystal element.

[0662] The structure described in this embodiment can be appropriately combined with any structure described in other embodiments.

[0663] (Example 12)

[0664] <Top-gate transistor>

[0665] In this embodiment, other structural examples of a display device that can be used as the transmissive display device described in the above embodiment will be described.

[0666] Fig.44A A schematic top view of a display device 300 is shown. Fig.44B Shown along Fig.44A Schematic cross-sectional views taken along A1-A2, A3-A4 and A5-A6 in FIG. Note that for clarity, Fig.44A Some components are not shown.

[0667] The display device 300 includes a display portion 302 , a signal line driver circuit 303 , a scan line driver circuit 304 , and an external connection terminal 305 over the top surface of a substrate 301 .

[0668] The display portion 302 includes a liquid crystal element 314. In the liquid crystal element 314, the alignment of liquid crystal is controlled by an electric field generated in a direction parallel to a substrate surface.

[0669] The display device 300 includes: an insulating layer 332, an insulating layer 334, an insulating layer 338, an insulating layer 341, an insulating layer 342, a transistor 311, a transistor 312, a liquid crystal element 314, an electrode 343, an electrode 352, an electrode 360, a liquid crystal 353, a color filter 327, a light blocking layer 328, and the like.

[0670] The pixel includes at least one switching transistor 312 and a storage capacitor formed by an electrode 343 and an electrode 360. The electrode 343 is electrically connected to one of a source electrode and a drain electrode of the transistor 312.

[0671] An electrode 352 is provided on the color filter 327 .

[0672] A light-transmitting conductive material or a reflective conductive material may be used for the electrode 343 .

[0673] The color filter 327 is arranged to overlap the electrode 343, the electrode 352 and the electrode 360. The light blocking layer 328 is arranged to cover the side surface of the color filter 327. Fig.44B The color filter 327 is disposed on the substrate 321, but the color filter 327 is not necessarily located at this position.

[0674] Liquid crystal 353 is provided between substrate 301 and substrate 321. An image can be displayed in the following manner: a voltage is applied between electrode 343 and electrode 360 ​​to generate an electric field, the alignment of liquid crystal 353 is controlled by the electric field, and polarization of light is controlled in each pixel. In the case where electrode 343 is a reflective electrode, an image can be displayed while controlling the amount of incident light to be reflected.

[0675] An alignment film for controlling the alignment of the liquid crystal 353 is preferably provided on the surface in contact with the liquid crystal 353. A light-transmitting material is used as the alignment film. Although not shown here, a polarizing plate is provided on the surface of the substrate 321 and the substrate 301 that does not face the liquid crystal element 314.

[0676] As the liquid crystal 353, thermotropic liquid crystal, low molecular liquid crystal, high molecular liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. In addition, liquid crystal exhibiting a blue phase is preferably used because an alignment film is not required and a wide viewing angle can be obtained.

[0677] In the case of displaying an image using the liquid crystal element 314, the electrode 352 (which may be provided as required) improves the alignment of the liquid crystal in some cases. Fig.44B The case where the electrode 352 is provided is shown. In this case, it is preferable to use a light-transmitting conductive material as the electrode 352 because the aperture ratio of the pixel can be increased.

[0678] Preferably, a material with low viscosity and high fluidity is used for the liquid crystal 353 .

[0679] Note that the liquid crystal element in this structural example can operate in the following modes: twisted nematic (TN) mode, in-plane switching (IPS) mode, scattered field switching (FFS) mode, axially symmetric alignment microcell (ASM) mode, optically compensated birefringence (OCB) mode, ferroelectric liquid crystal (FLC) mode, antiferroelectric liquid crystal (AFLC) mode, and the like.

[0680] The transistors (e.g., transistor 311 and transistor 312) provided in the display device 300 are top-gate transistors. Each transistor includes: a semiconductor layer 335, an insulating layer 334 as a gate insulating layer, and a gate electrode 333. In addition, an insulating layer 338 is provided to cover the gate electrode 333. A pair of electrodes 336 are provided to contact the semiconductor layer 335 through openings in the insulating layer 334 and the insulating layer 338.

[0681] Here, an oxide semiconductor is preferably used as the semiconductor layer 335. As the oxide semiconductor, for example, the oxide semiconductor described in the above embodiment can be used.

[0682] The semiconductor layer 335 may include a region as a source region or a drain region having a lower resistance than a region as a channel. For example, the source region and the drain region may be arranged so that they contact the pair of electrodes 336, or the region as a channel may be positioned between the source region and the drain region. For example, the source region and the drain region may be regions whose resistivity is controlled by the method described in the above embodiment.

[0683] By using an oxide semiconductor as the semiconductor layer 335 , for example, compared with the case of using polycrystalline silicon, a transistor with little variation can be formed in a large area at a low temperature.

[0684] An oxide semiconductor can also be used for the electrode 360 ​​.

[0685] In one embodiment of the present invention, an active matrix display device in which pixels include active elements, or a passive matrix display device in which pixels do not include active elements may be used.

[0686] As active elements (non-linear elements) in active matrix display devices, not only transistors but also various active elements (non-linear elements) can be used. For example, metal insulator metal (MIM) or thin film diode (TFD) can also be used. Since such elements can be manufactured with a small number of steps, the manufacturing cost can be reduced or the yield can be improved. Since the size of the element is small, the aperture ratio can be improved, thereby reducing power consumption or achieving higher brightness.

[0687] In addition to active matrix display devices, passive matrix display devices that do not use active elements (non-linear elements) can be used. Since no active elements (non-linear elements) are used, the number of manufacturing steps is small, so that the manufacturing cost can be reduced, or the yield can be improved. Since no active elements (non-linear elements) are used, the aperture ratio can be improved, so that power consumption can be reduced, or, for example, higher brightness can be achieved.

[0688] Note that this embodiment can be combined with any other embodiments in this specification as appropriate.

[0689] (Example 13)

[0690] In this embodiment, refer to Fig.45A and 45B , Fig.46A and 46B , Figures 47A-47E , Figures 48A-48E , describing a display device and a method for driving the display device according to an embodiment of the present invention.

[0691] Note that a display device according to an embodiment of the present invention may include: an information processing section, a computing section, a storage section, a display section, an input section, and the like.

[0692] By reducing the number of times a signal is written (also referred to as a refresh operation) for the same image (still image) to be displayed continuously, the power consumption of a display device of one embodiment of the present invention can be reduced. Note that the frequency of the refresh operation is referred to as a refresh rate (or a scanning frequency, or a vertical synchronization frequency). A display device whose refresh rate is reduced to cause little eye fatigue is described below.

[0693] Eye fatigue is divided into two categories: neural fatigue and muscle fatigue. Neural fatigue is caused by looking at the light emitted by the display device or flashing images for a long time, the brightness of which stimulates the retina and the nerves of the eyes and brain and fatigues them. Muscle fatigue is caused by overuse of the ciliary muscles used to adjust focus.

[0694] Fig.45A The display method of a conventional display device is schematically described. Fig.45A As shown, in conventional display devices, image rewriting is performed 60 times per second. Watching such a screen for a long time can stimulate the user's retina, optic nerve and brain, thus causing eye fatigue.

[0695] In one embodiment of the display device of the present invention, a transistor including an oxide semiconductor (for example, a transistor including CAAC-OS) is used as a pixel portion. The off-current of the transistor is extremely low. Thus, the brightness of the display device can be maintained even when the refresh rate is reduced.

[0696] In this way, Fig.45B As shown, the number of times the image is rewritten can be reduced to once every 5 seconds. This allows the user to look at the same image for as long as possible, thereby reducing the flicker on the screen that the user perceives. As a result, the stimulation to the user's retina, optic nerve, and brain can be reduced, resulting in less neural fatigue.

[0697] In the case where the size of each pixel is large (for example, the resolution is less than 150ppi), Fig.46A Blurred characters are displayed on the display device shown. When a user looks at the blurred characters displayed on the display device for a long time, the ciliary muscles keep working and it is difficult to adjust the focus, which may cause eye strain.

[0698] On the contrary, Fig.46B As shown, the display device of one embodiment of the present invention is capable of high-definition display, because the size of each pixel is small; thus, accurate and smooth display can be obtained. In this case, the ciliary muscle can easily adjust the focus, thereby reducing the muscle fatigue of the user. When the resolution of the display device is 150ppi or higher (preferably 200ppi or higher, more preferably 300ppi or higher), the muscle fatigue of the user can be effectively reduced.

[0699] Methods for quantifying eye fatigue have been studied. For example, the critical flicker (fusion) frequency (CFF) is known as an indicator for evaluating nerve fatigue. In addition, the adaptation time, the near point distance, etc. are known as indicators for evaluating muscle fatigue.

[0700] Other methods used to evaluate eyestrain include electroencephalography, thermography, counting blinks, measuring tear volume, measuring the speed of pupil constriction response, and asking about symptoms.

[0701] For example, the method for driving a display device according to one embodiment of the present invention may be checked by means of any of the methods described above.

[0702] <Method for driving display device>

[0703] Refer to the following Fig.47A -E describes a method for driving a display device according to an embodiment of the present invention.

[0704] [Display example of image information]

[0705] An example in which two images including different image information are displayed while they are moving is described below.

[0706] exist Fig.47A In the illustrated example, a window 451 and a first image 452 a which is a still image displayed in the window 451 are displayed on the display portion 450 .

[0707] At this time, the display is preferably performed at the first refresh rate. Note that the first refresh rate may be greater than or equal to 1.16×10 -15 Hz (approximately once a day) and less than or equal to 1 Hz, greater than or equal to 2.78×10 -4 Hz (approximately once per hour) and less than or equal to 0.5 Hz, or greater than or equal to 1.67 Hz × 10 -2 Hz (approximately once per minute) and less than or equal to 0.1 Hz.

[0708] When the frequency of rewriting the screen is reduced by setting the first refresh rate to an extremely small value, a substantially flicker-free display can be obtained and the user's eye fatigue can be reduced more effectively.

[0709] Window 451 is displayed, for example, by executing application software for image display, and includes a display area in which an image is displayed.

[0710] Furthermore, a button 453 for switching the displayed image information from one to another is provided in the lower portion of the window 451. When the user selects the button 453, an instruction for moving the image is given to the information processing section of the display device.

[0711] Note that the method by which the user operates the display device may be determined according to the input unit. For example, when a touch panel overlapped with the display portion 450 is used as the input unit, a touch operation of the button 453 can be performed with a finger, a stylus, etc., or an input operation can be performed by a gesture for sliding an image. In the case of performing an input operation by gesture or voice, it is not necessarily necessary to display the button 453.

[0712] When the information processing section of the display device receives the instruction to move the image, the image displayed in the window 451 starts to move ( Fig.47B ).

[0713] When Fig.47A In the case of displaying at the first refresh rate in the state shown, the refresh rate is preferably changed to the second refresh rate before the image moves. The second refresh rate is a value required for displaying moving images. For example, the second refresh rate may be greater than or equal to 30 Hz and less than or equal to 960 Hz, preferably greater than or equal to 60 Hz and less than or equal to 960 Hz, more preferably greater than or equal to 75 Hz and less than or equal to 960 Hz, more preferably greater than or equal to 120 Hz and less than or equal to 960 Hz, and more preferably greater than or equal to 240 Hz and less than or equal to 960 Hz.

[0714] When the second refresh rate is set to a value higher than the first refresh rate, a moving image can be displayed more smoothly and naturally. In addition, the flickering that occurs with rewriting is less recognized by the user, thereby reducing the user's eye fatigue.

[0715] At this time, an image combining the second image 452b to be displayed next and the first image 452a is displayed in the window 451. A part of the combined image is displayed in the window 451 while moving in one direction (leftward in this case).

[0716] As the combined image moves, the brightness of the image displayed in the window 451 changes from the initial brightness ( Fig.47A The brightness in the state) gradually decreases.

[0717] Fig.47C The state in which the image displayed in the window 451 reaches the predetermined coordinates is shown. Thus, the brightness of the image displayed in the window 451 is minimum at this time.

[0718] Fig.47C The predetermined coordinates in are set to (but not limited to) coordinates at which half of the first image 452a and half of the second image 452b are displayed; preferably, the user can arbitrarily set the predetermined coordinates.

[0719] For example, the predetermined coordinates may be set such that a ratio of a distance from the initial coordinates of the image to a distance between the initial coordinates and the final coordinates is greater than 0 and less than 1.

[0720] Preferably, the user can arbitrarily set the brightness of the image when it reaches the predetermined coordinates. For example, the ratio of the brightness when the image reaches the predetermined coordinates to the initial brightness can be greater than or equal to 0 and less than 1, preferably greater than or equal to 0 and less than or equal to 0.8, and more preferably greater than or equal to 0 and less than or equal to 0.5.

[0721] Next, the combined image displayed in window 451 is moved while gradually increasing in brightness ( Fig.47D ).

[0722] Fig.47E The state in which the combined image reaches the final coordinates is shown. In the window 451, only the second image 452b is displayed with a brightness equal to the initial brightness.

[0723] After the movement of the image is completed, the refresh rate is preferably changed from the second refresh rate to the first refresh rate.

[0724] In this display mode, since the image brightness is reduced, the user's eyes suffer less fatigue even when following the movement of the image. Thus, this driving method can achieve eye-friendly display.

[0725] [Example of displaying document information]

[0726] An example of displaying document information while the document information is being scrolled is described below, in which the size of the document is larger than the size of the display window.

[0727] exist Fig.48A In the illustrated example, a window 455 and a portion of document information 456 which is a still image displayed in the window 455 are displayed on the display portion 450 .

[0728] At this time, the display is preferably performed at the first refresh rate.

[0729] Window 455 is displayed, for example, by executing application software for document display, application software for document generation, or the like, and includes a display area that displays document information.

[0730] In the vertical direction, the size of the image of the document information 456 is larger than the size of the display area of ​​the window 455. Therefore, only a portion of the document information 456 is displayed in the window 455. Fig.48A As shown, window 455 may also have a scroll bar 457 for indicating which portion of document information 456 is displayed.

[0731] When an instruction for moving an image (also referred to herein as a scroll instruction) is input from the input section to the display device, movement of the document 456 starts ( Fig.48B ). In addition, the brightness of the displayed image is gradually reduced.

[0732] exist Fig.48A In the illustrated state, when displaying at the first refresh rate, it is preferable to change the refresh rate to the second refresh rate before the document information 456 is moved.

[0733] In this case, not only the brightness of the image displayed in the window 455 but also the brightness of the entire image displayed in the display portion 450 is lowered.

[0734] Fig.48C The state when the document information 456 reaches the predetermined coordinates is shown. At this time, the brightness of the entire image displayed on the display section 450 is the lowest.

[0735] Next, the document information 456 is displayed in the window 455 while being moved ( Fig.48D ). In this case, the brightness of the entire image displayed on the display portion 450 is gradually increased.

[0736] Fig.48E The state in which the document information 456 reaches the final coordinates is shown. In the window 455, a region of the document information 456 different from the region displayed in the initial state is displayed with a brightness equal to the initial brightness.

[0737] After the movement of the document information 456 is completed, the refresh rate is preferably changed to the first refresh rate.

[0738] Since the brightness of the image is reduced in this display mode, the user's eyes suffer less fatigue even when following the movement of the image. Thus, this driving method can achieve eye-friendly display.

[0739] In particular, the display of high-contrast document information or the like can cause severe fatigue to the user's eyes; therefore, for the display of document information, this driving method is preferably applied.

[0740] This embodiment may be implemented in combination with any other embodiment described in this specification as appropriate.

[0741] (Example 14)

[0742] In this embodiment, reference will be made to Fig.49 and Figures 50A-50G A display module and an electronic device including a semiconductor device according to an embodiment of the present invention are described.

[0743] exist Fig.49 In the display module 8000 shown, provided between an upper cover 8001 and a lower cover 8002 are: a touch panel 8004 connected to an FPC 8003 , a display panel 8006 connected to an FPC 8005 , a backlight 8007 , a frame 8009 , a printed board 8010 , and a battery 8011 .

[0744] The display device in one embodiment of the present invention can be used for the display panel 8006, for example.

[0745] The shapes and sizes of the upper cover 8001 and the lower cover 8002 can be appropriately changed according to the sizes of the touch panel 8004 and the display panel 8006 .

[0746] The touch panel 8004 may be a resistive touch panel or a capacitive touch panel and overlap the display panel 8006. Alternatively, a counter substrate (sealing substrate) of the display panel 8006 may have a touch panel function. Alternatively, a light sensor may be provided in each pixel of the display panel 8006 to form a light touch panel.

[0747] Backlight 8007 includes light source 8008. One embodiment of the present invention is not limited to Fig.49 A structure in which the light source 8008 is provided above the backlight 8007. For example, a structure in which the light source 8008 is provided at the end of the backlight 8007 and a light diffusion plate is provided may be used. Note that in the case of using a self-luminous light-emitting element such as an organic EL element or in the case of using a reflective panel or the like, the backlight 8007 does not need to be provided.

[0748] The frame 8009 protects the display panel 8006 and serves as an electromagnetic shield to block electromagnetic waves generated by the operation of the printed board 8010. The frame 8009 may also serve as a heat sink.

[0749] The printed board 8010 includes a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. An external commercial power supply or a separate battery 8011 can be used as a power supply for supplying power to the power supply circuit. In the case of using a commercial power supply, the battery 8011 can be omitted.

[0750] The display module 8000 may be additionally provided with, for example, a polarizing plate, a retardation plate, or a prism sheet.

[0751] Figures 50A-50G A variety of electronic devices are shown. These electronic devices may include: a housing 5000, a display portion 5001, a speaker 5003, an LED lamp 5004, an operation key 5005 (including a power switch or an operation switch), a connection terminal 5006, a sensor 5007 (having the function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation frequency, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow, humidity, gradient, oscillation, smell or infrared), a microphone 5008, etc.

[0752] Fig.50A A mobile computer is shown, which, in addition to the above, may also include: a switch 5009, an infrared port 5010, etc. Fig.50B A portable image reproducing device is shown, which is provided with a recording medium (eg, a DVD reproducing device), and may include, in addition to the above-mentioned components: a second display portion 5002, a recording medium reading portion 5011, and the like. Fig.50C A goggle-type display device is shown, which may include, in addition to the above components: a second display portion 5002, supporting legs 5012, headphones 5013, etc. Fig.50D A portable game console is shown, which may include a recording medium reading portion 5011 and the like in addition to the above-mentioned components. Fig.50E A digital camera is shown which has a television reception function and which may include, in addition to the above components, an antenna 5014, a shutter button 5015, an image receiving portion 5016, and the like. Fig.50F A portable game console is shown, which, in addition to the above components, may also include: a second display portion 5002, a recording medium reading portion 5011, etc. Figure 50G A portable television receiver is shown, which, in addition to the above components, may also include a charging stand 5017 capable of sending and receiving signals, etc.

[0753] Figures 50A-50G The electronic device in may have a variety of functions, such as: a function of displaying various information (e.g., still images, moving images, and text images) on a display portion, a touch panel function, a function of displaying a calendar, time, and date, etc., a function of controlling processing with various software (programs), a wireless communication function, a function of connecting to various computer networks through a wireless communication function, a function of sending and receiving various data through a wireless communication function, and a function of reading out programs or data stored in a recording medium and displaying them on a display portion. In addition, an electronic device including a plurality of display portions may have the following functions: mainly displaying image information in one display portion and mainly displaying text information in another display portion, displaying a three-dimensional image by displaying images in a plurality of display portions in consideration of parallax, and the like. In addition, an electronic device including an image receiving portion may have the following functions: shooting still images; shooting moving images; automatically or manually correcting the shot images; storing the shot images in a recording medium (an external recording medium or a recording medium included in a camera); displaying the shot images on a display portion; and the like. Note that, Figures 50A-50G The functions of the electronic devices in are not limited thereto, and these electronic devices may have various functions.

[0754] The electronic devices described in this embodiment each feature a display portion for displaying a certain type of information. The display device described in any other embodiment can be used as the display portion.

[0755] [Example 1]

[0756] In this example, the alignment state of liquid crystal in a liquid crystal element included in a pixel of one embodiment of the present invention is calculated. Figures 51A-51D and Figures 52A-52B The calculation results are shown.

[0757] Figures 51A-51D Shows that there is Figure 1 Calculation results for a pixel with the electrode structure shown schematically and a pixel with a comparative electrode structure. For this calculation, a liquid crystal alignment simulator, LCDMaster, manufactured by SHINTECH was used. The calculation conditions in this example are as follows: the pixel area is 174 μm × 55.5 μm, the thickness of the liquid crystal layer is 3.2 μm, and the optical anisotropy of the liquid crystal is Δ n is 0.0998, the dielectric anisotropy Δ ε is -3.0, the common electrode width and the pixel electrode width are both 3.0 μm, the liquid crystal in the initial state is aligned in a direction parallel to the scanning line, and the substrates above and below the liquid crystal layer are subjected to alignment treatment for anti-parallel alignment. Table 1 shows the potentials applied to the electrodes:

[0758] [Table 1]

[0759]

[0760] Figures 51A-51D A schematic top view of a calculated pixel is shown, along with the calculated two-dimensional distribution of light transmitted through the liquid crystal over the pixel electrode. Fig.51A is a schematic top view of a pixel in which the electrode has no curved portion, Fig.51B Shown in Fig.51A Two-dimensional distribution of light transmitted through liquid crystal in an electrode structure. Fig.51C shows a schematic top view of a pixel in which the electrode has a curved portion 1001, and Fig.51D Shown in Fig.51C The two-dimensional distribution of light transmitted through the liquid crystal in the electrode structure of FIG. In the two-dimensional distribution of light transmitted through the liquid crystal, the brightness is represented by gray levels from white to black; therefore, the darker the white, the stronger the brightness, that is, the higher the transmittance.

[0761] exist Fig.51B The alignment defect portion 1003 is observed in the electrode, while the electrode having the bent portion 1001 Fig.51D The alignment defects in the liquid crystal were reduced or disappeared. This result confirmed that the curved portion of the electrode can reduce the alignment defects of the liquid crystal, thereby improving the distribution of the transmitted light.

[0762] When the signal line potential affects the pixel, the liquid crystal alignment becomes disordered and the transmittance changes. In order to examine this change, calculations were performed in two cases where the distance between the signal line and the common electrode was different. Fig.52A and 52B The calculation results are shown.

[0763] Fig.52A FIG. 2 shows the two-dimensional distribution of light transmitted through the liquid crystal when the distance between the signal line and the common electrode is 6 μm. Fig.52A In FIG. 1 , area (a) shows calculation results for pixels provided with an electrode potential for black display, and area (b) shows calculation results for pixels provided with an electrode potential for white display. Fig.52B FIG. 2 shows the two-dimensional distribution of light transmitted through the liquid crystal when the distance between the signal line and the common electrode is 1 μm. Fig.52B , area (c) shows the calculation results of the pixels provided with the electrode potential for black display, and area (d) shows the calculation results of the pixels provided with the electrode potential for white display.

[0764] like Fig.52A The area (a) and Fig.52B As shown in the area (c) in FIG. 1 , in the structure where the distance between the signal line and the common electrode is small, the light leakage portion is small.

[0765] The results confirm that the reduction in the distance between the signal line and the common electrode can suppress light leakage caused by the disordered alignment of the liquid crystal. This is because the electric field of the common electrode blocks the electric field of the signal line, thereby reducing the influence of the electric field of the signal line on the pixel.

[0766] [Example 2]

[0767] In this example, the alignment state of liquid crystal in a liquid crystal element included in a pixel of one embodiment of the present invention is calculated. Figures 52A-53D The calculation results are shown.

[0768] The calculation is for Fig.42 The pixel electrode is schematically shown. For this calculation, a liquid crystal alignment simulator, LCD Master, manufactured by SHINTECH was used. The calculation conditions in this example are as follows: the pixel area is 174 μm × 58 μm, the thickness of the liquid crystal layer is 4.0 μm, and the optical anisotropy of the liquid crystal is Δ n is 0.0998, the dielectric anisotropy Δ ε is -3.0, the common electrode width and the pixel electrode width are both 3.0 μm, the distance between two adjacent comb-shaped parts of the pixel electrode and the distance between two adjacent comb-shaped parts of the common electrode are both 5.0 μm, the liquid crystal in the initial state is aligned at an inclination angle of 5° relative to the scanning line, and the substrates above and below the liquid crystal layer are subjected to alignment treatment for anti-parallel alignment. Table 2 shows the potentials applied to the electrodes:

[0769] [Table 2]

[0770]

[0771] The relationship between the transmittance of a pixel and the voltage applied between the pixel electrode and the common electrode (hereinafter referred to as VT characteristics) was calculated. In this example, the transmittance as a function of the signal line potential was also examined. The results are shown in Fig.53A and 53B The following explains Fig.53A and 53B The normalized intensity of the transmitted light represented by the vertical axis. The normalized intensity of the transmitted light is the value obtained by formula (2) under the following conditions. In this formula, X represents the amount of light transmitted through a structure in which a liquid crystal element is arranged between a pair of polarizing plates, and the polarizing plates are arranged so that their polarization directions are perpendicular to each other as in an actual display device; Y represents the amount of light transmitted through a structure in which a pair of polarizing plates are arranged so that their light transmission axes or light absorption axes are parallel to each other (parallel Nicols), and wherein the liquid crystal element is not located between the pair of polarizing plates.

[0772] [Formula 2]

[0773] Normalized intensity of transmitted light [%] = X / Y × 100 (2)

[0774] The pixel potential represented by the horizontal axis refers to the difference between the potential applied to the pixel electrode and the potential applied to the common electrode. The unit of the difference between the potential applied to the pixel electrode and the potential applied to the common electrode is V (volt).

[0775] For comparison, no potential was applied to the counter electrode ( Fig.53A ) and applying a potential to the counter electrode ( Fig.53B ) was evaluated under the conditions of .

[0776] The case where no potential is applied to the counter electrode is compared with the case where a potential is applied to the counter electrode. In the latter case, the VT characteristic ( Fig.53B The dotted line 1012 in the figure shows the VT characteristic when the signal line potential is 6V ( Fig.53B There is no deviation between the solid line 1013 in Fig.53B In FIG. 1 , the dotted line 1012 and the solid line 1013 overlap each other). Fig.53A Conversely, when no potential is applied to the counter electrode, a deviation occurs between the VT characteristics when the signal line potential is 0 V (dashed line 1010 in the figure) and the VT characteristics when the signal line potential is 6 V (solid line 1011 in the figure).

[0777] exist Fig.53C and Fig.53D , as the deviation of gray levels, the vertical axis represents the deviation between the intensity of transmitted light when the signal line potential is 0 V and the intensity of transmitted light when the signal line potential is 6 V. The pixel potential represented by the horizontal axis refers to the difference between the potential applied to the pixel electrode and the potential applied to the common electrode. When the potential is applied to the counter electrode, the deviation of the gray level shown by line 1008 is within 2 gray levels; when the potential is not applied to the counter electrode, the deviation of the gray level shown by line 1009 covers 5 gray levels.

[0778] Generally speaking, the minimum amount of gray level deviation that can be perceived by a user is about 2 gray levels; therefore, as long as the deviation amount is within 2 gray levels, the user will not perceive the gray level deviation. If the gray level deviation in the display device is repeated at regular time intervals, the user will perceive it as flicker; therefore, the gray level deviation needs to be reduced to a level that is not perceived by the user.

[0779] This example shows that Fig.42 The layout of pixel electrodes shown reduces display flicker.

[0780] [Example 3]

[0781] In this example, in order to support the calculation results of the liquid crystal alignment in Example 2, a display device in which a counter electrode was provided and a transistor including an oxide semiconductor was applied was manufactured, and it was examined whether grayscale deviation was suppressed. Table 3 shows the specifications of the manufactured display device.

[0782] [Table 3]

[0783]

[0784]

[0785] use Fig.42 Regarding the layout of the counter electrode in the display device, for example, reference can be made to Example 11. Fig.39 , Fig.40 and Fig.41 Description of the layout of the conductive film.

[0786] Fig.54A and 54B The results are shown. Fig.54A The characteristic of the time change of the gray level of the display device manufactured in this example is shown. Fig.54A , the deviation of the grayscale level of the display device with the counter electrode (indicated by characteristic curve 1020) is at most 2 grayscale levels, while the maximum deviation of the grayscale level of the display device without the counter electrode (indicated by characteristic curve 1016) is close to 10 grayscale levels.

[0787] Fig.54A The results show that the counter electrode suppresses grayscale deviation. In addition, in a display device made using a material having negative dielectric constant anisotropy, flicker due to the flexoelectric effect attributed to polarization of liquid crystal molecules can be reduced.

[0788] Fig.54B A photograph showing a display device displaying an image is shown. By using one embodiment of the present invention, a good display can be performed.

[0789] Furthermore, it was examined whether a reduction in the frame frequency of the display device described in this example results in a change in the grayscale level in one frame. Fig.55 The initial characteristics are shown. Fig.55 All lines 1028 in FIG. 1 (which show the change over time at 256 gray levels) are almost constantly flat, regardless of the time that has passed. These results confirm that no significant change over time is seen at any gray level.

[0790] Another result of the examination is given below. In the structure of the insulating film having different thicknesses for insulating the conductive film 21c as the signal line from the oxide semiconductor film 19c as the pixel electrode, the variation in the deviation amount of the amount of transmitted light at each grayscale level was examined. For the above-mentioned insulating film, for example, see Figure 2 In the description of the insulating films 23 and 25, Figure 2 is a schematic cross-sectional view of a display portion 71 of a display device 80 in Embodiment 1.

[0791] Fig.56A Corresponds to Figure 2 1 is a schematic cross-sectional view of the display portion 71 of the display device 80 in FIG. That is, a schematic cross-sectional view taken along the dashed line S1-T1. The thickness 1030 refers to the thickness of the above-mentioned insulating film.

[0792] Fig.56B The amount of deviation in the intensity of the transmitted light as a function of the gray level is shown using the thickness 1030 as a parameter. Fig.56B The vertical axis of represents the deviation between the intensity of the transmitted light when the signal line potential is 0 V and the intensity of the transmitted light when the signal line potential is 6 V, as a deviation of the grayscale level. The horizontal axis shows the grayscale level. The line connecting the values ​​when the thickness 1030 is 0.85 μm (hollow circles) has a small grayscale level deviation range compared to the line 1032 connecting the values ​​when the thickness 1030 is 0.45 μm (filled circles) and the line 1034 connecting the values ​​when the thickness 1030 is 0.65 μm (filled triangles).

[0793] This example confirms that the increase in the thickness 1030 can effectively suppress the deviation of the grayscale level caused by the electric field from the conductive film 21c as the signal line to the oxide semiconductor film 19c as the pixel electrode.

[0794] This specification is based on Japanese Patent Application serial number 2015-065357 filed in the Japan Patent Office on March 26, 2015, the entire contents of which are incorporated herein by reference.

Claims

1. A display device comprising a pixel, the pixel comprising: Pixel electrode; An insulating film on the pixel electrode; a common electrode on the insulating film; liquid crystal; a first substrate; transistor; A scan line extending in a first direction; and A signal line extending in a second direction intersecting the scan line, Wherein, the pixel electrode and the common electrode are located on the first substrate, The liquid crystal is driven by an electric field generated between the pixel electrode and the common electrode. The pixel includes a first region, a second region, a third region, a fourth region, a fifth region and a sixth region. The first area of ​​the pixel is located between the second area of ​​the pixel and the third area of ​​the pixel. The fourth region of the pixel is located between the sixth region of the pixel and the fifth region of the pixel, wherein, when viewed from above, the distance between the pixel electrode and the common electrode is constant in each of the first area of ​​the pixel and the fourth area of ​​the pixel, and the distance between the pixel electrode and the common electrode gradually decreases in each of the second area, the third area of ​​the pixel, the fifth area of ​​the pixel, and the sixth area of ​​the pixel, wherein a portion of the scan line is a gate electrode of the transistor, Wherein, the channel length direction of the transistor is parallel to the first direction, Wherein, the pixel electrode comprises: a first region disposed in the first region of the pixel, the second region of the pixel, and the third region of the pixel; and The second region is arranged in the fourth region of the pixel, the fifth region of the pixel, and the sixth region of the pixel, Wherein, the common electrode comprises: a first region, arranged in the first region of the pixel, the second region of the pixel, and the third region of the pixel; a second region disposed in the fourth region of the pixel, the fifth region of the pixel, and the sixth region of the pixel; and a third region, arranged between the third region of the pixel and the sixth region of the pixel, wherein the third region of the common electrode extends parallel to the first direction, Wherein, when viewed from above, the first region of the pixel electrode and the second region of the pixel electrode are line symmetrical with respect to the third region of the common electrode, Wherein, when viewed from above, the first region of the common electrode and the second region of the common electrode are line symmetrical with respect to the third region of the common electrode, wherein the signal line has a region whose width is smaller than other regions of the signal line, and Wherein, the third region of the common electrode overlaps with the region of the signal line.

2. The display device according to claim 1, further comprising a second common electrode and a second substrate, wherein the second common electrode is located on a side of the second substrate facing the first substrate, and The liquid crystal is driven by an electric field generated between the pixel electrode, the common electrode and the second common electrode. 3 . The display device of claim 1 , wherein the transistor is electrically connected to one of the pixel electrode and the common electrode. The display device as claimed in claim 3 , wherein the transistor is located on the first substrate.

5. The display device according to claim 3, wherein the transistor is a field effect transistor. The display device according to claim 3 , wherein the transistor comprises an oxide semiconductor.

7. An electronic device comprising: The display device as claimed in claim 1; and At least one of a switch, a speaker, and a housing.

8. A display device comprising a pixel, the pixel comprising: Pixel electrode; An insulating film on the pixel electrode; a common electrode on the insulating film; liquid crystal; a first substrate; transistor; as well as a scan line extending in a first direction; as well as A signal line extending in a second direction intersecting the scan line, Wherein, the pixel electrode and the common electrode are located on the first substrate, The liquid crystal is driven by an electric field generated between the pixel electrode and the common electrode. The pixel includes a first region, a second region, a third region, a fourth region, a fifth region and a sixth region. The first area of ​​the pixel is located between the second area of ​​the pixel and the third area of ​​the pixel. The fourth region of the pixel is located between the sixth region of the pixel and the fifth region of the pixel, Wherein, the pixel electrode comprises: a first region disposed in the first region of the pixel, the second region of the pixel, and the third region of the pixel; and The second region is arranged in the fourth region of the pixel, the fifth region of the pixel, and the sixth region of the pixel, Wherein, the common electrode comprises: a first region, arranged in the first region of the pixel, the second region of the pixel, and the third region of the pixel; a second region disposed in the fourth region of the pixel, the fifth region of the pixel, and the sixth region of the pixel; and a third region, arranged between the third region of the pixel and the sixth region of the pixel, wherein, in the first region of the pixel, when viewed from above, a first portion of the first region of the pixel electrode is parallel to a first portion of the first region of the common electrode, wherein, in the second region of the pixel, when viewed from above, the second portion of the first region of the common electrode is bent toward the first region of the pixel electrode, wherein, in the third region of the pixel, when viewed from above, the second portion of the first region of the pixel electrode is bent toward the first region of the common electrode, Wherein, in the fourth region of the pixel, when viewed from above, the first portion of the second region of the pixel electrode is parallel to the first portion of the second region of the common electrode; Wherein, in the fifth region of the pixel, when viewed from above, the second portion of the second region of the common electrode is bent toward the second region of the pixel electrode; Wherein, in the sixth region of the pixel, when viewed from above, the second portion of the second region of the pixel electrode is bent toward the second region of the common electrode; wherein a portion of the scan line is a gate electrode of the transistor, Wherein, the channel length direction of the transistor is parallel to the first direction, wherein the third region of the common electrode extends parallel to the first direction, Wherein, when viewed from above, the first region of the pixel electrode and the second region of the pixel electrode are line symmetrical with respect to the third region of the common electrode, Wherein, when viewed from above, the first region of the common electrode and the second region of the common electrode are line symmetrical with respect to the third region of the common electrode, wherein the signal line has a region whose width is smaller than other regions of the signal line, and Wherein, the third region of the common electrode overlaps with the region of the signal line.

9. The display device according to claim 8, further comprising a second common electrode and a second substrate, wherein the second common electrode is located on a side of the second substrate facing the first substrate, and The liquid crystal is driven by an electric field generated between the pixel electrode, the common electrode and the second common electrode.

10. The display device of claim 8, wherein the transistor is electrically connected to one of the pixel electrode and the common electrode.

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