A clock recovery circuit and method

Abstract

The present invention provides a clock recovery circuit and method. When selecting an optimal phase clock each time, the present invention selects an optimal phase clock from all phase clocks, and does not adopt the prior art of selecting an optimal phase clock from the phase clocks that were not selected last time. Therefore, when the optimal phase clock is selected each time, the optimal phase clock can be used to accurately and quickly sample the received serial data, thereby reducing the probability of serial data sampling failure.

Description

Technical Field

[0001] The present invention relates to the field of high-speed serial data transmission, and more particularly to a clock recovery circuit and method. Background Art

[0002] The USB2.0 high-speed serial data transmission system includes a transmitting circuit and a receiving circuit. The USB2.0 high-speed serial data transmission does not transmit the data synchronization clock and data together. Therefore, the receiving end needs to use the local clock and the received serial data to recover the synchronization clock for sampling and synchronizing the serial data.

[0003] The commonly used method for medium and high speed data clock recovery is the spatial oversampling method. Usually, N adjacent clocks with the same phase interval and the same frequency as the data rate are used to sample data simultaneously, and the sampled data is processed to find the optimal phase clock. When using the spatial oversampling method, the optimal phase clock is selected, and the process of using the selected phase clock to sample serial data includes:

[0004] First, an optimal phase clock is selected from all phase clocks, and then the selected phase clock is used to sample the received serial data. Thereafter, an optimal phase clock is selected from the remaining phase clocks, and the newly selected phase clock is used to continue sampling the received serial data.

[0005] When the phase clock selected for the first time is still better than the phase clock selected for the second time, the received serial data is continuously sampled using the phase clock selected for the second time, which may cause sampling failure of some serial data. Summary of the invention

[0006] In view of this, the present invention provides a clock recovery circuit and method to solve the problem that when the first selected phase clock is still better than the second selected phase clock, using the second selected phase clock to continue sampling the received serial data may cause sampling failure of some serial data.

[0007] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0008] A clock recovery circuit, comprising:

[0009] Oversampling and edge detection circuit, edge counting and voting selection circuit, clock selection circuit;

[0010] The oversampling and edge detection circuit, the edge counting and voting selection circuit, and the clock selection circuit are connected in sequence;

[0011] The oversampling and edge detection circuit is used to simultaneously sample serial data using N phase clocks when an optimal phase clock is selected from all phase clocks each time, and determine the data transition edge position according to the sampling results of two adjacent phase clocks; wherein N is a positive integer and N is not less than 2;

[0012] The edge counting and voting selection circuit is used to select a data edge position whose corresponding data edge number reaches a preset value first from all data edge positions according to the number of data edge at each data edge position, and send the selected data edge position to the clock selection circuit;

[0013] The clock selection circuit is used to select an optimal phase clock from the N phase clocks according to the received data transition edge position, so that the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock.

[0014] Preferably, when the oversampling and edge detection circuit is used to determine the data transition edge position according to the sampling results of two adjacent phase clocks, it is specifically used to:

[0015] The sampling results of two adjacent phase clocks are XORed to obtain the position of the data edge.

[0016] Preferably, the edge counting and voting selection circuit is used to select a data edge position whose corresponding number of data transition edges reaches a preset value first from all data edge positions according to the number of data transition edges at each data transition edge position, and is specifically used to:

[0017] Real-time statistics of the number of data transition edges at different data transition edge positions;

[0018] A data transition edge position whose corresponding number of data transition edges reaches a preset value first is selected from all data transition edge positions.

[0019] Preferably, the clock selection circuit is used to select an optimal phase clock from the N phase clocks according to the received data transition edge position, so that when the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock, it is specifically used to:

[0020] According to the preset correspondence between the data transition edge position and the phase clock, the phase clock corresponding to the received data transition edge position is determined, so that the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock.

[0021] Preferably, it also includes:

[0022] Data matching circuit; the data matching circuit is connected to the data sampling and serial-to-parallel circuit;

[0023] The data matching circuit is used to match the transmission delay of the serial data input to the oversampling and edge detection circuit with the serial data input to the data sampling and serial-to-parallel circuit, so as to ensure that the relative relationship between the data in the serial data input to the data sampling and serial-to-parallel circuit and the recovered clock is consistent with the relative relationship between the data in the serial data input to the oversampling and edge detection circuit and the phase clock corresponding to the recovered clock in the serial data.

[0024] A clock recovery method, comprising:

[0025] The oversampling and edge detection circuit uses N phase clocks to simultaneously sample serial data when selecting an optimal phase clock from all phase clocks each time, and determines the data transition edge position according to the sampling results of two adjacent phase clocks; wherein N is a positive integer and is not less than 2;

[0026] The edge counting and voting selection circuit selects a data edge position whose corresponding data edge number reaches a preset value first from all data edge positions according to the number of data edge at each data edge position, and sends the selected data edge position to the clock selection circuit;

[0027] The clock selection circuit selects an optimal phase clock from the N phase clocks according to the transition edge position of the received data, so that the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock.

[0028] Preferably, the oversampling and edge detection circuit determines the data transition edge position according to the sampling results of two adjacent phase clocks, including:

[0029] The sampling results of two adjacent phase clocks are XORed to obtain the position of the data edge.

[0030] Preferably, the edge counting and voting selection circuit selects a data edge position whose corresponding number of data transition edges reaches a preset value first from all data edge positions according to the number of data transition edges at each data transition edge position, including:

[0031] Real-time statistics of the number of data transition edges at different data transition edge positions;

[0032] A data transition edge position whose corresponding number of data transition edges reaches a preset value first is selected from all data transition edge positions.

[0033] Preferably, the clock selection circuit selects an optimal phase clock from the N phase clocks according to the received data transition edge position, so that when the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock, it is specifically used to:

[0034] According to the preset correspondence between the data transition edge position and the phase clock, the phase clock corresponding to the received data transition edge position is determined, so that the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock.

[0035] Preferably, the oversampling and edge detection circuit selects an optimal phase clock from all phase clocks each time, uses N phase clocks to simultaneously sample serial data, and before determining the data transition edge position according to the sampling results of two adjacent phase clocks, further includes:

[0036] The data matching circuit matches the transmission delay of the serial data input to the oversampling and edge detection circuit and the serial data input to the data sampling and serial-to-parallel circuit to ensure that the relative relationship between the data in the serial data input to the data sampling and serial-to-parallel circuit and the recovered clock is consistent with the relative relationship between the data in the serial data input to the oversampling and edge detection circuit and the phase clock corresponding to the recovered clock in the serial data.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] The present invention provides a clock recovery circuit and method. When selecting an optimal phase clock each time, the present invention selects an optimal phase clock from all phase clocks, and does not adopt the prior art of selecting an optimal phase clock from the phase clocks that were not selected last time. Therefore, when the optimal phase clock is selected each time, the optimal phase clock can be used to accurately and quickly sample the received serial data, thereby reducing the probability of serial data sampling failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0040] Figure 1 A schematic diagram of the structure of a clock recovery circuit provided by the present invention;

[0041] Figure 2 A schematic diagram of the structure of an oversampling and edge detection circuit provided by the present invention;

[0042] Figure 3 A schematic diagram of the structure of an edge counting and voting selection circuit provided by the present invention;

[0043] Figure 4 A schematic diagram of the structure of a counting and voting circuit provided by the present invention;

[0044] Figure 5 A schematic diagram of the structure of a clock selection circuit provided by the present invention;

[0045] Figure 6 A schematic diagram of the structure of a data sampling and serial-to-parallel circuit provided by the present invention;

[0046] Figure 7 A method flow chart of a clock recovery method provided by the present invention. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] The embodiment of the present invention provides a clock recovery circuit, referring to Figure 1 ,include:

[0049] Oversampling and edge detection circuit 101 , edge counting and voting selection circuit 103 , and clock selection circuit 104 .

[0050] The oversampling and edge detection circuit 101, the edge counting and voting selection circuit 103, and the clock selection circuit 104 are connected in sequence, and N phase clocks 102 are connected to the oversampling and edge detection circuit 101, the edge counting and voting selection circuit 103, and the clock selection circuit 104 respectively, N is a positive integer and N is not less than 2, preferably, N is 6.

[0051] Each phase clock of the N phase clocks 102 is used to provide a clock signal to the oversampling and edge detection circuit 101, the edge counting and voting selection circuit 103, and the clock selection circuit 104;

[0052] The oversampling and edge detection circuit 101 is used to simultaneously sample serial data using N phase clocks when an optimal phase clock is selected from all phase clocks each time, and determine the data transition edge position according to the sampling results of two adjacent phase clocks;

[0053] The edge counting and voting selection circuit 103 is used to select a data transition edge position whose corresponding data transition edge number first reaches a preset value from all data transition edge positions according to the number of data transition edges at each data transition edge position, and send the selected data transition edge position to the clock selection circuit; wherein the preset value is set in advance by a technician.

[0054] The clock selection circuit 104 is used to select an optimal phase clock from the N phase clocks according to the received data transition edge position, so that the data sampling and serial-to-parallel circuit 105 samples the serial data according to the selected phase clock.

[0055] Optionally, based on this embodiment, the method further includes:

[0056] Data matching circuit 106; data matching circuit 106 is connected to data sampling and serial-to-parallel circuit 105;

[0057] The data matching circuit 106 is used to match the transmission delay caused by different transmission paths between the serial data input to the oversampling and edge detection circuit 101 and the serial data input to the data sampling and serial-to-parallel circuit 105, so as to ensure that the relative relationship between the data in the serial data input to the data sampling and serial-to-parallel circuit 105 and the recovered clock is consistent with the relative relationship between the data in the serial data input to the oversampling and edge detection circuit 101 and the phase clock corresponding to the recovered clock in the serial data.

[0058] Specifically, the working process of each of the above circuits is as follows:

[0059] The input data is serial data, which is divided into two paths, one path is used for clock recovery and input into the oversampling and edge detection circuit 101, and the other path is used for recovered clock sampling and input into the data matching circuit 106. The purpose of clock recovery is to determine the phase clock, and the purpose of recovered clock sampling is to use the determined phase clock to sample the serial data to obtain data synchronized with the phase clock.

[0060] The 6-phase clock is a 480M clock with equal adjacent phase intervals generated by a phase-locked loop (with the local crystal oscillator clock as a reference).

[0061] After receiving the serial data, the oversampling and edge detection circuit 101 uses N phase clocks to sample the serial data simultaneously, and determines the data transition edge position according to the sampling results of two adjacent phase clocks. The edge counting and voting selection circuit 103 selects a data transition edge position whose corresponding data transition edge number first reaches a preset value from all data transition edge positions according to the number of data transition edges at each data transition edge position, and sends the selected data transition edge position to the clock selection circuit 104. The clock selection circuit 104 selects an optimal phase clock from the N phase clocks according to the received data transition edge position, and the data sampling and serial-to-parallel circuit 105 uses the selected phase clock to sample the serial data.

[0062] The data matching circuit 106 matches the transmission delay caused by different transmission paths between the serial data input to the oversampling and edge detection circuit 101 and the serial data input to the data sampling and serial-to-parallel circuit 105, so as to ensure that the relative relationship between the data in the serial data input to the data sampling and serial-to-parallel circuit 105 and the recovered clock is consistent with the relative relationship between the data in the serial data input to the oversampling and edge detection circuit 105 and the phase clock corresponding to the recovered clock in the serial data.

[0063] In this embodiment, each time the optimal phase clock is selected, an optimal phase clock is selected from all phase clocks, and the prior art of selecting an optimal phase clock from the phase clocks that were not selected last time is not adopted. Therefore, each time the optimal phase clock is selected, the optimal phase clock can be used to accurately and quickly sample the received serial data, thereby reducing the probability of serial data sampling failure.

[0064] Optionally, based on any of the above embodiments, when the oversampling and edge detection circuit is used to determine the data transition edge position according to the sampling results of two adjacent phase clocks, it is specifically used to:

[0065] The sampling results of two adjacent phase clocks are XORed to obtain the position of the data edge.

[0066] For details, please refer to the circuit diagram of oversampling and edge detection circuit. Figure 2 .

[0067] Figure 2 In the embodiment, the oversampling and edge detection circuit includes a plurality of triggers (trigger 1010 to trigger 10211) and a plurality of XOR gates (XOR gate 1020 to XOR gate 1025).

[0068] Among them, this embodiment takes 6-phase clock as an example, the frequencies of the 6-phase clocks are the same, the intervals between adjacent phase clocks are the same, all are 1 / 6 of a clock cycle, and the frequencies of the 6-phase clocks are the same as the maximum data rate of the input serial data.

[0069] It should be noted that, in this embodiment, not all triggers and XOR gates are drawn, but only some triggers and XOR gates are drawn.

[0070] The working process of each component of the oversampling and edge detection circuit is:

[0071] The received data, i.e., serial data, is sampled simultaneously by the trigger using a 6-phase clock. Specifically, trigger 1010 receives the clock signal PH0 of the zeroth phase clock input, trigger 1011 receives the clock signal PH1 of the first phase clock input, trigger 1012 receives the clock signal PH2 of the second phase clock input, trigger 1013 receives the clock signal PH3 of the third phase clock input, trigger 1014 receives the clock signal PH4 of the fourth phase clock input, and trigger 1015 receives the clock signal PH5 of the fifth phase clock input.

[0072] The sampling results of the six triggers correspond to q0~q5 respectively. The sampling results of adjacent phase clocks are XORed in pairs to determine the position of the data transition edge, and all output results are sent to the next level trigger for sampling.

[0073] The data output by each XOR gate is sampled to obtain com01-com50, that is, the transition edge information of different data transition edge positions is obtained. Among them, the signal output by XOR gate 1020 is sampled using the PH5 clock signal, the signal output by XOR gate 1021 is sampled using the PH0 clock signal, and so on, until the signal output by XOR gate 1025 is sampled using the PH4 clock signal.

[0074] Among them, when the data output by trigger 1026 is a high level, it means that the data transition edge position is between phases 0-1, and when the data output by trigger 1027 is a high level, it means that the data transition edge position is between phases 1-2, and so on, until the data output by trigger 10211 is a high level, it means that the data transition edge position is between phases 5-0.

[0075] It should be noted that this embodiment is explained by taking a 6-phase clock as an example. In addition, other phase clocks may also be used.

[0076] In this embodiment, a specific structural diagram of the oversampling and edge detection circuit is provided. According to the oversampling and edge detection circuit in this embodiment, the position of each data transition edge can be determined.

[0077] Optionally, based on any of the above embodiments, the edge counting and voting selection circuit is used to select a data edge position whose corresponding number of data transition edges reaches a preset value first from all data edge positions according to the number of data transition edges at each data transition edge position, and is specifically used to:

[0078] Real-time statistics of the number of data transition edges at different data transition edge positions;

[0079] A data transition edge position whose corresponding number of data transition edges reaches a preset value first is selected from all data transition edge positions.

[0080] The data transition edge position is the position between two adjacent phase clocks.

[0081] Specifically, the circuit structure of edge counting and voting selection circuit refers to Figure 3 .

[0082] The edge counting and voting selection circuit includes a plurality of counting and voting circuits (counting and voting circuit 1030-counting and voting circuit 1035) and a plurality of AND gates (AND gate 1040-AND gate 1045). PH0-PH5 are clock signals input by different phase clocks, wherein the present embodiment still takes the 6-phase clock as an example. com01-com50 are output signals of the oversampling and edge detection circuits, glb_rstn represents the chip global reset signal, when the chip is powered on, glb_rstn is first set to 0 and then set to 1. fc_rstn1 and fc_rstn2 are counter clearing and trigger reset signals, rstn1 <0> rstn2 <0> rstn1 <1> rstn2 <1> ……rstn1 <5> rstn2 <5> For the reset signal, select <0> To select <5> To determine the final data transition edge position, select <0> Represents the position between PH0 and PH1, select <1> Represents the position between PH1 and PH2, and so on. <5> It represents the position between PH5 and PH0. When any one of com01-com50 is at a high level, the corresponding counting circuit will add 1. When the number of data transition edges of a counting circuit reaches a preset value, a protection signal is generated to protect the select signal output by the counting and voting circuit from being reset. At the same time, rstn1 and rstn2 reset signals are generated. After passing through multiple AND gates 1041 to 1045, fc_rstn1 and fc_rstn2 signals are obtained to reset all counters and related triggers in the counting and voting circuits. The select signal that has not been reset will be output to the clock selection circuit. After that, the counters in the counting and voting circuits start counting again until a certain counter reaches a preset value.

[0083] For details, please refer to the internal structure diagram of edge counting and voting circuit. Figure 4 .

[0084] The com signal is the output of the oversampling and edge detection circuit, indicating the edge information of a certain position. For example, com01 indicates the information of the data transition edge at the position between PH0 and PH1. If there is a transition edge, com01 outputs a high level for a clock cycle, and if there is no edge, it outputs a low level. com can be com01 / com12 / com23 / com34 / com45 / com50; PH indicates a phase clock in the N-phase clock, which can be PH0~PH5, and PH_b is the reverse signal of PH; glb_rstn is the global reset signal of the chip, and a low level has Effective; fc_rstn1 / fc_rstn2 are counter clear and trigger reset signals, where fc_rstn1 and glb_rstn signals are logically ANDed together to clear the counter Counter, and fc_rstn2 and glb_rstn signals are logically ANDed together to reset the D flip-flop DFF1; GND represents a low level, and after passing through an inverter, a high level signal HIGH is generated; the counter samples the edge information of com and counts, and sends the result to the comparator Comparator. When the count value of the counter is the same as the preset value, the comparator outputs a high level, otherwise it outputs a low level. DFF1 samples the high level output of the comparator and latches the output of DFF1 together with mux (two-input and one-output selector). The output of DFF1 generates the rstn1 signal in reverse, and rstn1 is mainly used to generate the fc_rstn1 signal to clear all counters. DFF2 samples the rstn1 signal, and the input and output of the D flip-flop DFF2 are logically ORed to generate the rstn2 signal. Rstn2 is mainly used to generate the fc_rstn2 signal to reset all D flip-flops DFF. DFF3 samples the inverted signal of rstn1, and the input and output of DFF3 are logically ORed to generate the protect signal, which is used to protect the select signal generated by DFF4 from being reset when the count value of the counter reaches the preset value. DFF4 samples the output signal of DFF3 to output the position selection signal select.

[0085] In this embodiment, each time the data transition edge position is determined, a corresponding data transition edge position whose number of data transition edges reaches the preset value first can be selected from all the data transition edge positions, thereby ensuring that the selected phase clock is the best among all the phase clocks, ensuring that the input serial data can be correctly sampled. At the same time, the circuit can also ensure that no glitches are generated when the phase clock is switched.

[0086] Optionally, based on any of the above embodiments, the clock selection circuit is used to select an optimal phase clock from the N phase clocks according to the received data transition edge position, so that when the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock, it is specifically used to:

[0087] According to the preset correspondence between the data transition edge position and the phase clock, the phase clock corresponding to the received data transition edge position is determined, so that the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock.

[0088] Specifically, according to the received data transition edge position, the phase clock farthest from the received data transition edge position is selected from N phase clocks as the optimal data recovery clock, and this phase clock is sent to the data sampling and serial-to-parallel circuit for data sampling and serial-to-parallel conversion.

[0089] Specifically, the circuit structure of the clock selection circuit refers to Figure 5 .

[0090] The clock selection circuit has multiple NAND gates, NOR gates and inverters. In the input of the clock selection circuit, PH0-PH5 are clock signals output by different phase clocks. <0> -select <5> The counting and voting circuit output signals, PH0-PH5, select <0> -select <5> After the signal is input to multiple NAND gates, NOR gates and inverters, the final output is recov_clock, where recov_clock and select <0> -select <5> The high level signal in the signal is input to the same NAND gate with the same phase clock, that is, the select <0> -select <5> The high level signal in is input to the phase clock of the same NAND gate as the output.

[0091] Figure 5 In the figure, GND indicates the ground terminal. The function of this clock selection circuit is to select <0> -select <5> signal and select a phase clock as the recovered clock.

[0092] It should be noted that from Figure 5 As can be seen, when select <1> When the phase clock is high, the final phase clock selected is PH3. From the circuit principle, the phase clock selected is close to the data jump edge position (select <1> The phase clock with the farthest position between PH0 and PH1 is used as the optimal recovered clock.

[0093] When the currently selected optimal phase clock is the same as the last selected phase clock, the last selected phase clock will continue to be used. If the currently selected optimal phase clock is different from the last selected phase clock, the phase clock used will be replaced, and the data sampling and serial-to-parallel circuit will use the new phase clock to sample data.

[0094] The circuit structure of data sampling and serial-to-parallel circuit is shown in Figure 6 .

[0095] Figure 6 In the embodiment, the data sampling and serial-to-parallel circuit includes a plurality of DFFs (D flip-flops) and buffers. In this embodiment, a frequency division of 4, ie, div4, is adopted. Para_clk is a parallel output clock signal.

[0096] The input signals of the data sampling and serial-to-parallel circuit are the recov_clock, seri_data and glb_rstn signals output by the clock selection circuit, where seri_data is the received serial data and glb_rstn is the chip global reset signal. When seri_data reaches the data sampling and serial-to-parallel circuit, the data enters the first column DFF in series and is output in parallel through the second column DFF. It should be noted that the present embodiment uses a 4-frequency division, and other forms of frequency division may also be used.

[0097] In this embodiment, the phase clock corresponding to the received data transition edge position is determined according to the preset correspondence between the data transition edge position and the phase clock, in order to ensure that the optimal phase clock can be used to sample the serial data.

[0098] Optionally, another embodiment of the present invention provides a clock recovery method, referring to Figure 7 ,include:

[0099] S11, when the oversampling and edge detection circuit selects an optimal phase clock from all phase clocks each time, it uses N phase clocks to simultaneously sample the serial data, and determines the data transition edge position according to the sampling results of two adjacent phase clocks; wherein N is a positive integer and N is not less than 2;

[0100] S12, the edge counting and voting selection circuit selects a data transition edge position whose corresponding data transition edge number reaches a preset value first from all data transition edge positions according to the data transition edge number of each data transition edge position, and sends the selected data transition edge position to the clock selection circuit;

[0101] S13. The clock selection circuit selects an optimal phase clock from the N phase clocks according to the received data transition edge position, so that the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock.

[0102] Furthermore, the oversampling and edge detection circuit uses N phase clocks to simultaneously sample serial data each time an optimal phase clock is selected from all phase clocks, and before determining the data transition edge position according to the sampling results of two adjacent phase clocks, it also includes:

[0103] The data matching circuit matches the delays of the serial data input to the oversampling and edge detection circuit and the serial data input to the data sampling and serial-to-parallel circuit due to different transmission paths, so as to ensure that the relative relationship between the data in the serial data input to the data sampling and serial-to-parallel circuit and the recovered clock is consistent with the relative relationship between the data in the serial data input to the oversampling and edge detection circuit and the phase clock corresponding to the recovered clock in the serial data.

[0104] In this embodiment, each time the optimal phase clock is selected, an optimal phase clock is selected from all phase clocks, and the prior art of selecting an optimal phase clock from the phase clocks that were not selected last time is not adopted. Therefore, each time the optimal phase clock is selected, the optimal phase clock can be used to accurately and quickly sample the received serial data, thereby reducing the probability of serial data sampling failure.

[0105] Optionally, based on any of the above clock recovery method embodiments, the oversampling and edge detection circuit determines the data transition edge position according to the sampling results of two adjacent phase clocks, including:

[0106] The sampling results of two adjacent phase clocks are XORed to obtain the position of the data edge.

[0107] In this embodiment, a specific structural diagram of the oversampling and edge detection circuit is provided. According to the oversampling and edge detection circuit in this embodiment, the position of each data transition edge can be determined.

[0108] Optionally, based on any of the above embodiments of the clock recovery method, the edge counting and voting selection circuit selects a data edge position whose corresponding number of data transition edges reaches a preset value first from all data edge positions according to the number of data transition edges at each data transition edge position, including:

[0109] Real-time statistics of the number of data transition edges at different data transition edge positions;

[0110] A data transition edge position whose corresponding number of data transition edges reaches a preset value first is selected from all data transition edge positions.

[0111] In this embodiment, each time the data transition edge position is determined, a corresponding data transition edge position whose number of data transition edges reaches the preset value first can be selected from all the data transition edge positions, thereby ensuring that the selected phase clock is the best among all the phase clocks, ensuring that the input serial data can be correctly sampled. At the same time, the circuit can also ensure that no glitches are generated when the phase clock is switched.

[0112] Optionally, based on any of the above embodiments of the clock recovery method, the clock selection circuit selects an optimal phase clock from the N phase clocks according to the received data transition edge position, so that when the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock, it is specifically used to:

[0113] According to the preset correspondence between the data transition edge position and the phase clock, the phase clock corresponding to the received data transition edge position is determined, so that the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock.

[0114] In this embodiment, the phase clock corresponding to the received data transition edge position is determined according to the preset correspondence between the data transition edge position and the phase clock, in order to ensure that the optimal phase clock can be used to sample the serial data.

[0115] It should be noted that, for the specific structure and working process of each circuit in each of the above method steps, please refer to the corresponding description in the above embodiments, which will not be repeated here.

[0116] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A clock recovery circuit, characterized in that: include: Oversampling and edge detection circuit, edge counting and voting selection circuit, clock selection circuit; The oversampling and edge detection circuit, the edge counting and voting selection circuit, and the clock selection circuit are connected in sequence; The oversampling and edge detection circuit is used to simultaneously sample serial data using N phase clocks when an optimal phase clock is selected from all phase clocks each time, and determine the data transition edge position according to the sampling results of two adjacent phase clocks; wherein N is a positive integer and N is not less than 2; The edge counting and voting selection circuit is used to select a data edge position whose corresponding data edge number reaches a preset value first from all data edge positions according to the number of data edge at each data edge position, and send the selected data edge position to the clock selection circuit; The clock selection circuit is used to select an optimal phase clock from the N phase clocks according to the received data jump edge position, so that the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock; the oversampling and edge detection circuit includes a plurality of triggers and a plurality of XOR gates; the edge counting and voting selection circuit includes a plurality of counting and voting circuits and a plurality of AND gates; the data matching circuit; the data matching circuit is connected to the data sampling and serial-to-parallel circuit; The data matching circuit is used to match the transmission delay of the serial data input to the oversampling and edge detection circuit with the serial data input to the data sampling and serial-to-parallel circuit, so as to ensure that the relative relationship between the data in the serial data input to the data sampling and serial-to-parallel circuit and the recovered clock is consistent with the relative relationship between the data in the serial data input to the oversampling and edge detection circuit and the phase clock corresponding to the recovered clock in the serial data.

2. The clock recovery circuit according to claim 1, characterized in that: When the oversampling and edge detection circuit is used to determine the data transition edge position according to the sampling results of two adjacent phase clocks, it is specifically used to: The sampling results of two adjacent phase clocks are XORed to obtain the position of the data edge.

3. The clock recovery circuit according to claim 1, characterized in that: The edge counting and voting selection circuit is used to select a data transition edge position whose corresponding data transition edge number reaches a preset value first from all data transition edge positions according to the data transition edge number of each data transition edge position, and is specifically used to: Real-time statistics of the number of data transition edges at different data transition edge positions; A data transition edge position whose corresponding number of data transition edges reaches a preset value first is selected from all data transition edge positions.

4. The clock recovery circuit according to claim 1, characterized in that: The clock selection circuit is used to select an optimal phase clock from the N phase clocks according to the received data transition edge position, so that the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock, and is specifically used to: According to the preset correspondence between the data transition edge position and the phase clock, the phase clock corresponding to the received data transition edge position is determined, so that the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock.

5. A clock recovery method, characterized in that: The clock recovery circuit as claimed in claim 1 comprises: The oversampling and edge detection circuit uses N phase clocks to simultaneously sample serial data when selecting an optimal phase clock from all phase clocks each time, and determines the data transition edge position according to the sampling results of two adjacent phase clocks; wherein N is a positive integer and is not less than 2; The edge counting and voting selection circuit selects a data edge position whose corresponding data edge number reaches a preset value first from all data edge positions according to the number of data edge at each data edge position, and sends the selected data edge position to the clock selection circuit; The clock selection circuit selects an optimal phase clock from the N phase clocks according to the transition edge position of the received data, so that the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock.

6. The clock recovery method according to claim 5, characterized in that: The oversampling and edge detection circuit determines the data transition edge position according to the sampling results of two adjacent phase clocks, including: The sampling results of two adjacent phase clocks are XORed to obtain the position of the data edge.

7. The clock recovery method according to claim 5, characterized in that: The edge counting and voting selection circuit selects a data transition edge position whose corresponding data transition edge number reaches a preset value first from all data transition edge positions according to the number of data transition edges at each data transition edge position, including: Real-time statistics of the number of data transition edges at different data transition edge positions; A data transition edge position whose corresponding number of data transition edges reaches a preset value first is selected from all data transition edge positions.

8. The clock recovery method according to claim 5, characterized in that: The clock selection circuit selects an optimal phase clock from the N phase clocks according to the received data transition edge position, so that the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock, specifically for: According to the preset correspondence between the data transition edge position and the phase clock, the phase clock corresponding to the received data transition edge position is determined, so that the data sampling and serial-to-parallel circuit samples the serial data according to the selected phase clock.

9. The clock recovery method according to claim 5, characterized in that: The oversampling and edge detection circuit uses N phase clocks to simultaneously sample serial data each time an optimal phase clock is selected from all phase clocks, and before determining the data transition edge position according to the sampling results of two adjacent phase clocks, it also includes: The data matching circuit matches the transmission delay of the serial data input to the oversampling and edge detection circuit and the serial data input to the data sampling and serial-to-parallel circuit to ensure that the relative relationship between the data in the serial data input to the data sampling and serial-to-parallel circuit and the recovered clock is consistent with the relative relationship between the data in the serial data input to the oversampling and edge detection circuit and the phase clock corresponding to the recovered clock in the serial data.

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