Semiconductor device including support pattern

Abstract

A semiconductor device includes: a plurality of pillar structures on a semiconductor substrate; and a support pattern that contacts at least a portion of each of the pillar structures, the support pattern connecting the pillar structures to each other, wherein the support pattern includes support holes that expose side surfaces of the pillar structures, the support holes include second support holes and at least one first support hole that are spaced apart from each other, and the first support holes and the second support holes have shapes different from each other.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device including a support pattern. Background Art

[0002] Semiconductor devices are considered to be an important factor in the electronics industry due to their small size, multi-function and / or low manufacturing cost. Semiconductor devices are being highly integrated with the development of the electronics industry. For example, for the high integration of semiconductor devices, the line width of the pattern of semiconductor devices is reduced. However, new exposure techniques and / or expensive exposure techniques are needed to reduce the line width of the pattern to promote the high integration of semiconductor devices. Therefore, new integration techniques have been studied, such as burying word lines inside semiconductor substrates in dynamic random access memory (DRAM) memory devices. Summary of the invention

[0003] According to an exemplary embodiment, a semiconductor device may include: a plurality of pillar structures on a semiconductor substrate; and a support pattern that contacts at least a portion of each of the plurality of pillar structures, the support pattern connecting the plurality of pillar structures to each other, wherein the support pattern includes support holes that expose side surfaces of the plurality of pillar structures, the support holes including second support holes and at least one first support hole spaced apart from each other, the first support holes and the second support holes having shapes different from each other.

[0004] According to an exemplary embodiment, a semiconductor device may include: a plurality of pillar structures on a semiconductor substrate, the semiconductor substrate including a unit area and a dummy area; and a support pattern that contacts at least a portion of each of the plurality of pillar structures, the support pattern connecting the plurality of pillar structures to each other, wherein the support pattern includes support holes that expose side surfaces of the plurality of pillar structures, the support holes including a plurality of first support holes and at least one second support hole spaced apart from each other, wherein the plurality of first support holes have a shape different from a shape of the at least one second support hole, and wherein the support holes are on the unit area.

[0005] According to an exemplary embodiment, a semiconductor device may include: a plurality of electrode pillars on a semiconductor substrate; and a support pattern that contacts at least a portion of each of the plurality of electrode pillars, the support pattern connecting the plurality of electrode pillars to each other, wherein the support pattern includes support holes passing therethrough, the support holes including at least one first support hole and at least one second support hole spaced apart from each other, the first support hole and the second support hole having different shapes from each other in a top view. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0007] Figure 1 A top view of a semiconductor device according to an exemplary embodiment is shown.

[0008] Figure 2 Shown along Figure 1 A cross-sectional view taken along line CC'.

[0009] Figure 3 Shown along Figure 1 A cross-sectional view taken along line D-D'.

[0010] Figure 4 Show Figure 1 Top view of the arrangement of the bottom electrode.

[0011] Figures 5 to 11 A top view showing the relationship between the bottom electrode and the support hole.

[0012] Fig.12 A semiconductor device according to another exemplary embodiment is shown along Figure 1 Cross-sectional view along line CC'.

[0013] Figures 13 to 16 Shown to manufacture with Figure 2 A cross-sectional view of a semiconductor device at a stage in the method.

[0014] Fig.17 A top view illustrating a mask pattern for forming a support hole according to an exemplary embodiment. DETAILED DESCRIPTION

[0015] Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0016] Figure 1 is a top view showing a semiconductor device according to an exemplary embodiment. Figure 2 is along Figure 1 A cross-sectional view taken along line CC'. Figure 3 is along Figure 1 A cross-sectional view taken along line D-D'. Figure 4 It is shown Figure 1 Top view of the arrangement of the lower electrode.

[0017] Reference Figures 1 to 4 , a semiconductor substrate 102 may be provided. The semiconductor substrate 102 may include an actual cell region A and a dummy cell region B. Figure 1As shown in , the dummy cell region B may surround the actual cell region A. The actual cell region A and the dummy cell region B may be arranged on the storage block portion of the cell array region. The peripheral circuit region or the core region may be located outside the dummy cell region B. The actual cell region A may be a region in which the actual storage cell is arranged and operated. The dummy cell region B may have a structure similar to that of the actual cell region A, and may be a region in which an inoperable dummy storage cell is arranged. The dummy storage cell may be formed to prevent, for example, the pattern shape in the actual cell region A from being deformed due to interference or diffraction of light at the edge region of the unit storage region during the photolithography process. In addition, in the etching process, the unit storage region may have different etching conditions in its edge region than in its central region, for example, thereby generating a bridge between the patterns. Therefore, the dummy storage cell may be formed so that the edge region of the unit storage region has the same etching conditions as the etching conditions in the central region of the unit storage region, for example, the dummy cell region B may be the edge region of the actual cell region A to help the same etching conditions throughout the entire actual cell region A.

[0018] The semiconductor substrate 102 may be, for example, a single crystal silicon substrate. An interlayer dielectric layer 104 may be disposed on the semiconductor substrate 102. The interlayer dielectric layer 104 may be formed of, for example, a silicon oxide layer. A plurality of bottom electrode contacts 106 penetrate the interlayer dielectric layer 104 to be electrically connected to the semiconductor substrate 102. The bottom electrode contacts 106 may include at least one of an impurity-doped polysilicon pattern, a titanium nitride layer, and a tungsten layer.

[0019] Although not shown in the figure, the semiconductor substrate 102 may be configured with a device isolation layer defining an active region therein. The word lines may be buried in the semiconductor substrate 102. The gate dielectric layer and the cap pattern may insulate the word lines from the semiconductor substrate 102. The source / drain region may be provided to include an impurity region disposed in the semiconductor substrate 102 on the opposite side of each of the word lines. The impurity region on one side of each of the word lines may be electrically connected to a corresponding bit line. The bottom electrode contacts 106 may each be electrically connected to the impurity region on the other side of each of the word lines.

[0020] The etch stop layer 108 may be disposed on the interlayer dielectric layer 104. The etch stop layer 108 may be formed of, for example, a silicon nitride layer. The bottom electrodes BE and DBE penetrate the etch stop layer 108 to contact the corresponding bottom electrode contacts 106. In this specification, the bottom electrode BE disposed on the actual cell region A is referred to as the actual bottom electrode BE, and the bottom electrode DBE disposed on the dummy cell region B is referred to as the dummy bottom electrode DBE. Note that in Figure 1, the actual bottom electrode BE is shown by a solid boundary line, and the dummy bottom electrode DBE is shown by a dotted boundary line. Some of the dummy bottom electrodes DBE may be arranged on the actual cell region A and disposed on an edge portion of the actual cell region A so as to be adjacent to the dummy cell region B. All of the bottom electrodes BE and DBE may have the same shape and be formed of the same material. For example, the bottom electrodes BE and DBE may be formed of titanium nitride or impurity-doped polysilicon.

[0021] The bottom electrodes BE and DBE may be electrode pillars, ie, pillar structures. That is, the bottom electrodes BE and DBE may have a pillar shape having a circular cross section in a top view and a cylindrical shape in a cross-sectional view ( Figure 2 ) has a plug shape without an internal cavity. The bottom electrodes BE and DBE may include a storage pillar structure on the actual cell region A and a dummy pillar structure on the dummy cell region B, respectively. The storage pillar structure may perform a storage function, while the dummy pillar structure may not perform a storage function.

[0022] Reference Figure 4 , the bottom electrodes BE and DBE may be spaced apart from each other at the same interval. That is, the bottom electrodes BE and DBE may have a circular cross-section in a top view, and the straight line 3 connecting the center points of the most adjacent circles may be the same, for example, the distance between the center points of every two adjacent circles may be the same. When the center points of six bottom electrodes BE and DBE surrounding the central bottom electrode BE or DBE are connected, a hexagonal honeycomb shape may be obtained. Since the bottom electrodes BE and DBE are spaced apart from each other at the same interval, the dielectric layer and the top electrode may be formed to have a uniform thickness in a subsequent process.

[0023] like Figure 1-2 As shown in , the bottom electrodes BE and DBE may have upper sidewalls in contact with the support pattern 112. For example, the support pattern 112 may extend to contact the upper portion of the upper sidewall of the adjacent bottom electrode among the bottom electrodes BE and DBE to support the bottom electrodes BE and DBE. The support pattern 112 may be formed of, for example, a silicon nitride layer. The support pattern 112 may be in contact with the sidewalls of all the bottom electrodes BE and DBE. Figure 1 As shown in FIG. 1 , the support pattern 112 may include support holes 1a, 1b, and 1c. Note that the support pattern 112 is Figure 1 Indicated in pure grey.

[0024] In detail, Figure 1As shown in , the support holes 1a, 1b, and 1c may be provided on the actual cell region A, but not on the dummy cell region B. That is, the support holes 1a, 1b, and 1c may be provided only on the actual cell region A, so there may be no support holes 1a, 1b, and 1c (or portions thereof) on the dummy cell region B. In the actual cell region A, the support holes 1a, 1b, and 1c may partially expose the side surfaces of all the actual bottom electrodes BE, for example, the support holes 1a to 1c may be formed so that a portion of the side surface of each of the actual bottom electrodes BE faces the support holes. The support holes 1a, 1b, and 1c may expose some of the dummy bottom electrodes DBE arranged on the actual cell region A.

[0025] The support holes 1a, 1b and 1c may include a first support hole 1a, a second support hole 1b and a third support hole 1c. The first support hole 1a to the third support hole 1c may have different planar shapes from each other. The first support hole 1a may be provided in plurality. The first support hole 1a may be a majority hole that occupies the majority of the support holes 1a, 1b and 1c, for example, the majority of the support holes in all the support holes 1a to 1c are first support holes 1a. For example, the total number of the first support holes 1a may be greater than the total number of the second support holes 1b and / or the total number of the third support holes 1c. The first support hole 1a may be arranged on the central portion of the actual unit area A. Some of the first support holes 1a may also be arranged on the edge portion of the actual unit area A. The actual unit area A may be configured with at least one second support hole 1b and at least one third support hole 1c at its edge portion.

[0026] Figures 5 to 11 1 is a top view showing the relationship between the bottom electrodes BE, DBE and the supporting holes 1a to 1g.

[0027] Reference Figure 5 , when connecting the sidewalls of the first support hole 1a with the center points of the bottom electrodes BE and DBE exposed through the first support hole 1a, a circular shape may be obtained in a top view. For example, the first support hole 1a may have a circular cross-section in a top view, wherein the perimeter of the circle extends through the center points of three adjacent bottom electrodes BE and DBE, and wherein the center of the circle is at the center of the area between the three adjacent bottom electrodes BE and DBE. The first support hole 1a may partially expose the sidewalls of the three adjacent bottom electrodes BE and DBE.

[0028] Reference Figure 6When the sidewall of the second support hole 1b is connected to the center point of the bottom electrode BE and DBE exposed through the second support hole 1b, a quadrilateral connecting the five bottom electrodes BE and DBE can be obtained in the top view. For example, the second support hole 1b can have a trapezoidal cross-section in the top view, wherein the first side of the trapezoid connects the center points of two adjacent bottom electrodes BE and DBE, and the second side of the trapezoid is parallel to the first side and connects the center points of three adjacent bottom electrodes BE and DBE. The second support hole 1b can partially expose the sidewalls of the five bottom electrodes BE and DBE.

[0029] Reference Figure 7 When the sidewall of the third support hole 1c is connected to the center points of the bottom electrodes BE and DBE exposed through the third support hole 1c, a quadrilateral connecting the four bottom electrodes BE and DBE can be obtained in a top view. For example, the third support hole 1c can have a rhombus-shaped cross-section in a top view, wherein each side of the rhombus connects the center points of two adjacent bottom electrodes BE and DBE.

[0030] The supporting holes 1a, 1b and 1c may not be limited thereto but may be variously changed. This will be referred to below. Figure 8-11 is described.

[0031] Reference Figure 8 , the support pattern 112 may include a fourth support hole 1d. When the sidewall of the fourth support hole 1d is connected to the center point of the bottom electrode BE and DBE exposed through the fourth support hole 1d, an equilateral triangle may be obtained in a top view. For example, the fourth support hole 1d may have an equilateral triangle cross-section in a top view, wherein each side of the equilateral triangle connects the center points of two adjacent bottom electrodes BE and DBE.

[0032] Reference Fig. 9 , the support pattern 112 may include a fifth support hole 1e. When the sidewall of the fifth support hole 1e is connected to the center point of the bottom electrode BE and DBE exposed through the fifth support hole 1e, an isosceles triangle (having an angle of 120°) may be obtained in a top view. For example, the fifth support hole 1e may have an isosceles triangle cross-section in a top view, wherein each side of the isosceles triangle connects the center points of two adjacent bottom electrodes BE and DBE.

[0033] Reference Fig.10 , the support pattern 112 may include a sixth support hole 1f. When the sidewall of the sixth support hole 1f is connected to the center point of the bottom electrode BE and DBE exposed through the sixth support hole 1f, a deformed hexagon may be obtained in a top view. For example, the sixth support hole 1f may have a deformed hexagonal cross-section in a top view, wherein each side of the hexagon connects the center points of two adjacent bottom electrodes BE and DBE.

[0034] Reference Fig.11 , the support pattern 112 may include a seventh support hole 1g. When the sidewall of the seventh support hole 1g is connected to the center point of the bottom electrode BE and DBE exposed through the seventh support hole 1g, a deformed heptagon may be obtained in a top view. For example, the seventh support hole 1g may have a deformed heptagonal cross-section in a top view, wherein each side of the heptagon connects the center points of two adjacent bottom electrodes BE and DBE.

[0035] At least one of the second to seventh supporting holes 1b to 1g may be provided in Figure 1 The support pattern 112 is formed on an edge portion of the actual cell region A. One of the support holes 1a to 1g may partially expose sidewalls of three to seven bottom electrodes BE and DBE at the same time. The number of the support holes 1a to 1g may be at least one.

[0036] Reference Figure 2 , the dielectric layer 124 may conformally cover the exposed surface of the support pattern 112 and the exposed surface of the bottom electrodes BE and DBE, and the top electrode TE may be formed on the dielectric layer 124, for example, to fill the space between the bottom electrodes BE and DBE and extend over the bottom electrodes BE and DBE. That is, because the support holes 1a, 1b, and 1c partially expose the side surfaces of all the actual bottom electrodes BE during the manufacturing stage, the dielectric layer 124 may conformally cover the exposed surfaces of the bottom electrodes BE and DBE facing the support holes. For example, Figure 2 A portion of the first supporting hole 1a (between the two leftmost actual bottom electrodes BE) filled with a dielectric layer 124 and a top electrode TE is shown. The dielectric layer 124 may be formed of, for example, a metal oxide layer such as an aluminum oxide layer exhibiting a dielectric constant greater than that of a silicon oxide layer. The top electrode TE may be formed of, for example, at least one of a titanium nitride layer, a tungsten layer, an impurity-doped polysilicon layer, and an impurity-doped silicon germanium layer.

[0037] As described above, in the semiconductor device according to an exemplary embodiment, the support pattern 112 supporting the bottom electrodes BE and DBE may include at least one of the support holes 1a to 1g having shapes different from each other, for example, at least two of the support holes in the support pattern 112 may have shapes different from each other. As such, the support holes 1a to 1g may all be placed in the actual cell region A to expose the side surfaces of all the actual bottom electrodes BE used as memories on the actual cell region A without extending into the dummy cell region B. In addition, since the shapes of the support holes in the support pattern 112 are not all the same as each other, at least one of the shapes of the support holes in the support pattern 112 may be adjusted to ensure that all the support holes of the support pattern 112 are within the actual cell region A without extending into the dummy cell region B, thereby eliminating the need to horizontally extend the width of the support pattern 112 into the peripheral circuit region. In addition, since the support holes 1a to 1g expose the side surfaces of all the actual bottom electrodes BE in the actual cell region A, the dielectric layer 124 and the top electrode TE may be deposited to have a uniform thickness without collapse of the bottom electrode BE.

[0038] Fig.12 FIG. 1 shows a semiconductor device according to another exemplary embodiment. Figure 1 A cross-sectional view of the line C-C'. Fig.12 , the bottom electrodes BE and DBE may have a hollow cup shape. The dielectric layer 124 and the top electrode TE may also be formed to conform to the inner surfaces of the bottom electrodes BE and DBE.

[0039] Figures 13 to 16 It is shown that manufacturing has Figure 2 A cross-sectional view of a semiconductor device at a stage in the method. Fig.17 is a top view illustrating a mask pattern for forming a support hole according to an exemplary embodiment.

[0040] Reference Fig.13 , a semiconductor substrate 102 may be provided. Although not shown in the figure, an active region may be defined by forming a device isolation layer in the semiconductor substrate 102. Word lines may be formed in the semiconductor substrate 102. The word lines may be insulated from the semiconductor substrate 102 by a gate dielectric layer and a cap pattern. Impurity regions may be formed in the semiconductor substrate 102 on opposite sides of each of the word lines. Bit lines may be formed on the semiconductor substrate 102, and thus each is electrically connected to the impurity region on one side of each of the word lines.

[0041] An interlayer dielectric layer 104 may be formed on the semiconductor substrate 102. The interlayer dielectric layer 104 may be etched to form contact holes exposing each of the impurity regions on the other side of each of the word lines in the substrate 102, and the contact holes may be filled with a conductive material, followed by a planarization process of the conductive material to form a bottom electrode contact 106, for example, the top of the bottom electrode contact 106 may be flush with the top of the interlayer dielectric layer 104.

[0042] The etch stop layer 108 may be formed on the interlayer dielectric layer 104 and on the bottom electrode contact 106. The first mold layer 110, the support layer 112a, and the second mold layer 114 may be sequentially formed, for example, directly on the etch stop layer 108. The etch stop layer 108 may be formed of a material having an etch selectivity relative to the first mold layer 110. For example, the etch stop layer 108 may be formed of a silicon nitride layer, and the first mold layer 110 and the second mold layer 114 may be formed of a silicon oxide-based material. When polysilicon is not used to form the bottom electrodes BE and DBE discussed below, the first mold layer 110 and the second mold layer 114 may be formed of a polysilicon layer or a silicon germanium layer. The support layer 112a may be formed of, for example, a silicon nitride layer. The first mask pattern 116 may be formed on the second mold layer 114 to define an opening for a bottom electrode hole discussed below, for example, the opening of the first mask pattern 116 may overlap the bottom electrode contact 106. The first mask pattern 116 may include, for example, a photoresist pattern.

[0043] Reference Fig.14 , the first mask pattern 116 may be used as an etching mask to sequentially pattern the second mold layer 114, the support layer 112a, and the first mold layer 110, thereby exposing the etch stop layer 108. Then, the exposed etch stop layer 108 may be etched to form a bottom electrode hole 118 exposing the top surface of the bottom electrode contact 106.

[0044] Reference Fig.15 , the first mask pattern 116 may be removed. For example, when the first mask pattern 116 is formed of a photoresist pattern, an ashing process may be employed to remove the first mask pattern 116. Thus, the top surface of the second mold layer 114 may be exposed. Subsequently, a conductive layer may be formed, for example, stacked, in the bottom electrode hole 118, for example, to completely fill the bottom electrode hole 118, followed by a planarization etching process of the conductive layer to expose the top surface of the second mold layer 114 and simultaneously form bottom electrodes BE, DBE in the corresponding bottom electrode holes 118.

[0045] Reference Fig.16 and 17 , the second mask pattern 120 may be formed on the bottom electrodes BE, DBE and the second mold layer 114. The second mask pattern 120 may have a defined Figure 1 and Figures 5 to 11 For example, when only the first to third support holes 1a to 1c are included in the support pattern 112 discussed below, the second mask pattern 120 may include first mask holes 122a, second mask holes 122b, and third mask holes 122c having shapes and positions corresponding to the shapes and positions of the first to third support holes 1a to 1c. For example, Fig.17 As shown in , the first mask hole 122a may have a circular shape, the second mask hole 122b may have a trapezoidal shape, and the third mask hole 122c may have a rhombus shape. The first to third mask holes 122a, 122b, and 122c may be placed to overlap only a portion of the actual unit area A. Since the second mask hole 122b and the third mask hole 122c have a shape different from the shape of the first mask hole 122a (i.e., a circular shape), for example, a polygonal shape, the first to third mask holes 122a, 122b, and 122c may be provided only in the actual unit area A.

[0046] According to an embodiment, a photolithography process may be performed to form first to third mask holes 122a to 122c in the second mask pattern 120. Generally, the horizontal width of the support pattern is extended toward the peripheral region or the core region in consideration of the process margin of the photolithography process that may potentially cause some of the mask holes to at least partially extend into the dummy cell region, for example, overlap the dummy cell region. That is, in consideration of the process margin of the photolithography process, if all the mask holes have the same shape (e.g., circular), some of such mask holes will extend into the dummy cell region, for example, at least partially overlap the dummy cell region, so as to expose the sidewalls of all the actual bottom electrodes BE, thereby requiring the horizontal width of the support pattern to extend toward the peripheral region or the core region.

[0047] However, according to example embodiments, some shapes of the mask holes at the edge of the actual cell region A, such as the second mask hole 122b and the third mask hole 122c, may be modified to be non-circular so as to remain placed within the actual cell region A while also exposing the sidewalls of all the actual bottom electrodes BE. In other words, because all of the first to third mask holes 122a to 122c are placed within the actual cell region A due to the different shapes of the first to third mask holes 122a to 122c, i.e., none of the first to third mask holes 122a to 122c extends beyond the actual cell region A, the horizontal width of the support pattern 122 does not have to be extended, thereby facilitating high integration.

[0048] The second mask pattern 120 may be used as an etching mask to remove portions of the second mold layer 114 exposed through the first to third mask holes 122a to 122c, and also to remove portions of the support layer 112 below the removed second mold layer 114. As a result, the top surface of the first mold layer 110 may be exposed through the resulting openings, and at the same time, the support pattern 112 may be formed to include Figure 1 The first supporting hole 1a to the third supporting hole 1c.

[0049] Reference Figure 1 and 3 , the second mask pattern 120 may be removed to expose some of the side surfaces of the bottom electrodes BE and DBE, the top of the remaining portion of the second mold layer 114, and the top surface of the first mold layer 110. The isotropic etching process may be performed to completely remove the first and second mold layers 110 and 114 to expose the top and side surfaces of the bottom electrodes BE and DBE, the top surface of the etch stop layer 108, and the top, bottom, and side surfaces of the support pattern 112, for example. Figure 3 A portion of the support pattern 112 having a side surface exposed through the support hole is shown. In this step, the support pattern 112 contacts the upper portion of the side wall of the bottom electrodes BE and DBE, for example, connecting adjacent bottom electrodes of the bottom electrodes BE and DBE to prevent the collapse of the bottom electrodes BE and DBE. Since the support holes 1a to 1c partially expose the side surfaces of all the actual bottom electrodes BE, the etchant or etching gas can be provided toward the side surfaces of all the actual bottom electrodes BE through the support holes 1a to 1c. Therefore, regardless of the position in the actual cell area A, the first mold layer 110 and the second mold layer 114 can be completely removed, for example, with a uniform concentration distribution or etching rate near the side surface of the actual bottom electrode BE. Therefore, some of the actual bottom electrodes BE can be prevented from being excessively damaged.

[0050] The dielectric layer 124 may conformally cover the exposed surfaces of the support pattern 112 and the exposed surfaces of the bottom electrodes BE and DBE, and the top electrode TE may be sequentially formed on the dielectric layer 124. Therefore, a semiconductor device may be manufactured to have high integration and reliability.

[0051] As a summary and review, the embodiments provide a highly integrated semiconductor device. That is, in the semiconductor device according to the exemplary embodiment, the support pattern supporting the bottom electrode may include support holes having shapes different from each other. As such, the support holes may be exposed to the side surfaces of all actual bottom electrodes used as memory on the actual cell area without extending into the dummy cell area. In addition, since the support holes are all formed in the actual cell area, the width of the support pattern does not need to extend toward the peripheral circuit area. In addition, the support holes can be used to selectively remove the mold layer without damage to the bottom electrode. The dielectric layer and the top electrode can be formed to have a uniform thickness on the actual cell area. Therefore, it can be achieved that the semiconductor device is manufactured to have high integration and reliability.

[0052] Example embodiments have been disclosed herein, and although specific terms are used, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art at the time of filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with another embodiment, unless otherwise expressly indicated. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

[0053] Korean Patent Application No. 10-2016-0163751, entitled “Semiconductor Device Including Support Pattern,” filed on December 2, 2016 in the Korean Intellectual Property Office, is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device, comprising: a plurality of pillar structures on a semiconductor substrate, the semiconductor substrate comprising a cell region and a dummy region; as well as a supporting pattern in contact with at least a portion of each of the plurality of column structures, the supporting pattern connecting the plurality of column structures to each other, wherein the support pattern comprises support holes exposing side surfaces of the plurality of column structures, the support holes comprising at least one second support hole and a plurality of first support holes spaced apart from each other, the first support hole having a circular cross-section in a top view and the second support hole having a shape different from that of the first support hole, wherein the plurality of first supporting holes are disposed in the unit area and at least in a central portion of the unit area, and the at least one second supporting hole is only in an edge portion of the unit area, wherein each of the plurality of first supporting holes exposes the side surfaces of three adjacent column structures among the plurality of column structures, and The second supporting hole exposes the side surfaces of four to seven adjacent column structures among the plurality of column structures. 2 . The semiconductor device according to claim 1 , wherein the supporting hole further comprises a third supporting hole having a shape different from shapes of the first supporting hole and the second supporting hole.

3. The semiconductor device according to claim 1, wherein each of the plurality of pillar structures has a circular cross-section in a top view, and the support hole has a circular cross-section or a polygonal cross-section in a top view, and the cross-section of each of the support holes is defined by connecting the center points of the circular cross-sections of the plurality of pillar structures. 4 . The semiconductor device according to claim 1 , wherein the plurality of pillar structures are spaced apart from each other at the same interval, and six pillar structures surrounding each of the plurality of pillar structures constitute a honeycomb shape.

5. The semiconductor device according to claim 1, wherein: The plurality of pillar structures include a storage pillar structure on the cell region and a dummy pillar structure on the dummy region, and only the storage pillar structure among the plurality of pillar structures performs a storage function; and The supporting holes expose side surfaces of all the storage pillar structures. The semiconductor device according to claim 5 , wherein the supporting hole is on the cell region. 7 . The semiconductor device according to claim 5 , wherein at least one of the dummy pillar structures is on the cell region and has a side surface exposed through the supporting hole.

8. The semiconductor device according to claim 5, wherein: The plurality of first supporting holes have the same shape as each other, and A total number of the plurality of first supporting holes is greater than a total number of the at least one second supporting hole.

9. The semiconductor device according to claim 8, wherein: The plurality of first support holes have a circular cross-section in a top view, a perimeter of each circular cross-section extending through a center point of a cross-section of a column structure exposed through the plurality of first support holes in a top view, and The at least one second supporting hole has a polygonal cross-section in a top view, and a perimeter of the polygonal cross-section extends through a center point of a cross-section of the column structure exposed through the at least one second supporting hole in a top view. 10 . The semiconductor device according to claim 1 , wherein each of the plurality of pillar structures is a bottom electrode and has a plug shape or a cup shape.

11. The semiconductor device according to claim 1, further comprising: a dielectric layer conformally covering a surface of the support pattern and a surface of the plurality of pillar structures; as well as A top electrode is on the dielectric layer.

12. A semiconductor device comprising: a plurality of pillar structures on a semiconductor substrate, the semiconductor substrate comprising a cell region and a dummy region; as well as a supporting pattern in contact with at least a portion of each of the plurality of column structures, the supporting pattern connecting the plurality of column structures to each other, wherein the support pattern comprises support holes exposing side surfaces of the plurality of column structures, the support holes comprising a plurality of first support holes and at least one second support hole spaced apart from each other, wherein the plurality of first support holes have a circular cross-section in a top view and the at least one second support hole has a shape different from the shape of the plurality of first support holes, wherein the supporting hole is on the unit area, wherein each of the plurality of first supporting holes exposes the side surfaces of three adjacent column structures among the plurality of column structures, and The at least one second supporting hole is only at an edge portion of the unit area, and the second supporting hole exposes the side surfaces of adjacent four to seven column structures among the plurality of column structures. 13 . The semiconductor device according to claim 12 , wherein the plurality of pillar structures are spaced apart from each other at the same interval, and six pillar structures surrounding each of the plurality of pillar structures form a honeycomb shape.

14. A semiconductor device comprising: a plurality of electrode columns on a semiconductor substrate; as well as a supporting pattern in contact with at least a portion of each of the plurality of electrode pillars, the supporting pattern connecting the plurality of electrode pillars to each other, wherein the support pattern includes support holes passing therethrough, the support holes including a plurality of first support holes and at least one second support hole spaced apart from each other, the first support holes and the second support holes having shapes different from each other in a top view, the plurality of first support holes having a circular cross-section in a top view, wherein the total number of the plurality of first supporting holes is greater than the total number of the at least one second supporting hole, wherein each of the plurality of first supporting holes exposes side surfaces of three adjacent electrode columns among the plurality of electrode columns, and The second supporting hole exposes side surfaces of four to seven adjacent electrode columns among the plurality of electrode columns. 15 . The semiconductor device according to claim 14 , wherein the semiconductor substrate comprises a cell region and a dummy region, the supporting pattern overlaps the cell region and the dummy region, and the supporting hole overlaps only the cell region. 16 . The semiconductor device according to claim 15 , wherein the at least one second supporting hole is at an edge of the cell region.

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