subgraphs in the frequency domain and dynamic selection of convolution implementations on the gpu

Abstract

The invention relates to subgraphs in the frequency domain and dynamic selection of convolution implementations on GPUs. In an example, an apparatus comprises a plurality of execution units; and logic, at least partially comprising hardware logic, to determine a subgraph of a network that can be executed in the frequency domain and to apply computations in the frequency domain in the subgraph. Other embodiments are also disclosed and claimed.

Description

TECHNICAL FIELD

[0001] Embodiments relate generally to data processing, and more particularly to machine learning processing via general purpose graphics processing units. BACKGROUND

[0002] Machine learning has achieved success in solving many kinds of tasks. The computations that arise in training and using machine learning algorithms (e.g., neural networks) lend themselves naturally to efficient parallel implementations. As a result, parallel processors such as general purpose graphics processing units (GPGPUs) have played an important role in the practical implementation of deep neural networks. Parallel graphics processors with single instruction multiple thread (SIMT) architectures are designed to maximize the amount of parallel processing in a graphics pipeline. In a SIMT architecture, groups of parallel threads attempt to execute program instructions together as often as possible to increase processing efficiency. The efficiency provided by parallel machine learning algorithm implementations allows for the use of high-capacity networks and enables those networks to be trained on larger data sets. BRIEF DESCRIPTION OF DRAWINGS

[0003] In the following description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration various embodiments of the present application. It is to be understood that other embodiments can be utilized and structural or

[0004] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein.

[0005] Figures 2A-2D illustrates a parallel processor component, according to an embodiment.

[0006] Figures 3A-3B is a block diagram of a graphics multiprocessor, according to an embodiment.

[0007] Figures 4A-4F illustrates an exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi-core processors.

[0008] Figure 5 is a conceptual diagram of a graphics processing pipeline, according to an embodiment.

[0009] Figures 6A-6B and 7A-7E illustrate exemplary architectures and operations in the techniques in accordance with embodiments.

[0010] Figure 8 illustrates a machine learning software stack, according to an embodiment.

[0011] Figure 9FIG. illustrates a highly parallel general purpose graphics processing unit, in accordance with an embodiment.

[0012] Figure 10 FIG. illustrates a multi-GPU computing system, in accordance with an embodiment.

[0013] Figure 11A FIG. -B illustrates layers of an exemplary deep neural network.

[0014] Figure 12 FIG. illustrates an exemplary recurrent neural network.

[0015] Figure 13 FIG. illustrates training and deployment of a deep neural network.

[0016] Figure 14 FIG. is a block diagram illustrating distributed learning.

[0017] Figure 15 FIG. illustrates an exemplary inference system on chip (SOC) suitable for performing inference using a trained model.

[0018] Figure 16 FIG. is a block diagram of a processing system, in accordance with an embodiment.

[0019] Figure 17 FIG. is a block diagram of a processor, in accordance with an embodiment.

[0020] Figure 18 FIG. is a block diagram of a graphics processor, in accordance with an embodiment.

[0021] Figure 19 FIG. is a block diagram of a graphics processing engine of a graphics processor, in accordance with some embodiments.

[0022] Figure 20 FIG. is a block diagram of a graphics processor, provided by an additional embodiment.

[0023] Figure 21 FIG. illustrates thread execution logic including an array of processing elements employed in some embodiments.

[0024] Figure 22 FIG. is a block diagram illustrating a graphics processor instruction format, in accordance with some embodiments.

[0025] Figure 23 FIG. is a block diagram of a graphics processor, in accordance with another embodiment.

[0026] Figures 24A-24B FIG. illustrates graphics processor command formats and command sequences, in accordance with some embodiments.

[0027] Figure 25 FIG. illustrates an exemplary graphics software architecture for a data processing system, in accordance with some embodiments.

[0028] Figure 26 is a block diagram illustrating an IP core development system in accordance with an embodiment.

[0029] Figure 27 is a block diagram illustrating an exemplary system-on-a-chip integrated circuit in accordance with an embodiment.

[0030] Figure 28 is a block diagram illustrating an additional exemplary graphics processor.

[0031] Figure 29 is a block diagram illustrating an additional exemplary graphics processor of a system-on-a-chip integrated circuit in accordance with an embodiment. DETAILED DESCRIPTION

[0032] In the following description, numerous specific details are set forth to provide a thorough understanding of various embodiments. However, various embodiments can be practiced without the specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the particular embodiments. Further, various aspects of embodiments can be performed by various means, such as integrated semiconductor circuits ("hardware"), computer-readable instructions ("software"), or some combination of hardware and software. For the purpose of this disclosure, reference to "logic" shall mean either hardware, software, firmware, or some combination of hardware and software.

[0033] Some embodiments discussed herein can be applied in any processor, such as a GPCPU, CPU, GPU, etc., graphics controller, etc. Other embodiments are also disclosed and claimed.

[0034] Further, some embodiments can be applied in a computing system including one or more processors, such as those discussed herein, including, for example, mobile computing devices, such as smartphones, tablets, UMPCs (Ultra Mobile Personal Computers), laptop computers, ultrabooks TM computing devices, wearable devices, such as smartwatches or smartglasses, etc.

[0035] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to the host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / cores over a bus or another interconnect (e.g., a high-speed

[0036] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one of skill in the art that embodiments described herein can be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the details of the embodiments of the present application.

[0037] System Overview

[0038] Figure 1 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processor(s) 102 and a system memory 104 communicating via an interconnection path 1 15 that can include a memory hub 105. The memory hub 105 can be a separate component coupled with the processor(s) 102 via the interconnection path 1 15, or can be integrated within the one or more processor(s) 102. The memory hub 105 couples with the system memory 104 via the communication link 106 to provide memory access and memory

[0039] In one embodiment, processing subsystem 101 includes one or more parallel processor(s) 112 coupled to memory hub 105 via a bus or other communication link 113. Communication link 113 can be one of any number of standards-based communication links, such as a PCI Express, or can be a supplier- proprietary communication interface or communication structure. In one embodiment, one or more parallel processor(s) 112 form a computationally-intensive, parallel, or vector processing system that can include a number of processor cores, each with its own memory, cache, bus controller, or processor core la nding. In one embodiment, one or more parallel processor(s) 112 form a graphics processing subsystem that can output pixels to one or more display device(s) 110A coupled via I / O hub 107. The one or more parallel processor(s) 112 can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s) 110B.

[0040] Within I / O subsystem 111, system storage unit 114 can connect to I / O hub 107 to provide storage

[0041] Computing system 100 can include other components not explicitly shown, including USB or other port connections, an optical storage device, a video capture device, etc., which can also be connected to I / O hub 107. Communication paths interconnecting the various Figure 1 components in computing system 100 can include any suitable connections, including optical and / or electrical connections. Communication paths can convey both data and / or power. In one embodiment, the

[0042] In one embodiment, the one or more parallel processors 112 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU). In another embodiment, the one or more parallel processors 112 incorporate circuitry optimized for general-purpose processing while maintaining the underlying computing architecture described in more detail herein. In yet another embodiment, components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processors 112, memory hub 105, processor(s)102, and I / O hub 107 may be integrated into a system-on-a-chip (SoC) integrated circuit. Alternatively, components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may interconnect with other multi-chip modules to form a modular computing system.

[0043] It will be understood that the computing system 100 shown herein is illustrative and variations and modifications are possible. The connectivity topology can be modified as desired, including the number and arrangement of bridges, the number of processors(102), and the number of parallel processors(112). For example, in some embodiments, system memory 104 is connected directly to processors(102) rather than via bridges, while other devices communicate with system memory 104 via memory hub 105 and processors(102). In other alternative topologies, parallel processors(112) are connected to I / O hub 107 or directly to one of the processors(102), rather than to memory hub 105. In other embodiments, I / O hub 107 and memory hub 105 may be integrated into a single chip. Some embodiments may include two or more sets of processors(102) attached via multiple sockets, which may be coupled to two or more instances of parallel processors(112).

[0044] Some of the specific components shown in this document are optional and may not be included in all implementations of the computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. Furthermore, some architectures may use different terminology with... Figure 1 The components shown in the diagram are similar to those in the diagram. For example, in some architectures, the memory hub 105 may be referred to as the Northbridge, while the I / O hub 107 may be referred to as the Southbridge.

[0045] Figure 2AA parallel processor 200 is shown in accordance with an embodiment. Various components of the parallel processor 200 can be implemented using one or more integrated circuits, such as programmable processor, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). The illustrated parallel processor 200 is a parallel processor 112 of the type shown in FIG. 1, according to an embodiment. Figure 1 Variations of the one or more parallel processors 112 shown in FIG. 1 are possible.

[0046] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices including other instances of the parallel processing unit 202. The I / O unit 204 can be directly connected to the other devices. In one embodiment, the I / O unit 204 connects with other devices via the use of a hub or switch interface, such as the memory hub 105. The connections between the memory hub 105 and the I / O unit 204 form communication links 113. Within the parallel processing unit 202, the I / O unit 204 connects with a host interface 206 and a memory crossbar switch 216, where the host interface 206 receives commands required to carry out processing tasks and the memory crossbar switch 216 facilitates communication between the parallel processing unit 202 and the memory array 212.

[0047] When the host interface 206 receives a command buffer from the I / O unit 204, the host interface 206 can direct the work operations required to execute those commands to the front end 208. In one embodiment, the front end 208 is coupled with a scheduler 210 that is configured to distribute the commands or other work items to the processing clusters array 212. In one embodiment, the scheduler 210 ensures that the processing clusters array 212 is properly configured and in an active state before tasks are distributed to the processing clusters of the processing clusters array 212.

[0048] The processing clusters array 212 can include up to "N" processing clusters (e.g., cluster 214A, 214B through 214N). Each cluster 214A-214N of the processing clusters array 212 can execute a large number of concurrent threads. The scheduler 210 can use various scheduling and / or work distribution algorithms to allocate work to the clusters 214A-214N of the processing clusters array 212, which can vary depending on the workload generated by each type of program or computation. The scheduling can be handled dynamically by the scheduler 210, or can be assisted in part by compiler logic during the compilation of program logic configured for execution by the processing clusters array 212. In one embodiment, different clusters 214A-214N of the processing clusters array 212 can be allocated for processing different types of programs or for performing different types of computations.

[0049] The processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general-purpose parallel compute operations. For example, the processing cluster array 212 can include logic to perform processing tasks comprising filtering of video and / or audio data, performing modeling operations that include physics operations, and performing data transformations.

[0050] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In an embodiment in which the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 can include additional logic to support the execution of such graphics processing operations, including without limitation texture mapping logic to perform texture mapping operations associated with 3D graphics, and surface rendering logic and other vertex processing logic to perform surface rendering operations associated with 3D graphics. Further, the processing cluster array 212 can be configured to execute graphics processing-related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 can transfer data from the system memory to the processing cluster array 212 for processing via the I / O unit 204. During processing, the transferred data can be stored to on-chip memory (e.g., parallel processor memory 222) for processing, then written back to system memory after processing is complete.

[0051] In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 can be configured to divide the processing workload into approximately equal sized tasks, to better enable distribution of the graphics processing operations across multiple clusters 214A-214N of the processing cluster array 212. In some embodiments, portions of the processing cluster array 212 can be configured to perform different types of processing. For example a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform surface

[0052] During operation, the processing cluster array 212 can receive processing tasks to be performed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing task can include data to be processed (e.g., surface (patch) data, primitive data, vertex data, and / or pixel data), and state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). The scheduler 210 can be configured to fetch the indices of the commands or can receive the indices from the front end 208. The front end 208 can be configured to ensure the processing cluster array 212 is configured to an active state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0053] Each of the one or more instances of the parallel processing unit 202 can be coupled with a parallel processor memory 222. The parallel processor memory 222 can be accessed via a memory crossbar 216, which can receive memory requests from the processing cluster array 212 as well as the I / O unit 204. The memory crossbar 216 can access the parallel processor memory 222 via a memory interface 218. The memory interface 218 can include a number of partition units (e.g., partition unit 220A, partition unit 220B, through partition unit 220N) that each can be coupled to a portion (e.g., memory unit) of the parallel processor memory 222. In one implementation, the number of partition units 220A-220N is configured to be equal to the number of memory units, such that the first partition unit 220A has a corresponding first memory unit 224A, the second partition unit 220B has a corresponding memory unit 224B, and the Nth partition unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partition units 220A-220N can not be equal to the number of memory devices.

[0054] In various embodiments, memory units 224A-224N can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory units 224A-224N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of memory units 224A-224N can vary and can be selected from one of a variety of conventional designs. Render targets such as frame buffers or texture maps can be stored across memory units 224A-224N, allowing partition units 220A-220N to write portions of each render target in parallel for efficient use of the available bandwidth of parallel processor memory 222. In some embodiments, local instances of parallel processor memory 222 can be excluded, to support a unified memory design that utilizes system memory in combination with local cache memory.

[0055] In one embodiment, any of clusters 214A-214N of processing cluster array 212 can process data to be written to any of memory units 224A-224N within parallel processor memory 222. Memory crossbar 216 can be configured to communicate the output of each cluster 214A-214N to any partition unit 220A-220N or another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate through memory crossbar 216 with memory interface 218 to read from or write to various external memory devices. In one embodiment, memory crossbar 216 has a connection to memory interface 218 to communicate with I / O unit 204, and a connection to a local instance of parallel processor memory 222, to enable the processing units within the different processing clusters 214A-214N to communicate with system memory or other memories not local to the parallel processing units 202. In one embodiment, memory crossbar 216 can use virtual channels to separate traffic streams between clusters 214A-214N and partition units 220A-220N.

[0056] While a single instance of a parallel processing unit 202 is illustrated within parallel processor 200, any number of instances of parallel processing unit 202 can be included. For example, a multiplicity of parallel processing units 202 can be provided on a single add-in card, or multiple add-in cards can be interconnected. Even if different instances of parallel processing unit 202 are provided in different quantities, configurations, and / or combinations, they can be configured to interoperate, e.g., via

[0057] Figure 2B is a block diagram of a partition unit 220 according to an embodiment. In one embodiment, partition unit 220 is an instance of one of partition units 220A-220N of Figure 2A As illustrated, partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and an ROP 226 (raster operations unit). L2 cache 221 is a read / write cache that is configured to perform load and store operations received from memory crossbar 216 and ROP 226. L2 cache 221 outputs read misses and urgent write-back requests to frame buffer interface 225 for processing. Dirty updates can also be sent to a frame buffer via frame buffer interface 225 for opportunistic processing. In one embodiment, frame buffer interface 225 interfaces with one of the memory units in the parallel processor memory, such as memory units 224A-224N of FIG. 2 (e.g., within parallel processor memory 222).

[0058] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stencil, z-test, blending, and so forth. ROP 226 then outputs processed graphics data that is stored in graphics memory. In some embodiments, ROP 226 includes compression logic to compress z or color data that is written to memory and decompress z or color data read from memory. In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A-214N of FIG. 2) rather than in partition unit 220. In such embodiments, read and write requests for pixel data are transmitted through memory crossbar 216 rather than pixel fragment data. Processed graphics data can be displayed on a display device that is either local to or remote from parallel processor 200. Figure 1on one or more display devices 110, routed for further processing by processor(s) 102, or routed for further processing by one of the processing entities within parallel processor 200. Figure 2A

[0059] Figure 2C is a block diagram of a processing cluster 214 within a parallel processing unit of an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A-214N of FIG. 2. A processing cluster 214 can be configured to execute a plurality of threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In some embodiments, single-instruction-multiple-data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads on a single instruction word (SIMW). In other embodiments, single-instruction-multiple-thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronous threads using a common instruction word. In these embodiments, a common instruction word is issued to each of the processing cores within a processing cluster, and each processing core (or thread) can be configured to operate on different data sets using the same thread program. In some embodiments, a thread program can be written in a high-level programming language, and compiled into a form suitable for use by the parallel processor 200. For example, in some embodiments, a program written in a high-level language can be compiled into a form containing one or more instruction work items, where each instruction work item is suitable for execution by a separate processing cluster within parallel processor 200.

[0060] Operation of a processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to SIMT parallel processor. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages execution of those instructions via a graphics multiprocessor 234 and / or a texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of differing architectures can be included within a processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included within a processing cluster 214. The graphics multiprocessor 234 can process data and a data crossbar 240 can be used to distribute the processed data to one of multiple possible destinations. The pipeline manager 232 can facilitate distribution by specifying destinations for processed data to be distributed via the data crossbar 240.

[0061] ​Each graphics multiprocessor 234 within processing cluster 214 can include a set of identical functional execution units (e.g., arithmetic logic units, load-store units, etc.). The functional execution units can be configured in a pipelined manner in which instructions can be issued at one execution unit openseal while other execution units are in a staging, queuing, and retrieving of instructions. The functional execution units support a variety of operations including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and compute operations. In one embodiment, the same functional-unit hardware can be leveraged to perform different operations using different code and configurations.

[0062] The instructions transmitted to the processing cluster 214 form a thread. A set of threads executed by a collection of parallel processing engines forms a thread group. A thread group is assigned to a single data element in a SIMD operation. Each thread within the thread group can be assigned to a different processing engine within the graphics multiprocessor 234. The thread group can include fewer threads than there are processing engines within the graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines can be idle during the period that the thread group is processing. A thread group can also include more threads than there are processing engines within the graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within the graphics multiprocessor 234, multiple threads within the thread group can be assigned to single processing engines within the graphics multiprocessor 234. In one embodiment, a plurality of thread groups are in process on the graphics multiprocessor 234.

[0063] In one embodiment, the graphics multiprocessor 234 includes an internal cache. In one embodiment, the graphics multiprocessor 234 can abandon the internal cache and use the cache within the processing cluster 214 (e.g., the LI cache 308). Each graphics multiprocessor 234 is also able to access the L2 cache in a partition unit (e.g., partition units 220A-220N of FIG. 2) shared between all the processing clusters 214 and can be used to transfer data between threads. The graphics multiprocessor 234 can also access the off-chip global memory, which can include one or more of a local parallel processor memory and / or a system memory. Any memory external to the parallel processor 202 can be used as global memory. Embodiments where the processing cluster 214 includes multiple instances of the graphics multiprocessor 234 can share common instructions and data stored in the LI cache 308.

[0064] Each processing cluster 214 can include an MMU 245 (memory management unit) configured to translate virtual addresses into physical addresses. In other embodiments, one or more instances of the MMU 245 can reside within the memory interface 218 of FIG. 2. The MMU 245 includes a set of page table entries (PTEs) used to translate virtual addresses into physical addresses at a granularity of tiles (e.g., 64 bytes or 4 cache lines). The MMU 245 can include address translation lookaside buffers (TLBs) or caches to improve translation speed. The TLBs or caches can reside within the graphics processor 234 or the Ll cache or processing cluster 214.

[0065] In graphics and compute applications, the processing cluster 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. Texture data can be obtained from an internal texture Ll cache (not shown), or in some embodiments, from the Ll cache within the graphics multiprocessor 234, or, in some embodiments, from the L2 cache, local parallel processor memory, or system memory, as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 that couples to another processing cluster 214 for further processing or to a memory crossbar 216 for processing different tasks, or storage in an L2 cache, local parallel processor memory, or system memory. A preROP 242 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 234, direct data to a ROP unit which can be part of or coupled to a partition unit (e.g., partition unit 220A-220N of FIG. 2) as described herein. The preROP 242 unit can perform optimizations to minimize or eliminate bandwidth usage (bandwidth usage is the consumption of bandwidth of any sort, e.g., memory bandwidth or bus bandwidth), organize pixel color data, and perform address translations.

[0066] It will be appreciated that the core architecture described herein is illustrative and that variation and modification are possible. Any number of processing units, e.g., graphics multiprocessors 234, texture units 236, preROP 242, etc., can be included within a processing cluster 214. Further, while only one processing cluster 214 is illustrated, any number of parallel processing units can be included in the parallel processor as described herein. In one embodiment, each processing cluster 214 can be configured to operate independently of the other processing clusters 214 using separate and distinct processing units, Ll caches, etc.

[0067] Figure 2DA graphics multiprocessor 234 according to one embodiment is shown. In such embodiments, the graphics multiprocessor 234 is coupled with the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, without limitation, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled with a memory and cache interconnect 268 to a shared memory 270 and a shared cache 272.

[0068] In one embodiment, the instruction cache 252 receives a stream of instructions to execute from the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 can dispatch instructions as thread groups (e.g., warps) of instructions to execute on the GPGPU cores 262, with each thread group assigned to a different execution unit of the GPGPU cores 262. Instructions can access the local, shared, or global address spaces by specifying an address in the universal address space. The address mapping unit 256 can be used to convert an address in the universal address space to an address in a different memory address space that can be accessed by the load / store units 266.

[0069] The register file 258 provides a set of registers to the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for the data operands used by the data paths connected to the functional units (e.g., GPGPU cores 262, load / store units 266) of the graphics multiprocessor 324. In one embodiment, the register file 258 is divided into a set of registers specific for each of the functional units. In one embodiment, the register file 258 is divided into a set of registers specific for each of the different thread warps being executed by the graphics multiprocessor 324.

[0070] The GPGPU cores 262 can each include floating point, integer, and / or single instruction multiple data (SIMD) execution units supporting a variety of instruction sets, including the x86, ARM, and / or MIPS instruction sets. The GPGPU cores 262 can also include special function units (SFUs) including, for example, a video mipmap surface (VMS) unit, a video blitting unit, and / or a video codec unit. The GPGPU cores 262 can be similar to the GPGPU cores 262 described herein.

[0071] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics processing engine 320 to the register file 258 and shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect network that allows loads and stores from the load / store units 266 to be executed in parallel with memory operations. The register file 258 can operate at similar frequencies as the GPGPU cores 262, such that data transfer between the GPGPU cores 262 and the register file 258 is performed at low latency. The shared memory 270 can be used to enable fast global access to memory for threads being executed on the GPGPU cores 262. The shared memory 270 can also be used for shared memory address spaces for threads in a SIMD fashion, where each thread in the SIMT group is configured to execute identical instructions. In one embodiment, the shared memory 270 is on-chip memory. In another embodiment, the shared memory 270 is off-chip.

[0072] Figures 3A-3B Additional graphics processing engines according to embodiments are illustrated. The illustrated graphics processing engines 325, 350 are variants of the graphics processing engine 234 of Figure 2C The illustrated graphics processing engines 325, 350 can be configured as a streaming multiprocessor (SM) capable of executing a large number of execution threads in parallel.

[0073] Figure 3A A graphics processing engine 325 according to an additional embodiment is shown. The graphics processing engine 325 includes a number of the processing clusters 330 to perform graphics and / or compute operations. In one embodiment, the processing clusters 330 execute instructions to perform graphics and compute operations. The graphics processing engine 325 can also include shared memory coupling to the processing clusters 330. In one embodiment, shared memory is used to share the processing clusters' 330 data. The shared memory can be used by each of the processing clusters 330 to store and / or load data that other processing clusters 330 can access. Figure 2DThe graphics multiprocessor 234 can include multiple execution units 232A- 232B to perform integer and floating-point operations. The execution units 232A- 232B can also include support for single and double-precision integer and floating point data operations. The graphics multiprocessor 234 can further include one or more samplers 234A-234B for sampling of textures or images. The graphics multiprocessor 234 can also include one or more special function units 235A-235B to perform special mathematical functions such as trigonometric, square root, and other logarithmic and exponential functions. The various execution units, samplers, and special function units can be implemented using a variety of different architectures.

[0074] Figure 3B A graphics multiprocessor 350 is shown according to an additional embodiment. The graphics processor includes a plurality of sets of execution resources 356A- 356D, where each set of execution resources includes a plurality of instruction units, register file, GPGPU cores, and load store units as illustrated in Figure 2D and Figure 3A The execution resources 356A-356D can work in concert with the texture units 360A-360D for texture operations, while sharing the instruction cache 354 and shared memory 362. In one embodiment the execution resources 356A-356D can share the instruction cache 354 and shared memory 362, as well as multiple instances of the texture and / or data caches 358A-358B. The various components can communicate via an interconnect 352 similar to the interconnect 327 of Figure 3A .

[0075] Those of skill in the art will appreciate that Figure 1 , 2A The architectures described in 2D and 3A-3B are descriptive, rather than limiting, of the scope of embodiments of the present application. Thus, the techniques described herein can be implemented on any appropriately configured processing unit, including but not limited to one or more mobile application processors, one or more desktop computer or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units such as the parallel processing unit 202 of FIG. 2, and one or more graphics processors or specialized processing units, without departing from the scope of the embodiments described herein.

[0076] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate tasks for the host / processor. The GPU can be a discrete GPU (dGPU) that is communicatively coupled to a motherboard via a bus or other interconnect (e.g., PCIe, NVLink, etc.). Alternatively, the GPU can be integrated on the same package or chip as the processor core(s) (i.e., a system on a chip or SoC) and communicatively coupled to internal on-chip memory (i.e., within the same package or chip) via an internal processor bus / interconnect. In either implementation, the processor core(s) can allocate tasks to the GPU for processing and the GPU can execute those tasks using its own circuitry / logic. In one embodiment, the GPU can include many cores that are used to perform processing tasks for graphics processing, machine learning processing, pattern analysis processing, and a variety of other processing that can be performed on the GPU. The core(s) can be configured to execute many more threads in parallel than a typical processor core, enabling the GPU to be used for general-purpose computing.

[0077] Techniques for GPU to Host Processor Interconnect

[0078] Figure 4A FIG. 12 illustrates an exemplary architecture in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 over high-speed links 440-443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, high-speed links 440-443 support communication at a throughput level of 4GB / s, 30GB / s, 80GB / s or higher, depending on the implementation. Various interconnect protocols can be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the application are not limited to any particular communication protocol or throughput level.

[0079] In addition, in one embodiment, two or more of GPUs 410-413 are interconnected over high-speed links 444-445, which can be implemented using the same or different protocol / links as those used for high-speed links 440-443. Similarly, two or more of multi-core processors 405-406 can be connected by high-speed link 433, which can be a Symmetric Multi-Processor (SMP) bus operating at 20GB / s, 30GB / s, 120GB / s or higher. Alternatively, Figure 4A All communication between the various system components illustrated in FIG. 12 can be accomplished using the same protocol / links (e.g., over a common interconnect fabric). However, as mentioned, the underlying principles of the application are not limited to any particular type of interconnect technology.

[0080] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memories 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memories 420-423 through GPU memory interconnects 450-453, respectively. Memory interconnects 430-431 and 450-453 can utilize the same or different memory access technologies. By way of example and not limitation, processor memories 401-402 and GPU memories 420-423 can be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the memory can be volatile memory and another portion can be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0081] As described below, although various processors 405-406 and GPUs 410-413 can be physically coupled to particular memories 401-402, 420-423, respectively, a unified memory architecture can be implemented in which the same virtual system address space (also referred to as "effective address" space) is distributed across all of the various physical memories. For example, processor memories 401-402 can each include 64 GB of system memory address space, and GPU memories 420-423 can each include 32 GB of system memory address space (resulting in a total of 256 GB of addressable memory in this example).

[0082] Figure 4B Additional details of the interconnect between multi-core processor 407 and graphics acceleration module 446 are illustrated in accordance with one embodiment. Graphics acceleration module 446 can comprise one or more GPU chips integrated on a line card that is coupled to processor 407 via high-speed link 440. Alternatively, graphics acceleration module 446 can be integrated on the same package or chip as processor 407.

[0083] The illustrated processor 407 includes multiple cores 460A-460D each with a translation lookaside buffer 461 A-461 D and one or more caches 462A-462D. The cores can include various other components for executing instructions and processing data not illustrated, such as instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc., which are not illustrated to avoid obscuring the principles of the application. The caches 462A-462D can include level one (Ll) and level two (L2) caches. In addition, one or more shared caches 426 can be included in the cache hierarchy and shared by the set of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores each with its own Ll cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 caches and L3 caches are shared by two adjacent cores. The processor 407 and graphics accelerator integrated module 446 are connected with system memory 441, which can include processor memories 401-402.

[0084] Consistency for data and instructions stored in the various caches 462A-462D, 456 and system memory 441 is maintained via inter-core communication over the coherence bus 464. For example, each cache can have cache coherency logic / circuitry associated with it to communicate over the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snoop protocol is implemented over the coherence bus 464 to snoop cache accesses. Cache snoop / coherency techniques are well understood by those skilled in the art, and will not be described in detail here to avoid obscuring the principles of the application.

[0085] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer to the cores. Specifically, the interface 435 provides connectivity to the proxy circuit 425 over a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the link 440.

[0086] In one implementation, the accelerator integration circuit 436 provides cache management, memory access, context management, and interrupt management services for a number of graphics processing engines 431, 432, N of the graphics acceleration module 446. The graphics processing engines 431, 432, N can each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N can comprise different types of graphics processing engines within a GPU such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and bitblitz engines. In other words, the graphics acceleration module can be a GPU with a number of graphics processing engines 431-432, N or the graphics processing engines 431-432, N can be individual GPUs integrated on a common package, line card, or chip.

[0087] In one embodiment, the accelerator integration circuit 436 includes a memory management unit (MMU) 439 to provide for translation of virtual addresses into physical addresses, supply register information for memory access operations implemented by the graphics acceleration module 446, and supply permission information to carry out memory access operations. The MMU 439 could be a part of the accelerator integration circuit 436 or a separate component altogether. In one embodiment, the MMU 439 includes memory management translation tables to provide translations between virtual addresses used by the graphics processing engines 431-432, N and physical addresses used by the system 400. In one embodiment, the MMU 439 includes memory management translation tables to provide translations between virtual addresses used by the graphics processing engines 431-432, N and physical addresses used by the system 400. In another embodiment, the MMU 439 includes memory management translation tables to provide translations between virtual addresses used by the graphics processing engines 431-432, N and physical addresses used by the system 400. The memory management translation tables can be stored in on-chip memory blocks, off-chip in system memory, or some combination of on-chip and off-chip memory. In one embodiment, the memory management translation tables can include stage 1 translation tables that provide translations from virtual address to stage 2 translation table index, and stage 2 translation tables that provide translations from stage 2 translation table index to physical address. In another embodiment, the memory management translation tables can include stage 1 translation tables that provide translations from virtual address to physical address.

[0088] A set of registers 445 store program counter values and other context settings (e.g., processor mode) for each of the graphics processing engines 431-432, N. In one embodiment, the graphics processing engines 431-432, N share the set of registers 445. In another embodiment, the graphics processing engines 431-432, N each have a separate set of registers 445. Context management circuitry 448 manages context storage that is shared by each of the graphics processing engines 431-432, N. In one embodiment, the context storage includes a set of registers 445 that store program counter values and other context settings for each of the graphics processing engines 431-432, N. In one embodiment, the context management circuitry 448 manages execution of a first thread by a first graphics processing engine 431 and execution of a second thread by a second graphics processing engine 432 during a context switch. In one embodiment, the context management circuitry 448 saves the current state of the first thread, switches to the second thread, and restores the state of the second thread to the set of registers 445. In another embodiment, the context management circuitry 448 saves the current state of the first thread, switches to the second thread, and restores the state of the second thread to a separate set of registers 445.

[0089] In one implementation, virtual / effective addresses from the graphics processing engines 431 are translated to real / physical addresses in system memory 411 by the MMU 439. One embodiment of the accelerator integration circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator modules 446 can be dedicated to a single application executing on the processor 407 or can be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which resources of the graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). The resources can be subdivided into“slices” that are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0090] Thus, the accelerator integration circuit functions as a bridge to the system of the graphics acceleration module 446 and provides address translation and system memory cache services. In addition, the accelerator integration circuit 436 can provide virtualization facilities for the host processor to manage virtualization of graphics processing engines, interrupts, and memory management.

[0091] Because the hardware resources of the graphics processing engines 431-432, N are explicitly mapped to the real address space seen by the host processor 407, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integration circuit 436 is the physical separation of the graphics processing engines 431-432, N so that they appear as independent units to the system.

[0092] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are coupled to each of the graphics processing engines 431-432, N, respectively. The graphics memories 433-434, M store instructions and data being processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M can be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory such as 3D XPoint or Nano-Ram.

[0093] In one embodiment, to reduce data traffic on link 440, a biasing technique is used to ensure that data stored in graphics memory 433-434, M is data that will be most frequently used by graphics processing engines 431-432, N and is preferably not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to keep data required by the cores (and preferably not the graphics processing engines 431-432, N) in the caches 462A-462D, 456 and system memory 411 of the cores.

[0094] Figure 4C Another embodiment is illustrated in which accelerator integration circuit 436 is integrated within processor 407. In this embodiment, graphics processing engines 431-432, N communicate directly over high-speed link 440 to accelerator integration circuit 436 via interface 437 and interface 435 (which can utilize any form of bus or interface protocol, again). Accelerator integration circuit 436 can execute same operations as those described with respect to Figure 4B but can do so at a higher throughput given its close proximity to coherency bus 462 and caches 462A-462D, 426.

[0095] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The shared programming model can include a programming model controlled by accelerator integration circuit 436 and a programming model controlled by graphics acceleration module 446.

[0096] In one embodiment of the dedicated process model, graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. The single application can funnel other application requests to graphics engines 431-432, N, providing virtualization within the VM / partition.

[0097] In the dedicated process programming model, graphics processing engines 431-432, N can be shared by multiple VM / application partitions. The shared model requires a system hypervisor to virtualize graphics processing engines 431-432, N to allow access by each operating system. For a single-partition system without a hypervisor, graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431-432, N to provide access to each process or application.

[0098] For a shared programming model, graphics acceleration module 446 or the individual graphics processing engines 431-432, N use a process handle to select a process element. In one embodiment, the process element is stored in system memory 41 1 and can be addressed using the effective address to real address translation techniques described herein. The process handle can be an implementation specific value provided to the host process when it registers its context with the graphics processing engines 431-432, N (i.e., calls system software to add a process element to a process element linked list). The lower 16 bits of the process handle can be an offset into the process element linked list.

[0099] Figure 4D An exemplary accelerator integration slice 490 is illustrated. As used herein, a "slice" comprises a specified portion of the processing resources of accelerator integration circuit 436. An application effective address space 482 within system memory 41 1 stores process elements 483. In one embodiment, process elements 483 are stored in response to GPU invocations 481 from an application 480 executing on processor 407. Process elements 483 contain process state for the corresponding application 480. A work descriptor (WD) 484 contained in process element 483 can be a single job requested by an application, or can contain a pointer to a job queue. In the latter case, WD 484 is a pointer to an application's job request queue in the address space 482 of the application.

[0100] Graphics acceleration module 446 and / or the individual graphics processing engines 431-432, N can be shared by all or a subset of the processes in a system. Embodiments of the present invention include infrastructure for setting up process state and sending WDs 484 to graphics acceleration module 446 to start jobs in a virtualized environment.

[0101] In one implementation, a dedicated process programming model is implementation specific. In this model, a single process owns graphics acceleration module 446 or the individual graphics processing engines 431. Because graphics acceleration module 446 is owned by a single process, a hypervisor initializes accelerator integration circuit 436 for the owning partition and an operating system initializes accelerator integration circuit 436 for the owning process when graphics acceleration module 446 is assigned.

[0102] In operation, a WD fetch unit 491 in accelerator integration slice 490 fetches the next WD 484, which includes an indication of work to be done by one of the graphics processing engines of graphics acceleration module 446. Data from WD 484 can be stored in registers 445 and used by MMU 439, interrupt management circuit 447, and / or context management circuit 448 as illustrated. For example, one embodiment of MMU 439 includes segment / page walk circuitry for accessing segment / page tables 486 within OS virtual address space 485. Interrupt management circuit 447 can handle interrupt events 492 received from graphics acceleration module 446. When performing graphics operations, effective addresses 493 generated by graphics processing engines 431-432, N are translated to real addresses by MMU 439.

[0103] In one embodiment, the same set of registers 445 is replicated for each graphics processing engine 431-432, N and / or graphics acceleration module 446 and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in accelerator integration slice 490. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0104] 1 Slice Control Register 2 Real Address (RA) Scheduling Process Region Pointer 3 Authority Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Descriptor Register

[0105] Exemplary registers that can be initialized by an operating system are shown in Table 2.

[0106] 1 Process and Thread Identification 2 Effective Address (EA) Context Save / Restore Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Authority Mask 6 Work Descriptor

[0107] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information the graphics processing engine 431-432, N needs to do its work, or it can be a pointer to a memory location where the application has set up a command queue of work to be completed.

[0108] Figure 4E Additional details of one embodiment of a shared model are illustrated. This embodiment includes a hypervisor real address space 498 in which a list of process elements 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes the graphics acceleration module engine for an operating system 495.

[0109] The shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced sharing and graphics-directed sharing.

[0110] In this model, the system hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. To enable the graphics acceleration module 446 to support virtualization by the system hypervisor 496, the graphics acceleration module 446 can adhere to the following requirements: 1) Application job requests must be autonomous (i.e., state does not need to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The graphics acceleration module 446 guarantees completion of application job requests within a specified amount of time, including any translation faults, or the graphics acceleration module 446 provides the ability to preempt processing of a job. 3) When operating in directed shared programming model, fairness of the graphics acceleration module 446 must be guaranteed between processes.

[0111] In one embodiment, for the shared model, the application 480 is required to make an operating system 495 system call with a graphics acceleration module 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function for the system call. The graphics acceleration module 446 type can be a system specific value. The WD is formatted specifically for the graphics acceleration module 446 and can take the form of a graphics acceleration module 446 command, a valid address pointer to a user defined structure, a valid address pointer to a command queue, or any other data structure used to describe work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to how an application would set the AMR. If the accelerator integration circuit 436 and graphics acceleration module 446 implementation does not support a user authority mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in a hypervisor call. The hypervisor 496 can optionally apply the current authority mask override register (AMOR) value before placing the AMR in the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains a valid address of a region in the application's address space 482 to be used by the graphics acceleration module 446 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. The context save / restore region can be pinned system memory.

[0112] Upon receiving the system call, the operating system 495 can verify that the application 480 is registered and given authority to use the graphics acceleration module 446. The operating system 495 then invokes the hypervisor 496 with the information shown in Table 3.

[0113] 1 Work Descriptor (WD) 2 (A potentially masked) Authority Mask Register (AMR) Value 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0114] Upon receiving a hypervisor call, hypervisor 496 verifies that operating system 495 has been registered and granted permission to use graphics acceleration module 446. Hypervisor 496 then places process element 483 into a linked list of process elements corresponding to the graphics acceleration module 446 type. Process elements may include the information shown in Table 4.

[0115] 1 Work Descriptor (WD) 2 (A potentially masked) Authority Mask Register (AMR) Value 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt Vector Table Derived from Hypervisor Call Parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 12 Storage Descriptor Register (SDR)

[0116] In one embodiment, the hypervisor initializes multiple accelerator integration slice 490 registers 445.

[0117] like Figure 4F As illustrated, one embodiment of the invention employs a unified memory addressable via a shared virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations performed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion to second processor memory 402, a third portion to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 401-402 and GPU memories 420-423, allowing any processor or GPU to access that memory using virtual addresses mapped to any physical memory.

[0118] In one embodiment, the bias / coherence management circuitry 494A-494E within one or more of the MMUs 439A-439E ensures cache coherence between the host processor (e.g., 405) and the cache of the GPUs 410-413, and implements biasing techniques that indicate the physical memory where certain types of data should be stored. While in Figure 4F The diagram illustrates several instances of bias / coherence management circuitry 494A-494E, but bias / coherence circuitry can be implemented within the MMU of one or more host processors 405 and / or within the accelerator integrated circuit 436.

[0119] One embodiment allows GPU-attached memory 420-423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) techniques, but without suffering the typical performance penalties associated with full system cache coherency. The ability to access GPU-attached memory 420-423 as system memory without the heavy cache coherency overhead provides a favorable operating environment for GPU offload. This arrangement allows host processor 405 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. Such traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access GPU-attached memory 420-423 without cache coherency overhead can be critical to the execution time of offloaded computations. For example, in the case of a large amount of streaming write memory traffic, cache coherency overhead can significantly reduce the effective write bandwidth seen by GPU 410-413. Efficiency of operand setup, efficiency of result access, and efficiency of GPU computation all play a role in determining the effectiveness of GPU offload.

[0120] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granularity structure that includes 1 or 2 bits per GPU-attached memory page (i.e., controlled at the granularity of a memory page). The bias table can be implemented in the stolen memory range of one or more GPU-attached memories 420-423, with or without a bias cache in GPU 410-413 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0121] In one implementation, the bias table entry associated with each access to GPU-attached memory 420-423 is accessed prior to the actual access to GPU memory, resulting in the following operations. First, local requests from GPU 410-413 that find their page in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from the GPU that find their page in the host bias are forwarded to processor 405 (e.g., over a high-speed link as discussed above). In one embodiment, requests from processor 405 that find the requested page in the host processor bias complete the request like a normal memory read. Alternatively, requests involving a GPU bias page can be forwarded to GPU 410-413. If the GPU is not currently using the page, the GPU can then convert the page to the host processor bias.

[0122] The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or for a limited set of cases, a pure hardware-based mechanism.

[0123] One mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn invokes a device driver of the GPU that in turn sends a message to the GPU directing it to change the bias state (or enqueues a command descriptor) and for some transitions, performs a cache flush operation in the host. The cache flush operation is required for transitions from the host processor 405 bias to the GPU bias, but not for the reverse transitions.

[0124] In one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages that are not cacheable by the host processor 405. To access these pages, the processor 405 can request access from the GPU 410, which can or can not grant access immediately, depending on the implementation. Thus, to reduce communication between the processor 405 and the GPU 410, it is advantageous to ensure that the GPU-biased pages are those that are required by the GPU but not by the host processor 405, and vice versa.

[0125] Graphics Processing Pipeline

[0126] Figure 5 A graphics processing pipeline 500 is illustrated in accordance with an embodiment. In one embodiment, a graphics processor can implement the graphics processing pipeline 500 illustrated. The graphics processor can be included within a parallel processing subsystem (such as the parallel processor 200 of Figure 2) as described herein, which in one embodiment is a GPU. Figure 1The various parallel processing systems can implement the graphics processing pipeline 500 via one or more instances of the parallel processing units (e.g., the parallel processing unit 202 of FIG. 2) as described herein. For example, a shader unit (e.g., the graphics multiprocessor 234 of FIG. 3) can be configured to perform the functions of one or more of the vertex processing unit 504, the tessellation control processing unit 508, the tessellation evaluation processing unit 512, the geometry processing unit 516, and the fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operations unit 526 can also be performed by other processing engines and corresponding partition units within a processing cluster (e.g., processing cluster 214 of FIG. 3) as described herein. The graphics processing pipeline 500 can also be implemented using dedicated processing units for one or more of the functions. In one embodiment, one or more parts of the graphics processing pipeline 500 can be performed by parallel processing logic within a general purpose processor (e.g., a CPU). In one embodiment, one or more parts of the graphics processing pipeline 500 can access on-chip memory (e.g., parallel processor memory 222 in FIG. 2) via a memory interface 528, which can be an instance of the memory interface 218 of FIG. 2.

[0127] In one embodiment, the data assembler 502 is a processing unit that gathers vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to apply lighting and transformations to vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data, stored in caches, local or system memory, that is utilized to perform processing operations on the vertex data. The vertex processing unit 504 can be programmed to transform the vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0128] A first instance of the primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 reads stored vertex attributes as needed, and constructs graphics primitives for processing by the tessellation control processing unit 508. The graphics primitives include triangles, lines, points, patches, and / or the like, as supported by various graphics processing application programming interfaces (APIs).

[0129] The tessellation control processing unit 508 treats the input vertices as control points for the geometry patch. The control points are transformed from an input representation (e.g., a basis for the patch) from the patch to a representation suitable for use in surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 can also compute tessellation factors for edges of the geometry patch. The tessellation factors apply to individual edges and quantify a view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and to tessellate the patch into a plurality of geometric primitives, such as line, triangle, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on parametric coordinates of the tessellated patch to generate vertex attributes and a surface representation for each vertex associated with the geometric primitives.

[0130] A second instance of the primitive assembler 514 receives the vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphics primitives received from the primitive assembler 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide the graphics primitives into one or more new graphics primitives and to compute parameters for rasterizing the new graphics primitives.

[0131] In some embodiments, the geometry processing unit 516 can add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices that specify new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scale, cull, and clip unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use while processing the geometry data. The viewport scale, cull, and clip unit 520 performs clipping, culling, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522.

[0132] The rasterizer 522 can perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to perform fragment shader programs or pixel shader programs. The fragment / pixel processing unit 524 is configured to process received fragments or pixels from the rasterizer 522, as specified by the fragment or pixel shader programs. For example, the fragment / pixel processing unit 524 can be programmed to perform operations including, but not limited to, texture mapping, shading, blending, texture correction, and perspective correction to produce a colored fragment or pixel output to the raster operations unit 526. The fragment / pixel processing unit 524 can read data stored in the parallel processor memory or system memory in processing the fragment data. The fragment or pixel shader programs can be configured to color at a sample, pixel, tile, or other granularity depending on the sampling rate configured for the processing unit.

[0133] The raster operations unit 526 is a processing unit that performs raster operations including, but not limited to, stencil operations, z-test, blending, and the like, and outputs pixel data as processed graphics data to be stored in graphics memory (e.g., the parallel processor memory 222 as in FIG. 2, and / or the system memory 104 as in FIG. 1) for display on the one or more display devices 110 or for further processing by one or more of the processors 102 or parallel processor(s) 112. In some embodiments, the raster operations unit 526 is configured to compress z or color data that is written to memory and decompress z or color data that is read from memory. Figure 1

[0134] Many existing processes use a fast Fourier transform (FFT) on convolution layers in order to perform element-wise multiplication in the frequency domain. The back-and-forth conversion between domains is computationally expensive. To address this and others, different types of activations are published and entire subgraphs of the network are found that can be executed in the frequency domain. With such capabilities, the selection of the best convolution algorithm becomes a global graph optimization decision.

[0135] Referring to Figures 6A-6B In one aspect, a series of layers for which computations can be kept in the frequency domain and as many computations as possible are applied in the frequency domain are determined. Using this technique, a heuristic to select the best convolution algorithm across a complete network can require a full network analysis.

[0136] ​Currently, CuDNN statically selects between Winograd and the general matrix multiplication (GEMM) implementation for (size-based) convolutions, and this can also be manually selected by the developer. In some instances, the selection can not be optimal for every size of GPU, batch, and / or configuration. Further, useful sizes can change with algorithmic improvements. Training is time consuming and computationally expensive and thus optimization is important.

[0137] In some examples, a convolution implementation can be dynamically selected based on running a short comparison for each convolution in the network. There can be a cuDNN utility that will make the selection. This will improve run time because a static selection cannot be optimized ahead of time for all convolution sizes, batch sizes, and hardware settings that will be implemented in practice.

[0138] Reference Figures 7A-7B Because the activations of the layers become sparser as they are placed deeper in the network and because deeper layers can be compressed more than higher layers while maintaining accuracy, the most efficient point locations can be found to switch between doing dense convolutions and doing sparse convolutions. So the first layer uses a HW configuration for dense convolutions and the remaining layers will use a different HW configuration for doing sparse convolutions (because it is more efficient for them to work on sparse activations). The sparsity of the layer activations can be predicted using training sample statistics and can also be updated online in inference mode. The principle of adapting the HW to the layer can also be applied when choosing the number of bits to use in the media access controller operations. As a general principle, the first layer requires hiring precision than lower layers.

[0139] In some examples, it can be useful to use GPU rendering capabilities to generate synthetic data for GANs. In one aspect, it can be useful to expose embedded cast operations to load / store instructions in order to support loading according to variable integer precision (e.g., 2 bits, 3 bits, 7 bits, etc.). Internal computations can be kept in baseline precision (e.g., 8 bits or 16 bits).

[0140] Reference Figure 7C In some examples, two networks can be run in parallel in order to render new samples. This can be useful in three-dimensional (3D) rendering where the viewpoint can be changed.

[0141] Reference Figures 7D-7EIn some examples, a tiling approach can be used for some or all of the layers. For example, one can evaluate all convolutional layers for a tile in a neural network, then merge all tiles before the fully connected layers. This can increase cache coherency and save memory bandwidth between layers, and when using input from a tiled rendering engine. For example, tile processing can be added to the end of a graphics tile to emulate processing a depth-first search (DFS) style rather than a breadth-first search (BFS) style. One use that can be particularly beneficial is reinforcement learning of a game where one can even append this processing to the game's pixel shader (i.e., each pixel is a tile at the moment).

[0142] When input / filter sparsity is high enough and the right hardware (HW) is used, using sparse convolutions is much faster than using dense convolutions. The sparsity of the layer activations can be predicted using training sample statistics and can also be updated online in inference mode. This allows using sparse convolution HW only when it will improve performance. The principle of adapting the HW to the layer can also be applied when choosing the number of bits to use in the media access controller (MAC) operations.

[0143] In some examples, this can increase cache coherency and save memory bandwidth between layers, and we can add tile processing to the end of a graphics tile, for example, when using input from a tiled rendering engine.

[0144] Machine Learning Overview

[0145] Machine learning algorithms are algorithms that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a data set. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; regression algorithms can output a numerical value given an input; and pattern recognition algorithms can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0146] One example type of machine learning algorithm is a neural network. There are many types of neural networks; one simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph in which nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms input received by the input layer into a representation useful for generating output in the output layer. Network nodes are fully connected to nodes in adjacent layers via edges, but there are no edges between nodes within each layer. Data received at nodes of the input layer of a feedforward network is propagated (i.e., "fed forward") to nodes of the output layer via an activation function that computes a state of nodes of each successive layer in the network based on coefficients ("weights") respectively associated with each of the edges connecting the layers. The output from a neural network algorithm can take various forms depending on the particular model represented by the algorithm being executed.

[0147] A machine learning algorithm can be trained using a training data set before it can be used to model a particular problem. Training a neural network involves selecting a network topology, using a set of training data representing a problem modeled by the network, and adjusting weights until the network model performs with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, an output produced by the network in response to an input representing an instance of the training data set is compared to the "correct" labeled output for that instance, an error signal representing a difference between the output and the labeled output is computed, and when the error signal is propagated backwards through the layers of the network, weights associated with connections are adjusted to minimize the error. When the error for each output generated from an instance of the training data set is minimized, the network is considered to be "trained."

[0148] The accuracy of a machine learning algorithm can be significantly influenced by the quality of the data set used to train the algorithm. The training process can be computationally intensive and can require a significant amount of time on a conventional general-purpose processor. Therefore, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks because the computations performed in adjusting coefficients in a neural network lend themselves naturally to parallel implementation. In particular, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within a general-purpose graphics processing device.

[0149] Figure 8is a generalized diagram of the machine learning software stack 800. The machine learning applications 802 can be configured to train neural networks using training data sets or to implement machine intelligence using trained deep neural networks. The machine learning applications 802 can include specialized software that can be used to train neural networks prior to deployment and / or training and inference functionality of neural networks. The machine learning applications 802 can implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0150] Hardware acceleration for the machine learning applications 802 can be enabled via the machine learning framework 804. The machine learning framework 804 can provide a library of machine learning primitives. A machine learning primitive is a basic operation that is commonly performed by machine learning algorithms. Without the machine learning framework 804, developers of machine learning algorithms would be required to create and optimize the primary computational logic associated with the machine learning algorithm, then re-optimize that computational logic when new parallel processors are developed. Instead, the machine learning applications can be configured to perform the necessary computations using primitives provided by the machine learning framework 804. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed when training a convolutional neural network (CNN). The machine learning framework 804 can also provide primitives to implement basic linear algebra subprograms, such as matrix and vector operations, that are performed by many machine learning algorithms.

[0151] The machine learning framework 804 can process input data received from the machine learning applications 802 and generate appropriate input to the compute framework 806. The compute framework 806 can abstract the basic instructions provided to the GPGPU driver 808 to enable the machine learning framework 804 to leverage hardware acceleration via GPGPU hardware 810 without requiring the machine learning framework 804 to be very familiar with the architecture of the GPGPU hardware 810. Additionally, the compute framework 806 can enable hardware acceleration for the machine learning framework 804 across multiple types and generations of GPGPU hardware 810.

[0152] GPGPU Machine Learning Acceleration

[0153] Figure 9 A highly parallel general purpose graphics processing unit 900 is illustrated in accordance with an embodiment. In one embodiment, the general purpose processing unit (GPGPU) 900 can be configured to be particularly efficient when processing computational workloads of the type associated with training deep neural networks. Additionally, the GPGPU 900 can be directly linked to other instances of GPGPUs to create a multi-GPU cluster to improve the speed of training particularly deep neural networks.

[0154] GPGPU 900 includes a host interface 902 for enabling connectivity to a host processor. In one embodiment, the host interface 902 is a PCI Express interface. However, the host interface can be a proprietary

[0155] GPGPU 900 includes memory 914A-B coupled with the compute clusters 906A-H via a set of memory controllers 912A-B. In various embodiments, the memory 914A-B can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A-224N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM).

[0156] In one embodiment, each compute cluster 906A-H includes a set of graphics processing units, such as graphics processing unit 400 of FIG. 4. Figure 4A The graphics processing units of the compute clusters include multiple types of integer and floating point logic units that can perform compute operations at a range of precisions, including precisions suitable for machine learning computations. For example, and in one embodiment, at least a subset of the floating point units in each of the compute clusters 906A-H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units can be configured to perform 64-bit floating point operations.

[0157] Multiple instances of GPGPU 900 can be configured to operate as a compute cluster. The communication mechanism used by the compute cluster for synchronization and data exchange varies across embodiments. In one embodiment, multiple instances of GPGPU 900 communicate over host interface 902. In one embodiment, GPGPU 900 includes an I / O hub 909 that couples GPGPU 900 to a GPU link 910 that enables a direct connection to other instances of GPGPU. In one embodiment, GPU link 910 is coupled to a specialized GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 900. In one embodiment, GPU link 910 is coupled with a high-speed interconnect to transfer data to and from other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 900 are located in separate data processing systems and communicate via a network device that is accessible via host interface 902. In one embodiment, GPU link 910 can be configured to enable a connection to a host processor in addition to or as an alternative to host interface 902.

[0158] While the illustrated configuration of GPGPU 900 can be configured to train a neural network, one embodiment provides an alternative configuration of GPGPU 900 that can be configured for deployment within a high-performance or low-power inferencing platform. In an inferencing configuration, GPGPU 900 includes fewer compute clusters 906A-H relative to the training configuration. Additionally, the memory technology associated with memory 914A-B can differ between the inferencing configuration and the training configuration. In one embodiment, the inferencing configuration of GPGPU 900 can support inferencing-specific instructions. For example, the inferencing configuration can provide support for one or more 8-bit integer dot product instructions that are commonly used during inferencing operations for a deployed neural network.

[0159] Figure 10 A multi-GPU computing system 1000 is illustrated in accordance with an embodiment. Multi-GPU computing system 1000 can include a processor 1002 coupled to a plurality of GPGPUs 1006A-D via a host interface switch 1004. In one embodiment, host interface switch 1004 is a PCI express switch device that couples processor 1002 to a PCI express bus over which processor 1002 can communicate with the set of GPGPUs 1006A-D. Each of the plurality of GPGPUs 1006A-D can be Figure 9of GPGPUs 900. The GPGPUs 1006A-D can be interconnected via a set of high-speed point-to-point GPU-to-GPU link 1016. The high-speed GPU-to-GPU links can be connected to each of the GPGPUs 1006A-D via a dedicated GPU link, such as GPU link 910 in Figure 9 The P2P GPU links 1016 enable direct communication between each of the GPGPUs 1006A-D without requiring communication over the host interface bus to which the processor 1002 is connected. Where GPU-to-GPU traffic is concerned, the host interface bus can still be used for system memory access or communication with other instances of the multi-GPU computing system 1000, e.g., via one or more network devices. While in the illustrated embodiment the GPGPUs 1006A-D are connected to the processor 1002 via the host interface switch 1004, in one embodiment the processor 1002 includes direct support for the P2P GPU links 1016 and can connect directly to the GPGPUs 1006A-D.

[0160] Machine Learning Neural Network Implementation

[0161] The computing architecture provided by the embodiments described herein can be configured to perform parallel processing of the type particularly suited for training and deploying neural networks for machine learning. Neural networks can be generalized as networks of functions having a graph relationship. As is well known in the art, there are multiple types of neural network implementations used in machine learning. One exemplary type of neural network is a feedforward network as previously described.

[0162] A second exemplary type of neural network is a convolutional neural network (CNN). CNNs are specialized feedforward neural networks for processing data having a known grid-like topology, such as image data. Thus, CNNs are commonly used for computing vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. Nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors inspired by the receptive fields found in the retina) and the output of each set of filters is propagated to nodes in successive layers of the network. The computations for a CNN include applying a convolution mathematical operation to each filter to produce an output for that filter. Convolution is a specialized kind of mathematical operation performed by two functions to produce a third function that is a modified version of one of the two original functions. In convolution network terminology, the first function of the convolution can be referred to as the input, while the second function can be referred to as the convolution kernel. The output can be referred to as a feature map. For example, the input to a convolution layer can be a multidimensional data array that defines various color components of an input image. The convolution kernel can be a multidimensional array of parameters that are adapted through a training process for the neural network.

[0163] A recurrent neural network (RNN) is a type of feedforward neural network that includes feedback connections between layers. RNNs enable modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes loops. The loops represent the influence of a variable's present value on its own value in the future, as at least a portion of the output data from the RNN is used as feedback for processing subsequent input in the sequence. This feature makes RNNs particularly useful for language processing due to the variable nature that language data can include.

[0164] The figures described below present example feedforward, CNN, and RNN networks, and describe general processes for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any particular embodiment described herein, and that the concepts illustrated can be generally applied to deep neural networks and machine learning techniques in general.

[0165] The example neural networks described above can be used to perform deep learning. Deep learning is machine learning using deep neural networks. In contrast to shallow neural networks that include only a single hidden layer, deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Training deeper neural networks is generally more computationally intensive. However, the additional hidden layers of the network enable multi-step pattern recognition that results in reduced output error relative to shallow machine learning techniques.

[0166] Deep neural networks used in deep learning typically include a front-end network to perform feature recognition coupled to a back-end network representing a mathematical model that can perform operations based on the feature representation provided to the model (e.g., object classification, speech recognition, etc.). Deep learning enables machine learning without requiring handcrafted feature engineering for the model. Instead, the deep neural network can learn features based on statistical structure or correlations within the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical model used by the network is generally specific to the particular task to be performed, and different models will be used to perform different tasks.

[0167] Once a neural network is structured, a learning model can be applied to the network to train the network to perform a particular task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Backpropagation of error is one commonly used method for training neural networks. An input vector is presented to the network for processing. The output of the network is compared to the desired output using a loss function, and an error value is computed for each neuron in the output layer. The error values are then propagated backwards until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm such as a stochastic gradient descent algorithm to update the weights of the neural network.

[0168] Figure 11A - B illustrates an exemplary convolutional neural network. Figure 11A Various layers within a CNN are illustrated. As shown in Figure 11A An exemplary CNN used to model processing of an image can receive an input 1102 that describes the red, green, and blue (RGB) components of an input image, as shown in FIG. 11. The input 1102 can be processed by a plurality of convolutional layers, such as convolutional layer 1104, convolutional layer 1106. The output from the plurality of convolutional layers can optionally be processed by a set of fully connected layers 1108. Neurons in the fully connected layers have full connections to all activation functions in the previous layer, as previously described for feedforward networks. The output from the fully connected layers 1108 can be used to generate an output result from the network. The activations within the fully connected layers 1108 can be computed using matrix multiplication rather than convolution. Not all CNN implementations use fully connected layers 1108. For example, in some implementations, the convolutional layers 1106 can generate the output of the CNN.

[0169] Convolutional layers are sparsely connected, unlike the traditional neural network configuration found in fully connected layers 1108. Traditional neural network layers are fully connected, such that each output unit interacts with every input unit. However, convolutional layers are sparsely connected in that the output of the convolution of the field (rather than the respective state value of each node in the field) is input to the nodes of the subsequent layer, as illustrated. The kernel associated with a convolutional layer performs a convolution operation, the output of which is sent to the next layer. The dimensionality reduction performed within a convolutional layer is one aspect that enables a CNN to scale to process large images.

[0170] Figure 11BAn exemplary computation stage is illustrated within a convolutional layer of a CNN. An input 1112 to a convolutional layer of a CNN can be processed in three stages of a convolutional layer 1114. The three stages can include a convolution stage 1116, a detector stage 1118, and a pooling stage 1120. The convolutional layer 1114 can then output data to a successive convolutional layer. The last convolutional layer of a network can generate output feature map data or provide input to a fully connected layer, for example, to generate classification values for an input to the CNN.

[0171] In the convolution stage 1116, several convolutions are performed in parallel to produce a set of linear activations. The convolution stage 1116 can include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage computes the output of a function (e.g., a neuron) connected to a particular region in the input, which can be determined as a local region associated with the neuron. The neuron computes a dot product between the neuron's weights and the region in the local input to which the neuron is connected. The output from the convolution stage 1116 defines a set of linear activations that are processed by successive stages of the convolutional layer 1114.

[0172] The linear activations can be processed by the detector stage 1118. In the detector stage 1118, each linear activation is processed by a non-linear activation function. The non-linear activation function increases the non-linear properties of the overall network without affecting the receptive field of the convolutional layer. Several types of non-linear activation functions can be used. One particular type is a rectified linear unit (ReLU), which uses an activation function defined as f(x) = max( 0 , x ) such that the activation is thresholded at zero.

[0173] The pooling stage 1120 uses a pooling function that replaces the output of the convolutional layer 1106 with a summary statistic of nearby outputs. Pooling functions can be used to introduce translation invariance into a neural network, such that small translations in the input do not change the pooling output. Invariance to local translations can be useful in scenarios where the presence of a feature in the input data is more important than the exact position of the feature. Various types of pooling functions can be used during the pooling stage 1120, including max pooling, average pooling, and l2-norm pooling. Additionally, some CNN implementations do not include a pooling stage. Instead, such implementations replace and additional convolutional stage has an increased stride relative to the previous convolutional stage.

[0174] The output from the convolutional layer 1114 can then be processed by a next layer 1122. The next layer 1122 can be an additional convolutional layer or one of the fully connected layers 1108. For example, Figure 11AThe first convolutional layer 1104 can output to a second convolutional layer 1106, which can output to a first layer in a fully connected layer 1108.

[0175] Figure 12 An exemplary recurrent neural network 1200 is illustrated. In a recurrent neural network (RNN), the previous state of the network influences the output of the current state of the network. RNNs can be built in a variety of ways using a variety of functions. The use of RNNs generally revolves around using mathematical models to make predictions of the future based on a sequence of previous inputs. For example, RNNs can be used to perform statistical language modeling to predict an upcoming word given a sequence of previous words. The illustrated RNN 1200 can be described as having an input layer 1202 that receives an input vector, a hidden layer 1204 that implements a recurrent function, a feedback mechanism 1205 that enables a'memory' of previous states, and an output layer 1206 that outputs a result. The RNN 1200 operates based on time steps. The state of the RNN at a given time step is influenced based on previous time steps via the feedback mechanism 1205. The state of the hidden layer 1204 is defined for a given time step by the previous state and the input at the current time step. An initial input (xi) at a first time step can be processed by the hidden layer 1204. A second input (x2) can be processed by the hidden layer 1204 using state information determined during processing of the initial input (xi). The given state can be computed as s t = f Ux t Ws t-1 , where U and W are parameter matrices. The function f is generally non-linear, such as a hyperbolic tangent function (Tanh) or a variant of the rectified function f(x) = max( 0 , x ). However, the particular mathematical function used in the hidden layer 1204 can vary depending on the particular implementation details of the RNN 1200.

[0176] ​​In addition to the basic CNN and RNN networks described, variations of those networks can be enabled. One example RNN variant is a long short-term memory (LSTM) RNN. LSTM RNNs are capable of learning long-term dependencies that can be necessary for processing longer language sequences. A variant of a CNN is a convolutional deep belief network, which has a structure similar to a CNN and is trained in a manner similar to a deep belief network. A deep belief network (DBN) is a generative neural network composed of multiple layers of stochastic (random) variables. A DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of a DBN can then be used to provide a pre-trained neural network by determining a set of optimal initial weights for a neural network.

[0177] Figure 13 Training and deployment of a deep neural network is illustrated. Once a given network has been structured for a task, the neural network is trained using a training data set 1302. Various training frameworks have been developed to enable hardware acceleration of the training process. For example, Figure 8 The machine learning framework 804 of FIG. 8 can be configured as a training framework 1304. The training framework 1304 can hook into an untrained neural network 1306 and enable training of the untrained neural network using the parallel processing resources described herein to generate a trained neural network 1308.

[0178] To begin the training process, initial weights can be selected randomly or by pre-training using a deep belief network. Training loops are then performed in a supervised or unsupervised manner.

[0179] Supervised learning is a method of learning in which training is performed as a mediation operation, such as when the training data set 1302 includes inputs paired with desired outputs for the inputs, or in cases where the training data set includes inputs with known outputs and the output of the neural network is manually graded. The network processes the inputs and the resulting output is compared to a set of expected or desired outputs. Errors are then backpropagated through the system. The training framework 1304 can make adjustments to adjust the weights that control the untrained neural network 1306. The training framework 1304 can provide tools to monitor how well the untrained neural network 1306 is converging toward a model that is suitable for generating correct answers based on known input data. The training process iteratively occurs as the weights of the network are adjusted to improve the output generated by the neural network. The training process can continue until the neural network reaches a statistically expected accuracy associated with the trained neural network 1308. The trained neural network 1308 can then be deployed to implement any number of machine learning operations.

[0180] Unsupervised learning is a method of learning in which a network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training dataset 1302 will include input data without any associated output data. An untrained neural network 1306 can learn groupings within unlabeled input and can determine how individual inputs relate to the overall dataset. Unsupervised training can be used to generate a self-organizing map, which is one type of trained neural network 1307 that is able to perform operations useful in reducing the dimensionality of data. Unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in an input dataset that deviate from a normal pattern of data.

[0181] Variations of supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training dataset 1302 includes a mix of labeled and unlabeled data of the same distribution. Incremental learning is a variation of supervised learning in which input data is used continuously to further train a model. Incremental learning enables a trained neural network 1308 to adapt to new data 1312 without forgetting the knowledge instilled in the network during initial training.

[0182] Regardless of whether supervised or unsupervised, the training process for particularly deep neural networks can be too computationally intensive for a single computing node. Rather than using a single computing node, a distributed network of computing nodes can be used to speed up the training process.

[0183] Figure 14 is a block diagram illustrating distributed learning. Distributed learning is a trained model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. The distributed computing nodes can each include one or more host processors and one or more of general purpose processing nodes, such as a highly parallel general purpose graphics processing unit 900 as in FIG. 900. As illustrated, distributed learning can perform model parallelism 1402, data parallelism 1404, or a combination of model and data parallelism 1404.

[0184] In model parallelism 1402, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by different processing nodes of a distributed system. Benefits of model parallelism include the ability to scale to particularly large models. Splitting computations associated with different layers of a neural network enables the training of very large neural networks in which the weights of all layers would not fit into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0185] In data parallel 1404, different nodes of a distributed network have a complete instance of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. While different approaches for data parallel are possible, data parallel training approaches all require techniques to combine results and synchronize model parameters across each node. Example methods for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging except that updates to the model are transferred instead of the parameters from the nodes to the parameter server. Additionally, update-based data parallelism can be performed in a decentralized manner where updates are compressed and transferred between nodes.

[0186] For example, combined model and data parallel 1406 can be implemented in a distributed system where each compute node includes multiple GPUs. Each node can have a complete instance of the model, with individual GPUs within each node used to train different portions of the model.

[0187] Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques for reducing the overhead of distributed training, including techniques for enabling high-bandwidth GPU-to-GPU data transfers and accelerated remote data synchronization.

[0188] Exemplary Machine Learning Application

[0189] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active areas of research for machine learning applications. Applications of computer vision range from replicating human visual capabilities, such as recognizing faces, to creating new classes of visual capabilities. For example, a computer vision application can be configured to recognize sound waves from vibrations induced in objects visible in a video. Parallel processor-accelerated machine learning enables training of computer vision applications using significantly larger training data sets than previously feasible, and enables deployment of inference systems using low-power parallel processors.

[0190] Machine learning accelerated by parallel processors has applications in autonomous driving, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train a driving model based on a dataset that defines an appropriate response to a particular training input. Parallel processors described herein can enable fast training of increasingly complex neural networks for autonomous driving solutions and enable deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0191] Parallel processor-accelerated deep neural networks have enabled machine learning approaches for automatic speech recognition (ASR). ASR includes creating a function that computes the most likely sequence of words given an input acoustic sequence. Accelerated machine learning using deep neural networks has enabled replacing hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0192] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. Automated learning programs can use statistical inference algorithms to produce models that are robust to erroneous or unfamiliar input. An exemplary natural language processor application includes automatic machine translation between human languages.

[0193] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are generally highly parallel and include optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include the highly parallel general-purpose graphics processing unit 900 of FIG. 900 and the multi-GPU computing system 1000 of FIG. 1000. In contrast, deployed machine learning platforms generally include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0194] Figure 15An exemplary inference system-on-a-chip (SOC) 1500 suitable for performing inference using trained models is illustrated. The SOC 1500 can integrate processing components including a media processor 1502, a vision processor 1504, a GPGPU 1506, and a multi-core processor 1508. The SOC 1500 can additionally include on-chip memory 1505, which can enable a shared on-chip data pool accessible by each of the processing components. The processing components can be optimized for low-power operation to enable deployment to a variety of machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of the SOC 1500 can be used as part of a main control system for an autonomous vehicle. Where the SOC 1500 is configured for use in an autonomous vehicle, the SOC is designed and configured to meet relevant functional safety standards for the deployment jurisdiction.

[0195] During operation, the media processor 1502 and the vision processor 1504 can work in concert to accelerate computer vision operations. The media processor 1502 can enable low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 1505. The vision processor 1504 can then parse the decoded video and perform preliminary processing operations on frames of the decoded video in preparation for processing the frames using trained image recognition models. For example, the vision processor 1504 can accelerate convolution operations for CNNs used to perform image recognition on high-resolution video data, while back-end model computations are performed by the GPGPU 1506.

[0196] The multi-core processor 1508 can include control logic to help sequence and synchronize shared memory operations and data transfers performed by the media processor 1502 and the vision processor 1504. The multi-core processor 1508 can also act as an application processor to execute software applications that can use the inference computing capabilities of the GPGPU 1506. For example, at least a portion of navigation and driving logic can be implemented in software executing on the multi-core processor 1508. Such software can issue compute workloads directly to the GPGPU 1506, or can issue compute workloads to the multi-core processor 1508, which can offload at least a portion of those operations to the GPGPU 1506.

[0197] GPGPU 1506 can include compute clusters such as a low-power configuration of compute clusters 906A-906H within a highly parallel general-purpose graphics processing unit 900. Compute clusters within GPGPU 1506 can support instructions that are specifically optimized to perform inferencing computations on trained neural networks. For example, GPGPU 1506 can support instructions for performing low-precision computations such as 8-bit and 4-bit integer vector operations.

[0198] Additional Exemplary Graphics Processing System

[0199] Details of the embodiments described above can be incorporated within graphics processing systems and devices described below. Figures 21-29 The graphics processing systems and devices of FIGS. 1-3 illustrate alternative systems and graphics processing hardware that can implement any and all of the techniques described above.

[0200] Additional Exemplary Graphics Processing System Overview

[0201] Figure 16 is a block diagram of a processing system 1600 according to an embodiment. In various embodiments, system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and can be a single-processor desktop system, a multiprocessor workstation system, or a server system that includes a large number of processors 1602 or processor cores 1607. In one embodiment, system 1600 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0202] Embodiments of system 1600 can include a server-based gaming platform, a game console including a game and media console, a mobile gaming console, a handheld game console, or an online game console, or be incorporated within them. In some embodiments, system 1600 is a mobile phone, a smart phone, a tablet computing device, or a web appliance. Data processing system 1600 can also include a wearable device such as a smart watch wearable device, smart glasses device, augmented reality device, or virtual reality device, coupled to or integrated with the wearable device. In some embodiments, data processing system 1600 is a television or set-top box device having one or more processors 1602 and a graphical interface generated by one or more graphics processors 1608.

[0203] In some embodiments, the one or more processors 1602 each include one or more processor cores 1607 to process instructions which, when executed, implement operations for system and user software. In some embodiments, each of the one or more processor cores 1607 is configured to process a specific instruction set 1609. In some embodiments, instruction set 1609 can facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). Multiple processor cores 1607 can each process a different instruction set 1609, which can include instructions to facilitate the emulation of other instruction sets. Processor core 1607 can also include other processing devices, such as a digital signal processor (DSP).

[0204] In some embodiments, processor 1602 includes a cache memory 1604. Depending upon the configuration, processor 1602 can have a single internal cache or multiple levels of internal caches. In some embodiments, cache memory is shared among various components of processor 1602. In some embodiments, processor 1602 also uses an external cache (e.g., a Level 3 (L3) cache or Last Level Cache (LLC)) (not shown), which can be shared between processor cores 1607 using known cache coherency techniques. A register file 1606 is also included in processor 1602 which can include different types of registers to store different kinds of data (e.g., integer registers, floating point registers, status registers, and instruction pointer registers). Some registers can be general registers, while other registers can be specific to processor 1602 design.

[0205] In some embodiments, processor 1602 is coupled with a processor bus 1610 that transmits communication signals between processor 1602 and other components in system 1600, such as storage devices or input / output (I / O) devices. In one embodiment, system 1600 uses an exemplary 'hub' system architecture, including a memory controller hub 1616 and an I / O controller hub 1630. The memory controller hub 1616 facilitates communication between a memory device and other components in system 1600, while the I / O controller hub 1630 provides connections between the I / O devices and the local I / O bus. In one embodiment, the logic of memory controller hub 1616 is integrated within processor.

[0206] Memory device 1620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or some other memory device with suitable performance to act as process memory. In one embodiment, memory device 1620 may operate as system memory of system 1600 to store data 1622 and instructions 1621 for use by the one or more processors 1602 when executing an application or process. Memory controller hub 1616 is also coupled to an optional external graphics processor 1612, which may communicate with the one or more graphics processors 1608 in processor 1602 to perform graphics and media operations.

[0207] In some embodiments, ICH 1630 enables peripheral devices to connect to memory device 1620 and processor 1602 via a high-speed I / O bus. I / O peripheral devices include, but are not limited to, an audio controller 1646, a firmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi, Bluetooth), a data storage device 1624 (e.g., a hard disk drive, flash memory, etc.), and a legacy I / O controller 1640 for coupling legacy (e.g., a Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1642 connect input devices, such as a keyboard and mouse combination 1644. A network controller 1634 may also be coupled to ICH 1630. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 1610. It will be understood that the illustrated system 1600 is exemplary and not limiting, as other types of data processing systems with different configurations may also be used. For example, the I / O controller hub 1630 may be integrated within one or more processors 1602, or the memory controller hub 1616 and the I / O controller hub 1630 may be integrated into a discrete external graphics processor (such as external graphics processor 1612).

[0208] Figure 17 This is a block diagram of an embodiment of processor 1700, which has one or more processor cores 1702A-1702N, an integrated memory controller 1714, and an integrated graphics processor 1708. Figure 17Those elements of the with the same reference number (or name) as elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to so doing. The processor 1700 can include additional cores up to and including the additional core 1702N represented by the dashed box. Each of the processor cores 1702A-1702N includes one or more internal cache units 1704A-1704N. In some embodiments, each processor core is also able to access one or more shared cache units 1706.

[0209] The internal cache units 1704A-1704N and shared cache units 1706 represent a cache hierarchy within the processor 1700. The cache hierarchy can include at least one level of instruction and data caches within each processor core and one or more levels of shared mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of caches, where the highest level cache before main memory is classified as an LLC. In some embodiments, cache coherency logic maintains coherency among the various cache units 1706 and 1704A-1704N.

[0210] In some embodiments, the processor 1700 can also include a set of one or more bus controller units 1716 that manage a set of peripheral buses, such as one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express). A system agent core 1710 provides management functionality for the various processor components. In some embodiments, the system agent core 1710 includes one or more integrated memory controllers 1714 to manage access to various external memory devices (not shown).

[0211] In some embodiments, one or more of the processor cores 1702A-1702N include support for simultaneous multi-threading. In such embodiments, the system agent core 1710 includes components to coordinate and operate the processor cores 1702A-1702N during multi-threaded processing. The system agent core 1710 can additionally include a power control unit (PCU), including logic and components to regulate the power state of the processor cores 1702A-1702N, as well as the graphics processor 1708.

[0212] In some embodiments, the processor 1700 additionally includes a graphics processor 1708 for performing graphics processing operations. In some embodiments, the graphics processor 1708 is coupled with a set of shared cache units 1706 and system agent cores 1710, including the one or more integrated memory controllers 1714. In some embodiments, a display controller 1711 is coupled with the graphics processor 1708 to drive graphics processor output to one or more coupled displays. In some embodiments, the display controller 1711 can be a separate module coupled with the graphics processor via at least one interconnect, or can be integrated within the graphics processor 1708 or system agent cores 1710.

[0213] In some embodiments, a ring-based interconnect unit 1712 is used to couple internal components of the processor 1700. However, alternative interconnect units, such as point-to-point interconnect, switched interconnect, or other technologies, including those well known in the art, can be used. In some embodiments, the graphics processor 1708 is coupled with the ring interconnect 1712 via an I / O link 1713.

[0214] The exemplary I / O link 1713 represents at least one of a variety of I / O interconnects, including a package on I / O interconnect that facilitates communication between various processor components and a high performance embedded memory module 1718, such as an eDRAM module. In some embodiments, each of the processor cores 1702A-1702N and the graphics processor 1708 use the embedded memory module 1718 as a shared last level cache.

[0215] In some embodiments, the processor cores 1702A-1702N are homogeneous cores executing the same instruction set architecture. In another embodiment, the processor cores 1702A-1702N are heterogeneous in terms of instruction set architecture (ISA), where one or more of the processor cores 1702A-1702N execute a first instruction set and at least one of the other cores executes a subset or a different instruction set of the first instruction set. In one embodiment, the processor cores 1702A-1702N are heterogeneous in terms of microarchitecture, where one or more of the cores have a relatively higher power consumption and one or more of the cores have a lower power consumption. Additionally, the processor 1700 can be implemented on one or more chips or as a SoC integrated circuit having the illustrated components in addition to other components.

[0216] Figure 18is a block diagram of a graphics processor 1800 that can be a discrete graphics processing unit, or can be graphics processor integrated with one or more processing cores. In some embodiments, the graphics processor communicates with the processor(s) via an I / O interface to memory mapped I / O space on the graphics processor. In some embodiments, graphics processor 1800 includes a memory interface 1814 to access a memory. Memory interface 1814 can be to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0217] In some embodiments, graphics processor 1800 also includes a display controller 1802 to drive display output data to a display device 1820. Display controller 1802 includes hardware for one or more overlay planes for compositing and hardware for compositing layers of video or user interface elements. In some embodiments, graphics processor 1800 includes a video codec engine 1806 to encode, decode, or transcode media. In some embodiments, media

[0218] In some embodiments, graphics processor 1800 includes a block image transfer (BLIT) engine 1804 to perform two-dimensional (2D) rasterizer operations including, for example, bit boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of graphics processing engine (GPE) 1810. In some embodiments, GPE 1810 is a compute engine to perform graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0219] In some embodiments, GPE 1810 includes a 3D pipeline 1812 for processing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.). The 3D pipeline 1812 includes programmable and fixed function elements that perform various tasks on the 3D primitives. The 3D pipeline 1812

[0220] In some embodiments, media pipeline 1816 includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video convert.

[0221] In some embodiments, 3D / media subsystem 1815 includes logic to execute threads spawned by 3D pipeline 1812 and media pipeline 1816. In one embodiment, the pipelines send thread execution requests to 3D / media subsystem 1815, which includes thread dispatch logic to arbitrate the various requests and dispatch the requests to available thread execution resources. Execution resources include an array of graphics execution units for processing the 3D and media threads. In some embodiments, 3D / media subsystem 1815 includes one or more internal caches to cache it instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and store output data.

[0222] Graphics Processing Engine

[0223] Figure 19 is a block diagram of a graphics processing engine 1910 of a graphics processor, in accordance with some embodiments. In one embodiment, the graphics processing engine (GPE) 1910 is one version of the GPE 1810 shown in FIG. 18. Figure 18 Figure 19 ​elements having the same reference number (or name) as elements in any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to so doing. For example, it is illustrated that Figure 18 The 3D pipeline 1812 and media pipeline 1816 of FIG. 18A are merely provided as an example. In other embodiments, the GPE 1910 can include all of the pipelines 1812, 1816, a subset of the pipelines, none of the pipelines, or different pipelines. For example, an embodiment of the GPE 1910 can include a single pipeline that provides joint video and graphics processing for the GPE 1910. The single pipeline can receive commands for the GPE 1910 from the command streamer 1903. The single pipeline can process the commands and process video and / or graphics data to produce video or graphics data that is stored for use by the display processor 1920. In some embodiments, the media pipeline 1816 is optional and can not be included within the GPE 1910. For example, a separate media processor is coupled to the GPE 1910 to provide media processing capabilities.

[0224] In some embodiments, the GPE 1910 is coupled with or includes a command streamer 1903 that provides a command stream to the 3D pipeline 1812 and / or media pipeline 1816. In some embodiments, the command streamer 1903 is coupled with memory, which can be system memory, or one or more of internal caches and shared caches. In some embodiments, the command streamer 1903 receives commands from the memory and sends the commands to the 3D pipeline 1812 and / or media pipeline 1816. The commands are instructions for the 3D pipeline 1812 and media pipeline 1816. In one embodiment, the ring buffer additionally can include a batch command buffer that stores batches of commands. The commands for the 3D pipeline 1812 can also include references to data stored in memory, such as, but not limited to, vertex and geometry data used by the 3D pipeline 1812 and / or image data and memory objects used by the media pipeline 1816. The 3D pipeline 1812 and media pipeline 1816 process the commands and data, making use of the graphics processing cores within the graphics processor core array 1914 to perform processing of the commands and data. The graphics processor core array 1914 is coupled with and provides graphics processing core resources to the 3D pipeline 1812 and media pipeline 1816.

[0225] In various embodiments, the 3D pipeline 1812 can execute one or more shader programs, such as a vertex shader, a geometry shader, a pixel shader, a compute shader, or other shader programs, by processing the instructions and dispatching execution threads to the graphics processor core array 1914. The graphics processor core array 1914 provides unified execution resources for all shader programs, and these execution resources can be optimized for different shader program requirements. The execution resources can include general-purpose execution units coupled in an array, a SIMD engine, a geometry processing unit, or a special-purpose execution logic.

[0226] In some embodiments, graphics core array 1914 also includes execution logic to perform media functions, such as video and / or image processing. In one embodiment, the execution units additionally include logic to support parallel general purpose computing operations Figure 16 by processor core(s) 1607 or general purpose logic within processor cores 1702A- 1702N in graphics processor 1700 as in Figure 17 parallel or in conjunction with processing operations performed by the general purpose logic.

[0227] Output data from the threads executing on graphics core array 1914 can be output to memory in a unified return buffer (URB) 1918. URB 1918 can store data for multiple threads. In some embodiments, URB 1918 can be used to transmit data between different threads executing on graphics core array 1914. In some embodiments, URB 1918 can additionally be used to synchronize between fixed function logic within shared function logic 1920 and threads on the graphics core array.

[0228] In some embodiments, graphics core array 1914 is scalable, such that the array includes varying numbers of graphics cores, each having varying numbers of execution units based on target performance and power profiles of the GPE 1910. In one embodiment, the execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0229] Graphics core array 1914 is coupled with shared function logic 1920, which includes resources shared among the graphics cores in the graphics core array. Shared functions within shared function logic 1920 are hardware logic units that provide specialized supplemental functionality to graphics core array 1914. In various embodiments, shared function logic 1920 includes, without limitation, sampler 1921, math 1922, and inter-thread communication (ITC) 1923 logic. Additionally, some embodiments implement one or more caches 1925 within shared function logic 1920. Shared functions are implemented in cases where demand for a given specialized function is insufficient to include within graphics core array 1914. Instead, a single instantiation of that specialized function is implemented as a separate entity within shared function logic 1920 and shared among the execution resources within graphics core array 1914. The precise set of functions shared between graphics core array 1914 and included within graphics core array 1914 varies between embodiments.

[0230] Figure 20 is a block diagram of another embodiment of graphics processor 2000. Figure 20Elements having the same reference numbers (or names) as elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to so doing.

[0231] In some embodiments, graphics processor 2000 includes a ring interconnect 2002, a front-end 2004, a media engine 2037, and graphics cores 2080A-2080N. In some embodiments, ring interconnect 2002 couples the graphics processor to other processing units including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of a plurality of processors integrated within a multi-core processing system.

[0232] In some embodiments, graphics processor 2000 receives batches of commands via ring interconnect 2002. An incoming batch of commands is interpreted by a command streamer 2003 in front-end 2004. In some embodiments, graphics processor 2000 includes scalable execution logic to perform 3D geometry processing and media processing via the graphics cores 2080A-2080N. For 3D geometry processing commands, command streamer 2003 supplies commands to geometry pipeline 2036. For at least some media processing commands, command streamer 2003 supplies commands to a video front end 2034, which couples with a media engine 2037. In some embodiments, media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing and a multi-format encode / decode (MFX) 2033 engine to

[0233] In some embodiments, graphics processor 2000 includes a scalable thread execution resource featuring a modular architecture to enable various numbers of threads to be executed in parallel. Each modular architecture can be implemented both as a processor and as a core in a plurality of core complexes. One or more of graphics processor 2000 can each include multiple core complexes. For example, in some embodiments, graphics processor 2000 can include eight core complexes, with each core complex featuring a number of compute cores, including single programmable integer and floating point cores, multiple parallel floating point cores, or a combination of both. In other embodiments, graphics processor 2000 can include a single core complex that features a large number of compute cores, with this single core complex included in a multi-core complex. In still other embodiments, graphics processor 2000 can include three core complexes and one of these core complexes can be a high- performance core complex while the other two core complexes can be less powerful. In some embodiments, graphics processor 2000 can include a number of shader

[0234] Execution Unit

[0235] Figure 21 Figure illustrates thread execution logic 2100, which can be a part of the core complex of some embodiments. Thread execution logic 2100 includes an array of processing elements 2102A-2102N. Each processing element in the array can execute a different thread or the same thread. The array of processing elements 2102A-2102N can be implemented using any known technique for mounting a large number of processing elements into a small area. In some embodiments, processing elements 2102A-2102N are mounted on a substrate, which can then be mounted onto a larger substrate using known techniques. Figure 21 Elements having the same reference number (or designation) in FIGS. 1-10 as elements in any other figure herein can operate or function in any manner similar to the manner described elsewhere herein, but are not limited to so doing.

[0236] In some embodiments, thread execution logic 2100 includes a shader processor 2102, a thread dispatcher 2104, an instruction cache 2106, a scalable array of execution units including a plurality of execution units 2108A-2108N, a sampler 2110, a data cache 2112, and a data port 2114. In one embodiment, the scalable array of execution units can be dynamically scaled by enabling or disabling one or more execution units (e.g., any of execution units 2108A, 2108B, 2108C, 2108D to 2108N-1 and 2108N) based on workload computational requirements. In one embodiment, the included components are interconnected via an interconnect structure linking to each of the components. In some embodiments, thread execution logic 2100 includes one or more connections to memory (such as system memory or cache memory) via the instruction cache 2106, the data port 2114, the sampler 2110, and one or more of the execution units 2108A-2108N. In some embodiments, each execution unit (e.g., 2108A) is an independent, programmable, general-purpose computing unit capable of executing multiple concurrent hardware threads to process multiple data elements in parallel for each thread. In various embodiments, the array of execution units 2108A-2108N is scalable to include any number of individual execution units.

[0237] In some embodiments, execution units 2108A-2108N are primarily used to execute shader programs. Shader processor 2102 can handle various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2104. In one embodiment, the thread dispatcher includes logic for arbitrating thread requests from the graphics and media pipeline and instantiating the requested thread on one or more execution units in execution units 2108A-2108N. For example, a geometry pipeline (e.g., Figure 20 (2036) can dispatch vertex, surface tessellation, or geometry shader to thread execution logic 2100 ( Figure 21 This is used for processing. In some embodiments, the thread dispatcher 2104 can also handle a large number of requests generated from runtime threads executing shader programs.

[0238] In some embodiments, execution units 2108A-2108N support an instruction set that includes instructions for managing stencils, blends, and shader states. Specific shader instructions include instructions for loading bug and alpha values from registers or instructions for setting stencil, blend mode, blend factors, and shader opcode. Three dimensional (3D) graphics pipeline 2100 can also include a 3D pipeline 2110 for processing 3D graphics data. In some embodiments, 3D pipeline 2110 includes a vertex processor 2111, which is coupled to a graphics memory 2120, and a pixel processor 2112, which is also coupled to graphics memory 2120. Graphics memory 2120 can include a dedicated memory area for storing vertex data and another dedicated memory area for storing pixel data. In other embodiments, 3D pipeline 2110 can include multiple pixel processor 2112 and a single vertex processor 2111, multiple vertex processor 2111 and a single pixel processor 2112, or multiple vertex and pixel processors 2111, 2112. Other variations are possible.

[0239] Each of execution units 2108A-2108N operate on arrays of data elements. The number of data elements is the "execution size," or the number of channels for the instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control. The number of channels can be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In some embodiments, execution units 2108A-2108N support integer and floating-point data types.

[0240] The instruction set for execution units 2108A-2108N includes SIMD and VLIW instructions. Various data elements can be stored in registers and the execution units will process data in 64-bit, 128-bit, 256-bit, and 512-bit wide data registers, which can hold one, two, four, or eight 512-bit registers, respectively. The execution unit instructions for floating point, integer, and other GPGPU operations are described in more detail with respect to the execution unit architectures shown in FIGS. 2A and 2B.

[0241] One or more internal instruction caches (e.g., 2106) are included in thread execution logic 2100 to cache thread instructions for execution units. In some embodiments, one or more data caches (e.g., 2112) are included to cache thread data during thread execution. In some embodiments, a sampler 2110 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler 2110 includes specialized texture or media sampling functionality to handle texture or media data during the sampling process before the sampling data is provided to the execution units.

[0242] During execution, graphics and media pipelines send thread initiation requests to thread execution logic 2100 via thread burst generation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 2102 is invoked to further calculate output information and cause results to be written to an output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, pixel or fragment shaders calculate values of various vertex attributes to be interpolated across a rasterized object. In some embodiments, pixel processor logic within shader processor 2102 then executes an application programming interface (API)-supplied pixel or fragment shader program. To execute the shader program, shader processor 2102 dispatches threads to execution units (e.g., 2108A) via thread dispatcher 2104. In some embodiments, pixel shader 2102 uses texture sampling logic in sampler 2110 to access texture data in a texture map stored in memory. Arithmetic operations on texture data and input geometry data calculate pixel color data for each geometric fragment, or discard one or more pixels from further processing.

[0243] In some embodiments, data port 2114 provides a memory access mechanism for thread execution logic 2100 to output processed data to memory for processing on a graphics processor output pipeline. In some embodiments, data port 2114 includes or is coupled to one or more cache memories (e.g., data cache 2112) to cache data for memory access via the data port.

[0244] Figure 22is a block diagram illustrating a graphics processor instruction format 2200 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set that includes a number of instructions in multiple formats. The solid lined boxes illustrate the format of a typical instruction used by an execution unit in one embodiment and provided for illustrative purposes. The dashed line illustrates an alternate instruction format that can be used by the graphics processor in some embodiments. In some embodiments, graphics processor execution units support multiple instruction formats and can be capable of supporting additional instruction formats not illustrated here.

[0245] In some embodiments, a graphics processor execution unit natively supports the instruction in a 128-bit instruction format 2210. A 64-bit compact instruction format 2230 can be used for some instructions based on a selected instruction, instruction option, and number of operands. The native 128-bit instruction format 2210 provides access to all instruction options regardless of the instruction compact format chosen. Some instruction options and operations are restricted to the 64-bit compact instruction format 2230. A native instruction can be reconstructed from a compact instruction and control information appended to the compact instruction. The graphics processor execution unit can be capable of supporting the 64-bit compact instructions only, the 128-bit native instructions only, or both the 64-bit compact instructions and the 128-bit native instructions in different embodiments.

[0246] For each format, the instruction opcode 2212 defines the operation that the execution unit is to perform. The execution units execute each instruction in parallel across the multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the execution unit performs each instruction across all data channels of the

[0247] Some execution units have up to three operands, including two source operands, src0 2220, src1 2222, and one destination 2218. In some embodiments, an execution unit supports a dual destination instruction, where one of the destinations is implied. Data manipulation instructions can have a third source operand (e.g., SRC2 2224), where the instruction opcode 2212 determines the number of source operands. The last source operand can be an immediate (e.g., hard coded) value with the instruction.

[0248] In some embodiments, the 128-bit instruction format 2210 includes an access / address mode field 2226 that specifies, for example, whether a direct register addressing mode or an indirect register addressing mode is used. When the direct register addressing mode is used, the register address for one or more operands is provided directly by bits in the instruction.

[0249] In some embodiments, the 128-bit instruction format 2210 includes an access / address mode field 2226 that specifies the addressing mode and / or access mode of the instruction. In one embodiment, the access mode is used to qualify the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1 -byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction can use byte-aligned addressing for source and destination operands, and when in a second mode, the instruction can use 16-byte aligned addressing for all source and destination operands.

[0250] In one embodiment, the addressing mode portion of the access / address mode field 2226 determines whether the instruction is to use direct addressing or indirect addressing. When the direct register addressing mode is used, the register address for one or more operands is provided directly by bits in the instruction. When the indirect register addressing mode is used, the register address for one or more operands can be computed based on an address register value and an address immediate field in the instruction.

[0251] In some embodiments, instructions are grouped based on the opcode 2212 bit field to simplify opcode decoding 2240. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is exemplary only. In some embodiments, move and logic opcode group 2242 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, move and logic opcode group 2242 shares five most-significant bits (MSB), with move (mov) instructions taking the form 0000xxxxb and logic instructions taking the form 0001xxxxb. Flow control instruction group 2244 (e.g., call, jump (jmp)) includes instructions that take the form 0010xxxxb (e.g., Ox20). Misc instruction group 2246 includes a mix of instructions including synchronization instructions (e.g., wait, send) that take the form 0011xxxxb (e.g., Ox30). Parallel math instruction group 2248 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) that take the form 0100xxxxb (e.g., Ox40). Parallel math group 2248 performs arithmetic operations in parallel across data lanes. Vector math group 2250 includes arithmetic instructions (e.g., dp4) that take the form 0101xxxxb (e.g., Ox50). Vector math group performs arithmetic operations on vector operands, such as a dot product calculation.

[0252] Graphics Pipeline

[0253] Figure 23 is a block diagram of another embodiment of a graphics processor 2300. Figure 23 Elements of have the same reference numbers (or names) as elements of any other figure herein can operate or function in any manner similar to the manner described elsewhere herein, but are not limited to so doing.

[0254] In some embodiments, graphics processor 2300 includes graphics pipeline 2320, media pipeline 2330, display engine 2340, thread execution logic 2350, and render output pipeline 2370. In some embodiments, graphics processor 2300 is a graphics processor included in a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to the graphics processor 2300 via a ring interconnect 2302. In some embodiments, ring interconnect 2302 couples graphics processor 2300 to other processing components such as other graphics processors or general-purpose processors. Commands from ring interconnect 2302 are interpreted by a command streamer 2303, which supplies instructions to individual components of graphics pipeline 2320 or media pipeline 2330.

[0255] In some embodiments, the command streamer 2303 directs the operation of the vertex fetcher 2305, which reads vertex data from memory and executes vertex processing commands provided by the command streamer 2303. In some embodiments, the vertex fetcher 2305 provides the vertex data to the vertex shader 2307, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex fetcher 2305 and the vertex shader 2307 execute vertex processing instructions by dispatching execution threads to execution units 2352A-2352B via thread dispatcher 2331.

[0256] In some embodiments, the execution units 2352A-2352B are an array of similar vector processors that execute instructions for graphics and media operations. In some embodiments, the execution units 2352A-2352B have an attached Ll cache 2351 that is specific to each array or shared between arrays in the processing cluster. The cache can be configured as a data cache, an instruction cache, or both. In some embodiments, the processing cluster includes a scalar processor to process instruction from the scalar thread 2301.

[0257] In some embodiments, the graphics pipeline 2320 includes a tessellation component for hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 2311 configures tessellation operations. A programmable domain shader 2317 provides post-processing evaluation of tessellation output. A tessellator 2313 operates in the direction of the hull shader 2311 and includes specialized logic to generate a detailed set of geometric objects based on a coarse geometric model provided as input to the graphics pipeline 2320. In some embodiments, if tessellation is not used, the tessellation component (e.g., the hull shader 2311, the tessellator 2313, and the domain shader 2317) can be bypassed.

[0258] In some embodiments, a complete geometric object can be processed by the geometry shader 2319 via one or more threads dispatched to the execution units 2352A-2352B, or can proceed directly to the clipper 2329. In some embodiments, the geometry shader operates on entire geometric objects rather than on vertices or vertex patches as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 2319 receives input from the vertex shader 2307. In some embodiments, the geometry shader 2319 is programmable by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0259] The clipper 2329 processes vertex data prior to rasterization. The clipper 2329 can be a fixed function clipper or a programmable clipper with clip and geometry shader functionality. In some embodiments, the rasterizer and depth test components 2373 in the render output pipeline 2370 dispatch pixel shaders to convert a geometric object into its per-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 2350. In some embodiments, an application can bypass the rasterizer and depth test components 2373 and access un-rasterized vertex data via the egress unit 2323.

[0260] The graphics processor 2300 has an interconnect bus, interconnect fabric or some other interconnect mechanism to allow data and messages to be passed between components of the processor, including the execution unit(s) 2352A-2352B, the associated cache(s) 2351, the texture and media sampler 2354, and the render output pipeline components. In some embodiments, the sampler 2354, caches 2351, 2358, and execution unit(s) 2352A-2352B each have separate memory access ports to the local memory 2357 to enable simultaneous access to the same or different global memory 2355.

[0261] In some embodiments, the render output pipeline 2370 includes a rasterizer and depth test component 2373 that converts based on vertex data into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / shader unit for performing fixed function triangle and line rasterization. An associated render cache 2378 and depth cache 2379 are also available in some embodiments. Pixel operation components 2377 perform pixel-based operations on the data, although in some instances pixel operations associated with 2D operations (e.g., bit block image transfers with blending) are performed by the 2D engine 2341 or replaced at display time by the display controller 2343 using overlapping display planes. In some embodiments, a shared L3 cache 2375 is available for all graphics components, allowing sharing of data without the need to use main system memory.

[0262] In some embodiments, graphics processor media pipeline 2330 includes a media engine 2337 and a video front-end 2334. In some embodiments, video front-end 2334 receives pipeline commands from the command streamer 2303. In some embodiments, media pipeline 2330 includes a separate command streamer. In some embodiments, video front-end 2334 processes media commands before sending the media

[0263] In some embodiments, graphics processor 2300 includes a display engine 2340. In some embodiments, display engine 2340 is external to processor 2300 and coupled to the graphics processor via the ring interconnect 2302, or some other interconnect bus or fabric. In some embodiments, display engine 2340 includes a 2D engine 2341 and a display controller 2343. In some embodiments, display engine 2340 contains special purpose logic that is capable of operating independently of the 3D pipeline. In some embodiments, display controller 2343 is coupled to a (not shown) display device that can be a system integrated display device (such as in a laptop) or an external display device attached via an display device connector.

[0264] In some embodiments, graphics pipeline 2320 and media pipeline 2330 can be configured to perform operations based on a number of graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for a graphics processor translates API calls that are specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL) and / or the Open Computing Language (OpenCL) from the Khronos Group. In some embodiments, support can also be provided for the Direct3D library from the Microsoft Corporation. In some embodiments, a combination of

[0265] Graphics Pipeline Programming

[0266] Figure 24A FIG. 24 is a block diagram illustrating a graphics processor command format 2400 according to some embodiments. Figure 24B FIG. 25 is a block diagram illustrating a graphics processor command sequence 2410 according to an embodiment. Figure 24AThe solid-line boxes in the figure represent components that are generally included in the graphics commands, while the dashed lines include components that are optional or included only in a subset of the graphics commands. Figure 24A The exemplary graphics processor command format 2400 includes a data field to identify a target client 2402 for the command, a command operation code (opcode) 2404, and a data field for associated data for the command 2406. Some commands include a sub-opcode 2405 and a command size 2408 in some embodiments.

[0267] In some embodiments, the client 2402 specifies a client unit of the graphics device that processes the command data. In some embodiments, a graphics processor command parser examines the client field of each command to condition further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline to process commands. Once a command is received by a client unit, the client unit reads the opcode 2404 and the sub-opcode 2405 (if present) to determine the operation to perform. The client unit performs the command using information in the data field 2406. For some commands, an explicit command size 2408 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, commands are aligned via multiples of a doubleword.

[0268] Figure 24B The flow in the figure shows an exemplary graphics processor command sequence 2410. In some embodiments, a software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and tear down a set of graphics operations. A sample command sequence is shown and described for purposes of example, as embodiments are not limited to these specific commands or to this command sequence. Moreover, the described commands can be issued as a batch of commands in a command sequence, such that the graphics processor will process the sequence of commands in at least partially concurrence.

[0269] In some embodiments, the graphics processor command sequence 2410 can begin with a pipeline flush command 2412 to cause any active graphics pipeline to complete any ongoing commands in this pipeline. In some embodiments, 3D pipeline 2422 and media pipeline 2424 are not operating simultaneously. The execution pipeline flush can be used to ensure completion of the prior operation in the active pipeline before starting the execution of any exported commands from the command sequence. If a pipeline flush is not used, the pipeline architecture state can not be the same at the beginning of the pipeline operation as at the end of the pipeline operation, leading to potential instability.

[0270] In some embodiments, a pipeline select command 2413 is used when the command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, the pipeline select command 2413 is only needed once in the execution context, before the first pipeline command is issued, unless the context is issuing commands to two pipelines. In some embodiments, a pipeline flush command 2412 is required before the pipeline switch to the pipeline specified in the pipeline select command 2413.

[0271] In some embodiments, pipeline control commands 2414 configure the graphics pipeline for operation and configure pipeline state for the 3D pipeline 2422 and media pipeline 2424. In some embodiments, pipeline control commands 2414 configure the pipeline state for the active pipeline. In one embodiment, pipeline control commands 2414 are used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing a batch of commands.

[0272] In some embodiments, return buffer state commands 2416 are used to configure a set of return buffers for use by the respective pipeline to write data. Some pipeline operations require allocation, selection, or configuration of one or more return buffers to which intermediate or final data is written during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, return buffer state 2416 includes selection of the size and number of return buffers to use for a set of pipeline operations.

[0273] The remaining commands in the command sequence vary based on the active pipeline for operation. Based on the pipeline determination 2420, the command sequence is customized to work with either the 3D pipeline 2422 beginning with 3D pipeline state 2430 or the media pipeline 2424 beginning with media pipeline state 2440.

[0274] Commands for configuring 3D pipeline state 2430 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured prior to processing 3D primitive commands. The values for these commands are determined based at least in part on the particular 3D API in use. In some embodiments, 3D pipeline state 2430 commands can also selectively disable or bypass certain pipeline elements if those elements will not be used.

[0275] In some embodiments, 3D primitive 2432 commands are used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via 3D primitive 2432 commands are forwarded to a vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 2432 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, 3D primitive 2432 commands are used to perform vertex operations on 3D primitives via a vertex shader. To process the vertex shader, the 3D pipeline 2422 dispatches shader execution threads to graphics processor execution units.

[0276] In some embodiments, 3D pipeline 2422 is triggered via an execute 2434 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution to flush a command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for the 3D primitives. Once the operations are complete, the resulting geometry is rasterized and pixels are shaded by a pixel engine. Additional commands to control pixel shading and pixel back-end operations can also be included for those operations.

[0277] In some embodiments, graphics processor command sequences 2410 follow the media pipeline 2424 path when performing media operations. Generally, the specific use and manner of programming for the media pipeline 2424 depends on the media or compute operations to be performed. During media decode, specific media decode operations can be offloaded to this media pipeline. In some embodiments, this media pipeline can also be bypassed and media decode can be performed entirely or partially using resources provided by one or more general purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations where the graphics processor is used to perform SIMD vector operations using a compute shader program that is not explicitly related to the rendering of a graphics primitive.

[0278] In some embodiments, media pipeline 2424 is configured in a similar manner as 3D pipeline 2422. A set of commands to configure media pipeline state 2440 is dispatched or placed into a command queue, prior to media object command 2442. In some embodiments, the commands 2440 for the media pipeline state include data to configure media pipeline elements that will be used to process the media object. This includes data to configure video decode and video encode logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the commands 2440 for the media pipeline state enable the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0279] In some embodiments, media object command 2442 supplies a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline state must be valid prior to issuing media object command 2442. Once the pipeline state is configured and media object command 2442 is queued, the media pipeline 2424 is triggered via an execute command 2444 or equivalent execution event (e.g., register write). The output from the media pipeline 2424 can then be post-processed by operations provided by the 3D pipeline 2422 or the media pipeline 2424. In some embodiments, GPGPU operations are configured and executed in a similar manner as media operations.

[0280] Graphics Software Architecture

[0281] Figure 25 An exemplary graphics software architecture of a data processing system 2500 is illustrated in accordance with some embodiments. In some embodiments, the software architecture includes a 3D graphics application 2510, an operating system 2520, and at least one processor 2530. In some embodiments, processor 2530 includes a graphics processor 2532 and one or more general-purpose processor cores 2534. Graphics application 2510 and operating system 2520 each execute in system memory 2550 of the data processing system.

[0282] In some embodiments, 3D graphics application 2510 contains one or more shader programs including shader instructions 2512. The shader language instructions can be in a high-level shader language, such as the High-Level Shader Language (HLSL) or the OpenGL Shader Language (GLSL). The application also includes executable instructions 2514 in a machine language suitable for execution by the general- purpose processor core(s) 2534. The application also includes graphics objects defined by vertex data 2516.

[0283] In some embodiments, operating system 2520 is a Microsoft® Windows® operating system from Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel. Operating system 2520 can support a graphics API 2522, such as a Direct3D API, an OpenGL API, or a Vulkan API. When a Direct3D API is in use, operating system 2520 uses a front-end shader compiler 2524 to compile any shader instructions 2512 in HLSL into a lower-level shader language. The compilation can be a just-in-time (JIT) compilation or the application can perform shader pre- compilation. In some embodiments, high-level shaders are compiled into low-level shaders during compilation of a 3D graphics application 2510. In some embodiments, shader instructions 2512 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0284] In some embodiments, user mode graphics driver 2526 includes a back-end shader compiler 2527 to translate shader instructions 2512 into hardware specific representations. When an OpenGL API is in use, shader instructions 2512 in GLSL high level languages are passed to user mode graphics driver 2526 for compilation. In some embodiments, user mode graphics driver 2526 uses operating system kernel mode functions 2528 to communicate with kernel mode graphics driver 2529. In some embodiments, kernel mode graphics driver 2529 communicates with graphics processor 2532 to dispatch

[0285] IP Core Implementation

[0286] One or more aspects of at least one embodiment can be implemented by representative code stored on a machine-readable medium which represents and / or defines logic within an integrated circuit such as a processor. For example, a machine-readable medium can include instructions which represent various logic within the processor. When read by a machine, the instructions can cause the machine to fabricate the logic to perform the techniques described herein. Such representations, known as "IP cores," are reusable units of logic for an integrated circuit that can be stored on a tangible, machine-readable medium as a hardware model that a manufacturing machine can load to fabricate the integrated circuit. The

[0287] Figure 26is a block diagram illustrating an IP core development system 2600 that can be used to fabricate integrated circuits employed in implementations of the various embodiments described herein. The IP core development system 2600 can be used to generate modular, re-usable designs that can be incorporated into larger designs. A design facility 2630 can generate a software simulation 2610 of the IP core design in a high level programming language such as C / C++. The software simulation 2610 can be used to design, test, and verify the

[0288] The RTL design 2615, or equivalent, can be further synthesized, using a design facility, into a hardware model 2620, which can be in a hardware description language (HDL) or some other representation of the design. The HDL can be further simulated or tested to verify the IP core design. The IP core design can be stored in non-volatile memory 2640 (e.g., hard disk, flash memory, or any non-volatile storage medium) for delivery to a third party fabrication facility 2665. Alternatively, the IP core design can be transmitted (e.g., via the Internet) over a wired 2650 or wireless 2660 connection. The fabrication facility 2665 can then fabricate an integrated circuit based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

[0289] Exemplary System on a Chip Integrated Circuit

[0290] Figures 27-29 FIG. illustrates exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores, in accordance with various embodiments described herein. In addition to what is illustrated, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers or general purpose processor cores.

[0291] Figure 27is a block diagram illustrating an exemplary system on a chip integrated circuit 2700 that can be fabricated using one or more IP cores, according to an embodiment. The exemplary integrated circuit 2700 includes one or more application processors 2705 (e.g., CPUs), at least one graphics processor 2710, and can additionally include an image processor 2715 and / or a video processor 2720, any of which can be a modular IP core from the same or multiple different design facilities. The integrated circuit 2700 includes peripheral or bus logic including USB controllers 2725, UART controllers 2730, SPI / SDIO controllers 2735, and I2C controllers 2740. Additionally, the integrated circuit can include a display device 2745 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2750 and a mobile industry processor interface (MIPI) display interface 2755. Storage can be provided by a flash memory subsystem 2760 including flash memory and a flash memory controller. Memory interfaces can be provided via a memory controller 2765 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2770. 2 S / I 2 C controllers 2740. Additionally, the integrated circuit can include a display device 2745 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2750 and a mobile industry processor interface (MIPI) display interface 2755. Storage can be provided by a flash memory subsystem 2760 including flash memory and a flash memory controller. Memory interfaces can be provided via a memory controller 2765 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2770.

[0292] Figure 28 is a block diagram illustrating an exemplary graphics processor 2810 that can be fabricated in one or more IP cores, according to an embodiment. The graphics processor 2810 can be a variant of the graphics processor 2710 of Figure 27 . The graphics processor 2810 includes a vertex processor 2805 and one or more fragment processor(s) 2815A-2815N (e.g., 2815A, 2815B, 2815C, 2815D, through 2815N-1, and 2815N). The graphics processor 2810 can execute different shader programs via separate logic for vertex shader programs, which are executed asynchronously for vertex processing, and / or vertex shader programs, which are executed for each vertex or each primitive (e.g., triangle, quad, polygon) of a primitive. The graphics processor 2810 can integrate with per-pixel output capabilities for the direct display of the processed graphics, the processing of virtual worlds, the design of high resolution graphics, and the design of high resolution graphics.

[0293] Graphics processor 2810 additionally includes one or more memory management units (MMUs) 2820A-2820B, caches 2825A-2825B, and circuit interconnects 2830A-2830B. The one or more MMUs 2820A-2820B provide for virtual to physical address mapping for graphics processor 2810, including for vertex processor 2805 and / or fragment processor(s) 2815A-2815N, which can reference vertex or image / texture data stored in memory. In one embodiment, the one or more MMUs 2820A-2820B can be synchronized with other MMUs within the system, including the one or more MMUs associated with the one or more application processors 2705, graphics processor 2715, and / or video processor 2720 of system 2700, such that each processor 2705-2720 can participate in a shared or unified virtual memory system. The one or more circuit interconnects 2830A-2830B enable graphics processor 2810 to interface with other IP cores within the SoC, either via an internal bus of the SoC or via direct connections, according to embodiments. Figure 27

[0294] Figure 29 is a block diagram illustrating an additional exemplary graphics processor 2910 that can be fabricated using one or more IP cores, according to embodiments. Graphics processor 2910 can be a variant of graphics processor 2710 of system 2700. Graphics processor 2910 includes Figure 27 Figure 28

[0295] ​​​The graphics processor 2910 includes one or more shader cores 2915A-2915N (e.g., 2915A, 2915B, 2915C, 2915D, 2915E, 2915F through 2915N-1, and 2915N) that provide a unified shader core architecture, in which a single core or type or core can execute all types of programmable shader code including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores in the graphics processor 2910 can vary from one embodiment to another. In addition, the graphics processor 2910 includes an inter-core task manager 2905 that acts as a thread dispatcher to divide workloads between the one or more shader cores 2915A-2915N and to manage the dispatch of execution threads to the various shader cores 2915A-2915N, as well as a tiling unit 2918 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, such as to exploit local spatial coherence within a scene or to optimize use of an internal cache.

[0296] The following is directed to further examples.

[0297] Example 1 can optionally include a plurality of execution units; and logic, including at least in part hardware logic, to determine subgraphs of a network that can be executed in a frequency domain and to apply computations in the frequency domain in the subgraphs.

[0298] Example 2 can optionally include the apparatus of example 1, further comprising logic, including at least in part hardware logic, to dynamically select a convolution implementation based at least in part on running a transient comparison for each convolution in the network.

[0299] Example 3 can optionally include the apparatus of any of examples 1-2, wherein the selection is implemented at runtime.

[0300] Example 4 can optionally include an electronic device, the apparatus comprising a processor having a plurality of executions; and logic, including at least in part hardware logic, to determine subgraphs of a network that can be executed in a frequency domain and to apply computations in the frequency domain in the subgraphs.

[0301] Example 5 can optionally include the apparatus of any of examples 4, further comprising logic, including at least in part hardware logic, to dynamically select a convolution implementation based at least in part on running a transient comparison for each convolution in the network.

[0302] Example 6 can optionally include the apparatus of any of examples 1-5, wherein the selection is implemented at runtime.

[0303] Example 7 can optionally include an apparatus comprising a plurality of execution units; and logic, at least partially including hardware logic, to determine a subgraph of a network that can be performed in a frequency domain and apply a computation in the subgraph in the frequency domain.

[0304] Example 8 can optionally include the apparatus of any of Example 7, further comprising logic, at least partially including hardware logic, to convert the computation from the subgraph to a time domain.

[0305] Example 9 can optionally include an apparatus comprising a plurality of execution units; and logic, at least partially including hardware logic, to divide a neural network into a plurality of tiles and apply a convolution computation to the plurality of tiles.

[0306] Example 10 can optionally include the apparatus of Example 8, further comprising logic to merge results of the convolution computation.

[0307] In various embodiments, the operations discussed herein can be implemented as hardware (e.g., logic circuitry), software, firmware, or a combination thereof, which can be provided as a computer program product, for example, including a tangible (e.g., non-transitory) machine-readable or computer- readable medium having stored thereon instructions (or software processes) programmed to configure a computer to perform the processes discussed herein. The machine-readable medium can include a storage device.

[0308] In addition, such computer readable media can be downloaded as a computer program product, wherein the program can be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a bus, modem, or network connection) provided, for example, in carrier waves or other transport mechanisms.

[0309] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one implementation. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0310] Also, in the description and claims, the terms "coupled" and "connected," along with their derivatives, can be used. In some embodiments, "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" can mean that two or more elements are in direct physical or electrical contact with each other. However, "coupled" can also mean that two or more elements can not be in direct contact with each other, but can still cooperate or interact with each other.

[0311] Accordingly, although the embodiments have been described in language specific to structural features and / or methodological acts, it is to be understood that the subject claimed herein is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing the claimed subject matter.

Claims

1. A general-purpose graphics processor, comprising: Multiple execution units, including at least a first type of execution unit and a second type of execution unit, wherein the first type of execution unit has a first set of hardware execution resources and the second type of execution unit has a second set of hardware execution resources different from the first set of hardware execution resources; as well as Processing circuitry, used for: Determine the entire subgraph of a convolutional neural network that can be executed in the frequency domain; Generate prediction levels of activation sparsity for multiple layers of a convolutional neural network; as well as Convolution computation is applied in the subgraph in the frequency domain; wherein the most efficient point location is found to switch between dense convolution and sparse convolution, the first layer in the convolutional neural network uses a first set of hardware execution resources for dense convolution, and the remaining layers in the convolutional neural network use a second set of hardware execution resources for sparse convolution, wherein the depth of the remaining layers in the convolutional neural network is greater than that of the first layer.

2. The general-purpose graphics processor according to claim 1, wherein the processing circuit is configured to: The convolution implementation is selected dynamically, at least in part, based on performing brief comparisons for each convolution in the network; and Expose one or more embedded type cast operations to load / store instructions to support loading data with variable integer precision.

3. The general-purpose graphics processor according to claim 2, wherein the processing circuit is used for: Divide the convolutional layer of the convolutional neural network into multiple patches; Convolution calculations are applied to the multiple tiles.

4. The general-purpose graphics processor according to claim 3, wherein the processing circuit is used for: The results of the convolution calculations are combined.

5. The general-purpose graphics processor according to claim 1, wherein the processing circuit is used for: When the convolutional neural network operates in inference mode, the predicted level of activation sparsity of the multiple layers of the convolutional neural network is updated online.

6. An electronic device, comprising: General-purpose graphics processors, including: Multiple execution units, including at least a first type of execution unit and a second type of execution unit, wherein the first type of execution unit has a first set of hardware execution resources, and the second type of execution unit has a second set of hardware execution resources different from the first set of hardware execution resources; and Processing circuitry, used for: Determine the entire subgraph of a convolutional neural network that can be executed in the frequency domain; To generate prediction levels of activation sparsity for multiple layers of a convolutional neural network; and Convolution computation is applied in the subgraph in the frequency domain; wherein the most efficient point location is found to switch between dense convolution and sparse convolution, the first layer in the convolutional neural network uses a first set of hardware execution resources for dense convolution, and the remaining layers in the convolutional neural network use a second set of hardware execution resources for sparse convolution, wherein the depth of the remaining layers in the convolutional neural network is greater than that of the first layer.

7. The electronic device according to claim 6, wherein the processing circuit is configured to: The convolution implementation is selected dynamically, at least in part, based on performing brief comparisons for each convolution in the network; and Expose one or more embedded type cast operations to load / store instructions to support loading data with variable integer precision.

8. The electronic device according to claim 7, wherein: The selection is implemented at runtime.

9. The electronic device according to claim 7, wherein the processing circuit is used for: Divide the convolutional layer of the convolutional neural network into multiple patches; Convolution calculations are applied to the multiple tiles.

10. The electronic device according to claim 9, wherein the processing circuit is configured to: The results of the convolution calculations are combined.

11. The electronic device according to claim 6, wherein the processing circuit is used for: When the convolutional neural network operates in inference mode, the predicted level of activation sparsity of the multiple layers of the convolutional neural network is updated online.

12. A computer-implemented method, comprising: Data representing a convolutional neural network is received in a general-purpose graphics processor comprising multiple execution units, the multiple execution units including at least a first type of execution unit and a second type of execution unit, the first type of execution unit having a first set of hardware execution resources, and the second type of execution unit having a second set of hardware execution resources different from the first set of hardware execution resources; Determine the entire subgraph of a convolutional neural network that can be executed in the frequency domain; Generate prediction levels of activation sparsity for multiple layers of a convolutional neural network; as well as Convolution computation is applied in the subgraph in the frequency domain; wherein the most efficient point location is found to switch between dense convolution and sparse convolution, the first layer in the convolutional neural network uses a first set of hardware execution resources for dense convolution, and the remaining layers in the convolutional neural network use a second set of hardware execution resources for sparse convolution, wherein the depth of the remaining layers in the convolutional neural network is greater than that of the first layer.

13. The computer-implemented method according to claim 12, comprising: The convolution implementation is selected dynamically, at least in part, based on performing brief comparisons for each convolution in the network; as well as Expose one or more embedded type cast operations to load / store instructions to support loading data with variable integer precision.

14. The computer-implemented method according to claim 13, wherein: The selection is implemented at runtime.

15. The computer-implemented method according to claim 13, comprising: Divide the convolutional layer of the convolutional neural network into multiple patches; Convolution calculations are applied to the multiple tiles.

16. The computer-implemented method according to claim 15, comprising: The results of the convolution calculations are combined.

17. The computer-implemented method according to claim 12, comprising: When the convolutional neural network operates in inference mode, the predicted level of activation sparsity of the multiple layers of the convolutional neural network is updated online.

18. A non-transitory computer-readable medium comprising instructions that, when executed by a processor, cause the processor to perform the method according to any one of claims 12-17.

19. A computer program product comprising instructions that, when executed by a processor, cause the processor to perform the method according to any one of claims 12-17.

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